5 #include "pseudo_irg.h"
15 #ifdef obstack_chunk_alloc
16 # undef obstack_chunk_alloc
17 # define obstack_chunk_alloc malloc
19 # define obstack_chunk_alloc malloc
20 # define obstack_chunk_free free
23 #include "../bearch.h" /* the general register allocator interface */
24 #include "bearch_ia32_t.h"
26 #include "ia32_new_nodes.h" /* ia32 nodes interface */
27 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
28 #include "ia32_gen_decls.h" /* interface declaration emitter */
29 #include "ia32_transform.h"
30 #include "ia32_emitter.h"
31 #include "ia32_map_regs.h"
33 #define DEBUG_MODULE "ir.be.isa.ia32"
36 static set *cur_reg_set = NULL;
40 /**************************************************
43 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
44 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
45 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
46 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
49 **************************************************/
51 static ir_node *my_skip_proj(const ir_node *n) {
58 * Return register requirements for an ia32 node.
59 * If the node returns a tuple (mode_T) then the proj's
60 * will be asked for this information.
62 static const arch_register_req_t *ia32_get_irn_reg_req(const arch_irn_ops_t *self, arch_register_req_t *req, const ir_node *irn, int pos) {
63 const ia32_register_req_t *irn_req;
64 long node_pos = pos == -1 ? 0 : pos;
65 ir_mode *mode = get_irn_mode(irn);
66 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
68 if (mode == mode_T || mode == mode_M) {
69 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
73 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
77 node_pos = translate_proj_pos(irn);
83 irn = my_skip_proj(irn);
85 DBG((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
88 if (is_ia32_irn(irn)) {
90 irn_req = get_ia32_in_req(irn, pos);
93 irn_req = get_ia32_out_req(irn, node_pos);
96 DBG((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
98 memcpy(req, &(irn_req->req), sizeof(*req));
100 if (arch_register_req_is(&(irn_req->req), should_be_same) ||
101 arch_register_req_is(&(irn_req->req), should_be_different)) {
102 assert(irn_req->pos >= 0 && "should be same/different constraint for in -> out NYI");
103 req->other = get_irn_n(irn, irn_req->pos);
109 /* treat Phi like Const with default requirements */
111 DBG((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
112 if (mode_is_float(mode))
113 memcpy(req, &(ia32_default_req_ia32_floating_point.req), sizeof(*req));
114 else if (mode_is_int(mode) || mode_is_reference(mode))
115 memcpy(req, &(ia32_default_req_ia32_general_purpose.req), sizeof(*req));
116 else if (mode == mode_T || mode == mode_M) {
117 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
121 assert(0 && "unsupported Phi-Mode");
123 else if (get_irn_op(irn) == op_Start) {
124 DBG((mod, LEVEL_1, "returning reqs none for ProjX -> Start (%+F )\n", irn));
126 case pn_Start_X_initial_exec:
127 case pn_Start_P_value_arg_base:
128 case pn_Start_P_globals:
129 memcpy(req, &(ia32_default_req_none.req), sizeof(*req));
131 case pn_Start_P_frame_base:
132 memcpy(req, &(ia32_default_req_none.req), sizeof(*req));
134 case pn_Start_T_args:
135 assert(0 && "ProjT(pn_Start_T_args) should not be asked");
138 else if (get_irn_op(irn) == op_Return && pos > 0) {
139 DBG((mod, LEVEL_1, "returning reqs EAX for %+F\n", irn));
140 memcpy(req, &(ia32_default_req_ia32_general_purpose_eax.req), sizeof(*req));
143 DBG((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
151 static void ia32_set_irn_reg(const arch_irn_ops_t *self, ir_node *irn, const arch_register_t *reg) {
155 pos = translate_proj_pos(irn);
156 irn = my_skip_proj(irn);
159 if (is_ia32_irn(irn)) {
160 const arch_register_t **slots;
162 slots = get_ia32_slots(irn);
166 ia32_set_firm_reg(self, irn, reg, cur_reg_set);
170 static const arch_register_t *ia32_get_irn_reg(const arch_irn_ops_t *self, const ir_node *irn) {
172 const arch_register_t *reg = NULL;
175 pos = translate_proj_pos(irn);
176 irn = my_skip_proj(irn);
179 if (is_ia32_irn(irn)) {
180 const arch_register_t **slots;
181 slots = get_ia32_slots(irn);
185 reg = ia32_get_firm_reg(self, irn, cur_reg_set);
191 static arch_irn_class_t ia32_classify(const arch_irn_ops_t *self, const ir_node *irn) {
192 irn = my_skip_proj(irn);
194 return arch_irn_class_branch;
195 else if (is_ia32_irn(irn))
196 return arch_irn_class_normal;
201 static arch_irn_flags_t ia32_get_flags(const arch_irn_ops_t *self, const ir_node *irn) {
202 irn = my_skip_proj(irn);
203 if (is_ia32_irn(irn))
204 return get_ia32_flags(irn);
206 ir_printf("don't know flags of %+F\n", irn);
211 /* fill register allocator interface */
213 static const arch_irn_ops_t ia32_irn_ops = {
214 ia32_get_irn_reg_req,
223 /**************************************************
226 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
227 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
228 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
229 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
232 **************************************************/
234 typedef struct _ia32_isa_t {
235 const arch_isa_if_t *impl;
240 * Transforms the standard firm graph into
243 static void ia32_prepare_graph(void *self) {
244 ia32_code_gen_t *cg = self;
246 if (! is_pseudo_ir_graph(cg->irg))
247 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
253 * Dummy functions for hooks we don't need but which must be filled.
255 static void ia32_before_sched(void *self) {
258 static void ia32_before_ra(void *self) {
264 * Emits the code, closes the output file and frees
265 * the code generator interface.
267 static void ia32_codegen(void *self) {
268 ia32_code_gen_t *cg = self;
269 ir_graph *irg = cg->irg;
272 if (cg->emit_decls) {
273 ia32_gen_decls(cg->out);
277 // ia32_finish_irg(irg);
278 ia32_gen_routine(out, irg, cg->arch_env);
282 /* de-allocate code generator */
283 del_set(cg->reg_set);
287 static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env);
289 static const arch_code_generator_if_t ia32_code_gen_if = {
292 ia32_before_sched, /* before scheduling hook */
293 ia32_before_ra, /* before register allocation hook */
294 ia32_codegen /* emit && done */
298 * Initializes the code generator.
300 static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env) {
301 ia32_isa_t *isa = (ia32_isa_t *)arch_env->isa;
302 ia32_code_gen_t *cg = malloc(sizeof(*cg));
304 cg->impl = &ia32_code_gen_if;
306 cg->reg_set = new_set(cmp_irn_reg_assoc, 1024);
307 cg->mod = firm_dbg_register("be.transform.ia32");
309 cg->arch_env = arch_env;
313 if (isa->num_codegens > 1)
318 cur_reg_set = cg->reg_set;
320 return (arch_code_generator_t *)cg;
325 /*****************************************************************
326 * ____ _ _ _____ _____
327 * | _ \ | | | | |_ _|/ ____| /\
328 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
329 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
330 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
331 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
333 *****************************************************************/
336 * Initializes the backend ISA and opens the output file.
338 static void *ia32_init(void) {
339 static int inited = 0;
340 ia32_isa_t *isa = malloc(sizeof(*isa));
342 isa->impl = &ia32_isa_if;
349 isa->num_codegens = 0;
351 ia32_register_init();
352 ia32_create_opcodes();
360 * Closes the output file and frees the ISA structure.
362 static void ia32_done(void *self) {
368 static int ia32_get_n_reg_class(const void *self) {
372 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
373 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
374 return &ia32_reg_classes[i];
377 static const arch_irn_ops_t *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
378 return &ia32_irn_ops;
381 const arch_irn_handler_t ia32_irn_handler = {
385 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
386 return &ia32_irn_handler;
392 * Initializes the code generator interface.
394 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
395 return &ia32_code_gen_if;
399 * Returns the default scheduler
401 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
402 return reg_pressure_selector;
406 static void ia32_register_options(lc_opt_entry_t *ent)
409 #endif /* WITH_LIBCORE */
411 const arch_isa_if_t ia32_isa_if = {
413 ia32_register_options,
417 ia32_get_n_reg_class,
419 ia32_get_irn_handler,
420 ia32_get_code_generator_if,
421 ia32_get_list_sched_selector