2 * This is the main ia32 firm backend driver.
17 #include "pseudo_irg.h"
21 #include "iredges_t.h"
29 #include "../beabi.h" /* the general register allocator interface */
30 #include "../benode_t.h"
31 #include "../belower.h"
32 #include "../besched_t.h"
34 #include "bearch_ia32_t.h"
36 #include "ia32_new_nodes.h" /* ia32 nodes interface */
37 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
38 #include "ia32_gen_decls.h" /* interface declaration emitter */
39 #include "ia32_transform.h"
40 #include "ia32_emitter.h"
41 #include "ia32_map_regs.h"
42 #include "ia32_optimize.h"
44 #define DEBUG_MODULE "firm.be.ia32.isa"
47 static set *cur_reg_set = NULL;
50 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
52 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
53 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_XXX]);
56 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
57 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_fp_regs[REG_XXXX]);
60 /**************************************************
63 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
64 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
65 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
66 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
69 **************************************************/
71 static ir_node *my_skip_proj(const ir_node *n) {
78 * Return register requirements for an ia32 node.
79 * If the node returns a tuple (mode_T) then the proj's
80 * will be asked for this information.
82 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
83 const ia32_register_req_t *irn_req;
84 long node_pos = pos == -1 ? 0 : pos;
85 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
86 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
88 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
89 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
93 if (mode == mode_T && pos < 0) {
94 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
98 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
103 node_pos = ia32_translate_proj_pos(irn);
109 irn = my_skip_proj(irn);
111 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
114 if (is_ia32_irn(irn)) {
116 irn_req = get_ia32_in_req(irn, pos);
119 irn_req = get_ia32_out_req(irn, node_pos);
122 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
124 memcpy(req, &(irn_req->req), sizeof(*req));
126 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
127 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
128 req->other_same = get_irn_n(irn, irn_req->same_pos);
131 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
132 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
133 req->other_different = get_irn_n(irn, irn_req->different_pos);
137 /* treat Phi like Const with default requirements */
139 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
140 if (mode_is_float(mode))
141 memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req));
142 else if (mode_is_int(mode) || mode_is_reference(mode))
143 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
144 else if (mode == mode_T || mode == mode_M) {
145 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
149 assert(0 && "unsupported Phi-Mode");
152 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
160 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
162 const ia32_irn_ops_t *ops = self;
164 if (get_irn_mode(irn) == mode_X) {
168 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
171 pos = ia32_translate_proj_pos(irn);
172 irn = my_skip_proj(irn);
175 if (is_ia32_irn(irn)) {
176 const arch_register_t **slots;
178 slots = get_ia32_slots(irn);
182 ia32_set_firm_reg(irn, reg, cur_reg_set);
186 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
188 const arch_register_t *reg = NULL;
192 if (get_irn_mode(irn) == mode_X) {
196 pos = ia32_translate_proj_pos(irn);
197 irn = my_skip_proj(irn);
200 if (is_ia32_irn(irn)) {
201 const arch_register_t **slots;
202 slots = get_ia32_slots(irn);
206 reg = ia32_get_firm_reg(irn, cur_reg_set);
212 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
213 irn = my_skip_proj(irn);
215 return arch_irn_class_branch;
216 else if (is_ia32_irn(irn))
217 return arch_irn_class_normal;
222 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
223 irn = my_skip_proj(irn);
224 if (is_ia32_irn(irn))
225 return get_ia32_flags(irn);
231 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
232 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
235 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
237 const ia32_irn_ops_t *ops = self;
239 if (is_ia32_use_frame(irn) && bias != 0) {
240 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
242 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
243 snprintf(buf, sizeof(buf), "%d", bias);
244 add_ia32_am_offs(irn, buf);
246 set_ia32_am_flavour(irn, am_flav);
251 be_abi_call_flags_bits_t flags;
252 const arch_isa_t *isa;
256 static void *ia32_abi_init(const be_abi_call_t *call, const arch_isa_t *isa, ir_graph *irg)
258 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
259 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
260 env->flags = fl.bits;
266 static void ia32_abi_dont_save_regs(void *self, pset *s)
268 ia32_abi_env_t *env = self;
269 if(env->flags.try_omit_fp)
270 pset_insert_ptr(s, env->isa->bp);
273 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
275 ia32_abi_env_t *env = self;
276 const arch_register_t *frame_reg = env->isa->sp;
278 if(!env->flags.try_omit_fp) {
279 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
280 ir_node *bl = get_irg_start_block(env->irg);
281 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
282 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
283 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_XXX]);
286 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_along);
287 store_bp = new_rd_ia32_Store(NULL, env->irg, bl, curr_sp, curr_no_reg, curr_bp, *mem, mode_T);
288 set_ia32_am_support(store_bp, ia32_am_Dest);
289 set_ia32_am_flavour(store_bp, ia32_B);
290 set_ia32_op_type(store_bp, ia32_AddrModeD);
291 *mem = new_r_Proj(env->irg, bl, store_bp, mode_M, 0);
292 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
293 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
294 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
296 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
297 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
303 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
305 ia32_abi_env_t *env = self;
306 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
307 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
308 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_XXX]);
310 if(env->flags.try_omit_fp) {
311 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_against);
316 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
318 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
319 load_bp = new_rd_ia32_Load(NULL, env->irg, bl, curr_sp, curr_no_reg, *mem, mode_T);
320 set_ia32_am_support(load_bp, ia32_am_Source);
321 set_ia32_am_flavour(load_bp, ia32_B);
322 set_ia32_op_type(load_bp, ia32_AddrModeS);
323 set_ia32_ls_mode(load_bp, mode_bp);
324 curr_bp = new_r_Proj(env->irg, bl, load_bp, mode_bp, 0);
325 *mem = new_r_Proj(env->irg, bl, load_bp, mode_M, 1);
328 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
329 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
333 * Produces the type which sits between the stack args and the locals on the stack.
334 * it will contain the return address and space to store the old base pointer.
335 * @return The Firm type modeling the ABI between type.
337 static ir_type *ia32_abi_get_between_type(void *self)
339 static ir_type *omit_fp_between_type = NULL;
340 static ir_type *between_type = NULL;
342 ia32_abi_env_t *env = self;
346 entity *ret_addr_ent;
347 entity *omit_fp_ret_addr_ent;
349 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
350 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
352 between_type = new_type_class(new_id_from_str("ia32_between_type"));
353 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
354 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
356 set_entity_offset_bytes(old_bp_ent, 0);
357 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
358 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
360 omit_fp_between_type = new_type_class(new_id_from_str("ia32_between_type_omit_fp"));
361 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, new_id_from_str("ret_addr"), ret_addr_type);
363 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
364 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
367 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
370 static const be_abi_callbacks_t ia32_abi_callbacks = {
373 ia32_abi_get_between_type,
374 ia32_abi_dont_save_regs,
379 /* fill register allocator interface */
381 static const arch_irn_ops_if_t ia32_irn_ops_if = {
382 ia32_get_irn_reg_req,
387 ia32_get_frame_entity,
391 ia32_irn_ops_t ia32_irn_ops = {
398 /**************************************************
401 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
402 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
403 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
404 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
407 **************************************************/
410 * Transforms the standard firm graph into
413 static void ia32_prepare_graph(void *self) {
414 ia32_code_gen_t *cg = self;
415 firm_dbg_module_t *old_mod = cg->mod;
417 cg->mod = firm_dbg_register("firm.be.ia32.transform");
418 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
419 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
421 edges_deactivate(cg->irg);
422 dead_node_elimination(cg->irg);
423 edges_activate(cg->irg);
428 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
429 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
435 * Insert copies for all ia32 nodes where the should_be_same requirement
437 * Transform Sub into Neg -- Add if IN2 == OUT
439 static void ia32_finish_irg_walker(ir_node *irn, void *env) {
440 ia32_code_gen_t *cg = env;
441 const ia32_register_req_t **reqs;
442 const arch_register_t *out_reg, *in_reg;
444 ir_node *copy, *in_node, *block;
446 if (! is_ia32_irn(irn))
449 /* nodes with destination address mode don't produce values */
450 if (get_ia32_op_type(irn) == ia32_AddrModeD)
453 reqs = get_ia32_out_req_all(irn);
454 n_res = get_ia32_n_res(irn);
455 block = get_nodes_block(irn);
457 /* check all OUT requirements, if there is a should_be_same */
458 for (i = 0; i < n_res; i++) {
459 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
460 /* get in and out register */
461 out_reg = get_ia32_out_reg(irn, i);
462 in_node = get_irn_n(irn, reqs[i]->same_pos);
463 in_reg = arch_get_irn_register(cg->arch_env, in_node);
465 /* check if in and out register are equal */
466 if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
467 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
469 /* create copy from in register */
470 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
472 /* destination is the out register */
473 arch_set_irn_register(cg->arch_env, copy, out_reg);
475 /* insert copy before the node into the schedule */
476 sched_add_before(irn, copy);
479 set_irn_n(irn, reqs[i]->same_pos, copy);
484 /* check if there is a sub which need to be transformed */
485 ia32_transform_sub_to_neg_add(irn, cg);
487 /* transform a LEA into an Add if possible */
488 ia32_transform_lea_to_add(irn, cg);
492 * Add Copy nodes for not fulfilled should_be_equal constraints
494 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
495 irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
501 * Dummy functions for hooks we don't need but which must be filled.
503 static void ia32_before_sched(void *self) {
506 static void ia32_before_ra(void *self) {
512 * Transforms a be node into a Load.
514 static void transform_to_Load(ia32_transform_env_t *env) {
515 ir_node *irn = env->irn;
516 entity *ent = be_get_frame_entity(irn);
517 ir_mode *mode = env->mode;
518 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
519 ir_node *nomem = new_rd_NoMem(env->irg);
520 ir_node *sched_point = NULL;
521 ir_node *ptr = get_irn_n(irn, 0);
522 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
523 ir_node *new_op, *proj;
524 const arch_register_t *reg;
526 if (sched_is_scheduled(irn)) {
527 sched_point = sched_prev(irn);
530 if (mode_is_float(mode)) {
531 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
534 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
537 set_ia32_am_support(new_op, ia32_am_Source);
538 set_ia32_op_type(new_op, ia32_AddrModeS);
539 set_ia32_am_flavour(new_op, ia32_B);
540 set_ia32_ls_mode(new_op, mode);
541 set_ia32_frame_ent(new_op, ent);
542 set_ia32_use_frame(new_op);
544 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
547 sched_add_after(sched_point, new_op);
548 sched_add_after(new_op, proj);
553 /* copy the register from the old node to the new Load */
554 reg = arch_get_irn_register(env->cg->arch_env, irn);
555 arch_set_irn_register(env->cg->arch_env, new_op, reg);
562 * Transforms a be node into a Store.
564 static void transform_to_Store(ia32_transform_env_t *env) {
565 ir_node *irn = env->irn;
566 entity *ent = be_get_frame_entity(irn);
567 ir_mode *mode = env->mode;
568 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
569 ir_node *nomem = new_rd_NoMem(env->irg);
570 ir_node *ptr = get_irn_n(irn, 0);
571 ir_node *val = get_irn_n(irn, 1);
572 ir_node *new_op, *proj;
573 ir_node *sched_point = NULL;
575 if (sched_is_scheduled(irn)) {
576 sched_point = sched_prev(irn);
579 if (mode_is_float(mode)) {
580 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
582 else if (get_mode_size_bits(mode) == 8) {
583 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
586 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
589 set_ia32_am_support(new_op, ia32_am_Dest);
590 set_ia32_op_type(new_op, ia32_AddrModeD);
591 set_ia32_am_flavour(new_op, ia32_B);
592 set_ia32_ls_mode(new_op, get_irn_mode(val));
593 set_ia32_frame_ent(new_op, ent);
594 set_ia32_use_frame(new_op);
596 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
599 sched_add_after(sched_point, new_op);
600 sched_add_after(new_op, proj);
610 * Calls the transform functions for StackParam, Spill and Reload.
612 static void ia32_after_ra_walker(ir_node *node, void *env) {
613 ia32_code_gen_t *cg = env;
614 ia32_transform_env_t tenv;
619 tenv.block = get_nodes_block(node);
620 tenv.dbg = get_irn_dbg_info(node);
621 tenv.irg = current_ir_graph;
624 tenv.mode = get_irn_mode(node);
627 /* be_is_StackParam(node) || */
628 if (be_is_Reload(node)) {
629 transform_to_Load(&tenv);
631 else if (be_is_Spill(node)) {
632 transform_to_Store(&tenv);
637 * We transform StackParam, Spill and Reload here. This needs to be done before
638 * stack biasing otherwise we would miss the corrected offset for these nodes.
640 static void ia32_after_ra(void *self) {
641 ia32_code_gen_t *cg = self;
642 irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
647 * Emits the code, closes the output file and frees
648 * the code generator interface.
650 static void ia32_codegen(void *self) {
651 ia32_code_gen_t *cg = self;
652 ir_graph *irg = cg->irg;
655 if (cg->emit_decls) {
656 ia32_gen_decls(cg->out);
660 ia32_finish_irg(irg, cg);
661 be_dump(irg, "-finished", dump_ir_block_graph_sched);
662 ia32_gen_routine(out, irg, cg);
666 pmap_destroy(cg->tv_ent);
667 pmap_destroy(cg->types);
669 /* de-allocate code generator */
670 del_set(cg->reg_set);
674 static void *ia32_cg_init(FILE *F, const be_irg_t *birg);
676 static const arch_code_generator_if_t ia32_code_gen_if = {
678 NULL, /* before abi introduce hook */
680 ia32_before_sched, /* before scheduling hook */
681 ia32_before_ra, /* before register allocation hook */
682 ia32_after_ra, /* after register allocation hook */
683 ia32_codegen /* emit && done */
687 * Initializes the code generator.
689 static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
690 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
691 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
693 cg->impl = &ia32_code_gen_if;
695 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
696 cg->mod = firm_dbg_register("firm.be.ia32.cg");
698 cg->arch_env = birg->main_env->arch_env;
699 cg->types = pmap_create();
700 cg->tv_ent = pmap_create();
703 /* set optimizations */
706 cg->opt.placecnst = 1;
711 if (isa->name_obst_size) {
712 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
713 isa->name_obst_size = 0;
714 obstack_free(isa->name_obst, NULL);
715 obstack_init(isa->name_obst);
721 if (isa->num_codegens > 1)
726 cur_reg_set = cg->reg_set;
728 ia32_irn_ops.cg = cg;
730 return (arch_code_generator_t *)cg;
735 /*****************************************************************
736 * ____ _ _ _____ _____
737 * | _ \ | | | | |_ _|/ ____| /\
738 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
739 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
740 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
741 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
743 *****************************************************************/
745 static ia32_isa_t ia32_isa_template = {
746 &ia32_isa_if, /* isa interface implementation */
747 &ia32_gp_regs[REG_ESP], /* stack pointer register */
748 &ia32_gp_regs[REG_EBP], /* base pointer register */
749 -1, /* stack direction */
750 0, /* number of code generator objects so far */
751 NULL, /* 16bit register names */
752 NULL, /* 8bit register names */
754 NULL, /* name obstack */
755 0 /* name obst size */
760 * Initializes the backend ISA.
762 static void *ia32_init(void) {
763 static int inited = 0;
769 isa = xcalloc(1, sizeof(*isa));
770 memcpy(isa, &ia32_isa_template, sizeof(*isa));
772 ia32_register_init(isa);
773 ia32_create_opcodes();
775 isa->regs_16bit = pmap_create();
776 isa->regs_8bit = pmap_create();
778 ia32_build_16bit_reg_map(isa->regs_16bit);
779 ia32_build_8bit_reg_map(isa->regs_8bit);
782 isa->name_obst = xcalloc(1, sizeof(*(isa->name_obst)));
783 obstack_init(isa->name_obst);
784 isa->name_obst_size = 0;
795 * Closes the output file and frees the ISA structure.
797 static void ia32_done(void *self) {
798 ia32_isa_t *isa = self;
800 pmap_destroy(isa->regs_16bit);
801 pmap_destroy(isa->regs_8bit);
804 //printf("name obst size = %d bytes\n", isa->name_obst_size);
805 obstack_free(isa->name_obst, NULL);
813 static int ia32_get_n_reg_class(const void *self) {
817 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
818 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
819 return &ia32_reg_classes[i];
823 * Get the register class which shall be used to store a value of a given mode.
824 * @param self The this pointer.
825 * @param mode The mode in question.
826 * @return A register class which can hold values of the given mode.
828 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
829 if (mode_is_float(mode))
830 return &ia32_reg_classes[CLASS_ia32_fp];
832 return &ia32_reg_classes[CLASS_ia32_gp];
836 * Get the ABI restrictions for procedure calls.
837 * @param self The this pointer.
838 * @param method_type The type of the method (procedure) in question.
839 * @param abi The abi object to be modified
841 void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
844 unsigned cc = get_method_calling_convention(method_type);
845 int n = get_method_n_params(method_type);
848 int i, ignore_1, ignore_2;
850 const arch_register_t *reg;
851 be_abi_call_flags_t call_flags;
853 /* set abi flags for calls */
854 call_flags.bits.left_to_right = 0;
855 call_flags.bits.store_args_sequential = 0;
856 call_flags.bits.try_omit_fp = 1;
857 call_flags.bits.fp_free = 0;
858 call_flags.bits.call_has_imm = 1;
860 /* set stack parameter passing style */
861 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
863 /* collect the mode for each type */
864 modes = alloca(n * sizeof(modes[0]));
866 for (i = 0; i < n; i++) {
867 tp = get_method_param_type(method_type, i);
868 modes[i] = get_type_mode(tp);
871 /* set register parameters */
872 if (cc & cc_reg_param) {
873 /* determine the number of parameters passed via registers */
874 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
876 /* loop over all parameters and set the register requirements */
877 for (i = 0; i <= biggest_n; i++) {
878 reg = ia32_get_RegParam_reg(n, modes, i, cc);
879 assert(reg && "kaputt");
880 be_abi_call_param_reg(abi, i, reg);
887 /* set stack parameters */
888 for (i = stack_idx; i < n; i++) {
889 be_abi_call_param_stack(abi, i);
893 /* set return registers */
894 n = get_method_n_ress(method_type);
896 assert(n <= 2 && "more than two results not supported");
898 /* In case of 64bit returns, we will have two 32bit values */
900 tp = get_method_res_type(method_type, 0);
901 mode = get_type_mode(tp);
903 assert(!mode_is_float(mode) && "two FP results not supported");
905 tp = get_method_res_type(method_type, 1);
906 mode = get_type_mode(tp);
908 assert(!mode_is_float(mode) && "two FP results not supported");
910 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
911 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
914 tp = get_method_res_type(method_type, 0);
915 assert(is_atomic_type(tp));
916 mode = get_type_mode(tp);
918 be_abi_call_res_reg(abi, 0, mode_is_float(mode) ? &ia32_fp_regs[REG_XMM0] : &ia32_gp_regs[REG_EAX]);
923 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
924 return &ia32_irn_ops;
927 const arch_irn_handler_t ia32_irn_handler = {
931 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
932 return &ia32_irn_handler;
935 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
936 return is_ia32_irn(irn);
940 * Initializes the code generator interface.
942 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
943 return &ia32_code_gen_if;
946 list_sched_selector_t ia32_sched_selector;
949 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
951 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
952 memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
953 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
954 return &ia32_sched_selector;
958 static void ia32_register_options(lc_opt_entry_t *ent)
961 #endif /* WITH_LIBCORE */
963 const arch_isa_if_t ia32_isa_if = {
965 ia32_register_options,
969 ia32_get_n_reg_class,
971 ia32_get_reg_class_for_mode,
973 ia32_get_irn_handler,
974 ia32_get_code_generator_if,
975 ia32_get_list_sched_selector