2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
57 #include "../benode.h"
58 #include "../belower.h"
59 #include "../besched.h"
62 #include "../beirgmod.h"
63 #include "../be_dbgout.h"
64 #include "../beblocksched.h"
65 #include "../bemachine.h"
66 #include "../beilpsched.h"
67 #include "../bespillslots.h"
68 #include "../bemodule.h"
69 #include "../begnuas.h"
70 #include "../bestate.h"
71 #include "../beflags.h"
72 #include "../betranshlp.h"
73 #include "../belistsched.h"
74 #include "../beabihelper.h"
76 #include "bearch_ia32_t.h"
78 #include "ia32_new_nodes.h"
79 #include "gen_ia32_regalloc_if.h"
80 #include "gen_ia32_machine.h"
81 #include "ia32_common_transform.h"
82 #include "ia32_transform.h"
83 #include "ia32_emitter.h"
84 #include "ia32_map_regs.h"
85 #include "ia32_optimize.h"
87 #include "ia32_dbg_stat.h"
88 #include "ia32_finish.h"
89 #include "ia32_util.h"
91 #include "ia32_architecture.h"
94 #include "ia32_pbqp_transform.h"
96 transformer_t be_transformer = TRANSFORMER_DEFAULT;
99 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
101 ir_mode *mode_fpcw = NULL;
102 ia32_code_gen_t *ia32_current_cg = NULL;
104 /** The current omit-fp state */
105 static unsigned ia32_curr_fp_ommitted = 0;
106 static ir_type *omit_fp_between_type = NULL;
107 static ir_type *between_type = NULL;
108 static ir_entity *old_bp_ent = NULL;
109 static ir_entity *ret_addr_ent = NULL;
110 static ir_entity *omit_fp_ret_addr_ent = NULL;
113 * The environment for the intrinsic mapping.
115 static ia32_intrinsic_env_t intrinsic_env = {
117 NULL, /* the irg, these entities belong to */
118 NULL, /* entity for __divdi3 library call */
119 NULL, /* entity for __moddi3 library call */
120 NULL, /* entity for __udivdi3 library call */
121 NULL, /* entity for __umoddi3 library call */
125 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
128 * Used to create per-graph unique pseudo nodes.
130 static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
131 create_const_node_func func,
132 const arch_register_t* reg)
134 ir_node *block, *res;
139 block = get_irg_start_block(cg->irg);
140 res = func(NULL, block);
141 arch_set_irn_register(res, reg);
147 /* Creates the unique per irg GP NoReg node. */
148 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg)
150 return create_const(cg, &cg->noreg_gp, new_bd_ia32_NoReg_GP,
151 &ia32_gp_regs[REG_GP_NOREG]);
154 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg)
156 return create_const(cg, &cg->noreg_vfp, new_bd_ia32_NoReg_VFP,
157 &ia32_vfp_regs[REG_VFP_NOREG]);
160 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg)
162 return create_const(cg, &cg->noreg_xmm, new_bd_ia32_NoReg_XMM,
163 &ia32_xmm_regs[REG_XMM_NOREG]);
166 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg)
168 return create_const(cg, &cg->fpu_trunc_mode, new_bd_ia32_ChangeCW,
169 &ia32_fp_cw_regs[REG_FPCW]);
174 * Returns the admissible noreg register node for input register pos of node irn.
176 static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
178 const arch_register_req_t *req = arch_get_register_req(irn, pos);
180 assert(req != NULL && "Missing register requirements");
181 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
182 return ia32_new_NoReg_gp(cg);
184 if (ia32_cg_config.use_sse2) {
185 return ia32_new_NoReg_xmm(cg);
187 return ia32_new_NoReg_vfp(cg);
191 static arch_irn_class_t ia32_classify(const ir_node *irn)
193 arch_irn_class_t classification = 0;
195 assert(is_ia32_irn(irn));
197 if (is_ia32_is_reload(irn))
198 classification |= arch_irn_class_reload;
200 if (is_ia32_is_spill(irn))
201 classification |= arch_irn_class_spill;
203 if (is_ia32_is_remat(irn))
204 classification |= arch_irn_class_remat;
206 return classification;
210 * The IA32 ABI callback object.
213 be_abi_call_flags_bits_t flags; /**< The call flags. */
214 ir_graph *irg; /**< The associated graph. */
217 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
219 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
222 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
224 if (is_be_node(node))
225 be_node_set_frame_entity(node, entity);
227 set_ia32_frame_ent(node, entity);
230 static void ia32_set_frame_offset(ir_node *irn, int bias)
232 if (get_ia32_frame_ent(irn) == NULL)
235 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
236 ir_graph *irg = get_irn_irg(irn);
237 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
238 if (layout->sp_relative) {
239 /* Pop nodes modify the stack pointer before calculating the
240 * destination address, so fix this here
245 add_ia32_am_offs_int(irn, bias);
248 static int ia32_get_sp_bias(const ir_node *node)
250 if (is_ia32_Call(node))
251 return -(int)get_ia32_call_attr_const(node)->pop;
253 if (is_ia32_Push(node))
256 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
263 * Generate the routine prologue.
265 * @param self The callback object.
266 * @param mem A pointer to the mem node. Update this if you define new memory.
267 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
268 * @param stack_bias Points to the current stack bias, can be modified if needed.
270 * @return The register which shall be used as a stack frame base.
272 * All nodes which define registers in @p reg_map must keep @p reg_map current.
274 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
276 ia32_abi_env_t *env = self;
277 ia32_code_gen_t *cg = ia32_current_cg;
278 const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
280 ia32_curr_fp_ommitted = env->flags.try_omit_fp;
281 if (! env->flags.try_omit_fp) {
282 ir_node *bl = get_irg_start_block(env->irg);
283 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
284 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
285 ir_node *noreg = ia32_new_NoReg_gp(cg);
288 /* mark bp register as ignore */
289 be_set_constr_single_reg_out(get_Proj_pred(curr_bp),
290 get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
293 push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
294 curr_sp = new_r_Proj(push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
295 *mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
297 /* the push must have SP out register */
298 arch_set_irn_register(curr_sp, arch_env->sp);
300 /* this modifies the stack bias, because we pushed 32bit */
303 /* move esp to ebp */
304 curr_bp = be_new_Copy(arch_env->bp->reg_class, bl, curr_sp);
305 be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
306 arch_register_req_type_ignore);
308 /* beware: the copy must be done before any other sp use */
309 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
310 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
311 arch_register_req_type_produces_sp);
313 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
314 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
323 * Generate the routine epilogue.
324 * @param self The callback object.
325 * @param bl The block for the epilog
326 * @param mem A pointer to the mem node. Update this if you define new memory.
327 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
328 * @return The register which shall be used as a stack frame base.
330 * All nodes which define registers in @p reg_map must keep @p reg_map current.
332 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
334 ia32_abi_env_t *env = self;
335 const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
336 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
337 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
339 if (env->flags.try_omit_fp) {
340 /* simply remove the stack frame here */
341 curr_sp = be_new_IncSP(arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
343 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
345 if (ia32_cg_config.use_leave) {
349 leave = new_bd_ia32_Leave(NULL, bl, curr_bp);
350 curr_bp = new_r_Proj(leave, mode_bp, pn_ia32_Leave_frame);
351 curr_sp = new_r_Proj(leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
355 /* the old SP is not needed anymore (kill the proj) */
356 assert(is_Proj(curr_sp));
359 /* copy ebp to esp */
360 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], bl, curr_bp);
361 arch_set_irn_register(curr_sp, arch_env->sp);
362 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
363 arch_register_req_type_ignore);
366 pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
367 curr_bp = new_r_Proj(pop, mode_bp, pn_ia32_Pop_res);
368 curr_sp = new_r_Proj(pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
370 *mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
372 arch_set_irn_register(curr_sp, arch_env->sp);
373 arch_set_irn_register(curr_bp, arch_env->bp);
376 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
377 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
381 * Initialize the callback object.
382 * @param call The call object.
383 * @param irg The graph with the method.
384 * @return Some pointer. This pointer is passed to all other callback functions as self object.
386 static void *ia32_abi_init(const be_abi_call_t *call, ir_graph *irg)
388 ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
389 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
390 env->flags = fl.bits;
396 * Destroy the callback object.
397 * @param self The callback object.
399 static void ia32_abi_done(void *self)
405 * Build the between type and entities if not already build.
407 static void ia32_build_between_type(void)
409 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
410 if (! between_type) {
411 ir_type *old_bp_type = new_type_primitive(mode_Iu);
412 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
414 between_type = new_type_struct(IDENT("ia32_between_type"));
415 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
416 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
418 set_entity_offset(old_bp_ent, 0);
419 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
420 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
421 set_type_state(between_type, layout_fixed);
423 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
424 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
426 set_entity_offset(omit_fp_ret_addr_ent, 0);
427 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
428 set_type_state(omit_fp_between_type, layout_fixed);
434 * Produces the type which sits between the stack args and the locals on the stack.
435 * it will contain the return address and space to store the old base pointer.
436 * @return The Firm type modeling the ABI between type.
438 static ir_type *ia32_abi_get_between_type(void *self)
440 ia32_abi_env_t *env = self;
442 ia32_build_between_type();
443 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
447 * Return the stack entity that contains the return address.
449 ir_entity *ia32_get_return_address_entity(void)
451 ia32_build_between_type();
452 return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent;
456 * Return the stack entity that contains the frame address.
458 ir_entity *ia32_get_frame_address_entity(void)
460 ia32_build_between_type();
461 return ia32_curr_fp_ommitted ? NULL : old_bp_ent;
465 * Get the estimated cycle count for @p irn.
467 * @param self The this pointer.
468 * @param irn The node.
470 * @return The estimated cycle count for this operation
472 static int ia32_get_op_estimated_cost(const ir_node *irn)
475 ia32_op_type_t op_tp;
479 if (!is_ia32_irn(irn))
482 assert(is_ia32_irn(irn));
484 cost = get_ia32_latency(irn);
485 op_tp = get_ia32_op_type(irn);
487 if (is_ia32_CopyB(irn)) {
490 else if (is_ia32_CopyB_i(irn)) {
491 int size = get_ia32_copyb_size(irn);
492 cost = 20 + (int)ceil((4/3) * size);
494 /* in case of address mode operations add additional cycles */
495 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
497 In case of stack access and access to fixed addresses add 5 cycles
498 (we assume they are in cache), other memory operations cost 20
501 if (is_ia32_use_frame(irn) || (
502 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
503 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
515 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
517 * @param irn The original operation
518 * @param i Index of the argument we want the inverse operation to yield
519 * @param inverse struct to be filled with the resulting inverse op
520 * @param obstack The obstack to use for allocation of the returned nodes array
521 * @return The inverse operation or NULL if operation invertible
523 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
534 ir_node *block, *noreg, *nomem;
537 /* we cannot invert non-ia32 irns */
538 if (! is_ia32_irn(irn))
541 /* operand must always be a real operand (not base, index or mem) */
542 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
545 /* we don't invert address mode operations */
546 if (get_ia32_op_type(irn) != ia32_Normal)
549 /* TODO: adjust for new immediates... */
550 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
554 block = get_nodes_block(irn);
555 mode = get_irn_mode(irn);
556 irn_mode = get_irn_mode(irn);
557 noreg = get_irn_n(irn, 0);
559 dbg = get_irn_dbg_info(irn);
561 /* initialize structure */
562 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
566 switch (get_ia32_irn_opcode(irn)) {
569 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
570 /* we have an add with a const here */
571 /* invers == add with negated const */
572 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
574 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
575 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
576 set_ia32_commutative(inverse->nodes[0]);
578 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
579 /* we have an add with a symconst here */
580 /* invers == sub with const */
581 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
583 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
586 /* normal add: inverse == sub */
587 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
594 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
595 /* we have a sub with a const/symconst here */
596 /* invers == add with this const */
597 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
598 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
599 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
603 if (i == n_ia32_binary_left) {
604 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
607 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
615 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
616 /* xor with const: inverse = xor */
617 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
618 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
619 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
623 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
629 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
634 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
639 /* inverse operation not supported */
647 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
649 if (mode_is_float(mode))
656 * Get the mode that should be used for spilling value node
658 static ir_mode *get_spill_mode(const ir_node *node)
660 ir_mode *mode = get_irn_mode(node);
661 return get_spill_mode_mode(mode);
665 * Checks whether an addressmode reload for a node with mode mode is compatible
666 * with a spillslot of mode spill_mode
668 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
670 return !mode_is_float(mode) || mode == spillmode;
674 * Check if irn can load its operand at position i from memory (source addressmode).
675 * @param irn The irn to be checked
676 * @param i The operands position
677 * @return Non-Zero if operand can be loaded
679 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
681 ir_node *op = get_irn_n(irn, i);
682 const ir_mode *mode = get_irn_mode(op);
683 const ir_mode *spillmode = get_spill_mode(op);
685 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
686 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
687 !ia32_is_spillmode_compatible(mode, spillmode) ||
688 is_ia32_use_frame(irn)) /* must not already use frame */
691 switch (get_ia32_am_support(irn)) {
696 if (i != n_ia32_unary_op)
702 case n_ia32_binary_left: {
703 const arch_register_req_t *req;
704 if (!is_ia32_commutative(irn))
707 /* we can't swap left/right for limited registers
708 * (As this (currently) breaks constraint handling copies)
710 req = arch_get_in_register_req(irn, n_ia32_binary_left);
711 if (req->type & arch_register_req_type_limited)
716 case n_ia32_binary_right:
725 panic("Unknown AM type");
728 /* HACK: must not already use "real" memory.
729 * This can happen for Call and Div */
730 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
736 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
740 ir_mode *dest_op_mode;
742 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
744 set_ia32_op_type(irn, ia32_AddrModeS);
746 load_mode = get_irn_mode(get_irn_n(irn, i));
747 dest_op_mode = get_ia32_ls_mode(irn);
748 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
749 set_ia32_ls_mode(irn, load_mode);
751 set_ia32_use_frame(irn);
752 set_ia32_need_stackent(irn);
754 if (i == n_ia32_binary_left &&
755 get_ia32_am_support(irn) == ia32_am_binary &&
756 /* immediates are only allowed on the right side */
757 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
758 ia32_swap_left_right(irn);
759 i = n_ia32_binary_right;
762 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
764 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
765 set_irn_n(irn, n_ia32_mem, spill);
766 set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i));
767 set_ia32_is_reload(irn);
770 static const be_abi_callbacks_t ia32_abi_callbacks = {
773 ia32_abi_get_between_type,
778 /* register allocator interface */
779 static const arch_irn_ops_t ia32_irn_ops = {
781 ia32_get_frame_entity,
782 ia32_set_frame_offset,
785 ia32_get_op_estimated_cost,
786 ia32_possible_memory_operand,
787 ia32_perform_memory_operand,
790 static ir_entity *mcount = NULL;
792 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
794 static void ia32_before_abi(void *self)
796 ia32_code_gen_t *cg = self;
798 if (mcount == NULL) {
799 ir_type *tp = new_type_method(0, 0);
800 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
801 /* FIXME: enter the right ld_ident here */
802 set_entity_ld_ident(mcount, get_entity_ident(mcount));
803 set_entity_visibility(mcount, ir_visibility_external);
805 instrument_initcall(cg->irg, mcount);
810 * Transforms the standard firm graph into
813 static void ia32_prepare_graph(void *self)
815 ia32_code_gen_t *cg = self;
818 switch (be_transformer) {
819 case TRANSFORMER_DEFAULT:
820 /* transform remaining nodes into assembler instructions */
821 ia32_transform_graph(cg);
824 case TRANSFORMER_PBQP:
825 case TRANSFORMER_RAND:
826 /* transform nodes into assembler instructions by PBQP magic */
827 ia32_transform_graph_by_pbqp(cg);
831 panic("invalid transformer");
834 ia32_transform_graph(cg);
837 /* do local optimizations (mainly CSE) */
838 optimize_graph_df(cg->irg);
841 dump_ir_graph(cg->irg, "transformed");
843 /* optimize address mode */
844 ia32_optimize_graph(cg);
846 /* do code placement, to optimize the position of constants */
850 dump_ir_graph(cg->irg, "place");
853 ir_node *turn_back_am(ir_node *node)
855 dbg_info *dbgi = get_irn_dbg_info(node);
856 ir_node *block = get_nodes_block(node);
857 ir_node *base = get_irn_n(node, n_ia32_base);
858 ir_node *index = get_irn_n(node, n_ia32_index);
859 ir_node *mem = get_irn_n(node, n_ia32_mem);
862 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
863 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
865 ia32_copy_am_attrs(load, node);
866 if (is_ia32_is_reload(node))
867 set_ia32_is_reload(load);
868 set_irn_n(node, n_ia32_mem, new_NoMem());
870 switch (get_ia32_am_support(node)) {
872 set_irn_n(node, n_ia32_unary_op, load_res);
876 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
877 set_irn_n(node, n_ia32_binary_left, load_res);
879 set_irn_n(node, n_ia32_binary_right, load_res);
884 panic("Unknown AM type");
886 noreg = ia32_new_NoReg_gp(ia32_current_cg);
887 set_irn_n(node, n_ia32_base, noreg);
888 set_irn_n(node, n_ia32_index, noreg);
889 set_ia32_am_offs_int(node, 0);
890 set_ia32_am_sc(node, NULL);
891 set_ia32_am_scale(node, 0);
892 clear_ia32_am_sc_sign(node);
894 /* rewire mem-proj */
895 if (get_irn_mode(node) == mode_T) {
896 const ir_edge_t *edge;
897 foreach_out_edge(node, edge) {
898 ir_node *out = get_edge_src_irn(edge);
899 if (get_irn_mode(out) == mode_M) {
900 set_Proj_pred(out, load);
901 set_Proj_proj(out, pn_ia32_Load_M);
907 set_ia32_op_type(node, ia32_Normal);
908 if (sched_is_scheduled(node))
909 sched_add_before(node, load);
914 static ir_node *flags_remat(ir_node *node, ir_node *after)
916 /* we should turn back source address mode when rematerializing nodes */
921 if (is_Block(after)) {
924 block = get_nodes_block(after);
927 type = get_ia32_op_type(node);
934 /* TODO implement this later... */
935 panic("found DestAM with flag user %+F this should not happen", node);
938 default: assert(type == ia32_Normal); break;
941 copy = exact_copy(node);
942 set_nodes_block(copy, block);
943 sched_add_after(after, copy);
949 * Called before the register allocator.
951 static void ia32_before_ra(void *self)
953 ia32_code_gen_t *cg = self;
955 /* setup fpu rounding modes */
956 ia32_setup_fpu_mode(cg);
959 be_sched_fix_flags(cg->irg, &ia32_reg_classes[CLASS_ia32_flags],
962 be_add_missing_keeps(cg->irg);
967 * Transforms a be_Reload into a ia32 Load.
969 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node)
971 ir_graph *irg = get_irn_irg(node);
972 dbg_info *dbg = get_irn_dbg_info(node);
973 ir_node *block = get_nodes_block(node);
974 ir_entity *ent = be_get_frame_entity(node);
975 ir_mode *mode = get_irn_mode(node);
976 ir_mode *spillmode = get_spill_mode(node);
977 ir_node *noreg = ia32_new_NoReg_gp(cg);
978 ir_node *sched_point = NULL;
979 ir_node *ptr = get_irg_frame(irg);
980 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
981 ir_node *new_op, *proj;
982 const arch_register_t *reg;
984 if (sched_is_scheduled(node)) {
985 sched_point = sched_prev(node);
988 if (mode_is_float(spillmode)) {
989 if (ia32_cg_config.use_sse2)
990 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
992 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
994 else if (get_mode_size_bits(spillmode) == 128) {
995 /* Reload 128 bit SSE registers */
996 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
999 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
1001 set_ia32_op_type(new_op, ia32_AddrModeS);
1002 set_ia32_ls_mode(new_op, spillmode);
1003 set_ia32_frame_ent(new_op, ent);
1004 set_ia32_use_frame(new_op);
1005 set_ia32_is_reload(new_op);
1007 DBG_OPT_RELOAD2LD(node, new_op);
1009 proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
1012 sched_add_after(sched_point, new_op);
1016 /* copy the register from the old node to the new Load */
1017 reg = arch_get_irn_register(node);
1018 arch_set_irn_register(proj, reg);
1020 SET_IA32_ORIG_NODE(new_op, node);
1022 exchange(node, proj);
1026 * Transforms a be_Spill node into a ia32 Store.
1028 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node)
1030 ir_graph *irg = get_irn_irg(node);
1031 dbg_info *dbg = get_irn_dbg_info(node);
1032 ir_node *block = get_nodes_block(node);
1033 ir_entity *ent = be_get_frame_entity(node);
1034 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1035 ir_mode *mode = get_spill_mode(spillval);
1036 ir_node *noreg = ia32_new_NoReg_gp(cg);
1037 ir_node *nomem = new_NoMem();
1038 ir_node *ptr = get_irg_frame(irg);
1039 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1041 ir_node *sched_point = NULL;
1043 if (sched_is_scheduled(node)) {
1044 sched_point = sched_prev(node);
1047 if (mode_is_float(mode)) {
1048 if (ia32_cg_config.use_sse2)
1049 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
1051 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
1052 } else if (get_mode_size_bits(mode) == 128) {
1053 /* Spill 128 bit SSE registers */
1054 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
1055 } else if (get_mode_size_bits(mode) == 8) {
1056 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
1058 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
1061 set_ia32_op_type(store, ia32_AddrModeD);
1062 set_ia32_ls_mode(store, mode);
1063 set_ia32_frame_ent(store, ent);
1064 set_ia32_use_frame(store);
1065 set_ia32_is_spill(store);
1066 SET_IA32_ORIG_NODE(store, node);
1067 DBG_OPT_SPILL2ST(node, store);
1070 sched_add_after(sched_point, store);
1074 exchange(node, store);
1077 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
1079 dbg_info *dbg = get_irn_dbg_info(node);
1080 ir_node *block = get_nodes_block(node);
1081 ir_node *noreg = ia32_new_NoReg_gp(cg);
1082 ir_graph *irg = get_irn_irg(node);
1083 ir_node *frame = get_irg_frame(irg);
1085 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
1087 set_ia32_frame_ent(push, ent);
1088 set_ia32_use_frame(push);
1089 set_ia32_op_type(push, ia32_AddrModeS);
1090 set_ia32_ls_mode(push, mode_Is);
1091 set_ia32_is_spill(push);
1093 sched_add_before(schedpoint, push);
1097 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
1099 dbg_info *dbg = get_irn_dbg_info(node);
1100 ir_node *block = get_nodes_block(node);
1101 ir_node *noreg = ia32_new_NoReg_gp(cg);
1102 ir_graph *irg = get_irn_irg(node);
1103 ir_node *frame = get_irg_frame(irg);
1105 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
1107 set_ia32_frame_ent(pop, ent);
1108 set_ia32_use_frame(pop);
1109 set_ia32_op_type(pop, ia32_AddrModeD);
1110 set_ia32_ls_mode(pop, mode_Is);
1111 set_ia32_is_reload(pop);
1113 sched_add_before(schedpoint, pop);
1118 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1120 dbg_info *dbg = get_irn_dbg_info(node);
1121 ir_mode *spmode = mode_Iu;
1122 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1125 sp = new_rd_Proj(dbg, pred, spmode, pos);
1126 arch_set_irn_register(sp, spreg);
1132 * Transform MemPerm, currently we do this the ugly way and produce
1133 * push/pop into/from memory cascades. This is possible without using
1136 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
1138 ir_node *block = get_nodes_block(node);
1139 ir_node *sp = be_abi_get_ignore_irn(be_get_irg_abi(cg->irg), &ia32_gp_regs[REG_ESP]);
1140 int arity = be_get_MemPerm_entity_arity(node);
1141 ir_node **pops = ALLOCAN(ir_node*, arity);
1145 const ir_edge_t *edge;
1146 const ir_edge_t *next;
1149 for (i = 0; i < arity; ++i) {
1150 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1151 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1152 ir_type *enttype = get_entity_type(inent);
1153 unsigned entsize = get_type_size_bytes(enttype);
1154 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1155 ir_node *mem = get_irn_n(node, i + 1);
1158 /* work around cases where entities have different sizes */
1159 if (entsize2 < entsize)
1161 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1163 push = create_push(cg, node, node, sp, mem, inent);
1164 sp = create_spproj(node, push, pn_ia32_Push_stack);
1166 /* add another push after the first one */
1167 push = create_push(cg, node, node, sp, mem, inent);
1168 add_ia32_am_offs_int(push, 4);
1169 sp = create_spproj(node, push, pn_ia32_Push_stack);
1172 set_irn_n(node, i, new_Bad());
1176 for (i = arity - 1; i >= 0; --i) {
1177 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1178 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1179 ir_type *enttype = get_entity_type(outent);
1180 unsigned entsize = get_type_size_bytes(enttype);
1181 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1184 /* work around cases where entities have different sizes */
1185 if (entsize2 < entsize)
1187 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1189 pop = create_pop(cg, node, node, sp, outent);
1190 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1192 add_ia32_am_offs_int(pop, 4);
1194 /* add another pop after the first one */
1195 pop = create_pop(cg, node, node, sp, outent);
1196 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1203 keep = be_new_Keep(block, 1, in);
1204 sched_add_before(node, keep);
1206 /* exchange memprojs */
1207 foreach_out_edge_safe(node, edge, next) {
1208 ir_node *proj = get_edge_src_irn(edge);
1209 int p = get_Proj_proj(proj);
1213 set_Proj_pred(proj, pops[p]);
1214 set_Proj_proj(proj, pn_ia32_Pop_M);
1217 /* remove memperm */
1218 arity = get_irn_arity(node);
1219 for (i = 0; i < arity; ++i) {
1220 set_irn_n(node, i, new_Bad());
1226 * Block-Walker: Calls the transform functions Spill and Reload.
1228 static void ia32_after_ra_walker(ir_node *block, void *env)
1230 ir_node *node, *prev;
1231 ia32_code_gen_t *cg = env;
1233 /* beware: the schedule is changed here */
1234 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1235 prev = sched_prev(node);
1237 if (be_is_Reload(node)) {
1238 transform_to_Load(cg, node);
1239 } else if (be_is_Spill(node)) {
1240 transform_to_Store(cg, node);
1241 } else if (be_is_MemPerm(node)) {
1242 transform_MemPerm(cg, node);
1248 * Collects nodes that need frame entities assigned.
1250 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1252 be_fec_env_t *env = data;
1253 const ir_mode *mode;
1256 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1257 mode = get_spill_mode_mode(get_irn_mode(node));
1258 align = get_mode_size_bytes(mode);
1259 } else if (is_ia32_irn(node) &&
1260 get_ia32_frame_ent(node) == NULL &&
1261 is_ia32_use_frame(node)) {
1262 if (is_ia32_need_stackent(node))
1265 switch (get_ia32_irn_opcode(node)) {
1267 case iro_ia32_Load: {
1268 const ia32_attr_t *attr = get_ia32_attr_const(node);
1270 if (attr->data.need_32bit_stackent) {
1272 } else if (attr->data.need_64bit_stackent) {
1275 mode = get_ia32_ls_mode(node);
1276 if (is_ia32_is_reload(node))
1277 mode = get_spill_mode_mode(mode);
1279 align = get_mode_size_bytes(mode);
1283 case iro_ia32_vfild:
1285 case iro_ia32_xLoad: {
1286 mode = get_ia32_ls_mode(node);
1291 case iro_ia32_FldCW: {
1292 /* although 2 byte would be enough 4 byte performs best */
1300 panic("unexpected frame user while collection frame entity nodes");
1302 case iro_ia32_FnstCW:
1303 case iro_ia32_Store8Bit:
1304 case iro_ia32_Store:
1307 case iro_ia32_vfist:
1308 case iro_ia32_vfisttp:
1310 case iro_ia32_xStore:
1311 case iro_ia32_xStoreSimple:
1318 be_node_needs_frame_entity(env, node, mode, align);
1322 * We transform Spill and Reload here. This needs to be done before
1323 * stack biasing otherwise we would miss the corrected offset for these nodes.
1325 static void ia32_after_ra(void *self)
1327 ia32_code_gen_t *cg = self;
1328 ir_graph *irg = cg->irg;
1329 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->irg);
1331 /* create and coalesce frame entities */
1332 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1333 be_assign_entities(fec_env, ia32_set_frame_entity);
1334 be_free_frame_entity_coalescer(fec_env);
1336 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1340 * Last touchups for the graph before emit: x87 simulation to replace the
1341 * virtual with real x87 instructions, creating a block schedule and peephole
1344 static void ia32_finish(void *self)
1346 ia32_code_gen_t *cg = self;
1347 ir_graph *irg = cg->irg;
1349 ia32_finish_irg(irg, cg);
1351 /* we might have to rewrite x87 virtual registers */
1352 if (cg->do_x87_sim) {
1353 x87_simulate_graph(cg->irg);
1356 /* do peephole optimisations */
1357 ia32_peephole_optimization(cg);
1359 /* create block schedule, this also removes empty blocks which might
1360 * produce critical edges */
1361 cg->blk_sched = be_create_block_schedule(irg);
1365 * Emits the code, closes the output file and frees
1366 * the code generator interface.
1368 static void ia32_codegen(void *self)
1370 ia32_code_gen_t *cg = self;
1371 ir_graph *irg = cg->irg;
1373 if (ia32_cg_config.emit_machcode) {
1374 ia32_gen_binary_routine(cg, irg);
1376 ia32_gen_routine(cg, irg);
1379 /* remove it from the isa */
1382 assert(ia32_current_cg == cg);
1383 ia32_current_cg = NULL;
1385 /* de-allocate code generator */
1390 * Returns the node representing the PIC base.
1392 static ir_node *ia32_get_pic_base(void *self)
1395 ia32_code_gen_t *cg = self;
1396 ir_node *get_eip = cg->get_eip;
1397 if (get_eip != NULL)
1400 block = get_irg_start_block(cg->irg);
1401 get_eip = new_bd_ia32_GetEIP(NULL, block);
1402 cg->get_eip = get_eip;
1404 be_dep_on_frame(get_eip);
1408 static void *ia32_cg_init(ir_graph *irg);
1410 static const arch_code_generator_if_t ia32_code_gen_if = {
1412 ia32_get_pic_base, /* return node used as base in pic code addresses */
1413 ia32_before_abi, /* before abi introduce hook */
1416 ia32_before_ra, /* before register allocation hook */
1417 ia32_after_ra, /* after register allocation hook */
1418 ia32_finish, /* called before codegen */
1419 ia32_codegen /* emit && done */
1423 * Initializes a IA32 code generator.
1425 static void *ia32_cg_init(ir_graph *irg)
1427 ia32_isa_t *isa = (ia32_isa_t *)be_get_irg_arch_env(irg);
1428 ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t);
1430 cg->impl = &ia32_code_gen_if;
1433 cg->blk_sched = NULL;
1434 cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1435 cg->gprof = (be_get_irg_options(irg)->gprof) ? 1 : 0;
1438 /* Linux gprof implementation needs base pointer */
1439 be_get_irg_options(irg)->omit_fp = 0;
1446 if (isa->name_obst) {
1447 obstack_free(isa->name_obst, NULL);
1448 obstack_init(isa->name_obst);
1452 assert(ia32_current_cg == NULL);
1453 ia32_current_cg = cg;
1455 return (arch_code_generator_t *)cg;
1460 * Set output modes for GCC
1462 static const tarval_mode_info mo_integer = {
1469 * set the tarval output mode of all integer modes to decimal
1471 static void set_tarval_output_modes(void)
1475 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1476 ir_mode *mode = get_irp_mode(i);
1478 if (mode_is_int(mode))
1479 set_tarval_mode_output_option(mode, &mo_integer);
1483 const arch_isa_if_t ia32_isa_if;
1486 * The template that generates a new ISA object.
1487 * Note that this template can be changed by command line
1490 static ia32_isa_t ia32_isa_template = {
1492 &ia32_isa_if, /* isa interface implementation */
1493 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1494 &ia32_gp_regs[REG_EBP], /* base pointer register */
1495 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1496 -1, /* stack direction */
1497 2, /* power of two stack alignment, 2^2 == 4 */
1498 NULL, /* main environment */
1499 7, /* costs for a spill instruction */
1500 5, /* costs for a reload instruction */
1501 false, /* no custom abi handling */
1503 NULL, /* 16bit register names */
1504 NULL, /* 8bit register names */
1505 NULL, /* 8bit register names high */
1508 NULL, /* current code generator */
1509 NULL, /* abstract machine */
1511 NULL, /* name obstack */
1515 static void init_asm_constraints(void)
1517 be_init_default_asm_constraint_flags();
1519 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1520 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1521 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1522 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1523 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1524 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1525 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1526 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1527 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1528 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1529 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1530 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1531 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1532 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1533 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1534 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1535 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1536 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1537 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1538 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1540 /* no support for autodecrement/autoincrement */
1541 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1542 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1543 /* no float consts */
1544 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1545 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1546 /* makes no sense on x86 */
1547 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1548 /* no support for sse consts yet */
1549 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1550 /* no support for x87 consts yet */
1551 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1552 /* no support for mmx registers yet */
1553 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1554 /* not available in 32bit mode */
1555 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1556 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1558 /* no code yet to determine register class needed... */
1559 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1563 * Initializes the backend ISA.
1565 static arch_env_t *ia32_init(FILE *file_handle)
1567 static int inited = 0;
1575 set_tarval_output_modes();
1577 isa = XMALLOC(ia32_isa_t);
1578 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1580 if (mode_fpcw == NULL) {
1581 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1584 ia32_register_init();
1585 ia32_create_opcodes(&ia32_irn_ops);
1587 be_emit_init(file_handle);
1588 isa->regs_16bit = pmap_create();
1589 isa->regs_8bit = pmap_create();
1590 isa->regs_8bit_high = pmap_create();
1591 isa->types = pmap_create();
1592 isa->tv_ent = pmap_create();
1593 isa->cpu = ia32_init_machine_description();
1595 ia32_build_16bit_reg_map(isa->regs_16bit);
1596 ia32_build_8bit_reg_map(isa->regs_8bit);
1597 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1600 isa->name_obst = XMALLOC(struct obstack);
1601 obstack_init(isa->name_obst);
1604 /* enter the ISA object into the intrinsic environment */
1605 intrinsic_env.isa = isa;
1607 /* emit asm includes */
1608 n = get_irp_n_asms();
1609 for (i = 0; i < n; ++i) {
1610 be_emit_cstring("#APP\n");
1611 be_emit_ident(get_irp_asm(i));
1612 be_emit_cstring("\n#NO_APP\n");
1615 /* needed for the debug support */
1616 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1617 be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
1618 be_emit_write_line();
1626 * Closes the output file and frees the ISA structure.
1628 static void ia32_done(void *self)
1630 ia32_isa_t *isa = self;
1632 /* emit now all global declarations */
1633 be_gas_emit_decls(isa->base.main_env);
1635 pmap_destroy(isa->regs_16bit);
1636 pmap_destroy(isa->regs_8bit);
1637 pmap_destroy(isa->regs_8bit_high);
1638 pmap_destroy(isa->tv_ent);
1639 pmap_destroy(isa->types);
1642 obstack_free(isa->name_obst, NULL);
1652 * Return the number of register classes for this architecture.
1653 * We report always these:
1654 * - the general purpose registers
1655 * - the SSE floating point register set
1656 * - the virtual floating point registers
1657 * - the SSE vector register set
1659 static unsigned ia32_get_n_reg_class(void)
1665 * Return the register class for index i.
1667 static const arch_register_class_t *ia32_get_reg_class(unsigned i)
1669 assert(i < N_CLASSES);
1670 return &ia32_reg_classes[i];
1674 * Get the register class which shall be used to store a value of a given mode.
1675 * @param self The this pointer.
1676 * @param mode The mode in question.
1677 * @return A register class which can hold values of the given mode.
1679 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1681 if (mode_is_float(mode)) {
1682 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1685 return &ia32_reg_classes[CLASS_ia32_gp];
1689 * Returns the register for parameter nr.
1691 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1692 const ir_mode *mode)
1694 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1695 &ia32_gp_regs[REG_ECX],
1696 &ia32_gp_regs[REG_EDX],
1699 static const unsigned MAXNUM_GPREG_ARGS = 3;
1701 static const arch_register_t *gpreg_param_reg_regparam[] = {
1702 &ia32_gp_regs[REG_EAX],
1703 &ia32_gp_regs[REG_EDX],
1704 &ia32_gp_regs[REG_ECX]
1707 static const arch_register_t *gpreg_param_reg_this[] = {
1708 &ia32_gp_regs[REG_ECX],
1713 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1714 &ia32_xmm_regs[REG_XMM0],
1715 &ia32_xmm_regs[REG_XMM1],
1716 &ia32_xmm_regs[REG_XMM2],
1717 &ia32_xmm_regs[REG_XMM3],
1718 &ia32_xmm_regs[REG_XMM4],
1719 &ia32_xmm_regs[REG_XMM5],
1720 &ia32_xmm_regs[REG_XMM6],
1721 &ia32_xmm_regs[REG_XMM7]
1724 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1725 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1727 static const unsigned MAXNUM_SSE_ARGS = 8;
1729 if ((cc & cc_this_call) && nr == 0)
1730 return gpreg_param_reg_this[0];
1732 if (! (cc & cc_reg_param))
1735 if (mode_is_float(mode)) {
1736 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1738 if (nr >= MAXNUM_SSE_ARGS)
1741 if (cc & cc_this_call) {
1742 return fpreg_sse_param_reg_this[nr];
1744 return fpreg_sse_param_reg_std[nr];
1745 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1746 unsigned num_regparam;
1748 if (get_mode_size_bits(mode) > 32)
1751 if (nr >= MAXNUM_GPREG_ARGS)
1754 if (cc & cc_this_call) {
1755 return gpreg_param_reg_this[nr];
1757 num_regparam = cc & ~cc_bits;
1758 if (num_regparam == 0) {
1759 /* default fastcall */
1760 return gpreg_param_reg_fastcall[nr];
1762 if (nr < num_regparam)
1763 return gpreg_param_reg_regparam[nr];
1767 panic("unknown argument mode");
1771 * Get the ABI restrictions for procedure calls.
1772 * @param self The this pointer.
1773 * @param method_type The type of the method (procedure) in question.
1774 * @param abi The abi object to be modified
1776 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1784 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1788 /* set abi flags for calls */
1789 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1790 call_flags.bits.store_args_sequential = 0;
1791 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1792 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1793 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1795 /* set parameter passing style */
1796 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1798 cc = get_method_calling_convention(method_type);
1799 if (get_method_variadicity(method_type) == variadicity_variadic) {
1800 /* pass all parameters of a variadic function on the stack */
1801 cc = cc_cdecl_set | (cc & cc_this_call);
1803 if (get_method_additional_properties(method_type) & mtp_property_private &&
1804 ia32_cg_config.optimize_cc) {
1805 /* set the fast calling conventions (allowing up to 3) */
1806 cc = SET_FASTCALL(cc) | 3;
1810 /* we have to pop the shadow parameter ourself for compound calls */
1811 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1812 && !(cc & cc_reg_param)) {
1813 pop_amount += get_mode_size_bytes(mode_P_data);
1816 n = get_method_n_params(method_type);
1817 for (i = regnum = 0; i < n; i++) {
1819 const arch_register_t *reg = NULL;
1821 tp = get_method_param_type(method_type, i);
1822 mode = get_type_mode(tp);
1824 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1827 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1830 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1831 * movl has a shorter opcode than mov[sz][bw]l */
1832 ir_mode *load_mode = mode;
1835 unsigned size = get_mode_size_bytes(mode);
1837 if (cc & cc_callee_clear_stk) {
1838 pop_amount += (size + 3U) & ~3U;
1841 if (size < 4) load_mode = mode_Iu;
1844 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1848 be_abi_call_set_pop(abi, pop_amount);
1850 /* set return registers */
1851 n = get_method_n_ress(method_type);
1853 assert(n <= 2 && "more than two results not supported");
1855 /* In case of 64bit returns, we will have two 32bit values */
1857 tp = get_method_res_type(method_type, 0);
1858 mode = get_type_mode(tp);
1860 assert(!mode_is_float(mode) && "two FP results not supported");
1862 tp = get_method_res_type(method_type, 1);
1863 mode = get_type_mode(tp);
1865 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1867 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX], ABI_CONTEXT_BOTH);
1868 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX], ABI_CONTEXT_BOTH);
1871 const arch_register_t *reg;
1873 tp = get_method_res_type(method_type, 0);
1874 assert(is_atomic_type(tp));
1875 mode = get_type_mode(tp);
1877 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1879 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1883 static int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1887 if (!is_ia32_irn(irn)) {
1891 if (is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1892 || is_ia32_ChangeCW(irn) || is_ia32_Immediate(irn))
1899 * Initializes the code generator interface.
1901 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1904 return &ia32_code_gen_if;
1908 * Returns the estimated execution time of an ia32 irn.
1910 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn)
1913 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
1916 list_sched_selector_t ia32_sched_selector;
1919 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1921 static const list_sched_selector_t *ia32_get_list_sched_selector(
1922 const void *self, list_sched_selector_t *selector)
1925 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1926 ia32_sched_selector.exectime = ia32_sched_exectime;
1927 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1928 return &ia32_sched_selector;
1931 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1938 * Returns the necessary byte alignment for storing a register of given class.
1940 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1942 ir_mode *mode = arch_register_class_mode(cls);
1943 int bytes = get_mode_size_bytes(mode);
1945 if (mode_is_float(mode) && bytes > 8)
1950 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1953 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1954 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1955 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1958 static const be_execution_unit_t *_allowed_units_GP[] = {
1959 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1960 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1961 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1962 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1963 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1964 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1965 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1968 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1969 &be_machine_execution_units_DUMMY[0],
1972 static const be_execution_unit_t **_units_callret[] = {
1973 _allowed_units_BRANCH,
1976 static const be_execution_unit_t **_units_other[] = {
1980 static const be_execution_unit_t **_units_dummy[] = {
1981 _allowed_units_DUMMY,
1984 const be_execution_unit_t ***ret;
1986 if (is_ia32_irn(irn)) {
1987 ret = get_ia32_exec_units(irn);
1988 } else if (is_be_node(irn)) {
1989 if (be_is_Return(irn)) {
1990 ret = _units_callret;
1991 } else if (be_is_Barrier(irn)) {
2005 * Return the abstract ia32 machine.
2007 static const be_machine_t *ia32_get_machine(const void *self)
2009 const ia32_isa_t *isa = self;
2014 * Return irp irgs in the desired order.
2016 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2023 static void ia32_mark_remat(ir_node *node)
2025 if (is_ia32_irn(node)) {
2026 set_ia32_is_remat(node);
2031 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
2033 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
2043 cmp = get_Proj_pred(sel);
2047 cmp_l = get_Cmp_left(cmp);
2048 cmp_r = get_Cmp_right(cmp);
2049 if (!mode_is_float(get_irn_mode(cmp_l)))
2052 /* check for min/max. They're defined as (C-Semantik):
2053 * min(a, b) = a < b ? a : b
2054 * or min(a, b) = a <= b ? a : b
2055 * max(a, b) = a > b ? a : b
2056 * or max(a, b) = a >= b ? a : b
2057 * (Note we only handle float min/max here)
2059 pnc = get_Proj_proj(sel);
2064 if (cmp_l == mux_true && cmp_r == mux_false)
2070 if (cmp_l == mux_true && cmp_r == mux_false)
2076 if (cmp_l == mux_false && cmp_r == mux_true)
2082 if (cmp_l == mux_false && cmp_r == mux_true)
2093 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
2095 ir_mode *mode = get_irn_mode(mux_true);
2098 if (!mode_is_int(mode) && !mode_is_reference(mode)
2102 if (is_Const(mux_true) && is_Const(mux_false)) {
2103 /* we can create a set plus up two 3 instructions for any combination of constants */
2110 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
2115 if (!mode_is_float(get_irn_mode(mux_true)))
2118 return is_Const(mux_true) && is_Const(mux_false);
2121 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
2134 cmp = get_Proj_pred(sel);
2138 mode = get_irn_mode(mux_true);
2139 if (mode_is_signed(mode) || mode_is_float(mode))
2142 pn = get_Proj_proj(sel);
2143 cmp_left = get_Cmp_left(cmp);
2144 cmp_right = get_Cmp_right(cmp);
2146 /* "move" zero constant to false input */
2147 if (is_Const(mux_true) && is_Const_null(mux_true)) {
2148 ir_node *tmp = mux_false;
2149 mux_false = mux_true;
2151 pn = get_negated_pnc(pn, mode);
2153 if (!is_Const(mux_false) || !is_Const_null(mux_false))
2155 if (!is_Sub(mux_true))
2157 sub_left = get_Sub_left(mux_true);
2158 sub_right = get_Sub_right(mux_true);
2160 /* Mux(a >=u b, 0, a-b) */
2161 if ((pn == pn_Cmp_Gt || pn == pn_Cmp_Ge)
2162 && sub_left == cmp_left && sub_right == cmp_right)
2164 /* Mux(a <=u b, 0, b-a) */
2165 if ((pn == pn_Cmp_Lt || pn == pn_Cmp_Le)
2166 && sub_left == cmp_right && sub_right == cmp_left)
2172 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
2177 /* we can handle Set for all modes and compares */
2178 if (mux_is_set(sel, mux_true, mux_false))
2180 /* SSE has own min/max operations */
2181 if (ia32_cg_config.use_sse2
2182 && mux_is_float_min_max(sel, mux_true, mux_false))
2184 /* we can handle Mux(?, Const[f], Const[f]) */
2185 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
2186 #ifdef FIRM_GRGEN_BE
2187 /* well, some code selectors can't handle it */
2188 if (be_transformer != TRANSFORMER_PBQP
2189 || be_transformer != TRANSFORMER_RAND)
2196 /* no support for 64bit inputs to cmov */
2197 mode = get_irn_mode(mux_true);
2198 if (get_mode_size_bits(mode) > 32)
2200 /* we can handle Abs for all modes and compares (except 64bit) */
2201 if (be_mux_is_abs(sel, mux_true, mux_false) != 0)
2203 /* we can't handle MuxF yet */
2204 if (mode_is_float(mode))
2207 if (mux_is_doz(sel, mux_true, mux_false))
2210 /* Check Cmp before the node */
2212 ir_node *cmp = get_Proj_pred(sel);
2214 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(cmp));
2216 /* we can't handle 64bit compares */
2217 if (get_mode_size_bits(cmp_mode) > 32)
2220 /* we can't handle float compares */
2221 if (mode_is_float(cmp_mode))
2226 /* did we disable cmov generation? */
2227 if (!ia32_cg_config.use_cmov)
2230 /* we can use a cmov */
2234 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2238 /* we already added all our simple flags to the flags modifier list in
2239 * init, so this flag we don't know. */
2240 return ASM_CONSTRAINT_FLAG_INVALID;
2243 static int ia32_is_valid_clobber(const char *clobber)
2245 return ia32_get_clobber_register(clobber) != NULL;
2248 static void ia32_lower_for_target(void)
2250 int n_irgs = get_irp_n_irgs();
2252 lower_mode_b_config_t lower_mode_b_config = {
2253 mode_Iu, /* lowered mode */
2254 mode_Bu, /* preferred mode for set */
2255 0, /* don't lower direct compares */
2258 /* perform doubleword lowering */
2259 lwrdw_param_t lower_dw_params = {
2260 1, /* little endian */
2261 64, /* doubleword size */
2262 ia32_create_intrinsic_fkt,
2265 lower_dw_ops(&lower_dw_params);
2267 /* lower for mode_b stuff */
2268 for (i = 0; i < n_irgs; ++i) {
2269 ir_graph *irg = get_irp_irg(i);
2270 ir_lower_mode_b(irg, &lower_mode_b_config);
2275 * Create the trampoline code.
2277 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2279 ir_node *st, *p = trampoline;
2280 ir_mode *mode = get_irn_mode(p);
2283 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xb9), 0);
2284 mem = new_r_Proj(st, mode_M, pn_Store_M);
2285 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2286 st = new_r_Store(block, mem, p, env, 0);
2287 mem = new_r_Proj(st, mode_M, pn_Store_M);
2288 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2290 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xe9), 0);
2291 mem = new_r_Proj(st, mode_M, pn_Store_M);
2292 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2293 st = new_r_Store(block, mem, p, callee, 0);
2294 mem = new_r_Proj(st, mode_M, pn_Store_M);
2295 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2301 * Returns the libFirm configuration parameter for this backend.
2303 static const backend_params *ia32_get_libfirm_params(void)
2305 static const ir_settings_arch_dep_t ad = {
2306 1, /* also use subs */
2307 4, /* maximum shifts */
2308 31, /* maximum shift amount */
2309 ia32_evaluate_insn, /* evaluate the instruction sequence */
2311 1, /* allow Mulhs */
2312 1, /* allow Mulus */
2313 32, /* Mulh allowed up to 32 bit */
2315 static backend_params p = {
2316 1, /* support inline assembly */
2317 1, /* support Rotl nodes */
2318 0, /* little endian */
2319 ia32_lower_for_target,
2320 NULL, /* will be set later */
2321 ia32_is_mux_allowed,
2322 NULL, /* float arithmetic mode, will be set below */
2323 12, /* size of trampoline code */
2324 4, /* alignment of trampoline code */
2325 ia32_create_trampoline_fkt,
2326 4 /* alignment of stack parameter */
2329 ia32_setup_cg_config();
2331 /* doesn't really belong here, but this is the earliest place the backend
2333 init_asm_constraints();
2336 if (! ia32_cg_config.use_sse2)
2337 p.mode_float_arithmetic = mode_E;
2341 static const lc_opt_enum_int_items_t gas_items[] = {
2342 { "elf", OBJECT_FILE_FORMAT_ELF },
2343 { "mingw", OBJECT_FILE_FORMAT_COFF },
2344 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2348 static lc_opt_enum_int_var_t gas_var = {
2349 (int*) &be_gas_object_file_format, gas_items
2352 #ifdef FIRM_GRGEN_BE
2353 static const lc_opt_enum_int_items_t transformer_items[] = {
2354 { "default", TRANSFORMER_DEFAULT },
2355 { "pbqp", TRANSFORMER_PBQP },
2356 { "random", TRANSFORMER_RAND },
2360 static lc_opt_enum_int_var_t transformer_var = {
2361 (int*)&be_transformer, transformer_items
2365 static const lc_opt_table_entry_t ia32_options[] = {
2366 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2367 #ifdef FIRM_GRGEN_BE
2368 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2370 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2371 &ia32_isa_template.base.stack_alignment),
2375 const arch_isa_if_t ia32_isa_if = {
2378 ia32_handle_intrinsics,
2379 ia32_get_n_reg_class,
2381 ia32_get_reg_class_for_mode,
2383 ia32_get_code_generator_if,
2384 ia32_get_list_sched_selector,
2385 ia32_get_ilp_sched_selector,
2386 ia32_get_reg_class_alignment,
2387 ia32_get_libfirm_params,
2388 ia32_get_allowed_execution_units,
2392 ia32_parse_asm_constraint,
2393 ia32_is_valid_clobber
2396 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
2397 void be_init_arch_ia32(void)
2399 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2400 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2402 lc_opt_add_table(ia32_grp, ia32_options);
2403 be_register_isa_if("ia32", &ia32_isa_if);
2405 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2407 ia32_init_emitter();
2409 ia32_init_optimize();
2410 ia32_init_transform();
2412 ia32_init_architecture();