2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
28 #include "lc_opts_enum.h"
36 #include "iredges_t.h"
49 #include "iroptimize.h"
50 #include "instrument.h"
53 #include "lower_calls.h"
54 #include "lower_mode_b.h"
55 #include "lower_softfloat.h"
56 #include "firmstat_t.h"
65 #include "beblocksched.h"
66 #include "bespillutil.h"
67 #include "bespillslots.h"
72 #include "betranshlp.h"
73 #include "belistsched.h"
74 #include "beabihelper.h"
77 #include "bearch_ia32_t.h"
79 #include "ia32_new_nodes.h"
80 #include "gen_ia32_regalloc_if.h"
81 #include "ia32_common_transform.h"
82 #include "ia32_transform.h"
83 #include "ia32_emitter.h"
84 #include "ia32_optimize.h"
86 #include "ia32_dbg_stat.h"
87 #include "ia32_finish.h"
89 #include "ia32_architecture.h"
92 #include "ia32_pbqp_transform.h"
94 transformer_t be_transformer = TRANSFORMER_DEFAULT;
97 ir_mode *ia32_mode_fpcw;
101 /** The current omit-fp state */
102 static ir_type *omit_fp_between_type = NULL;
103 static ir_type *between_type = NULL;
104 static ir_entity *old_bp_ent = NULL;
105 static ir_entity *ret_addr_ent = NULL;
106 static ir_entity *omit_fp_ret_addr_ent = NULL;
109 * The environment for the intrinsic mapping.
111 static ia32_intrinsic_env_t intrinsic_env = {
113 NULL, /* the irg, these entities belong to */
114 NULL, /* entity for __divdi3 library call */
115 NULL, /* entity for __moddi3 library call */
116 NULL, /* entity for __udivdi3 library call */
117 NULL, /* entity for __umoddi3 library call */
121 typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
124 * Used to create per-graph unique pseudo nodes.
126 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
127 create_const_node_func func,
128 const arch_register_t* reg)
130 ir_node *block, *res;
135 block = get_irg_start_block(irg);
136 res = func(NULL, block);
137 arch_set_irn_register(res, reg);
143 /* Creates the unique per irg GP NoReg node. */
144 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
146 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
147 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
148 &ia32_registers[REG_GP_NOREG]);
151 ir_node *ia32_new_NoReg_fp(ir_graph *irg)
153 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
154 return create_const(irg, &irg_data->noreg_fp, new_bd_ia32_NoReg_FP,
155 &ia32_registers[REG_FP_NOREG]);
158 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
160 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
161 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
162 &ia32_registers[REG_XMM_NOREG]);
165 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
167 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
168 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
169 &ia32_registers[REG_FPCW]);
174 * Returns the admissible noreg register node for input register pos of node irn.
176 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
178 ir_graph *irg = get_irn_irg(irn);
179 const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
181 assert(req != NULL && "Missing register requirements");
182 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
183 return ia32_new_NoReg_gp(irg);
185 if (ia32_cg_config.use_sse2) {
186 return ia32_new_NoReg_xmm(irg);
188 return ia32_new_NoReg_fp(irg);
192 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
194 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
197 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
199 if (is_be_node(node))
200 be_node_set_frame_entity(node, entity);
202 set_ia32_frame_ent(node, entity);
205 static void ia32_set_frame_offset(ir_node *irn, int bias)
207 if (get_ia32_frame_ent(irn) == NULL)
210 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
211 ir_graph *irg = get_irn_irg(irn);
212 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
213 if (layout->sp_relative) {
214 /* Pop nodes modify the stack pointer before calculating the
215 * destination address, so fix this here
220 add_ia32_am_offs_int(irn, bias);
223 static int ia32_get_sp_bias(const ir_node *node)
225 if (is_ia32_Call(node))
226 return -(int)get_ia32_call_attr_const(node)->pop;
228 if (is_ia32_Push(node))
231 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
234 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
235 return SP_BIAS_RESET;
242 * Build the between type and entities if not already build.
244 static void ia32_build_between_type(void)
246 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
247 if (between_type == NULL) {
248 ir_type *old_bp_type = new_type_primitive(mode_Iu);
249 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
251 between_type = new_type_struct(IDENT("ia32_between_type"));
252 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
253 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
255 set_entity_offset(old_bp_ent, 0);
256 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
257 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
258 set_type_state(between_type, layout_fixed);
260 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
261 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
263 set_entity_offset(omit_fp_ret_addr_ent, 0);
264 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
265 set_type_state(omit_fp_between_type, layout_fixed);
271 * Produces the type which sits between the stack args and the locals on the stack.
272 * it will contain the return address and space to store the old base pointer.
273 * @return The Firm type modeling the ABI between type.
275 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
277 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
278 ia32_build_between_type();
279 return layout->sp_relative ? omit_fp_between_type : between_type;
283 * Return the stack entity that contains the return address.
285 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
287 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
288 ia32_build_between_type();
289 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
293 * Return the stack entity that contains the frame address.
295 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
297 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
298 ia32_build_between_type();
299 return layout->sp_relative ? NULL : old_bp_ent;
303 * Get the estimated cycle count for @p irn.
305 * @param self The this pointer.
306 * @param irn The node.
308 * @return The estimated cycle count for this operation
310 static int ia32_get_op_estimated_cost(const ir_node *irn)
313 ia32_op_type_t op_tp;
317 if (!is_ia32_irn(irn))
320 assert(is_ia32_irn(irn));
322 cost = get_ia32_latency(irn);
323 op_tp = get_ia32_op_type(irn);
325 if (is_ia32_CopyB(irn)) {
328 else if (is_ia32_CopyB_i(irn)) {
329 int size = get_ia32_copyb_size(irn);
330 cost = 20 + (int)ceil((4/3) * size);
332 /* in case of address mode operations add additional cycles */
333 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
335 In case of stack access and access to fixed addresses add 5 cycles
336 (we assume they are in cache), other memory operations cost 20
339 if (is_ia32_use_frame(irn) || (
340 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
341 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
352 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
354 if (mode_is_float(mode))
361 * Get the mode that should be used for spilling value node
363 static ir_mode *get_spill_mode(const ir_node *node)
365 ir_mode *mode = get_irn_mode(node);
366 return get_spill_mode_mode(mode);
370 * Checks whether an addressmode reload for a node with mode mode is compatible
371 * with a spillslot of mode spill_mode
373 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
375 return !mode_is_float(mode) || mode == spillmode;
379 * Check if irn can load its operand at position i from memory (source addressmode).
380 * @param irn The irn to be checked
381 * @param i The operands position
382 * @return Non-Zero if operand can be loaded
384 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
386 ir_node *op = get_irn_n(irn, i);
387 const ir_mode *mode = get_irn_mode(op);
388 const ir_mode *spillmode = get_spill_mode(op);
390 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
391 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
392 !ia32_is_spillmode_compatible(mode, spillmode) ||
393 is_ia32_use_frame(irn)) /* must not already use frame */
396 switch (get_ia32_am_support(irn)) {
401 if (i != n_ia32_unary_op)
407 case n_ia32_binary_left: {
408 if (!is_ia32_commutative(irn))
411 /* we can't swap left/right for limited registers
412 * (As this (currently) breaks constraint handling copies) */
413 arch_register_req_t const *const req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
414 if (arch_register_req_is(req, limited))
419 case n_ia32_binary_right:
428 panic("Unknown AM type");
431 /* HACK: must not already use "real" memory.
432 * This can happen for Call and Div */
433 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
439 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
443 ir_mode *dest_op_mode;
445 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
447 set_ia32_op_type(irn, ia32_AddrModeS);
449 load_mode = get_irn_mode(get_irn_n(irn, i));
450 dest_op_mode = get_ia32_ls_mode(irn);
451 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
452 set_ia32_ls_mode(irn, load_mode);
454 set_ia32_use_frame(irn);
455 set_ia32_need_stackent(irn);
457 if (i == n_ia32_binary_left &&
458 get_ia32_am_support(irn) == ia32_am_binary &&
459 /* immediates are only allowed on the right side */
460 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
461 ia32_swap_left_right(irn);
462 i = n_ia32_binary_right;
465 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
467 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
468 set_irn_n(irn, n_ia32_mem, spill);
469 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
470 set_ia32_is_reload(irn);
473 static const be_abi_callbacks_t ia32_abi_callbacks = {
474 ia32_abi_get_between_type,
477 /* register allocator interface */
478 static const arch_irn_ops_t ia32_irn_ops = {
479 ia32_get_frame_entity,
480 ia32_set_frame_offset,
482 ia32_get_op_estimated_cost,
483 ia32_possible_memory_operand,
484 ia32_perform_memory_operand,
487 static int gprof = 0;
489 static void ia32_before_abi(ir_graph *irg)
492 static ir_entity *mcount = NULL;
493 if (mcount == NULL) {
494 ir_type *tp = new_type_method(0, 0);
495 ident *id = new_id_from_str("mcount");
496 mcount = new_entity(get_glob_type(), id, tp);
497 /* FIXME: enter the right ld_ident here */
498 set_entity_ld_ident(mcount, get_entity_ident(mcount));
499 set_entity_visibility(mcount, ir_visibility_external);
501 instrument_initcall(irg, mcount);
506 * Transforms the standard firm graph into
509 static void ia32_prepare_graph(ir_graph *irg)
511 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
514 switch (be_transformer) {
515 case TRANSFORMER_DEFAULT:
516 /* transform remaining nodes into assembler instructions */
517 ia32_transform_graph(irg);
520 case TRANSFORMER_PBQP:
521 case TRANSFORMER_RAND:
522 /* transform nodes into assembler instructions by PBQP magic */
523 ia32_transform_graph_by_pbqp(irg);
527 panic("invalid transformer");
530 ia32_transform_graph(irg);
533 /* do local optimizations (mainly CSE) */
534 optimize_graph_df(irg);
535 /* backend code expects that outedges are always enabled */
539 dump_ir_graph(irg, "transformed");
541 /* optimize address mode */
542 ia32_optimize_graph(irg);
544 /* do code placement, to optimize the position of constants */
546 /* backend code expects that outedges are always enabled */
550 dump_ir_graph(irg, "place");
553 ir_node *ia32_turn_back_am(ir_node *node)
555 dbg_info *dbgi = get_irn_dbg_info(node);
556 ir_graph *irg = get_irn_irg(node);
557 ir_node *block = get_nodes_block(node);
558 ir_node *base = get_irn_n(node, n_ia32_base);
559 ir_node *idx = get_irn_n(node, n_ia32_index);
560 ir_node *mem = get_irn_n(node, n_ia32_mem);
563 ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
564 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
566 ia32_copy_am_attrs(load, node);
567 if (is_ia32_is_reload(node))
568 set_ia32_is_reload(load);
569 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
571 switch (get_ia32_am_support(node)) {
573 set_irn_n(node, n_ia32_unary_op, load_res);
577 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
578 set_irn_n(node, n_ia32_binary_left, load_res);
580 set_irn_n(node, n_ia32_binary_right, load_res);
585 panic("Unknown AM type");
587 noreg = ia32_new_NoReg_gp(irg);
588 set_irn_n(node, n_ia32_base, noreg);
589 set_irn_n(node, n_ia32_index, noreg);
590 set_ia32_am_offs_int(node, 0);
591 set_ia32_am_sc(node, NULL);
592 set_ia32_am_scale(node, 0);
593 clear_ia32_am_sc_sign(node);
595 /* rewire mem-proj */
596 if (get_irn_mode(node) == mode_T) {
597 foreach_out_edge(node, edge) {
598 ir_node *out = get_edge_src_irn(edge);
599 if (get_irn_mode(out) == mode_M) {
600 set_Proj_pred(out, load);
601 set_Proj_proj(out, pn_ia32_Load_M);
607 set_ia32_op_type(node, ia32_Normal);
608 if (sched_is_scheduled(node))
609 sched_add_before(node, load);
614 static ir_node *flags_remat(ir_node *node, ir_node *after)
616 /* we should turn back source address mode when rematerializing nodes */
621 if (is_Block(after)) {
624 block = get_nodes_block(after);
627 type = get_ia32_op_type(node);
630 ia32_turn_back_am(node);
634 /* TODO implement this later... */
635 panic("found DestAM with flag user %+F this should not happen", node);
637 default: assert(type == ia32_Normal); break;
640 copy = exact_copy(node);
641 set_nodes_block(copy, block);
642 sched_add_after(after, copy);
648 * Called before the register allocator.
650 static void ia32_before_ra(ir_graph *irg)
652 /* setup fpu rounding modes */
653 ia32_setup_fpu_mode(irg);
656 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
659 be_add_missing_keeps(irg);
664 * Transforms a be_Reload into a ia32 Load.
666 static void transform_to_Load(ir_node *node)
668 ir_graph *irg = get_irn_irg(node);
669 dbg_info *dbgi = get_irn_dbg_info(node);
670 ir_node *block = get_nodes_block(node);
671 ir_entity *ent = be_get_frame_entity(node);
672 ir_mode *mode = get_irn_mode(node);
673 ir_mode *spillmode = get_spill_mode(node);
674 ir_node *noreg = ia32_new_NoReg_gp(irg);
675 ir_node *sched_point = NULL;
676 ir_node *ptr = get_irg_frame(irg);
677 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
678 ir_node *new_op, *proj;
679 const arch_register_t *reg;
681 if (sched_is_scheduled(node)) {
682 sched_point = sched_prev(node);
685 if (mode_is_float(spillmode)) {
686 if (ia32_cg_config.use_sse2)
687 new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
689 new_op = new_bd_ia32_fld(dbgi, block, ptr, noreg, mem, spillmode);
691 else if (get_mode_size_bits(spillmode) == 128) {
692 /* Reload 128 bit SSE registers */
693 new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
696 new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
698 set_ia32_op_type(new_op, ia32_AddrModeS);
699 set_ia32_ls_mode(new_op, spillmode);
700 set_ia32_frame_ent(new_op, ent);
701 set_ia32_use_frame(new_op);
702 set_ia32_is_reload(new_op);
704 DBG_OPT_RELOAD2LD(node, new_op);
706 proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
709 sched_add_after(sched_point, new_op);
713 /* copy the register from the old node to the new Load */
714 reg = arch_get_irn_register(node);
715 arch_set_irn_register(proj, reg);
717 SET_IA32_ORIG_NODE(new_op, node);
719 exchange(node, proj);
723 * Transforms a be_Spill node into a ia32 Store.
725 static void transform_to_Store(ir_node *node)
727 ir_graph *irg = get_irn_irg(node);
728 dbg_info *dbgi = get_irn_dbg_info(node);
729 ir_node *block = get_nodes_block(node);
730 ir_entity *ent = be_get_frame_entity(node);
731 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
732 ir_mode *mode = get_spill_mode(spillval);
733 ir_node *noreg = ia32_new_NoReg_gp(irg);
734 ir_node *nomem = get_irg_no_mem(irg);
735 ir_node *ptr = get_irg_frame(irg);
736 ir_node *val = get_irn_n(node, n_be_Spill_val);
739 ir_node *sched_point = NULL;
741 if (sched_is_scheduled(node)) {
742 sched_point = sched_prev(node);
745 if (mode_is_float(mode)) {
746 if (ia32_cg_config.use_sse2) {
747 store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
748 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
750 store = new_bd_ia32_fst(dbgi, block, ptr, noreg, nomem, val, mode);
751 res = new_r_Proj(store, mode_M, pn_ia32_fst_M);
753 } else if (get_mode_size_bits(mode) == 128) {
754 /* Spill 128 bit SSE registers */
755 store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
756 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
757 } else if (get_mode_size_bits(mode) == 8) {
758 store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
759 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
761 store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
762 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
765 set_ia32_op_type(store, ia32_AddrModeD);
766 set_ia32_ls_mode(store, mode);
767 set_ia32_frame_ent(store, ent);
768 set_ia32_use_frame(store);
769 set_ia32_is_spill(store);
770 SET_IA32_ORIG_NODE(store, node);
771 DBG_OPT_SPILL2ST(node, store);
774 sched_add_after(sched_point, store);
781 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
783 dbg_info *dbgi = get_irn_dbg_info(node);
784 ir_node *block = get_nodes_block(node);
785 ir_graph *irg = get_irn_irg(node);
786 ir_node *noreg = ia32_new_NoReg_gp(irg);
787 ir_node *frame = get_irg_frame(irg);
789 ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
791 set_ia32_frame_ent(push, ent);
792 set_ia32_use_frame(push);
793 set_ia32_op_type(push, ia32_AddrModeS);
794 set_ia32_ls_mode(push, mode_Is);
795 set_ia32_is_spill(push);
797 sched_add_before(schedpoint, push);
801 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
803 dbg_info *dbgi = get_irn_dbg_info(node);
804 ir_node *block = get_nodes_block(node);
805 ir_graph *irg = get_irn_irg(node);
806 ir_node *noreg = ia32_new_NoReg_gp(irg);
807 ir_node *frame = get_irg_frame(irg);
809 ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
810 get_irg_no_mem(irg), sp);
812 set_ia32_frame_ent(pop, ent);
813 set_ia32_use_frame(pop);
814 set_ia32_op_type(pop, ia32_AddrModeD);
815 set_ia32_ls_mode(pop, mode_Is);
816 set_ia32_is_reload(pop);
818 sched_add_before(schedpoint, pop);
823 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
825 dbg_info *dbgi = get_irn_dbg_info(node);
826 ir_mode *spmode = mode_Iu;
827 const arch_register_t *spreg = &ia32_registers[REG_ESP];
830 sp = new_rd_Proj(dbgi, pred, spmode, pos);
831 arch_set_irn_register(sp, spreg);
837 * Transform MemPerm, currently we do this the ugly way and produce
838 * push/pop into/from memory cascades. This is possible without using
841 static void transform_MemPerm(ir_node *node)
843 ir_node *block = get_nodes_block(node);
844 ir_graph *irg = get_irn_irg(node);
845 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
846 int arity = be_get_MemPerm_entity_arity(node);
847 ir_node **pops = ALLOCAN(ir_node*, arity);
853 for (i = 0; i < arity; ++i) {
854 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
855 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
856 ir_type *enttype = get_entity_type(inent);
857 unsigned entsize = get_type_size_bytes(enttype);
858 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
859 ir_node *mem = get_irn_n(node, i + 1);
862 /* work around cases where entities have different sizes */
863 if (entsize2 < entsize)
865 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
867 push = create_push(node, node, sp, mem, inent);
868 sp = create_spproj(node, push, pn_ia32_Push_stack);
870 /* add another push after the first one */
871 push = create_push(node, node, sp, mem, inent);
872 add_ia32_am_offs_int(push, 4);
873 sp = create_spproj(node, push, pn_ia32_Push_stack);
876 set_irn_n(node, i, new_r_Bad(irg, mode_X));
880 for (i = arity - 1; i >= 0; --i) {
881 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
882 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
883 ir_type *enttype = get_entity_type(outent);
884 unsigned entsize = get_type_size_bytes(enttype);
885 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
888 /* work around cases where entities have different sizes */
889 if (entsize2 < entsize)
891 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
893 pop = create_pop(node, node, sp, outent);
894 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
896 add_ia32_am_offs_int(pop, 4);
898 /* add another pop after the first one */
899 pop = create_pop(node, node, sp, outent);
900 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
907 keep = be_new_Keep(block, 1, in);
908 sched_add_before(node, keep);
910 /* exchange memprojs */
911 foreach_out_edge_safe(node, edge) {
912 ir_node *proj = get_edge_src_irn(edge);
913 int p = get_Proj_proj(proj);
917 set_Proj_pred(proj, pops[p]);
918 set_Proj_proj(proj, pn_ia32_Pop_M);
927 * Block-Walker: Calls the transform functions Spill and Reload.
929 static void ia32_after_ra_walker(ir_node *block, void *env)
931 ir_node *node, *prev;
934 /* beware: the schedule is changed here */
935 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
936 prev = sched_prev(node);
938 if (be_is_Reload(node)) {
939 transform_to_Load(node);
940 } else if (be_is_Spill(node)) {
941 transform_to_Store(node);
942 } else if (be_is_MemPerm(node)) {
943 transform_MemPerm(node);
949 * Collects nodes that need frame entities assigned.
951 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
953 be_fec_env_t *env = (be_fec_env_t*)data;
957 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
958 mode = get_spill_mode_mode(get_irn_mode(node));
959 align = get_mode_size_bytes(mode);
960 } else if (is_ia32_irn(node) &&
961 get_ia32_frame_ent(node) == NULL &&
962 is_ia32_use_frame(node)) {
963 if (is_ia32_need_stackent(node))
966 switch (get_ia32_irn_opcode(node)) {
968 case iro_ia32_Load: {
969 const ia32_attr_t *attr = get_ia32_attr_const(node);
971 if (attr->data.need_32bit_stackent) {
973 } else if (attr->data.need_64bit_stackent) {
976 mode = get_ia32_ls_mode(node);
977 if (is_ia32_is_reload(node))
978 mode = get_spill_mode_mode(mode);
980 align = get_mode_size_bytes(mode);
986 case iro_ia32_xLoad: {
987 mode = get_ia32_ls_mode(node);
992 case iro_ia32_FldCW: {
993 /* although 2 byte would be enough 4 byte performs best */
1001 panic("unexpected frame user while collection frame entity nodes");
1003 case iro_ia32_FnstCW:
1004 case iro_ia32_Store8Bit:
1005 case iro_ia32_Store:
1008 case iro_ia32_fisttp:
1009 case iro_ia32_xStore:
1010 case iro_ia32_xStoreSimple:
1017 be_node_needs_frame_entity(env, node, mode, align);
1020 static int determine_ebp_input(ir_node *ret)
1022 const arch_register_t *bp = &ia32_registers[REG_EBP];
1023 int arity = get_irn_arity(ret);
1026 for (i = 0; i < arity; ++i) {
1027 ir_node *input = get_irn_n(ret, i);
1028 if (arch_get_irn_register(input) == bp)
1031 panic("no ebp input found at %+F", ret);
1034 static void introduce_epilog(ir_node *ret)
1036 const arch_register_t *sp = &ia32_registers[REG_ESP];
1037 const arch_register_t *bp = &ia32_registers[REG_EBP];
1038 ir_graph *irg = get_irn_irg(ret);
1039 ir_type *frame_type = get_irg_frame_type(irg);
1040 unsigned frame_size = get_type_size_bytes(frame_type);
1041 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1042 ir_node *block = get_nodes_block(ret);
1043 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1044 ir_node *curr_sp = first_sp;
1045 ir_mode *mode_gp = ia32_reg_classes[CLASS_ia32_gp].mode;
1047 if (!layout->sp_relative) {
1048 int n_ebp = determine_ebp_input(ret);
1049 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1050 if (ia32_cg_config.use_leave) {
1051 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1052 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1053 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1054 arch_set_irn_register(curr_bp, bp);
1055 arch_set_irn_register(curr_sp, sp);
1056 sched_add_before(ret, leave);
1059 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1060 /* copy ebp to esp */
1061 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1062 arch_set_irn_register(curr_sp, sp);
1063 sched_add_before(ret, curr_sp);
1066 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1067 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1068 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1069 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1070 arch_set_irn_register(curr_bp, bp);
1071 arch_set_irn_register(curr_sp, sp);
1072 sched_add_before(ret, pop);
1074 set_irn_n(ret, n_be_Return_mem, curr_mem);
1076 set_irn_n(ret, n_ebp, curr_bp);
1078 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1079 sched_add_before(ret, incsp);
1082 set_irn_n(ret, n_be_Return_sp, curr_sp);
1084 /* keep verifier happy... */
1085 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1086 kill_node(first_sp);
1091 * put the Prolog code at the beginning, epilog code before each return
1093 static void introduce_prolog_epilog(ir_graph *irg)
1095 const arch_register_t *sp = &ia32_registers[REG_ESP];
1096 const arch_register_t *bp = &ia32_registers[REG_EBP];
1097 ir_node *start = get_irg_start(irg);
1098 ir_node *block = get_nodes_block(start);
1099 ir_type *frame_type = get_irg_frame_type(irg);
1100 unsigned frame_size = get_type_size_bytes(frame_type);
1101 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1102 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1103 ir_node *curr_sp = initial_sp;
1104 ir_mode *mode_gp = mode_Iu;
1106 if (!layout->sp_relative) {
1108 ir_node *mem = get_irg_initial_mem(irg);
1109 ir_node *noreg = ia32_new_NoReg_gp(irg);
1110 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1111 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, initial_bp, initial_sp);
1114 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1115 arch_set_irn_register(curr_sp, sp);
1116 sched_add_after(start, push);
1118 /* move esp to ebp */
1119 ir_node *const curr_bp = be_new_Copy(block, curr_sp);
1120 sched_add_after(push, curr_bp);
1121 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1122 curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
1123 sched_add_after(curr_bp, curr_sp);
1124 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1125 edges_reroute_except(initial_bp, curr_bp, push);
1127 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1128 edges_reroute_except(initial_sp, incsp, push);
1129 sched_add_after(curr_sp, incsp);
1131 /* make sure the initial IncSP is really used by someone */
1132 if (get_irn_n_edges(incsp) <= 1) {
1133 ir_node *in[] = { incsp };
1134 ir_node *keep = be_new_Keep(block, 1, in);
1135 sched_add_after(incsp, keep);
1138 layout->initial_bias = -4;
1140 ir_node *const incsp = be_new_IncSP(sp, block, initial_sp, frame_size, 0);
1141 edges_reroute_except(initial_sp, incsp, incsp);
1142 sched_add_after(start, incsp);
1145 /* introduce epilog for every return node */
1147 ir_node *end_block = get_irg_end_block(irg);
1148 int arity = get_irn_arity(end_block);
1151 for (i = 0; i < arity; ++i) {
1152 ir_node *ret = get_irn_n(end_block, i);
1153 assert(be_is_Return(ret));
1154 introduce_epilog(ret);
1160 * Last touchups for the graph before emit: x87 simulation to replace the
1161 * virtual with real x87 instructions, creating a block schedule and peephole
1164 static void ia32_finish_graph(ir_graph *irg)
1166 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1167 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1168 bool at_begin = stack_layout->sp_relative ? true : false;
1169 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1171 /* create and coalesce frame entities */
1172 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1173 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1174 be_free_frame_entity_coalescer(fec_env);
1176 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1178 introduce_prolog_epilog(irg);
1180 /* fix stack entity offsets */
1181 be_abi_fix_stack_nodes(irg);
1182 be_abi_fix_stack_bias(irg);
1184 /* fix 2-address code constraints */
1185 ia32_finish_irg(irg);
1187 /* we might have to rewrite x87 virtual registers */
1188 if (irg_data->do_x87_sim) {
1189 ia32_x87_simulate_graph(irg);
1192 /* do peephole optimisations */
1193 ia32_peephole_optimization(irg);
1195 be_remove_dead_nodes_from_schedule(irg);
1197 /* create block schedule, this also removes empty blocks which might
1198 * produce critical edges */
1199 irg_data->blk_sched = be_create_block_schedule(irg);
1203 * Emits the code, closes the output file and frees
1204 * the code generator interface.
1206 static void ia32_emit(ir_graph *irg)
1208 if (ia32_cg_config.emit_machcode) {
1209 ia32_gen_binary_routine(irg);
1211 ia32_gen_routine(irg);
1216 * Returns the node representing the PIC base.
1218 static ir_node *ia32_get_pic_base(ir_graph *irg)
1220 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1222 ir_node *get_eip = irg_data->get_eip;
1223 if (get_eip != NULL)
1226 block = get_irg_start_block(irg);
1227 get_eip = new_bd_ia32_GetEIP(NULL, block);
1228 irg_data->get_eip = get_eip;
1234 * Initializes a IA32 code generator.
1236 static void ia32_init_graph(ir_graph *irg)
1238 struct obstack *obst = be_get_be_obst(irg);
1239 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1241 irg_data->dump = (be_options.dump_flags & DUMP_BE) ? 1 : 0;
1244 /* Linux gprof implementation needs base pointer */
1245 be_options.omit_fp = 0;
1248 be_birg_from_irg(irg)->isa_link = irg_data;
1251 static const tarval_mode_info mo_integer = {
1258 * set the tarval output mode of all integer modes to decimal
1260 static void set_tarval_output_modes(void)
1264 for (i = ir_get_n_modes(); i > 0;) {
1265 ir_mode *mode = ir_get_mode(--i);
1267 if (mode_is_int(mode))
1268 set_tarval_mode_output_option(mode, &mo_integer);
1272 extern const arch_isa_if_t ia32_isa_if;
1274 static void init_asm_constraints(void)
1276 be_init_default_asm_constraint_flags();
1278 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1279 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1280 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1281 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1282 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1283 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1284 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1285 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1286 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1287 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1288 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1289 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1290 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1291 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1292 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1293 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1294 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1295 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1296 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1297 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1299 /* no support for autodecrement/autoincrement */
1300 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1301 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1302 /* no float consts */
1303 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1304 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1305 /* makes no sense on x86 */
1306 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1307 /* no support for sse consts yet */
1308 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1309 /* no support for x87 consts yet */
1310 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1311 /* no support for mmx registers yet */
1312 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1313 /* not available in 32bit mode */
1314 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1315 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1317 /* no code yet to determine register class needed... */
1318 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1322 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1324 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1329 ir_relation relation;
1334 cmp_l = get_Cmp_left(sel);
1335 cmp_r = get_Cmp_right(sel);
1336 if (!mode_is_float(get_irn_mode(cmp_l)))
1339 /* check for min/max. They're defined as (C-Semantik):
1340 * min(a, b) = a < b ? a : b
1341 * or min(a, b) = a <= b ? a : b
1342 * max(a, b) = a > b ? a : b
1343 * or max(a, b) = a >= b ? a : b
1344 * (Note we only handle float min/max here)
1346 relation = get_Cmp_relation(sel);
1348 case ir_relation_greater_equal:
1349 case ir_relation_greater:
1351 if (cmp_l == mux_true && cmp_r == mux_false)
1354 case ir_relation_less_equal:
1355 case ir_relation_less:
1357 if (cmp_l == mux_true && cmp_r == mux_false)
1360 case ir_relation_unordered_greater_equal:
1361 case ir_relation_unordered_greater:
1363 if (cmp_l == mux_false && cmp_r == mux_true)
1366 case ir_relation_unordered_less_equal:
1367 case ir_relation_unordered_less:
1369 if (cmp_l == mux_false && cmp_r == mux_true)
1380 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1382 ir_mode *mode = get_irn_mode(mux_true);
1385 if (!mode_is_int(mode) && !mode_is_reference(mode)
1389 if (is_Const(mux_true) && is_Const(mux_false)) {
1390 /* we can create a set plus up two 3 instructions for any combination
1398 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1403 if (!mode_is_float(get_irn_mode(mux_true)))
1406 return is_Const(mux_true) && is_Const(mux_false);
1409 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1416 ir_relation relation;
1421 mode = get_irn_mode(mux_true);
1422 if (mode_is_signed(mode) || mode_is_float(mode))
1425 relation = get_Cmp_relation(sel);
1426 cmp_left = get_Cmp_left(sel);
1427 cmp_right = get_Cmp_right(sel);
1429 /* "move" zero constant to false input */
1430 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1431 ir_node *tmp = mux_false;
1432 mux_false = mux_true;
1434 relation = get_negated_relation(relation);
1436 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1438 if (!is_Sub(mux_true))
1440 sub_left = get_Sub_left(mux_true);
1441 sub_right = get_Sub_right(mux_true);
1443 /* Mux(a >=u b, 0, a-b) */
1444 if ((relation & ir_relation_greater)
1445 && sub_left == cmp_left && sub_right == cmp_right)
1447 /* Mux(a <=u b, 0, b-a) */
1448 if ((relation & ir_relation_less)
1449 && sub_left == cmp_right && sub_right == cmp_left)
1455 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1460 /* middleend can handle some things */
1461 if (ir_is_optimizable_mux(sel, mux_false, mux_true))
1463 /* we can handle Set for all modes and compares */
1464 if (mux_is_set(sel, mux_true, mux_false))
1466 /* SSE has own min/max operations */
1467 if (ia32_cg_config.use_sse2
1468 && mux_is_float_min_max(sel, mux_true, mux_false))
1470 /* we can handle Mux(?, Const[f], Const[f]) */
1471 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1472 #ifdef FIRM_GRGEN_BE
1473 /* well, some code selectors can't handle it */
1474 if (be_transformer != TRANSFORMER_PBQP
1475 || be_transformer != TRANSFORMER_RAND)
1482 /* no support for 64bit inputs to cmov */
1483 mode = get_irn_mode(mux_true);
1484 if (get_mode_size_bits(mode) > 32)
1486 /* we can handle Abs for all modes and compares (except 64bit) */
1487 if (ir_mux_is_abs(sel, mux_false, mux_true) != 0)
1489 /* we can't handle MuxF yet */
1490 if (mode_is_float(mode))
1493 if (mux_is_doz(sel, mux_true, mux_false))
1496 /* Check Cmp before the node */
1498 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1500 /* we can't handle 64bit compares */
1501 if (get_mode_size_bits(cmp_mode) > 32)
1504 /* we can't handle float compares */
1505 if (mode_is_float(cmp_mode))
1509 /* did we disable cmov generation? */
1510 if (!ia32_cg_config.use_cmov)
1513 /* we can use a cmov */
1518 * Create the trampoline code.
1520 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
1522 ir_graph *const irg = get_irn_irg(block);
1523 ir_node * p = trampoline;
1524 ir_mode *const mode = get_irn_mode(p);
1525 ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
1526 ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
1530 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
1531 mem = new_r_Proj(st, mode_M, pn_Store_M);
1532 p = new_r_Add(block, p, one, mode);
1533 st = new_r_Store(block, mem, p, env, cons_none);
1534 mem = new_r_Proj(st, mode_M, pn_Store_M);
1535 p = new_r_Add(block, p, four, mode);
1537 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
1538 mem = new_r_Proj(st, mode_M, pn_Store_M);
1539 p = new_r_Add(block, p, one, mode);
1540 st = new_r_Store(block, mem, p, callee, cons_none);
1541 mem = new_r_Proj(st, mode_M, pn_Store_M);
1546 static const ir_settings_arch_dep_t ia32_arch_dep = {
1547 1, /* also use subs */
1548 4, /* maximum shifts */
1549 63, /* maximum shift amount */
1550 ia32_evaluate_insn, /* evaluate the instruction sequence */
1552 1, /* allow Mulhs */
1553 1, /* allow Mulus */
1554 32, /* Mulh allowed up to 32 bit */
1556 static backend_params ia32_backend_params = {
1557 1, /* support inline assembly */
1558 1, /* support Rotl nodes */
1559 0, /* little endian */
1560 1, /* modulo shift efficient */
1561 0, /* non-modulo shift not efficient */
1562 &ia32_arch_dep, /* will be set later */
1563 ia32_is_mux_allowed,
1564 32, /* machine_size */
1565 NULL, /* float arithmetic mode, will be set below */
1566 NULL, /* long long type */
1567 NULL, /* unsigned long long type */
1568 NULL, /* long double type */
1569 12, /* size of trampoline code */
1570 4, /* alignment of trampoline code */
1571 ia32_create_trampoline_fkt,
1572 4 /* alignment of stack parameter */
1576 * Initializes the backend ISA.
1578 static void ia32_init(void)
1580 ir_mode *mode_long_long;
1581 ir_mode *mode_unsigned_long_long;
1582 ir_type *type_long_long;
1583 ir_type *type_unsigned_long_long;
1585 ia32_setup_cg_config();
1587 init_asm_constraints();
1589 ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0);
1591 /* note mantissa is 64bit but with explicitely encoded 1 so the really
1592 * usable part as counted by firm is only 63 bits */
1593 ia32_mode_E = new_float_mode("E", irma_x86_extended_float, 15, 63);
1594 ia32_type_E = new_type_primitive(ia32_mode_E);
1595 set_type_size_bytes(ia32_type_E, 12);
1596 set_type_alignment_bytes(ia32_type_E, 4);
1598 mode_long_long = new_int_mode("long long", irma_twos_complement, 64, 1, 64);
1599 type_long_long = new_type_primitive(mode_long_long);
1600 mode_unsigned_long_long
1601 = new_int_mode("unsigned long long", irma_twos_complement, 64, 0, 64);
1602 type_unsigned_long_long = new_type_primitive(mode_unsigned_long_long);
1604 ia32_backend_params.type_long_long = type_long_long;
1605 ia32_backend_params.type_unsigned_long_long = type_unsigned_long_long;
1607 if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
1608 ia32_backend_params.mode_float_arithmetic = NULL;
1609 ia32_backend_params.type_long_double = NULL;
1611 ia32_backend_params.mode_float_arithmetic = ia32_mode_E;
1612 ia32_backend_params.type_long_double = ia32_type_E;
1615 ia32_register_init();
1616 obstack_init(&opcodes_obst);
1617 ia32_create_opcodes(&ia32_irn_ops);
1620 static void ia32_finish(void)
1622 if (between_type != NULL) {
1623 free_type(between_type);
1624 between_type = NULL;
1626 ia32_free_opcodes();
1627 obstack_free(&opcodes_obst, NULL);
1631 * The template that generates a new ISA object.
1632 * Note that this template can be changed by command line
1635 static ia32_isa_t ia32_isa_template = {
1637 &ia32_isa_if, /* isa interface implementation */
1642 &ia32_registers[REG_ESP], /* stack pointer register */
1643 &ia32_registers[REG_EBP], /* base pointer register */
1644 2, /* power of two stack alignment, 2^2 == 4 */
1645 NULL, /* main environment */
1646 7, /* costs for a spill instruction */
1647 5, /* costs for a reload instruction */
1648 false, /* no custom abi handling */
1651 IA32_FPU_ARCH_X87, /* FPU architecture */
1654 static arch_env_t *ia32_begin_codegeneration(const be_main_env_t *env)
1656 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1658 set_tarval_output_modes();
1660 *isa = ia32_isa_template;
1661 isa->tv_ent = pmap_create();
1663 /* enter the ISA object into the intrinsic environment */
1664 intrinsic_env.isa = isa;
1666 be_emit_init(env->file_handle);
1667 be_gas_begin_compilation_unit(env);
1673 * Closes the output file and frees the ISA structure.
1675 static void ia32_end_codegeneration(void *self)
1677 ia32_isa_t *isa = (ia32_isa_t*)self;
1679 /* emit now all global declarations */
1680 be_gas_end_compilation_unit(isa->base.main_env);
1684 pmap_destroy(isa->tv_ent);
1689 * Returns the register for parameter nr.
1691 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1692 const ir_mode *mode)
1694 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1695 &ia32_registers[REG_ECX],
1696 &ia32_registers[REG_EDX],
1699 static const unsigned MAXNUM_GPREG_ARGS = 3;
1701 static const arch_register_t *gpreg_param_reg_regparam[] = {
1702 &ia32_registers[REG_EAX],
1703 &ia32_registers[REG_EDX],
1704 &ia32_registers[REG_ECX]
1707 static const arch_register_t *gpreg_param_reg_this[] = {
1708 &ia32_registers[REG_ECX],
1713 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1714 &ia32_registers[REG_XMM0],
1715 &ia32_registers[REG_XMM1],
1716 &ia32_registers[REG_XMM2],
1717 &ia32_registers[REG_XMM3],
1718 &ia32_registers[REG_XMM4],
1719 &ia32_registers[REG_XMM5],
1720 &ia32_registers[REG_XMM6],
1721 &ia32_registers[REG_XMM7]
1724 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1725 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1727 static const unsigned MAXNUM_SSE_ARGS = 8;
1729 if ((cc & cc_this_call) && nr == 0)
1730 return gpreg_param_reg_this[0];
1732 if (! (cc & cc_reg_param))
1735 if (mode_is_float(mode)) {
1736 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1738 if (nr >= MAXNUM_SSE_ARGS)
1741 if (cc & cc_this_call) {
1742 return fpreg_sse_param_reg_this[nr];
1744 return fpreg_sse_param_reg_std[nr];
1745 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1746 unsigned num_regparam;
1748 if (get_mode_size_bits(mode) > 32)
1751 if (nr >= MAXNUM_GPREG_ARGS)
1754 if (cc & cc_this_call) {
1755 return gpreg_param_reg_this[nr];
1757 num_regparam = cc & ~cc_bits;
1758 if (num_regparam == 0) {
1759 /* default fastcall */
1760 return gpreg_param_reg_fastcall[nr];
1762 if (nr < num_regparam)
1763 return gpreg_param_reg_regparam[nr];
1767 panic("unknown argument mode");
1771 * Get the ABI restrictions for procedure calls.
1773 static void ia32_get_call_abi(ir_type *method_type, be_abi_call_t *abi)
1778 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1780 /* set abi flags for calls */
1781 /* call_flags.try_omit_fp not changed: can handle both settings */
1782 call_flags.call_has_imm = false; /* No call immediate, we handle this by ourselves */
1784 /* set parameter passing style */
1785 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1787 cc = get_method_calling_convention(method_type);
1788 if (get_method_variadicity(method_type) == variadicity_variadic) {
1789 /* pass all parameters of a variadic function on the stack */
1790 cc = cc_cdecl_set | (cc & cc_this_call);
1792 if (get_method_additional_properties(method_type) & mtp_property_private &&
1793 ia32_cg_config.optimize_cc) {
1794 /* set the fast calling conventions (allowing up to 3) */
1795 cc = SET_FASTCALL(cc) | 3;
1799 /* we have to pop the shadow parameter ourself for compound calls */
1800 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1801 && !(cc & cc_reg_param)) {
1802 pop_amount += get_mode_size_bytes(mode_P_data);
1805 n = get_method_n_params(method_type);
1806 for (i = regnum = 0; i < n; i++) {
1807 const arch_register_t *reg = NULL;
1808 ir_type *tp = get_method_param_type(method_type, i);
1809 ir_mode *mode = get_type_mode(tp);
1812 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1815 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1818 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1819 * movl has a shorter opcode than mov[sz][bw]l */
1820 ir_mode *load_mode = mode;
1823 unsigned size = get_mode_size_bytes(mode);
1825 if (cc & cc_callee_clear_stk) {
1826 pop_amount += (size + 3U) & ~3U;
1829 if (size < 4) load_mode = mode_Iu;
1832 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1836 be_abi_call_set_pop(abi, pop_amount);
1838 /* set return registers */
1839 n = get_method_n_ress(method_type);
1841 assert(n <= 2 && "more than two results not supported");
1843 /* In case of 64bit returns, we will have two 32bit values */
1845 ir_type *tp = get_method_res_type(method_type, 0);
1846 ir_mode *mode = get_type_mode(tp);
1848 assert(!mode_is_float(mode) && "two FP results not supported");
1850 tp = get_method_res_type(method_type, 1);
1851 mode = get_type_mode(tp);
1853 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1855 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1856 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1859 ir_type *tp = get_method_res_type(method_type, 0);
1860 ir_mode *mode = get_type_mode(tp);
1861 const arch_register_t *reg;
1862 assert(is_atomic_type(tp));
1864 reg = mode_is_float(mode) ? &ia32_registers[REG_ST0] : &ia32_registers[REG_EAX];
1866 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1870 static void ia32_mark_remat(ir_node *node)
1872 if (is_ia32_irn(node)) {
1873 set_ia32_is_remat(node);
1877 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
1881 /* we already added all our simple flags to the flags modifier list in
1882 * init, so this flag we don't know. */
1883 return ASM_CONSTRAINT_FLAG_INVALID;
1886 static int ia32_is_valid_clobber(const char *clobber)
1888 return ia32_get_clobber_register(clobber) != NULL;
1891 static void ia32_lower_for_target(void)
1893 ir_mode *mode_gp = ia32_reg_classes[CLASS_ia32_gp].mode;
1894 size_t i, n_irgs = get_irp_n_irgs();
1896 /* perform doubleword lowering */
1897 lwrdw_param_t lower_dw_params = {
1898 1, /* little endian */
1899 64, /* doubleword size */
1900 ia32_create_intrinsic_fkt,
1904 /* lower compound param handling
1905 * Note: we lower compound arguments ourself, since on ia32 we don't
1906 * have hidden parameters but know where to find the structs on the stack.
1907 * (This also forces us to always allocate space for the compound arguments
1908 * on the callframe and we can't just use an arbitrary position on the
1911 lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS);
1913 /* replace floating point operations by function calls */
1914 if (ia32_cg_config.use_softfloat) {
1915 lower_floating_point();
1918 for (i = 0; i < n_irgs; ++i) {
1919 ir_graph *irg = get_irp_irg(i);
1920 /* break up switches with wide ranges */
1921 lower_switch(irg, 4, 256, mode_gp);
1924 ir_prepare_dw_lowering(&lower_dw_params);
1927 for (i = 0; i < n_irgs; ++i) {
1928 ir_graph *irg = get_irp_irg(i);
1929 /* lower for mode_b stuff */
1930 ir_lower_mode_b(irg, mode_Iu);
1933 for (i = 0; i < n_irgs; ++i) {
1934 ir_graph *irg = get_irp_irg(i);
1935 /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
1936 * so we can generate rep movs later, and turn all big CopyBs into
1938 lower_CopyB(irg, 64, 8193, true);
1943 * Returns the libFirm configuration parameter for this backend.
1945 static const backend_params *ia32_get_libfirm_params(void)
1947 return &ia32_backend_params;
1951 * Check if the given register is callee or caller save.
1953 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
1956 /* check for callee saved */
1957 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
1958 switch (reg->index) {
1969 /* check for caller saved */
1970 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
1971 switch (reg->index) {
1979 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
1980 /* all XMM registers are caller save */
1981 return reg->index != REG_XMM_NOREG;
1982 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_fp]) {
1983 /* all FP registers are caller save */
1984 return reg->index != REG_FP_NOREG;
1990 static const lc_opt_enum_int_items_t gas_items[] = {
1991 { "elf", OBJECT_FILE_FORMAT_ELF },
1992 { "mingw", OBJECT_FILE_FORMAT_COFF },
1993 { "macho", OBJECT_FILE_FORMAT_MACH_O },
1997 static lc_opt_enum_int_var_t gas_var = {
1998 (int*) &be_gas_object_file_format, gas_items
2001 #ifdef FIRM_GRGEN_BE
2002 static const lc_opt_enum_int_items_t transformer_items[] = {
2003 { "default", TRANSFORMER_DEFAULT },
2004 { "pbqp", TRANSFORMER_PBQP },
2005 { "random", TRANSFORMER_RAND },
2009 static lc_opt_enum_int_var_t transformer_var = {
2010 (int*)&be_transformer, transformer_items
2014 static const lc_opt_table_entry_t ia32_options[] = {
2015 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2016 #ifdef FIRM_GRGEN_BE
2017 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2019 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2020 &ia32_isa_template.base.stack_alignment),
2021 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2025 const arch_isa_if_t ia32_isa_if = {
2028 ia32_get_libfirm_params,
2029 ia32_lower_for_target,
2030 ia32_parse_asm_constraint,
2031 ia32_is_valid_clobber,
2033 ia32_begin_codegeneration,
2034 ia32_end_codegeneration,
2038 ia32_get_pic_base, /* return node used as base in pic code addresses */
2041 ia32_register_saved_by,
2043 ia32_handle_intrinsics,
2044 ia32_before_abi, /* before abi introduce hook */
2046 ia32_before_ra, /* before register allocation hook */
2047 ia32_finish_graph, /* called before codegen */
2048 ia32_emit, /* emit && done */
2051 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2052 void be_init_arch_ia32(void)
2054 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2055 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2057 lc_opt_add_table(ia32_grp, ia32_options);
2058 be_register_isa_if("ia32", &ia32_isa_if);
2060 ia32_init_emitter();
2062 ia32_init_optimize();
2063 ia32_init_transform();
2065 ia32_init_architecture();