2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
31 #include "lc_opts_enum.h"
35 #include "pseudo_irg.h"
40 #include "iredges_t.h"
53 #include "iroptimize.h"
54 #include "instrument.h"
57 #include "../beirg_t.h"
58 #include "../benode_t.h"
59 #include "../belower.h"
60 #include "../besched_t.h"
63 #include "../beirgmod.h"
64 #include "../be_dbgout.h"
65 #include "../beblocksched.h"
66 #include "../bemachine.h"
67 #include "../beilpsched.h"
68 #include "../bespillslots.h"
69 #include "../bemodule.h"
70 #include "../begnuas.h"
71 #include "../bestate.h"
72 #include "../beflags.h"
74 #include "bearch_ia32_t.h"
76 #include "ia32_new_nodes.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "gen_ia32_machine.h"
79 #include "ia32_common_transform.h"
80 #include "ia32_transform.h"
81 #include "ia32_emitter.h"
82 #include "ia32_map_regs.h"
83 #include "ia32_optimize.h"
85 #include "ia32_dbg_stat.h"
86 #include "ia32_finish.h"
87 #include "ia32_util.h"
89 #include "ia32_architecture.h"
92 #include "ia32_pbqp_transform.h"
95 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
98 static set *cur_reg_set = NULL;
100 ir_mode *mode_fpcw = NULL;
101 ia32_code_gen_t *ia32_current_cg = NULL;
104 * The environment for the intrinsic mapping.
106 static ia32_intrinsic_env_t intrinsic_env = {
108 NULL, /* the irg, these entities belong to */
109 NULL, /* entity for first div operand (move into FPU) */
110 NULL, /* entity for second div operand (move into FPU) */
111 NULL, /* entity for converts ll -> d */
112 NULL, /* entity for converts d -> ll */
113 NULL, /* entity for __divdi3 library call */
114 NULL, /* entity for __moddi3 library call */
115 NULL, /* entity for __udivdi3 library call */
116 NULL, /* entity for __umoddi3 library call */
117 NULL, /* bias value for conversion from float to unsigned 64 */
121 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
123 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
124 create_const_node_func func,
125 const arch_register_t* reg)
127 ir_node *block, *res;
132 block = get_irg_start_block(cg->irg);
133 res = func(NULL, cg->irg, block);
134 arch_set_irn_register(cg->arch_env, res, reg);
137 add_irn_dep(get_irg_end(cg->irg), res);
138 /* add_irn_dep(get_irg_start(cg->irg), res); */
143 /* Creates the unique per irg GP NoReg node. */
144 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
145 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
146 &ia32_gp_regs[REG_GP_NOREG]);
149 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
150 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
151 &ia32_vfp_regs[REG_VFP_NOREG]);
154 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
155 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
156 &ia32_xmm_regs[REG_XMM_NOREG]);
159 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
160 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
161 &ia32_gp_regs[REG_GP_UKNWN]);
164 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
165 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
166 &ia32_vfp_regs[REG_VFP_UKNWN]);
169 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
170 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
171 &ia32_xmm_regs[REG_XMM_UKNWN]);
174 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
175 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
176 &ia32_fp_cw_regs[REG_FPCW]);
181 * Returns the admissible noreg register node for input register pos of node irn.
183 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
184 const arch_register_req_t *req;
186 req = arch_get_register_req(cg->arch_env, irn, pos);
187 assert(req != NULL && "Missing register requirements");
188 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
189 return ia32_new_NoReg_gp(cg);
191 if (ia32_cg_config.use_sse2) {
192 return ia32_new_NoReg_xmm(cg);
194 return ia32_new_NoReg_vfp(cg);
198 /**************************************************
201 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
202 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
203 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
204 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
207 **************************************************/
210 * Return register requirements for an ia32 node.
211 * If the node returns a tuple (mode_T) then the proj's
212 * will be asked for this information.
214 static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node,
217 ir_mode *mode = get_irn_mode(node);
220 if (mode == mode_X || is_Block(node)) {
221 return arch_no_register_req;
224 if (mode == mode_T && pos < 0) {
225 return arch_no_register_req;
228 node_pos = pos == -1 ? 0 : pos;
230 if (mode == mode_M || pos >= 0) {
231 return arch_no_register_req;
234 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
235 node = skip_Proj_const(node);
238 if (is_ia32_irn(node)) {
239 const arch_register_req_t *req;
241 req = get_ia32_in_req(node, pos);
243 req = get_ia32_out_req(node, node_pos);
250 /* unknowns should be transformed already */
251 assert(!is_Unknown(node));
252 return arch_no_register_req;
255 static void ia32_set_irn_reg(ir_node *irn, const arch_register_t *reg)
259 if (get_irn_mode(irn) == mode_X) {
264 pos = get_Proj_proj(irn);
265 irn = skip_Proj(irn);
268 if (is_ia32_irn(irn)) {
269 const arch_register_t **slots;
271 slots = get_ia32_slots(irn);
274 ia32_set_firm_reg(irn, reg, cur_reg_set);
278 static const arch_register_t *ia32_get_irn_reg(const ir_node *irn)
281 const arch_register_t *reg = NULL;
285 if (get_irn_mode(irn) == mode_X) {
289 pos = get_Proj_proj(irn);
290 irn = skip_Proj_const(irn);
293 if (is_ia32_irn(irn)) {
294 const arch_register_t **slots;
295 slots = get_ia32_slots(irn);
296 assert(pos < get_ia32_n_res(irn));
299 reg = ia32_get_firm_reg(irn, cur_reg_set);
305 static arch_irn_class_t ia32_classify(const ir_node *irn) {
306 arch_irn_class_t classification = arch_irn_class_normal;
308 irn = skip_Proj_const(irn);
311 classification |= arch_irn_class_branch;
313 if (! is_ia32_irn(irn))
314 return classification & ~arch_irn_class_normal;
317 classification |= arch_irn_class_load;
320 classification |= arch_irn_class_store;
322 if (is_ia32_need_stackent(irn))
323 classification |= arch_irn_class_reload;
325 return classification;
328 static arch_irn_flags_t ia32_get_flags(const ir_node *irn) {
329 arch_irn_flags_t flags = arch_irn_flags_none;
332 return arch_irn_flags_ignore;
334 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
335 ir_node *pred = get_Proj_pred(irn);
337 if(is_ia32_irn(pred)) {
338 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
344 if (is_ia32_irn(irn)) {
345 flags |= get_ia32_flags(irn);
352 * The IA32 ABI callback object.
355 be_abi_call_flags_bits_t flags; /**< The call flags. */
356 const arch_env_t *aenv; /**< The architecture environment. */
357 ir_graph *irg; /**< The associated graph. */
360 static ir_entity *ia32_get_frame_entity(const ir_node *irn) {
361 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
364 static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) {
365 set_ia32_frame_ent(irn, ent);
368 static void ia32_set_frame_offset(ir_node *irn, int bias)
370 if (get_ia32_frame_ent(irn) == NULL)
373 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
374 ia32_code_gen_t *cg = ia32_current_cg;
375 int omit_fp = be_abi_omit_fp(cg->birg->abi);
377 /* Pop nodes modify the stack pointer before calculating the
378 * destination address, so fix this here
383 add_ia32_am_offs_int(irn, bias);
386 static int ia32_get_sp_bias(const ir_node *node)
388 if (is_ia32_Push(node))
391 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
398 * Put all registers which are saved by the prologue/epilogue in a set.
400 * @param self The callback object.
401 * @param s The result set.
403 static void ia32_abi_dont_save_regs(void *self, pset *s)
405 ia32_abi_env_t *env = self;
406 if(env->flags.try_omit_fp)
407 pset_insert_ptr(s, env->aenv->bp);
411 * Generate the routine prologue.
413 * @param self The callback object.
414 * @param mem A pointer to the mem node. Update this if you define new memory.
415 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
416 * @param stack_bias Points to the current stack bias, can be modified if needed.
418 * @return The register which shall be used as a stack frame base.
420 * All nodes which define registers in @p reg_map must keep @p reg_map current.
422 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
424 ia32_abi_env_t *env = self;
425 ia32_code_gen_t *cg = ia32_current_cg;
426 const arch_env_t *arch_env = env->aenv;
428 if (! env->flags.try_omit_fp) {
429 ir_graph *irg =env->irg;
430 ir_node *bl = get_irg_start_block(irg);
431 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
432 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
433 ir_node *noreg = ia32_new_NoReg_gp(cg);
436 /* ALL nodes representing bp must be set to ignore. */
437 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
440 push = new_rd_ia32_Push(NULL, irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
441 curr_sp = new_r_Proj(irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
442 *mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M);
444 /* the push must have SP out register */
445 arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
446 set_ia32_flags(push, arch_irn_flags_ignore);
448 /* this modifies the stack bias, because we pushed 32bit */
451 /* move esp to ebp */
452 curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp);
453 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp);
454 arch_set_irn_register(arch_env, curr_bp, arch_env->bp);
455 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
457 /* beware: the copy must be done before any other sp use */
458 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
459 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), arch_env->sp);
460 arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
461 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
463 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
464 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
473 * Generate the routine epilogue.
474 * @param self The callback object.
475 * @param bl The block for the epilog
476 * @param mem A pointer to the mem node. Update this if you define new memory.
477 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
478 * @return The register which shall be used as a stack frame base.
480 * All nodes which define registers in @p reg_map must keep @p reg_map current.
482 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
484 ia32_abi_env_t *env = self;
485 const arch_env_t *arch_env = env->aenv;
486 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
487 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
488 ir_graph *irg = env->irg;
490 if (env->flags.try_omit_fp) {
491 /* simply remove the stack frame here */
492 curr_sp = be_new_IncSP(arch_env->sp, irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
494 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
496 if (ia32_cg_config.use_leave) {
500 leave = new_rd_ia32_Leave(NULL, irg, bl, curr_bp);
501 set_ia32_flags(leave, arch_irn_flags_ignore);
502 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
503 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
507 /* the old SP is not needed anymore (kill the proj) */
508 assert(is_Proj(curr_sp));
511 /* copy ebp to esp */
512 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
513 arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
514 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
517 pop = new_rd_ia32_Pop(NULL, env->irg, bl, *mem, curr_sp);
518 set_ia32_flags(pop, arch_irn_flags_ignore);
519 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
520 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
522 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
524 arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
525 arch_set_irn_register(arch_env, curr_bp, arch_env->bp);
528 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
529 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
533 * Initialize the callback object.
534 * @param call The call object.
535 * @param aenv The architecture environment.
536 * @param irg The graph with the method.
537 * @return Some pointer. This pointer is passed to all other callback functions as self object.
539 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
541 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
542 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
543 env->flags = fl.bits;
550 * Destroy the callback object.
551 * @param self The callback object.
553 static void ia32_abi_done(void *self) {
558 * Produces the type which sits between the stack args and the locals on the stack.
559 * it will contain the return address and space to store the old base pointer.
560 * @return The Firm type modeling the ABI between type.
562 static ir_type *ia32_abi_get_between_type(void *self)
564 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
565 static ir_type *omit_fp_between_type = NULL;
566 static ir_type *between_type = NULL;
568 ia32_abi_env_t *env = self;
570 if (! between_type) {
571 ir_entity *old_bp_ent;
572 ir_entity *ret_addr_ent;
573 ir_entity *omit_fp_ret_addr_ent;
575 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
576 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
578 between_type = new_type_struct(IDENT("ia32_between_type"));
579 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
580 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
582 set_entity_offset(old_bp_ent, 0);
583 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
584 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
585 set_type_state(between_type, layout_fixed);
587 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
588 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
590 set_entity_offset(omit_fp_ret_addr_ent, 0);
591 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
592 set_type_state(omit_fp_between_type, layout_fixed);
595 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
600 * Get the estimated cycle count for @p irn.
602 * @param self The this pointer.
603 * @param irn The node.
605 * @return The estimated cycle count for this operation
607 static int ia32_get_op_estimated_cost(const ir_node *irn)
610 ia32_op_type_t op_tp;
614 if (!is_ia32_irn(irn))
617 assert(is_ia32_irn(irn));
619 cost = get_ia32_latency(irn);
620 op_tp = get_ia32_op_type(irn);
622 if (is_ia32_CopyB(irn)) {
625 else if (is_ia32_CopyB_i(irn)) {
626 int size = get_ia32_copyb_size(irn);
627 cost = 20 + (int)ceil((4/3) * size);
629 /* in case of address mode operations add additional cycles */
630 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
632 In case of stack access and access to fixed addresses add 5 cycles
633 (we assume they are in cache), other memory operations cost 20
636 if (is_ia32_use_frame(irn) || (
637 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
638 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
650 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
652 * @param irn The original operation
653 * @param i Index of the argument we want the inverse operation to yield
654 * @param inverse struct to be filled with the resulting inverse op
655 * @param obstack The obstack to use for allocation of the returned nodes array
656 * @return The inverse operation or NULL if operation invertible
658 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
662 ir_node *block, *noreg, *nomem;
665 /* we cannot invert non-ia32 irns */
666 if (! is_ia32_irn(irn))
669 /* operand must always be a real operand (not base, index or mem) */
670 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
673 /* we don't invert address mode operations */
674 if (get_ia32_op_type(irn) != ia32_Normal)
677 /* TODO: adjust for new immediates... */
678 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
682 irg = get_irn_irg(irn);
683 block = get_nodes_block(irn);
684 mode = get_irn_mode(irn);
685 irn_mode = get_irn_mode(irn);
686 noreg = get_irn_n(irn, 0);
687 nomem = new_r_NoMem(irg);
688 dbg = get_irn_dbg_info(irn);
690 /* initialize structure */
691 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
695 switch (get_ia32_irn_opcode(irn)) {
698 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
699 /* we have an add with a const here */
700 /* invers == add with negated const */
701 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
703 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
704 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
705 set_ia32_commutative(inverse->nodes[0]);
707 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
708 /* we have an add with a symconst here */
709 /* invers == sub with const */
710 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
712 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
715 /* normal add: inverse == sub */
716 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
723 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
724 /* we have a sub with a const/symconst here */
725 /* invers == add with this const */
726 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
727 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
728 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
732 if (i == n_ia32_binary_left) {
733 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
736 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
744 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
745 /* xor with const: inverse = xor */
746 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
747 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
748 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
752 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
758 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
763 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
768 /* inverse operation not supported */
775 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
777 if(mode_is_float(mode))
784 * Get the mode that should be used for spilling value node
786 static ir_mode *get_spill_mode(const ir_node *node)
788 ir_mode *mode = get_irn_mode(node);
789 return get_spill_mode_mode(mode);
793 * Checks whether an addressmode reload for a node with mode mode is compatible
794 * with a spillslot of mode spill_mode
796 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
798 if(mode_is_float(mode)) {
799 return mode == spillmode;
806 * Check if irn can load its operand at position i from memory (source addressmode).
807 * @param self Pointer to irn ops itself
808 * @param irn The irn to be checked
809 * @param i The operands position
810 * @return Non-Zero if operand can be loaded
812 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i) {
813 ir_node *op = get_irn_n(irn, i);
814 const ir_mode *mode = get_irn_mode(op);
815 const ir_mode *spillmode = get_spill_mode(op);
818 (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
819 ! is_ia32_irn(irn) || /* must be an ia32 irn */
820 get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */
821 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
822 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
823 ! ia32_is_spillmode_compatible(mode, spillmode) ||
824 is_ia32_use_frame(irn)) /* must not already use frame */
827 if (i == n_ia32_binary_left) {
828 const arch_register_req_t *req;
829 if(!is_ia32_commutative(irn))
831 /* we can't swap left/right for limited registers
832 * (As this (currently) breaks constraint handling copies)
834 req = get_ia32_in_req(irn, n_ia32_binary_left);
835 if (req->type & arch_register_req_type_limited) {
843 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
847 ir_mode *dest_op_mode;
849 ia32_code_gen_t *cg = ia32_current_cg;
851 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
853 if (i == n_ia32_binary_left) {
854 ia32_swap_left_right(irn);
857 set_ia32_op_type(irn, ia32_AddrModeS);
859 load_mode = get_irn_mode(get_irn_n(irn, i));
860 dest_op_mode = get_ia32_ls_mode(irn);
861 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
862 set_ia32_ls_mode(irn, load_mode);
864 set_ia32_use_frame(irn);
865 set_ia32_need_stackent(irn);
867 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
868 set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
869 set_irn_n(irn, n_ia32_mem, spill);
870 set_ia32_is_reload(irn);
872 /* immediates are only allowed on the right side */
873 if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
874 ia32_swap_left_right(irn);
878 static const be_abi_callbacks_t ia32_abi_callbacks = {
881 ia32_abi_get_between_type,
882 ia32_abi_dont_save_regs,
887 /* fill register allocator interface */
889 static const arch_irn_ops_t ia32_irn_ops = {
890 ia32_get_irn_reg_req,
895 ia32_get_frame_entity,
896 ia32_set_frame_entity,
897 ia32_set_frame_offset,
900 ia32_get_op_estimated_cost,
901 ia32_possible_memory_operand,
902 ia32_perform_memory_operand,
905 /**************************************************
908 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
909 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
910 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
911 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
914 **************************************************/
916 static ir_entity *mcount = NULL;
918 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
920 static void ia32_before_abi(void *self) {
921 lower_mode_b_config_t lower_mode_b_config = {
922 mode_Iu, /* lowered mode */
923 mode_Bu, /* prefered mode for set */
924 0, /* don't lower direct compares */
926 ia32_code_gen_t *cg = self;
928 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
930 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
932 if (mcount == NULL) {
933 ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
934 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
935 /* FIXME: enter the right ld_ident here */
936 set_entity_ld_ident(mcount, get_entity_ident(mcount));
937 set_entity_visibility(mcount, visibility_external_allocated);
939 instrument_initcall(cg->irg, mcount);
943 transformer_t be_transformer = TRANSFORMER_DEFAULT;
946 * Transforms the standard firm graph into
949 static void ia32_prepare_graph(void *self) {
950 ia32_code_gen_t *cg = self;
952 /* do local optimizations */
953 optimize_graph_df(cg->irg);
955 /* TODO: we often have dead code reachable through out-edges here. So for
956 * now we rebuild edges (as we need correct user count for code selection)
959 edges_deactivate(cg->irg);
960 edges_activate(cg->irg);
964 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
966 switch (be_transformer) {
967 case TRANSFORMER_DEFAULT:
968 /* transform remaining nodes into assembler instructions */
969 ia32_transform_graph(cg);
973 case TRANSFORMER_PBQP:
974 case TRANSFORMER_RAND:
975 // disable CSE, because of two-step node-construction
978 /* transform nodes into assembler instructions by PBQP magic */
979 ia32_transform_graph_by_pbqp(cg);
985 default: panic("invalid transformer");
988 /* do local optimizations (mainly CSE) */
989 optimize_graph_df(cg->irg);
992 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
994 /* optimize address mode */
995 ia32_optimize_graph(cg);
998 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
1000 /* do code placement, to optimize the position of constants */
1001 place_code(cg->irg);
1004 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
1008 * Dummy functions for hooks we don't need but which must be filled.
1010 static void ia32_before_sched(void *self) {
1014 static void turn_back_am(ir_node *node)
1016 ir_graph *irg = current_ir_graph;
1017 dbg_info *dbgi = get_irn_dbg_info(node);
1018 ir_node *block = get_nodes_block(node);
1019 ir_node *base = get_irn_n(node, n_ia32_base);
1020 ir_node *index = get_irn_n(node, n_ia32_index);
1021 ir_node *mem = get_irn_n(node, n_ia32_mem);
1022 ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg);
1026 const ir_edge_t *edge;
1028 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1029 load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1031 ia32_copy_am_attrs(load, node);
1032 if (is_ia32_is_reload(node))
1033 set_ia32_is_reload(load);
1034 set_irn_n(node, n_ia32_mem, new_NoMem());
1036 switch (get_ia32_am_arity(node)) {
1038 set_irn_n(node, n_ia32_unary_op, load_res);
1041 case ia32_am_binary:
1042 if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
1043 assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) ||
1044 is_ia32_Test(node) || is_ia32_Test8Bit(node));
1045 set_irn_n(node, n_ia32_binary_left, load_res);
1047 set_irn_n(node, n_ia32_binary_right, load_res);
1051 case ia32_am_ternary:
1052 set_irn_n(node, n_ia32_binary_right, load_res);
1057 set_irn_n(node, n_ia32_base, noreg);
1058 set_irn_n(node, n_ia32_index, noreg);
1059 set_ia32_am_offs_int(node, 0);
1060 set_ia32_am_sc(node, NULL);
1061 set_ia32_am_scale(node, 0);
1062 clear_ia32_am_sc_sign(node);
1064 /* rewire mem-proj */
1065 if (get_irn_mode(node) == mode_T) {
1067 foreach_out_edge(node, edge) {
1068 ir_node *out = get_edge_src_irn(edge);
1069 if(get_irn_mode(out) == mode_M) {
1070 assert(mem_proj == NULL);
1075 if(mem_proj != NULL) {
1076 set_Proj_pred(mem_proj, load);
1077 set_Proj_proj(mem_proj, pn_ia32_Load_M);
1081 set_ia32_op_type(node, ia32_Normal);
1082 if (sched_is_scheduled(node))
1083 sched_add_before(node, load);
1086 static ir_node *flags_remat(ir_node *node, ir_node *after)
1088 /* we should turn back source address mode when rematerializing nodes */
1089 ia32_op_type_t type;
1093 if (is_Block(after)) {
1096 block = get_nodes_block(after);
1099 type = get_ia32_op_type(node);
1101 case ia32_AddrModeS:
1105 case ia32_AddrModeD:
1106 /* TODO implement this later... */
1107 panic("found DestAM with flag user %+F this should not happen", node);
1110 default: assert(type == ia32_Normal); break;
1113 copy = exact_copy(node);
1114 set_nodes_block(copy, block);
1115 sched_add_after(after, copy);
1121 * Called before the register allocator.
1123 static void ia32_before_ra(void *self) {
1124 ia32_code_gen_t *cg = self;
1126 /* setup fpu rounding modes */
1127 ia32_setup_fpu_mode(cg);
1130 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1133 ia32_add_missing_keeps(cg);
1138 * Transforms a be_Reload into a ia32 Load.
1140 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1141 ir_graph *irg = get_irn_irg(node);
1142 dbg_info *dbg = get_irn_dbg_info(node);
1143 ir_node *block = get_nodes_block(node);
1144 ir_entity *ent = be_get_frame_entity(node);
1145 ir_mode *mode = get_irn_mode(node);
1146 ir_mode *spillmode = get_spill_mode(node);
1147 ir_node *noreg = ia32_new_NoReg_gp(cg);
1148 ir_node *sched_point = NULL;
1149 ir_node *ptr = get_irg_frame(irg);
1150 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1151 ir_node *new_op, *proj;
1152 const arch_register_t *reg;
1154 if (sched_is_scheduled(node)) {
1155 sched_point = sched_prev(node);
1158 if (mode_is_float(spillmode)) {
1159 if (ia32_cg_config.use_sse2)
1160 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
1162 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
1164 else if (get_mode_size_bits(spillmode) == 128) {
1165 /* Reload 128 bit SSE registers */
1166 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1169 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1171 set_ia32_op_type(new_op, ia32_AddrModeS);
1172 set_ia32_ls_mode(new_op, spillmode);
1173 set_ia32_frame_ent(new_op, ent);
1174 set_ia32_use_frame(new_op);
1175 set_ia32_is_reload(new_op);
1177 DBG_OPT_RELOAD2LD(node, new_op);
1179 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1182 sched_add_after(sched_point, new_op);
1186 /* copy the register from the old node to the new Load */
1187 reg = arch_get_irn_register(cg->arch_env, node);
1188 arch_set_irn_register(cg->arch_env, new_op, reg);
1190 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1192 exchange(node, proj);
1196 * Transforms a be_Spill node into a ia32 Store.
1198 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1199 ir_graph *irg = get_irn_irg(node);
1200 dbg_info *dbg = get_irn_dbg_info(node);
1201 ir_node *block = get_nodes_block(node);
1202 ir_entity *ent = be_get_frame_entity(node);
1203 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1204 ir_mode *mode = get_spill_mode(spillval);
1205 ir_node *noreg = ia32_new_NoReg_gp(cg);
1206 ir_node *nomem = new_rd_NoMem(irg);
1207 ir_node *ptr = get_irg_frame(irg);
1208 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1210 ir_node *sched_point = NULL;
1212 if (sched_is_scheduled(node)) {
1213 sched_point = sched_prev(node);
1216 /* No need to spill unknown values... */
1217 if(is_ia32_Unknown_GP(val) ||
1218 is_ia32_Unknown_VFP(val) ||
1219 is_ia32_Unknown_XMM(val)) {
1224 exchange(node, store);
1228 if (mode_is_float(mode)) {
1229 if (ia32_cg_config.use_sse2)
1230 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
1232 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
1233 } else if (get_mode_size_bits(mode) == 128) {
1234 /* Spill 128 bit SSE registers */
1235 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
1236 } else if (get_mode_size_bits(mode) == 8) {
1237 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
1239 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
1242 set_ia32_op_type(store, ia32_AddrModeD);
1243 set_ia32_ls_mode(store, mode);
1244 set_ia32_frame_ent(store, ent);
1245 set_ia32_use_frame(store);
1246 set_ia32_is_spill(store);
1247 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1248 DBG_OPT_SPILL2ST(node, store);
1251 sched_add_after(sched_point, store);
1255 exchange(node, store);
1258 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1259 ir_graph *irg = get_irn_irg(node);
1260 dbg_info *dbg = get_irn_dbg_info(node);
1261 ir_node *block = get_nodes_block(node);
1262 ir_node *noreg = ia32_new_NoReg_gp(cg);
1263 ir_node *frame = get_irg_frame(irg);
1265 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
1267 set_ia32_frame_ent(push, ent);
1268 set_ia32_use_frame(push);
1269 set_ia32_op_type(push, ia32_AddrModeS);
1270 set_ia32_ls_mode(push, mode_Is);
1272 sched_add_before(schedpoint, push);
1276 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1277 ir_graph *irg = get_irn_irg(node);
1278 dbg_info *dbg = get_irn_dbg_info(node);
1279 ir_node *block = get_nodes_block(node);
1280 ir_node *noreg = ia32_new_NoReg_gp(cg);
1281 ir_node *frame = get_irg_frame(irg);
1283 ir_node *pop = new_rd_ia32_PopMem(dbg, irg, block, frame, noreg, new_NoMem(), sp);
1285 set_ia32_frame_ent(pop, ent);
1286 set_ia32_use_frame(pop);
1287 set_ia32_op_type(pop, ia32_AddrModeD);
1288 set_ia32_ls_mode(pop, mode_Is);
1290 sched_add_before(schedpoint, pop);
1295 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
1296 ir_graph *irg = get_irn_irg(node);
1297 dbg_info *dbg = get_irn_dbg_info(node);
1298 ir_node *block = get_nodes_block(node);
1299 ir_mode *spmode = mode_Iu;
1300 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1303 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1304 arch_set_irn_register(cg->arch_env, sp, spreg);
1310 * Transform MemPerm, currently we do this the ugly way and produce
1311 * push/pop into/from memory cascades. This is possible without using
1314 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1315 ir_graph *irg = get_irn_irg(node);
1316 ir_node *block = get_nodes_block(node);
1320 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1321 const ir_edge_t *edge;
1322 const ir_edge_t *next;
1325 arity = be_get_MemPerm_entity_arity(node);
1326 pops = alloca(arity * sizeof(pops[0]));
1329 for(i = 0; i < arity; ++i) {
1330 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1331 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1332 ir_type *enttype = get_entity_type(inent);
1333 unsigned entsize = get_type_size_bytes(enttype);
1334 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1335 ir_node *mem = get_irn_n(node, i + 1);
1338 /* work around cases where entities have different sizes */
1339 if(entsize2 < entsize)
1341 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1343 push = create_push(cg, node, node, sp, mem, inent);
1344 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1346 /* add another push after the first one */
1347 push = create_push(cg, node, node, sp, mem, inent);
1348 add_ia32_am_offs_int(push, 4);
1349 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1352 set_irn_n(node, i, new_Bad());
1356 for(i = arity - 1; i >= 0; --i) {
1357 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1358 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1359 ir_type *enttype = get_entity_type(outent);
1360 unsigned entsize = get_type_size_bytes(enttype);
1361 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1364 /* work around cases where entities have different sizes */
1365 if(entsize2 < entsize)
1367 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1369 pop = create_pop(cg, node, node, sp, outent);
1370 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1372 add_ia32_am_offs_int(pop, 4);
1374 /* add another pop after the first one */
1375 pop = create_pop(cg, node, node, sp, outent);
1376 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1383 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1384 sched_add_before(node, keep);
1386 /* exchange memprojs */
1387 foreach_out_edge_safe(node, edge, next) {
1388 ir_node *proj = get_edge_src_irn(edge);
1389 int p = get_Proj_proj(proj);
1393 set_Proj_pred(proj, pops[p]);
1394 set_Proj_proj(proj, pn_ia32_Pop_M);
1397 /* remove memperm */
1398 arity = get_irn_arity(node);
1399 for(i = 0; i < arity; ++i) {
1400 set_irn_n(node, i, new_Bad());
1406 * Block-Walker: Calls the transform functions Spill and Reload.
1408 static void ia32_after_ra_walker(ir_node *block, void *env) {
1409 ir_node *node, *prev;
1410 ia32_code_gen_t *cg = env;
1412 /* beware: the schedule is changed here */
1413 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1414 prev = sched_prev(node);
1416 if (be_is_Reload(node)) {
1417 transform_to_Load(cg, node);
1418 } else if (be_is_Spill(node)) {
1419 transform_to_Store(cg, node);
1420 } else if (be_is_MemPerm(node)) {
1421 transform_MemPerm(cg, node);
1427 * Collects nodes that need frame entities assigned.
1429 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1431 be_fec_env_t *env = data;
1433 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1434 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1435 int align = get_mode_size_bytes(mode);
1436 be_node_needs_frame_entity(env, node, mode, align);
1437 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1438 && is_ia32_use_frame(node)) {
1439 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1440 const ir_mode *mode = get_ia32_ls_mode(node);
1441 const ia32_attr_t *attr = get_ia32_attr_const(node);
1444 if (is_ia32_is_reload(node)) {
1445 mode = get_spill_mode_mode(mode);
1448 if(attr->data.need_64bit_stackent) {
1451 if(attr->data.need_32bit_stackent) {
1454 align = get_mode_size_bytes(mode);
1455 be_node_needs_frame_entity(env, node, mode, align);
1456 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
1457 || is_ia32_vfld(node)) {
1458 const ir_mode *mode = get_ia32_ls_mode(node);
1460 be_node_needs_frame_entity(env, node, mode, align);
1461 } else if(is_ia32_FldCW(node)) {
1462 /* although 2 byte would be enough 4 byte performs best */
1463 const ir_mode *mode = mode_Iu;
1465 be_node_needs_frame_entity(env, node, mode, align);
1468 assert(is_ia32_St(node) ||
1469 is_ia32_xStoreSimple(node) ||
1470 is_ia32_vfst(node) ||
1471 is_ia32_vfist(node) ||
1472 is_ia32_vfisttp(node) ||
1473 is_ia32_FnstCW(node));
1480 * We transform Spill and Reload here. This needs to be done before
1481 * stack biasing otherwise we would miss the corrected offset for these nodes.
1483 static void ia32_after_ra(void *self) {
1484 ia32_code_gen_t *cg = self;
1485 ir_graph *irg = cg->irg;
1486 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1488 /* create and coalesce frame entities */
1489 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1490 be_assign_entities(fec_env);
1491 be_free_frame_entity_coalescer(fec_env);
1493 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1497 * Last touchups for the graph before emit: x87 simulation to replace the
1498 * virtual with real x87 instructions, creating a block schedule and peephole
1501 static void ia32_finish(void *self) {
1502 ia32_code_gen_t *cg = self;
1503 ir_graph *irg = cg->irg;
1505 ia32_finish_irg(irg, cg);
1507 /* we might have to rewrite x87 virtual registers */
1508 if (cg->do_x87_sim) {
1509 x87_simulate_graph(cg->arch_env, cg->birg);
1512 /* do peephole optimisations */
1513 ia32_peephole_optimization(cg);
1515 /* create block schedule, this also removes empty blocks which might
1516 * produce critical edges */
1517 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1521 * Emits the code, closes the output file and frees
1522 * the code generator interface.
1524 static void ia32_codegen(void *self) {
1525 ia32_code_gen_t *cg = self;
1526 ir_graph *irg = cg->irg;
1528 ia32_gen_routine(cg, irg);
1532 /* remove it from the isa */
1535 assert(ia32_current_cg == cg);
1536 ia32_current_cg = NULL;
1538 /* de-allocate code generator */
1539 del_set(cg->reg_set);
1544 * Returns the node representing the PIC base.
1546 static ir_node *ia32_get_pic_base(void *self) {
1548 ia32_code_gen_t *cg = self;
1549 ir_node *get_eip = cg->get_eip;
1550 if (get_eip != NULL)
1553 block = get_irg_start_block(cg->irg);
1554 get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block);
1555 cg->get_eip = get_eip;
1557 add_irn_dep(get_eip, get_irg_frame(cg->irg));
1562 static void *ia32_cg_init(be_irg_t *birg);
1564 static const arch_code_generator_if_t ia32_code_gen_if = {
1566 ia32_get_pic_base, /* return node used as base in pic code addresses */
1567 ia32_before_abi, /* before abi introduce hook */
1570 ia32_before_sched, /* before scheduling hook */
1571 ia32_before_ra, /* before register allocation hook */
1572 ia32_after_ra, /* after register allocation hook */
1573 ia32_finish, /* called before codegen */
1574 ia32_codegen /* emit && done */
1578 * Initializes a IA32 code generator.
1580 static void *ia32_cg_init(be_irg_t *birg) {
1581 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
1582 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1584 cg->impl = &ia32_code_gen_if;
1585 cg->irg = birg->irg;
1586 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1588 cg->arch_env = birg->main_env->arch_env;
1590 cg->blk_sched = NULL;
1591 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1592 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1595 /* Linux gprof implementation needs base pointer */
1596 birg->main_env->options->omit_fp = 0;
1603 if (isa->name_obst) {
1604 obstack_free(isa->name_obst, NULL);
1605 obstack_init(isa->name_obst);
1609 cur_reg_set = cg->reg_set;
1611 assert(ia32_current_cg == NULL);
1612 ia32_current_cg = cg;
1614 return (arch_code_generator_t *)cg;
1619 /*****************************************************************
1620 * ____ _ _ _____ _____
1621 * | _ \ | | | | |_ _|/ ____| /\
1622 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1623 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1624 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1625 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1627 *****************************************************************/
1630 * Set output modes for GCC
1632 static const tarval_mode_info mo_integer = {
1639 * set the tarval output mode of all integer modes to decimal
1641 static void set_tarval_output_modes(void)
1645 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1646 ir_mode *mode = get_irp_mode(i);
1648 if (mode_is_int(mode))
1649 set_tarval_mode_output_option(mode, &mo_integer);
1653 const arch_isa_if_t ia32_isa_if;
1656 * The template that generates a new ISA object.
1657 * Note that this template can be changed by command line
1660 static ia32_isa_t ia32_isa_template = {
1662 &ia32_isa_if, /* isa interface implementation */
1663 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1664 &ia32_gp_regs[REG_EBP], /* base pointer register */
1665 -1, /* stack direction */
1666 2, /* power of two stack alignment, 2^2 == 4 */
1667 NULL, /* main environment */
1668 7, /* costs for a spill instruction */
1669 5, /* costs for a reload instruction */
1671 NULL, /* 16bit register names */
1672 NULL, /* 8bit register names */
1673 NULL, /* 8bit register names high */
1676 NULL, /* current code generator */
1677 NULL, /* abstract machine */
1679 NULL, /* name obstack */
1683 static void init_asm_constraints(void)
1685 be_init_default_asm_constraint_flags();
1687 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1688 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1689 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1690 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1691 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1692 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1693 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1694 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1695 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1696 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1697 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1698 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1699 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1700 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1701 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1702 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1703 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1704 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1705 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1706 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1708 /* no support for autodecrement/autoincrement */
1709 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1710 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1711 /* no float consts */
1712 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1713 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1714 /* makes no sense on x86 */
1715 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1716 /* no support for sse consts yet */
1717 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1718 /* no support for x87 consts yet */
1719 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1720 /* no support for mmx registers yet */
1721 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1722 /* not available in 32bit mode */
1723 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1724 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1726 /* no code yet to determine register class needed... */
1727 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1731 * Initializes the backend ISA.
1733 static arch_env_t *ia32_init(FILE *file_handle) {
1734 static int inited = 0;
1742 set_tarval_output_modes();
1744 isa = xmalloc(sizeof(*isa));
1745 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1747 if(mode_fpcw == NULL) {
1748 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1751 ia32_register_init();
1752 ia32_create_opcodes(&ia32_irn_ops);
1754 be_emit_init(file_handle);
1755 isa->regs_16bit = pmap_create();
1756 isa->regs_8bit = pmap_create();
1757 isa->regs_8bit_high = pmap_create();
1758 isa->types = pmap_create();
1759 isa->tv_ent = pmap_create();
1760 isa->cpu = ia32_init_machine_description();
1762 ia32_build_16bit_reg_map(isa->regs_16bit);
1763 ia32_build_8bit_reg_map(isa->regs_8bit);
1764 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1767 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1768 obstack_init(isa->name_obst);
1771 /* enter the ISA object into the intrinsic environment */
1772 intrinsic_env.isa = isa;
1773 ia32_handle_intrinsics();
1775 /* emit asm includes */
1776 n = get_irp_n_asms();
1777 for (i = 0; i < n; ++i) {
1778 be_emit_cstring("#APP\n");
1779 be_emit_ident(get_irp_asm(i));
1780 be_emit_cstring("\n#NO_APP\n");
1783 /* needed for the debug support */
1784 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1785 be_emit_cstring(".Ltext0:\n");
1786 be_emit_write_line();
1788 /* we mark referenced global entities, so we can only emit those which
1789 * are actually referenced. (Note: you mustn't use the type visited flag
1790 * elsewhere in the backend)
1792 inc_master_type_visited();
1794 return &isa->arch_env;
1800 * Closes the output file and frees the ISA structure.
1802 static void ia32_done(void *self) {
1803 ia32_isa_t *isa = self;
1805 /* emit now all global declarations */
1806 be_gas_emit_decls(isa->arch_env.main_env, 1);
1808 pmap_destroy(isa->regs_16bit);
1809 pmap_destroy(isa->regs_8bit);
1810 pmap_destroy(isa->regs_8bit_high);
1811 pmap_destroy(isa->tv_ent);
1812 pmap_destroy(isa->types);
1815 obstack_free(isa->name_obst, NULL);
1825 * Return the number of register classes for this architecture.
1826 * We report always these:
1827 * - the general purpose registers
1828 * - the SSE floating point register set
1829 * - the virtual floating point registers
1830 * - the SSE vector register set
1832 static unsigned ia32_get_n_reg_class(const void *self) {
1838 * Return the register class for index i.
1840 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1844 assert(i < N_CLASSES);
1845 return &ia32_reg_classes[i];
1849 * Get the register class which shall be used to store a value of a given mode.
1850 * @param self The this pointer.
1851 * @param mode The mode in question.
1852 * @return A register class which can hold values of the given mode.
1854 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1855 const ir_mode *mode)
1859 if (mode_is_float(mode)) {
1860 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1863 return &ia32_reg_classes[CLASS_ia32_gp];
1867 * Get the ABI restrictions for procedure calls.
1868 * @param self The this pointer.
1869 * @param method_type The type of the method (procedure) in question.
1870 * @param abi The abi object to be modified
1872 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1880 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1884 /* set abi flags for calls */
1885 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1886 call_flags.bits.store_args_sequential = 0;
1887 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1888 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1889 call_flags.bits.call_has_imm = 1; /* No call immediates, we handle this by ourselves */
1891 /* set parameter passing style */
1892 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1894 if (get_method_variadicity(method_type) == variadicity_variadic) {
1895 /* pass all parameters of a variadic function on the stack */
1898 cc = get_method_calling_convention(method_type);
1899 if (get_method_additional_properties(method_type) & mtp_property_private &&
1900 ia32_cg_config.optimize_cc) {
1901 /* set the calling conventions to register parameter */
1902 cc = (cc & ~cc_bits) | cc_reg_param;
1906 /* we have to pop the shadow parameter ourself for compound calls */
1907 if( (get_method_calling_convention(method_type) & cc_compound_ret)
1908 && !(cc & cc_reg_param)) {
1909 pop_amount += get_mode_size_bytes(mode_P_data);
1912 n = get_method_n_params(method_type);
1913 for (i = regnum = 0; i < n; i++) {
1915 const arch_register_t *reg = NULL;
1917 tp = get_method_param_type(method_type, i);
1918 mode = get_type_mode(tp);
1920 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1923 be_abi_call_param_reg(abi, i, reg);
1926 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1927 * movl has a shorter opcode than mov[sz][bw]l */
1928 ir_mode *load_mode = mode;
1931 unsigned size = get_mode_size_bytes(mode);
1933 if (cc & cc_callee_clear_stk) {
1934 pop_amount += (size + 3U) & ~3U;
1937 if (size < 4) load_mode = mode_Iu;
1940 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1944 be_abi_call_set_pop(abi, pop_amount);
1946 /* set return registers */
1947 n = get_method_n_ress(method_type);
1949 assert(n <= 2 && "more than two results not supported");
1951 /* In case of 64bit returns, we will have two 32bit values */
1953 tp = get_method_res_type(method_type, 0);
1954 mode = get_type_mode(tp);
1956 assert(!mode_is_float(mode) && "two FP results not supported");
1958 tp = get_method_res_type(method_type, 1);
1959 mode = get_type_mode(tp);
1961 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1963 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1964 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1967 const arch_register_t *reg;
1969 tp = get_method_res_type(method_type, 0);
1970 assert(is_atomic_type(tp));
1971 mode = get_type_mode(tp);
1973 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1975 be_abi_call_res_reg(abi, 0, reg);
1979 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1983 if(!is_ia32_irn(irn)) {
1987 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1988 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1989 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1990 || is_ia32_Immediate(irn))
1997 * Initializes the code generator interface.
1999 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
2002 return &ia32_code_gen_if;
2006 * Returns the estimated execution time of an ia32 irn.
2008 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
2010 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
2013 list_sched_selector_t ia32_sched_selector;
2016 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
2018 static const list_sched_selector_t *ia32_get_list_sched_selector(
2019 const void *self, list_sched_selector_t *selector)
2022 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
2023 ia32_sched_selector.exectime = ia32_sched_exectime;
2024 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
2025 return &ia32_sched_selector;
2028 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
2035 * Returns the necessary byte alignment for storing a register of given class.
2037 static int ia32_get_reg_class_alignment(const void *self,
2038 const arch_register_class_t *cls)
2040 ir_mode *mode = arch_register_class_mode(cls);
2041 int bytes = get_mode_size_bytes(mode);
2044 if (mode_is_float(mode) && bytes > 8)
2049 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
2050 const void *self, const ir_node *irn)
2052 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
2053 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
2054 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
2057 static const be_execution_unit_t *_allowed_units_GP[] = {
2058 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
2059 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
2060 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
2061 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
2062 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
2063 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
2064 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2067 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2068 &be_machine_execution_units_DUMMY[0],
2071 static const be_execution_unit_t **_units_callret[] = {
2072 _allowed_units_BRANCH,
2075 static const be_execution_unit_t **_units_other[] = {
2079 static const be_execution_unit_t **_units_dummy[] = {
2080 _allowed_units_DUMMY,
2083 const be_execution_unit_t ***ret;
2086 if (is_ia32_irn(irn)) {
2087 ret = get_ia32_exec_units(irn);
2089 else if (is_be_node(irn)) {
2090 if (be_is_Call(irn) || be_is_Return(irn)) {
2091 ret = _units_callret;
2093 else if (be_is_Barrier(irn)) {
2108 * Return the abstract ia32 machine.
2110 static const be_machine_t *ia32_get_machine(const void *self) {
2111 const ia32_isa_t *isa = self;
2116 * Return irp irgs in the desired order.
2118 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2125 static void ia32_mark_remat(const void *self, ir_node *node) {
2127 if (is_ia32_irn(node)) {
2128 set_ia32_is_remat(node);
2133 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2134 * @return 1 if allowed, 0 otherwise
2136 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2139 ir_node *cmp = NULL;
2141 /* we can't handle psis with 64bit compares yet */
2143 cmp = get_Proj_pred(sel);
2145 ir_node *left = get_Cmp_left(cmp);
2146 ir_mode *cmp_mode = get_irn_mode(left);
2147 if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
2154 if (ia32_cg_config.use_cmov) {
2155 if (ia32_cg_config.use_sse2 && cmp != NULL) {
2156 pn_Cmp pn = get_Proj_proj(sel);
2157 ir_node *cl = get_Cmp_left(cmp);
2158 ir_node *cr = get_Cmp_right(cmp);
2160 /* check the Phi nodes: no 64bit and no floating point cmov */
2161 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2162 ir_mode *mode = get_irn_mode(phi);
2164 if (mode_is_float(mode)) {
2165 /* check for Min, Max */
2166 ir_node *t = get_Phi_pred(phi, i);
2167 ir_node *f = get_Phi_pred(phi, j);
2170 /* SSE2 supports Min & Max */
2171 if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2172 if (cl == t && cr == f) {
2173 /* Psi(a <=/>= b, a, b) => MIN, MAX */
2175 } else if (cl == f && cr == t) {
2176 /* Psi(a <=/>= b, b, a) => MAX, MIN */
2183 } else if (get_mode_size_bits(mode) > 32)
2187 /* check the Phi nodes: no 64bit and no floating point cmov */
2188 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2189 ir_mode *mode = get_irn_mode(phi);
2191 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2201 /* No cmov, only some special cases */
2205 /* Now some supported cases here */
2206 pn = get_Proj_proj(sel);
2207 cl = get_Cmp_left(cmp);
2208 cr = get_Cmp_right(cmp);
2210 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2211 ir_mode *mode = get_irn_mode(phi);
2215 t = get_Phi_pred(phi, i);
2216 f = get_Phi_pred(phi, j);
2218 /* no floating point and no 64bit yet */
2219 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2222 if (is_Const(t) && is_Const(f)) {
2223 if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
2224 /* always support Psi(x, C1, C2) */
2227 } else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2230 } else if (cl == t && cr == f) {
2231 /* Psi(a <=/>= b, a, b) => Min, Max */
2233 } else if (cl == f && cr == t) {
2234 /* Psi(a <=/>= b, b, a) => Max, Min */
2237 } else if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
2238 is_Const(f) && is_Const_null(f) && is_Sub(t) &&
2239 get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
2240 /* Psi(a >=u b, a - b, 0) unsigned Doz */
2242 } else if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
2243 is_Const(t) && is_Const_null(t) && is_Sub(f) &&
2244 get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
2245 /* Psi(a <=u b, 0, a - b) unsigned Doz */
2247 } else if (is_Const(cr) && is_Const_null(cr)) {
2248 if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
2249 /* Psi(a <=/>= 0 ? a : -a) Nabs/Abs */
2251 } else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
2252 /* Psi(a <=/>= 0 ? -a : a) Abs/Nabs */
2260 /* all checks passed */
2266 static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const char **c)
2271 /* we already added all our simple flags to the flags modifier list in
2272 * init, so this flag we don't know. */
2273 return ASM_CONSTRAINT_FLAG_INVALID;
2276 static int ia32_is_valid_clobber(const void *self, const char *clobber)
2280 return ia32_get_clobber_register(clobber) != NULL;
2284 * Returns the libFirm configuration parameter for this backend.
2286 static const backend_params *ia32_get_libfirm_params(void) {
2287 static const ir_settings_if_conv_t ifconv = {
2288 4, /* maxdepth, doesn't matter for Psi-conversion */
2289 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2291 static const ir_settings_arch_dep_t ad = {
2292 1, /* also use subs */
2293 4, /* maximum shifts */
2294 31, /* maximum shift amount */
2295 ia32_evaluate_insn, /* evaluate the instruction sequence */
2297 1, /* allow Mulhs */
2298 1, /* allow Mulus */
2299 32 /* Mulh allowed up to 32 bit */
2301 static backend_params p = {
2302 1, /* need dword lowering */
2303 1, /* support inline assembly */
2304 0, /* no immediate floating point mode. */
2305 NULL, /* no additional opcodes */
2306 NULL, /* will be set later */
2307 ia32_create_intrinsic_fkt,
2308 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2309 NULL, /* will be set below */
2310 NULL /* will be set below */
2313 ia32_setup_cg_config();
2315 /* doesn't really belong here, but this is the earliest place the backend
2317 init_asm_constraints();
2320 p.if_conv_info = &ifconv;
2324 static const lc_opt_enum_int_items_t gas_items[] = {
2325 { "elf", GAS_FLAVOUR_ELF },
2326 { "mingw", GAS_FLAVOUR_MINGW },
2327 { "yasm", GAS_FLAVOUR_YASM },
2328 { "macho", GAS_FLAVOUR_MACH_O },
2332 static lc_opt_enum_int_var_t gas_var = {
2333 (int*) &be_gas_flavour, gas_items
2336 static const lc_opt_enum_int_items_t transformer_items[] = {
2337 { "default", TRANSFORMER_DEFAULT },
2338 #ifdef FIRM_GRGEN_BE
2339 { "pbqp", TRANSFORMER_PBQP },
2340 { "random", TRANSFORMER_RAND },
2345 static lc_opt_enum_int_var_t transformer_var = {
2346 (int*)&be_transformer, transformer_items
2349 static const lc_opt_table_entry_t ia32_options[] = {
2350 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2351 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2352 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2353 &ia32_isa_template.arch_env.stack_alignment),
2357 const arch_isa_if_t ia32_isa_if = {
2360 ia32_get_n_reg_class,
2362 ia32_get_reg_class_for_mode,
2364 ia32_get_code_generator_if,
2365 ia32_get_list_sched_selector,
2366 ia32_get_ilp_sched_selector,
2367 ia32_get_reg_class_alignment,
2368 ia32_get_libfirm_params,
2369 ia32_get_allowed_execution_units,
2373 ia32_parse_asm_constraint,
2374 ia32_is_valid_clobber
2377 void ia32_init_emitter(void);
2378 void ia32_init_finish(void);
2379 void ia32_init_optimize(void);
2380 void ia32_init_transform(void);
2381 void ia32_init_x87(void);
2383 void be_init_arch_ia32(void)
2385 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2386 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2388 lc_opt_add_table(ia32_grp, ia32_options);
2389 be_register_isa_if("ia32", &ia32_isa_if);
2391 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2393 ia32_init_emitter();
2395 ia32_init_optimize();
2396 ia32_init_transform();
2398 ia32_init_architecture();
2401 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);