2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
57 #include "../benode.h"
58 #include "../belower.h"
59 #include "../besched.h"
62 #include "../beirgmod.h"
63 #include "../be_dbgout.h"
64 #include "../beblocksched.h"
65 #include "../bemachine.h"
66 #include "../bespillslots.h"
67 #include "../bemodule.h"
68 #include "../begnuas.h"
69 #include "../bestate.h"
70 #include "../beflags.h"
71 #include "../betranshlp.h"
72 #include "../belistsched.h"
73 #include "../beabihelper.h"
75 #include "bearch_ia32_t.h"
77 #include "ia32_new_nodes.h"
78 #include "gen_ia32_regalloc_if.h"
79 #include "gen_ia32_machine.h"
80 #include "ia32_common_transform.h"
81 #include "ia32_transform.h"
82 #include "ia32_emitter.h"
83 #include "ia32_optimize.h"
85 #include "ia32_dbg_stat.h"
86 #include "ia32_finish.h"
88 #include "ia32_architecture.h"
91 #include "ia32_pbqp_transform.h"
93 transformer_t be_transformer = TRANSFORMER_DEFAULT;
96 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
98 ir_mode *ia32_mode_fpcw = NULL;
100 /** The current omit-fp state */
101 static ir_type *omit_fp_between_type = NULL;
102 static ir_type *between_type = NULL;
103 static ir_entity *old_bp_ent = NULL;
104 static ir_entity *ret_addr_ent = NULL;
105 static ir_entity *omit_fp_ret_addr_ent = NULL;
108 * The environment for the intrinsic mapping.
110 static ia32_intrinsic_env_t intrinsic_env = {
112 NULL, /* the irg, these entities belong to */
113 NULL, /* entity for __divdi3 library call */
114 NULL, /* entity for __moddi3 library call */
115 NULL, /* entity for __udivdi3 library call */
116 NULL, /* entity for __umoddi3 library call */
120 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
123 * Used to create per-graph unique pseudo nodes.
125 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
126 create_const_node_func func,
127 const arch_register_t* reg)
129 ir_node *block, *res;
134 block = get_irg_start_block(irg);
135 res = func(NULL, block);
136 arch_set_irn_register(res, reg);
142 /* Creates the unique per irg GP NoReg node. */
143 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
145 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
146 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
147 &ia32_registers[REG_GP_NOREG]);
150 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
152 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
153 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
154 &ia32_registers[REG_VFP_NOREG]);
157 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
159 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
160 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
161 &ia32_registers[REG_XMM_NOREG]);
164 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
166 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
167 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
168 &ia32_registers[REG_FPCW]);
173 * Returns the admissible noreg register node for input register pos of node irn.
175 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
177 ir_graph *irg = get_irn_irg(irn);
178 const arch_register_req_t *req = arch_get_register_req(irn, pos);
180 assert(req != NULL && "Missing register requirements");
181 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
182 return ia32_new_NoReg_gp(irg);
184 if (ia32_cg_config.use_sse2) {
185 return ia32_new_NoReg_xmm(irg);
187 return ia32_new_NoReg_vfp(irg);
191 static arch_irn_class_t ia32_classify(const ir_node *irn)
193 arch_irn_class_t classification = arch_irn_class_none;
195 assert(is_ia32_irn(irn));
197 if (is_ia32_is_reload(irn))
198 classification |= arch_irn_class_reload;
200 if (is_ia32_is_spill(irn))
201 classification |= arch_irn_class_spill;
203 if (is_ia32_is_remat(irn))
204 classification |= arch_irn_class_remat;
206 return classification;
210 * The IA32 ABI callback object.
213 be_abi_call_flags_bits_t flags; /**< The call flags. */
214 ir_graph *irg; /**< The associated graph. */
217 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
219 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
222 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
224 if (is_be_node(node))
225 be_node_set_frame_entity(node, entity);
227 set_ia32_frame_ent(node, entity);
230 static void ia32_set_frame_offset(ir_node *irn, int bias)
232 if (get_ia32_frame_ent(irn) == NULL)
235 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
236 ir_graph *irg = get_irn_irg(irn);
237 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
238 if (layout->sp_relative) {
239 /* Pop nodes modify the stack pointer before calculating the
240 * destination address, so fix this here
245 add_ia32_am_offs_int(irn, bias);
248 static int ia32_get_sp_bias(const ir_node *node)
250 if (is_ia32_Call(node))
251 return -(int)get_ia32_call_attr_const(node)->pop;
253 if (is_ia32_Push(node))
256 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
259 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
260 return SP_BIAS_RESET;
267 * Build the between type and entities if not already build.
269 static void ia32_build_between_type(void)
271 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
272 if (! between_type) {
273 ir_type *old_bp_type = new_type_primitive(mode_Iu);
274 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
276 between_type = new_type_struct(IDENT("ia32_between_type"));
277 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
278 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
280 set_entity_offset(old_bp_ent, 0);
281 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
282 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
283 set_type_state(between_type, layout_fixed);
285 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
286 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
288 set_entity_offset(omit_fp_ret_addr_ent, 0);
289 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
290 set_type_state(omit_fp_between_type, layout_fixed);
296 * Produces the type which sits between the stack args and the locals on the stack.
297 * it will contain the return address and space to store the old base pointer.
298 * @return The Firm type modeling the ABI between type.
300 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
302 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
303 ia32_build_between_type();
304 return layout->sp_relative ? omit_fp_between_type : between_type;
308 * Return the stack entity that contains the return address.
310 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
312 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
313 ia32_build_between_type();
314 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
318 * Return the stack entity that contains the frame address.
320 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
322 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
323 ia32_build_between_type();
324 return layout->sp_relative ? NULL : old_bp_ent;
328 * Get the estimated cycle count for @p irn.
330 * @param self The this pointer.
331 * @param irn The node.
333 * @return The estimated cycle count for this operation
335 static int ia32_get_op_estimated_cost(const ir_node *irn)
338 ia32_op_type_t op_tp;
342 if (!is_ia32_irn(irn))
345 assert(is_ia32_irn(irn));
347 cost = get_ia32_latency(irn);
348 op_tp = get_ia32_op_type(irn);
350 if (is_ia32_CopyB(irn)) {
353 else if (is_ia32_CopyB_i(irn)) {
354 int size = get_ia32_copyb_size(irn);
355 cost = 20 + (int)ceil((4/3) * size);
357 /* in case of address mode operations add additional cycles */
358 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
360 In case of stack access and access to fixed addresses add 5 cycles
361 (we assume they are in cache), other memory operations cost 20
364 if (is_ia32_use_frame(irn) || (
365 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
366 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
378 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
380 * @param irn The original operation
381 * @param i Index of the argument we want the inverse operation to yield
382 * @param inverse struct to be filled with the resulting inverse op
383 * @param obstack The obstack to use for allocation of the returned nodes array
384 * @return The inverse operation or NULL if operation invertible
386 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
397 ir_node *block, *noreg, *nomem;
400 /* we cannot invert non-ia32 irns */
401 if (! is_ia32_irn(irn))
404 /* operand must always be a real operand (not base, index or mem) */
405 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
408 /* we don't invert address mode operations */
409 if (get_ia32_op_type(irn) != ia32_Normal)
412 /* TODO: adjust for new immediates... */
413 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
417 block = get_nodes_block(irn);
418 mode = get_irn_mode(irn);
419 irn_mode = get_irn_mode(irn);
420 noreg = get_irn_n(irn, 0);
421 nomem = get_irg_no_mem(irg);
422 dbg = get_irn_dbg_info(irn);
424 /* initialize structure */
425 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
429 switch (get_ia32_irn_opcode(irn)) {
431 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
432 /* we have an add with a const here */
433 /* invers == add with negated const */
434 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
436 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
437 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
438 set_ia32_commutative(inverse->nodes[0]);
440 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
441 /* we have an add with a symconst here */
442 /* invers == sub with const */
443 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
445 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
448 /* normal add: inverse == sub */
449 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
454 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
455 /* we have a sub with a const/symconst here */
456 /* invers == add with this const */
457 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
458 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
459 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
463 if (i == n_ia32_binary_left) {
464 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
467 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
473 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
474 /* xor with const: inverse = xor */
475 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
476 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
477 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
481 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
486 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
491 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
496 /* inverse operation not supported */
504 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
506 if (mode_is_float(mode))
513 * Get the mode that should be used for spilling value node
515 static ir_mode *get_spill_mode(const ir_node *node)
517 ir_mode *mode = get_irn_mode(node);
518 return get_spill_mode_mode(mode);
522 * Checks whether an addressmode reload for a node with mode mode is compatible
523 * with a spillslot of mode spill_mode
525 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
527 return !mode_is_float(mode) || mode == spillmode;
531 * Check if irn can load its operand at position i from memory (source addressmode).
532 * @param irn The irn to be checked
533 * @param i The operands position
534 * @return Non-Zero if operand can be loaded
536 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
538 ir_node *op = get_irn_n(irn, i);
539 const ir_mode *mode = get_irn_mode(op);
540 const ir_mode *spillmode = get_spill_mode(op);
542 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
543 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
544 !ia32_is_spillmode_compatible(mode, spillmode) ||
545 is_ia32_use_frame(irn)) /* must not already use frame */
548 switch (get_ia32_am_support(irn)) {
553 if (i != n_ia32_unary_op)
559 case n_ia32_binary_left: {
560 const arch_register_req_t *req;
561 if (!is_ia32_commutative(irn))
564 /* we can't swap left/right for limited registers
565 * (As this (currently) breaks constraint handling copies)
567 req = arch_get_in_register_req(irn, n_ia32_binary_left);
568 if (req->type & arch_register_req_type_limited)
573 case n_ia32_binary_right:
582 panic("Unknown AM type");
585 /* HACK: must not already use "real" memory.
586 * This can happen for Call and Div */
587 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
593 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
597 ir_mode *dest_op_mode;
599 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
601 set_ia32_op_type(irn, ia32_AddrModeS);
603 load_mode = get_irn_mode(get_irn_n(irn, i));
604 dest_op_mode = get_ia32_ls_mode(irn);
605 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
606 set_ia32_ls_mode(irn, load_mode);
608 set_ia32_use_frame(irn);
609 set_ia32_need_stackent(irn);
611 if (i == n_ia32_binary_left &&
612 get_ia32_am_support(irn) == ia32_am_binary &&
613 /* immediates are only allowed on the right side */
614 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
615 ia32_swap_left_right(irn);
616 i = n_ia32_binary_right;
619 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
621 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
622 set_irn_n(irn, n_ia32_mem, spill);
623 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
624 set_ia32_is_reload(irn);
627 static const be_abi_callbacks_t ia32_abi_callbacks = {
628 ia32_abi_get_between_type,
631 /* register allocator interface */
632 static const arch_irn_ops_t ia32_irn_ops = {
634 ia32_get_frame_entity,
635 ia32_set_frame_offset,
638 ia32_get_op_estimated_cost,
639 ia32_possible_memory_operand,
640 ia32_perform_memory_operand,
643 static ir_entity *mcount = NULL;
644 static int gprof = 0;
646 static void ia32_before_abi(ir_graph *irg)
649 if (mcount == NULL) {
650 ir_type *tp = new_type_method(0, 0);
651 ident *id = new_id_from_str("mcount");
652 mcount = new_entity(get_glob_type(), id, tp);
653 /* FIXME: enter the right ld_ident here */
654 set_entity_ld_ident(mcount, get_entity_ident(mcount));
655 set_entity_visibility(mcount, ir_visibility_external);
657 instrument_initcall(irg, mcount);
662 * Transforms the standard firm graph into
665 static void ia32_prepare_graph(ir_graph *irg)
667 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
670 switch (be_transformer) {
671 case TRANSFORMER_DEFAULT:
672 /* transform remaining nodes into assembler instructions */
673 ia32_transform_graph(irg);
676 case TRANSFORMER_PBQP:
677 case TRANSFORMER_RAND:
678 /* transform nodes into assembler instructions by PBQP magic */
679 ia32_transform_graph_by_pbqp(irg);
683 panic("invalid transformer");
686 ia32_transform_graph(irg);
689 /* do local optimizations (mainly CSE) */
690 optimize_graph_df(irg);
693 dump_ir_graph(irg, "transformed");
695 /* optimize address mode */
696 ia32_optimize_graph(irg);
698 /* do code placement, to optimize the position of constants */
702 dump_ir_graph(irg, "place");
705 ir_node *ia32_turn_back_am(ir_node *node)
707 dbg_info *dbgi = get_irn_dbg_info(node);
708 ir_graph *irg = get_irn_irg(node);
709 ir_node *block = get_nodes_block(node);
710 ir_node *base = get_irn_n(node, n_ia32_base);
711 ir_node *index = get_irn_n(node, n_ia32_index);
712 ir_node *mem = get_irn_n(node, n_ia32_mem);
715 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
716 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
718 ia32_copy_am_attrs(load, node);
719 if (is_ia32_is_reload(node))
720 set_ia32_is_reload(load);
721 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
723 switch (get_ia32_am_support(node)) {
725 set_irn_n(node, n_ia32_unary_op, load_res);
729 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
730 set_irn_n(node, n_ia32_binary_left, load_res);
732 set_irn_n(node, n_ia32_binary_right, load_res);
737 panic("Unknown AM type");
739 noreg = ia32_new_NoReg_gp(current_ir_graph);
740 set_irn_n(node, n_ia32_base, noreg);
741 set_irn_n(node, n_ia32_index, noreg);
742 set_ia32_am_offs_int(node, 0);
743 set_ia32_am_sc(node, NULL);
744 set_ia32_am_scale(node, 0);
745 clear_ia32_am_sc_sign(node);
747 /* rewire mem-proj */
748 if (get_irn_mode(node) == mode_T) {
749 const ir_edge_t *edge;
750 foreach_out_edge(node, edge) {
751 ir_node *out = get_edge_src_irn(edge);
752 if (get_irn_mode(out) == mode_M) {
753 set_Proj_pred(out, load);
754 set_Proj_proj(out, pn_ia32_Load_M);
760 set_ia32_op_type(node, ia32_Normal);
761 if (sched_is_scheduled(node))
762 sched_add_before(node, load);
767 static ir_node *flags_remat(ir_node *node, ir_node *after)
769 /* we should turn back source address mode when rematerializing nodes */
774 if (is_Block(after)) {
777 block = get_nodes_block(after);
780 type = get_ia32_op_type(node);
783 ia32_turn_back_am(node);
787 /* TODO implement this later... */
788 panic("found DestAM with flag user %+F this should not happen", node);
791 default: assert(type == ia32_Normal); break;
794 copy = exact_copy(node);
795 set_nodes_block(copy, block);
796 sched_add_after(after, copy);
802 * Called before the register allocator.
804 static void ia32_before_ra(ir_graph *irg)
806 /* setup fpu rounding modes */
807 ia32_setup_fpu_mode(irg);
810 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
813 be_add_missing_keeps(irg);
818 * Transforms a be_Reload into a ia32 Load.
820 static void transform_to_Load(ir_node *node)
822 ir_graph *irg = get_irn_irg(node);
823 dbg_info *dbg = get_irn_dbg_info(node);
824 ir_node *block = get_nodes_block(node);
825 ir_entity *ent = be_get_frame_entity(node);
826 ir_mode *mode = get_irn_mode(node);
827 ir_mode *spillmode = get_spill_mode(node);
828 ir_node *noreg = ia32_new_NoReg_gp(irg);
829 ir_node *sched_point = NULL;
830 ir_node *ptr = get_irg_frame(irg);
831 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
832 ir_node *new_op, *proj;
833 const arch_register_t *reg;
835 if (sched_is_scheduled(node)) {
836 sched_point = sched_prev(node);
839 if (mode_is_float(spillmode)) {
840 if (ia32_cg_config.use_sse2)
841 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
843 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
845 else if (get_mode_size_bits(spillmode) == 128) {
846 /* Reload 128 bit SSE registers */
847 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
850 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
852 set_ia32_op_type(new_op, ia32_AddrModeS);
853 set_ia32_ls_mode(new_op, spillmode);
854 set_ia32_frame_ent(new_op, ent);
855 set_ia32_use_frame(new_op);
856 set_ia32_is_reload(new_op);
858 DBG_OPT_RELOAD2LD(node, new_op);
860 proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
863 sched_add_after(sched_point, new_op);
867 /* copy the register from the old node to the new Load */
868 reg = arch_get_irn_register(node);
869 arch_set_irn_register(proj, reg);
871 SET_IA32_ORIG_NODE(new_op, node);
873 exchange(node, proj);
877 * Transforms a be_Spill node into a ia32 Store.
879 static void transform_to_Store(ir_node *node)
881 ir_graph *irg = get_irn_irg(node);
882 dbg_info *dbg = get_irn_dbg_info(node);
883 ir_node *block = get_nodes_block(node);
884 ir_entity *ent = be_get_frame_entity(node);
885 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
886 ir_mode *mode = get_spill_mode(spillval);
887 ir_node *noreg = ia32_new_NoReg_gp(irg);
888 ir_node *nomem = get_irg_no_mem(irg);
889 ir_node *ptr = get_irg_frame(irg);
890 ir_node *val = get_irn_n(node, n_be_Spill_val);
892 ir_node *sched_point = NULL;
894 if (sched_is_scheduled(node)) {
895 sched_point = sched_prev(node);
898 if (mode_is_float(mode)) {
899 if (ia32_cg_config.use_sse2)
900 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
902 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
903 } else if (get_mode_size_bits(mode) == 128) {
904 /* Spill 128 bit SSE registers */
905 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
906 } else if (get_mode_size_bits(mode) == 8) {
907 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
909 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
912 set_ia32_op_type(store, ia32_AddrModeD);
913 set_ia32_ls_mode(store, mode);
914 set_ia32_frame_ent(store, ent);
915 set_ia32_use_frame(store);
916 set_ia32_is_spill(store);
917 SET_IA32_ORIG_NODE(store, node);
918 DBG_OPT_SPILL2ST(node, store);
921 sched_add_after(sched_point, store);
925 exchange(node, store);
928 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
930 dbg_info *dbg = get_irn_dbg_info(node);
931 ir_node *block = get_nodes_block(node);
932 ir_graph *irg = get_irn_irg(node);
933 ir_node *noreg = ia32_new_NoReg_gp(irg);
934 ir_node *frame = get_irg_frame(irg);
936 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
938 set_ia32_frame_ent(push, ent);
939 set_ia32_use_frame(push);
940 set_ia32_op_type(push, ia32_AddrModeS);
941 set_ia32_ls_mode(push, mode_Is);
942 set_ia32_is_spill(push);
944 sched_add_before(schedpoint, push);
948 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
950 dbg_info *dbg = get_irn_dbg_info(node);
951 ir_node *block = get_nodes_block(node);
952 ir_graph *irg = get_irn_irg(node);
953 ir_node *noreg = ia32_new_NoReg_gp(irg);
954 ir_node *frame = get_irg_frame(irg);
956 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg,
957 get_irg_no_mem(irg), sp);
959 set_ia32_frame_ent(pop, ent);
960 set_ia32_use_frame(pop);
961 set_ia32_op_type(pop, ia32_AddrModeD);
962 set_ia32_ls_mode(pop, mode_Is);
963 set_ia32_is_reload(pop);
965 sched_add_before(schedpoint, pop);
970 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
972 dbg_info *dbg = get_irn_dbg_info(node);
973 ir_mode *spmode = mode_Iu;
974 const arch_register_t *spreg = &ia32_registers[REG_ESP];
977 sp = new_rd_Proj(dbg, pred, spmode, pos);
978 arch_set_irn_register(sp, spreg);
984 * Transform MemPerm, currently we do this the ugly way and produce
985 * push/pop into/from memory cascades. This is possible without using
988 static void transform_MemPerm(ir_node *node)
990 ir_node *block = get_nodes_block(node);
991 ir_graph *irg = get_irn_irg(node);
992 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
993 int arity = be_get_MemPerm_entity_arity(node);
994 ir_node **pops = ALLOCAN(ir_node*, arity);
998 const ir_edge_t *edge;
999 const ir_edge_t *next;
1002 for (i = 0; i < arity; ++i) {
1003 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1004 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1005 ir_type *enttype = get_entity_type(inent);
1006 unsigned entsize = get_type_size_bytes(enttype);
1007 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1008 ir_node *mem = get_irn_n(node, i + 1);
1011 /* work around cases where entities have different sizes */
1012 if (entsize2 < entsize)
1014 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1016 push = create_push(node, node, sp, mem, inent);
1017 sp = create_spproj(node, push, pn_ia32_Push_stack);
1019 /* add another push after the first one */
1020 push = create_push(node, node, sp, mem, inent);
1021 add_ia32_am_offs_int(push, 4);
1022 sp = create_spproj(node, push, pn_ia32_Push_stack);
1025 set_irn_n(node, i, new_r_Bad(irg));
1029 for (i = arity - 1; i >= 0; --i) {
1030 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1031 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1032 ir_type *enttype = get_entity_type(outent);
1033 unsigned entsize = get_type_size_bytes(enttype);
1034 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1037 /* work around cases where entities have different sizes */
1038 if (entsize2 < entsize)
1040 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1042 pop = create_pop(node, node, sp, outent);
1043 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1045 add_ia32_am_offs_int(pop, 4);
1047 /* add another pop after the first one */
1048 pop = create_pop(node, node, sp, outent);
1049 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1056 keep = be_new_Keep(block, 1, in);
1057 sched_add_before(node, keep);
1059 /* exchange memprojs */
1060 foreach_out_edge_safe(node, edge, next) {
1061 ir_node *proj = get_edge_src_irn(edge);
1062 int p = get_Proj_proj(proj);
1066 set_Proj_pred(proj, pops[p]);
1067 set_Proj_proj(proj, pn_ia32_Pop_M);
1070 /* remove memperm */
1071 arity = get_irn_arity(node);
1072 for (i = 0; i < arity; ++i) {
1073 set_irn_n(node, i, new_r_Bad(irg));
1079 * Block-Walker: Calls the transform functions Spill and Reload.
1081 static void ia32_after_ra_walker(ir_node *block, void *env)
1083 ir_node *node, *prev;
1086 /* beware: the schedule is changed here */
1087 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1088 prev = sched_prev(node);
1090 if (be_is_Reload(node)) {
1091 transform_to_Load(node);
1092 } else if (be_is_Spill(node)) {
1093 transform_to_Store(node);
1094 } else if (be_is_MemPerm(node)) {
1095 transform_MemPerm(node);
1101 * Collects nodes that need frame entities assigned.
1103 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1105 be_fec_env_t *env = (be_fec_env_t*)data;
1106 const ir_mode *mode;
1109 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1110 mode = get_spill_mode_mode(get_irn_mode(node));
1111 align = get_mode_size_bytes(mode);
1112 } else if (is_ia32_irn(node) &&
1113 get_ia32_frame_ent(node) == NULL &&
1114 is_ia32_use_frame(node)) {
1115 if (is_ia32_need_stackent(node))
1118 switch (get_ia32_irn_opcode(node)) {
1120 case iro_ia32_Load: {
1121 const ia32_attr_t *attr = get_ia32_attr_const(node);
1123 if (attr->data.need_32bit_stackent) {
1125 } else if (attr->data.need_64bit_stackent) {
1128 mode = get_ia32_ls_mode(node);
1129 if (is_ia32_is_reload(node))
1130 mode = get_spill_mode_mode(mode);
1132 align = get_mode_size_bytes(mode);
1136 case iro_ia32_vfild:
1138 case iro_ia32_xLoad: {
1139 mode = get_ia32_ls_mode(node);
1144 case iro_ia32_FldCW: {
1145 /* although 2 byte would be enough 4 byte performs best */
1153 panic("unexpected frame user while collection frame entity nodes");
1155 case iro_ia32_FnstCW:
1156 case iro_ia32_Store8Bit:
1157 case iro_ia32_Store:
1160 case iro_ia32_vfist:
1161 case iro_ia32_vfisttp:
1163 case iro_ia32_xStore:
1164 case iro_ia32_xStoreSimple:
1171 be_node_needs_frame_entity(env, node, mode, align);
1174 static int determine_ebp_input(ir_node *ret)
1176 const arch_register_t *bp = &ia32_registers[REG_EBP];
1177 int arity = get_irn_arity(ret);
1180 for (i = 0; i < arity; ++i) {
1181 ir_node *input = get_irn_n(ret, i);
1182 if (arch_get_irn_register(input) == bp)
1185 panic("no ebp input found at %+F", ret);
1188 static void introduce_epilog(ir_node *ret)
1190 const arch_register_t *sp = &ia32_registers[REG_ESP];
1191 const arch_register_t *bp = &ia32_registers[REG_EBP];
1192 ir_graph *irg = get_irn_irg(ret);
1193 ir_type *frame_type = get_irg_frame_type(irg);
1194 unsigned frame_size = get_type_size_bytes(frame_type);
1195 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1196 ir_node *block = get_nodes_block(ret);
1197 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1198 ir_node *curr_sp = first_sp;
1199 ir_mode *mode_gp = mode_Iu;
1201 if (!layout->sp_relative) {
1202 int n_ebp = determine_ebp_input(ret);
1203 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1204 if (ia32_cg_config.use_leave) {
1205 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1206 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1207 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1208 arch_set_irn_register(curr_bp, bp);
1209 arch_set_irn_register(curr_sp, sp);
1210 sched_add_before(ret, leave);
1213 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1214 /* copy ebp to esp */
1215 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1216 arch_set_irn_register(curr_sp, sp);
1217 sched_add_before(ret, curr_sp);
1220 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1221 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1222 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1223 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1224 arch_set_irn_register(curr_bp, bp);
1225 arch_set_irn_register(curr_sp, sp);
1226 sched_add_before(ret, pop);
1228 set_irn_n(ret, n_be_Return_mem, curr_mem);
1230 set_irn_n(ret, n_ebp, curr_bp);
1232 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1233 sched_add_before(ret, incsp);
1236 set_irn_n(ret, n_be_Return_sp, curr_sp);
1238 /* keep verifier happy... */
1239 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1240 kill_node(first_sp);
1245 * put the Prolog code at the beginning, epilog code before each return
1247 static void introduce_prolog_epilog(ir_graph *irg)
1249 const arch_register_t *sp = &ia32_registers[REG_ESP];
1250 const arch_register_t *bp = &ia32_registers[REG_EBP];
1251 ir_node *start = get_irg_start(irg);
1252 ir_node *block = get_nodes_block(start);
1253 ir_type *frame_type = get_irg_frame_type(irg);
1254 unsigned frame_size = get_type_size_bytes(frame_type);
1255 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1256 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1257 ir_node *curr_sp = initial_sp;
1258 ir_mode *mode_gp = mode_Iu;
1260 if (!layout->sp_relative) {
1262 ir_node *mem = get_irg_initial_mem(irg);
1263 ir_node *noreg = ia32_new_NoReg_gp(irg);
1264 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1265 ir_node *curr_bp = initial_bp;
1266 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
1269 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1270 mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
1271 arch_set_irn_register(curr_sp, sp);
1272 sched_add_after(start, push);
1274 /* move esp to ebp */
1275 curr_bp = be_new_Copy(bp->reg_class, block, curr_sp);
1276 sched_add_after(push, curr_bp);
1277 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1278 curr_sp = be_new_CopyKeep_single(sp->reg_class, block, curr_sp, curr_bp, mode_gp);
1279 sched_add_after(curr_bp, curr_sp);
1280 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1281 edges_reroute(initial_bp, curr_bp);
1282 set_irn_n(push, n_ia32_Push_val, initial_bp);
1284 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1285 edges_reroute(initial_sp, incsp);
1286 set_irn_n(push, n_ia32_Push_stack, initial_sp);
1287 sched_add_after(curr_sp, incsp);
1289 layout->initial_bias = -4;
1291 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1292 edges_reroute(initial_sp, incsp);
1293 be_set_IncSP_pred(incsp, curr_sp);
1294 sched_add_after(start, incsp);
1297 /* introduce epilog for every return node */
1299 ir_node *end_block = get_irg_end_block(irg);
1300 int arity = get_irn_arity(end_block);
1303 for (i = 0; i < arity; ++i) {
1304 ir_node *ret = get_irn_n(end_block, i);
1305 assert(be_is_Return(ret));
1306 introduce_epilog(ret);
1312 * We transform Spill and Reload here. This needs to be done before
1313 * stack biasing otherwise we would miss the corrected offset for these nodes.
1315 static void ia32_after_ra(ir_graph *irg)
1317 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1318 bool at_begin = stack_layout->sp_relative ? true : false;
1319 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1321 /* create and coalesce frame entities */
1322 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1323 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1324 be_free_frame_entity_coalescer(fec_env);
1326 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1328 introduce_prolog_epilog(irg);
1332 * Last touchups for the graph before emit: x87 simulation to replace the
1333 * virtual with real x87 instructions, creating a block schedule and peephole
1336 static void ia32_finish(ir_graph *irg)
1338 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1340 ia32_finish_irg(irg);
1342 /* we might have to rewrite x87 virtual registers */
1343 if (irg_data->do_x87_sim) {
1344 ia32_x87_simulate_graph(irg);
1347 /* do peephole optimisations */
1348 ia32_peephole_optimization(irg);
1350 /* create block schedule, this also removes empty blocks which might
1351 * produce critical edges */
1352 irg_data->blk_sched = be_create_block_schedule(irg);
1356 * Emits the code, closes the output file and frees
1357 * the code generator interface.
1359 static void ia32_emit(ir_graph *irg)
1361 if (ia32_cg_config.emit_machcode) {
1362 ia32_gen_binary_routine(irg);
1364 ia32_gen_routine(irg);
1369 * Returns the node representing the PIC base.
1371 static ir_node *ia32_get_pic_base(ir_graph *irg)
1373 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1375 ir_node *get_eip = irg_data->get_eip;
1376 if (get_eip != NULL)
1379 block = get_irg_start_block(irg);
1380 get_eip = new_bd_ia32_GetEIP(NULL, block);
1381 irg_data->get_eip = get_eip;
1387 * Initializes a IA32 code generator.
1389 static void ia32_init_graph(ir_graph *irg)
1391 struct obstack *obst = be_get_be_obst(irg);
1392 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1394 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1397 /* Linux gprof implementation needs base pointer */
1398 be_get_irg_options(irg)->omit_fp = 0;
1401 be_birg_from_irg(irg)->isa_link = irg_data;
1406 * Set output modes for GCC
1408 static const tarval_mode_info mo_integer = {
1415 * set the tarval output mode of all integer modes to decimal
1417 static void set_tarval_output_modes(void)
1421 for (i = get_irp_n_modes(); i > 0;) {
1422 ir_mode *mode = get_irp_mode(--i);
1424 if (mode_is_int(mode))
1425 set_tarval_mode_output_option(mode, &mo_integer);
1429 extern const arch_isa_if_t ia32_isa_if;
1432 * The template that generates a new ISA object.
1433 * Note that this template can be changed by command line
1436 static ia32_isa_t ia32_isa_template = {
1438 &ia32_isa_if, /* isa interface implementation */
1443 &ia32_registers[REG_ESP], /* stack pointer register */
1444 &ia32_registers[REG_EBP], /* base pointer register */
1445 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1446 2, /* power of two stack alignment, 2^2 == 4 */
1447 NULL, /* main environment */
1448 7, /* costs for a spill instruction */
1449 5, /* costs for a reload instruction */
1450 false, /* no custom abi handling */
1454 NULL, /* abstract machine */
1457 static void init_asm_constraints(void)
1459 be_init_default_asm_constraint_flags();
1461 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1462 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1463 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1464 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1465 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1466 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1467 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1468 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1469 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1470 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1471 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1472 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1473 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1474 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1475 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1476 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1477 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1478 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1479 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1480 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1482 /* no support for autodecrement/autoincrement */
1483 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1484 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1485 /* no float consts */
1486 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1487 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1488 /* makes no sense on x86 */
1489 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1490 /* no support for sse consts yet */
1491 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1492 /* no support for x87 consts yet */
1493 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1494 /* no support for mmx registers yet */
1495 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1496 /* not available in 32bit mode */
1497 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1498 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1500 /* no code yet to determine register class needed... */
1501 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1505 * Initializes the backend ISA.
1507 static arch_env_t *ia32_init(FILE *file_handle)
1509 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1511 set_tarval_output_modes();
1513 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1515 if (ia32_mode_fpcw == NULL) {
1516 ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1519 ia32_register_init();
1520 ia32_create_opcodes(&ia32_irn_ops);
1522 be_emit_init(file_handle);
1523 isa->types = pmap_create();
1524 isa->tv_ent = pmap_create();
1525 isa->cpu = ia32_init_machine_description();
1527 /* enter the ISA object into the intrinsic environment */
1528 intrinsic_env.isa = isa;
1536 * Closes the output file and frees the ISA structure.
1538 static void ia32_done(void *self)
1540 ia32_isa_t *isa = (ia32_isa_t*)self;
1542 /* emit now all global declarations */
1543 be_gas_emit_decls(isa->base.main_env);
1545 pmap_destroy(isa->tv_ent);
1546 pmap_destroy(isa->types);
1555 * Get the register class which shall be used to store a value of a given mode.
1556 * @param self The this pointer.
1557 * @param mode The mode in question.
1558 * @return A register class which can hold values of the given mode.
1560 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1562 if (mode_is_float(mode)) {
1563 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1566 return &ia32_reg_classes[CLASS_ia32_gp];
1570 * Returns the register for parameter nr.
1572 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1573 const ir_mode *mode)
1575 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1576 &ia32_registers[REG_ECX],
1577 &ia32_registers[REG_EDX],
1580 static const unsigned MAXNUM_GPREG_ARGS = 3;
1582 static const arch_register_t *gpreg_param_reg_regparam[] = {
1583 &ia32_registers[REG_EAX],
1584 &ia32_registers[REG_EDX],
1585 &ia32_registers[REG_ECX]
1588 static const arch_register_t *gpreg_param_reg_this[] = {
1589 &ia32_registers[REG_ECX],
1594 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1595 &ia32_registers[REG_XMM0],
1596 &ia32_registers[REG_XMM1],
1597 &ia32_registers[REG_XMM2],
1598 &ia32_registers[REG_XMM3],
1599 &ia32_registers[REG_XMM4],
1600 &ia32_registers[REG_XMM5],
1601 &ia32_registers[REG_XMM6],
1602 &ia32_registers[REG_XMM7]
1605 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1606 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1608 static const unsigned MAXNUM_SSE_ARGS = 8;
1610 if ((cc & cc_this_call) && nr == 0)
1611 return gpreg_param_reg_this[0];
1613 if (! (cc & cc_reg_param))
1616 if (mode_is_float(mode)) {
1617 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1619 if (nr >= MAXNUM_SSE_ARGS)
1622 if (cc & cc_this_call) {
1623 return fpreg_sse_param_reg_this[nr];
1625 return fpreg_sse_param_reg_std[nr];
1626 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1627 unsigned num_regparam;
1629 if (get_mode_size_bits(mode) > 32)
1632 if (nr >= MAXNUM_GPREG_ARGS)
1635 if (cc & cc_this_call) {
1636 return gpreg_param_reg_this[nr];
1638 num_regparam = cc & ~cc_bits;
1639 if (num_regparam == 0) {
1640 /* default fastcall */
1641 return gpreg_param_reg_fastcall[nr];
1643 if (nr < num_regparam)
1644 return gpreg_param_reg_regparam[nr];
1648 panic("unknown argument mode");
1652 * Get the ABI restrictions for procedure calls.
1653 * @param self The this pointer.
1654 * @param method_type The type of the method (procedure) in question.
1655 * @param abi The abi object to be modified
1657 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1665 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1669 /* set abi flags for calls */
1670 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1671 call_flags.bits.store_args_sequential = 0;
1672 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1673 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1674 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1676 /* set parameter passing style */
1677 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1679 cc = get_method_calling_convention(method_type);
1680 if (get_method_variadicity(method_type) == variadicity_variadic) {
1681 /* pass all parameters of a variadic function on the stack */
1682 cc = cc_cdecl_set | (cc & cc_this_call);
1684 if (get_method_additional_properties(method_type) & mtp_property_private &&
1685 ia32_cg_config.optimize_cc) {
1686 /* set the fast calling conventions (allowing up to 3) */
1687 cc = SET_FASTCALL(cc) | 3;
1691 /* we have to pop the shadow parameter ourself for compound calls */
1692 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1693 && !(cc & cc_reg_param)) {
1694 pop_amount += get_mode_size_bytes(mode_P_data);
1697 n = get_method_n_params(method_type);
1698 for (i = regnum = 0; i < n; i++) {
1700 const arch_register_t *reg = NULL;
1702 tp = get_method_param_type(method_type, i);
1703 mode = get_type_mode(tp);
1705 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1708 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1711 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1712 * movl has a shorter opcode than mov[sz][bw]l */
1713 ir_mode *load_mode = mode;
1716 unsigned size = get_mode_size_bytes(mode);
1718 if (cc & cc_callee_clear_stk) {
1719 pop_amount += (size + 3U) & ~3U;
1722 if (size < 4) load_mode = mode_Iu;
1725 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1729 be_abi_call_set_pop(abi, pop_amount);
1731 /* set return registers */
1732 n = get_method_n_ress(method_type);
1734 assert(n <= 2 && "more than two results not supported");
1736 /* In case of 64bit returns, we will have two 32bit values */
1738 tp = get_method_res_type(method_type, 0);
1739 mode = get_type_mode(tp);
1741 assert(!mode_is_float(mode) && "two FP results not supported");
1743 tp = get_method_res_type(method_type, 1);
1744 mode = get_type_mode(tp);
1746 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1748 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1749 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1752 const arch_register_t *reg;
1754 tp = get_method_res_type(method_type, 0);
1755 assert(is_atomic_type(tp));
1756 mode = get_type_mode(tp);
1758 reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
1760 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1765 * Returns the necessary byte alignment for storing a register of given class.
1767 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1769 ir_mode *mode = arch_register_class_mode(cls);
1770 int bytes = get_mode_size_bytes(mode);
1772 if (mode_is_float(mode) && bytes > 8)
1778 * Return irp irgs in the desired order.
1780 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1787 static void ia32_mark_remat(ir_node *node)
1789 if (is_ia32_irn(node)) {
1790 set_ia32_is_remat(node);
1795 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1797 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1802 ir_relation relation;
1807 cmp_l = get_Cmp_left(sel);
1808 cmp_r = get_Cmp_right(sel);
1809 if (!mode_is_float(get_irn_mode(cmp_l)))
1812 /* check for min/max. They're defined as (C-Semantik):
1813 * min(a, b) = a < b ? a : b
1814 * or min(a, b) = a <= b ? a : b
1815 * max(a, b) = a > b ? a : b
1816 * or max(a, b) = a >= b ? a : b
1817 * (Note we only handle float min/max here)
1819 relation = get_Cmp_relation(sel);
1821 case ir_relation_greater_equal:
1822 case ir_relation_greater:
1824 if (cmp_l == mux_true && cmp_r == mux_false)
1827 case ir_relation_less_equal:
1828 case ir_relation_less:
1830 if (cmp_l == mux_true && cmp_r == mux_false)
1833 case ir_relation_unordered_greater_equal:
1834 case ir_relation_unordered_greater:
1836 if (cmp_l == mux_false && cmp_r == mux_true)
1839 case ir_relation_unordered_less_equal:
1840 case ir_relation_unordered_less:
1842 if (cmp_l == mux_false && cmp_r == mux_true)
1853 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1855 ir_mode *mode = get_irn_mode(mux_true);
1858 if (!mode_is_int(mode) && !mode_is_reference(mode)
1862 if (is_Const(mux_true) && is_Const(mux_false)) {
1863 /* we can create a set plus up two 3 instructions for any combination
1871 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1876 if (!mode_is_float(get_irn_mode(mux_true)))
1879 return is_Const(mux_true) && is_Const(mux_false);
1882 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1889 ir_relation relation;
1894 mode = get_irn_mode(mux_true);
1895 if (mode_is_signed(mode) || mode_is_float(mode))
1898 relation = get_Cmp_relation(sel);
1899 cmp_left = get_Cmp_left(sel);
1900 cmp_right = get_Cmp_right(sel);
1902 /* "move" zero constant to false input */
1903 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1904 ir_node *tmp = mux_false;
1905 mux_false = mux_true;
1907 relation = get_negated_relation(relation);
1909 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1911 if (!is_Sub(mux_true))
1913 sub_left = get_Sub_left(mux_true);
1914 sub_right = get_Sub_right(mux_true);
1916 /* Mux(a >=u b, 0, a-b) */
1917 if ((relation & ir_relation_greater)
1918 && sub_left == cmp_left && sub_right == cmp_right)
1920 /* Mux(a <=u b, 0, b-a) */
1921 if ((relation & ir_relation_less)
1922 && sub_left == cmp_right && sub_right == cmp_left)
1928 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1933 /* we can handle Set for all modes and compares */
1934 if (mux_is_set(sel, mux_true, mux_false))
1936 /* SSE has own min/max operations */
1937 if (ia32_cg_config.use_sse2
1938 && mux_is_float_min_max(sel, mux_true, mux_false))
1940 /* we can handle Mux(?, Const[f], Const[f]) */
1941 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1942 #ifdef FIRM_GRGEN_BE
1943 /* well, some code selectors can't handle it */
1944 if (be_transformer != TRANSFORMER_PBQP
1945 || be_transformer != TRANSFORMER_RAND)
1952 /* no support for 64bit inputs to cmov */
1953 mode = get_irn_mode(mux_true);
1954 if (get_mode_size_bits(mode) > 32)
1956 /* we can handle Abs for all modes and compares (except 64bit) */
1957 if (be_mux_is_abs(sel, mux_true, mux_false) != 0)
1959 /* we can't handle MuxF yet */
1960 if (mode_is_float(mode))
1963 if (mux_is_doz(sel, mux_true, mux_false))
1966 /* Check Cmp before the node */
1968 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1970 /* we can't handle 64bit compares */
1971 if (get_mode_size_bits(cmp_mode) > 32)
1974 /* we can't handle float compares */
1975 if (mode_is_float(cmp_mode))
1979 /* did we disable cmov generation? */
1980 if (!ia32_cg_config.use_cmov)
1983 /* we can use a cmov */
1987 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
1991 /* we already added all our simple flags to the flags modifier list in
1992 * init, so this flag we don't know. */
1993 return ASM_CONSTRAINT_FLAG_INVALID;
1996 static int ia32_is_valid_clobber(const char *clobber)
1998 return ia32_get_clobber_register(clobber) != NULL;
2001 static ir_node *ia32_create_set(ir_node *cond)
2003 /* ia32-set function produces 8-bit results which have to be converted */
2004 ir_node *set = ir_create_mux_set(cond, mode_Bu);
2005 ir_node *block = get_nodes_block(set);
2006 return new_r_Conv(block, set, mode_Iu);
2009 static void ia32_lower_for_target(void)
2011 size_t i, n_irgs = get_irp_n_irgs();
2012 lower_mode_b_config_t lower_mode_b_config = {
2013 mode_Iu, /* lowered mode */
2015 0, /* don't lower direct compares */
2017 lower_params_t params = {
2018 4, /* def_ptr_alignment */
2019 LF_COMPOUND_RETURN | LF_RETURN_HIDDEN, /* flags */
2020 ADD_HIDDEN_ALWAYS_IN_FRONT, /* hidden_params */
2021 NULL, /* find pointer type */
2022 NULL, /* ret_compound_in_regs */
2025 /* perform doubleword lowering */
2026 lwrdw_param_t lower_dw_params = {
2027 1, /* little endian */
2028 64, /* doubleword size */
2029 ia32_create_intrinsic_fkt,
2033 /* lower compound param handling */
2034 lower_calls_with_compounds(¶ms);
2036 lower_dw_ops(&lower_dw_params);
2038 for (i = 0; i < n_irgs; ++i) {
2039 ir_graph *irg = get_irp_irg(i);
2040 /* lower for mode_b stuff */
2041 ir_lower_mode_b(irg, &lower_mode_b_config);
2042 /* break up switches with wide ranges */
2043 lower_switch(irg, 256, true);
2048 * Create the trampoline code.
2050 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2052 ir_graph *irg = get_irn_irg(block);
2053 ir_node *p = trampoline;
2054 ir_mode *mode = get_irn_mode(p);
2058 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
2059 mem = new_r_Proj(st, mode_M, pn_Store_M);
2060 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2061 st = new_r_Store(block, mem, p, env, cons_none);
2062 mem = new_r_Proj(st, mode_M, pn_Store_M);
2063 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2065 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
2066 mem = new_r_Proj(st, mode_M, pn_Store_M);
2067 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2068 st = new_r_Store(block, mem, p, callee, cons_none);
2069 mem = new_r_Proj(st, mode_M, pn_Store_M);
2070 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2076 * Returns the libFirm configuration parameter for this backend.
2078 static const backend_params *ia32_get_libfirm_params(void)
2080 static const ir_settings_arch_dep_t ad = {
2081 1, /* also use subs */
2082 4, /* maximum shifts */
2083 63, /* maximum shift amount */
2084 ia32_evaluate_insn, /* evaluate the instruction sequence */
2086 1, /* allow Mulhs */
2087 1, /* allow Mulus */
2088 32, /* Mulh allowed up to 32 bit */
2090 static backend_params p = {
2091 1, /* support inline assembly */
2092 1, /* support Rotl nodes */
2093 0, /* little endian */
2094 NULL, /* will be set later */
2095 ia32_is_mux_allowed,
2096 NULL, /* float arithmetic mode, will be set below */
2097 12, /* size of trampoline code */
2098 4, /* alignment of trampoline code */
2099 ia32_create_trampoline_fkt,
2100 4 /* alignment of stack parameter */
2103 ia32_setup_cg_config();
2105 /* doesn't really belong here, but this is the earliest place the backend
2107 init_asm_constraints();
2110 if (! ia32_cg_config.use_sse2)
2111 p.mode_float_arithmetic = mode_E;
2115 static const lc_opt_enum_int_items_t gas_items[] = {
2116 { "elf", OBJECT_FILE_FORMAT_ELF },
2117 { "mingw", OBJECT_FILE_FORMAT_COFF },
2118 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2122 static lc_opt_enum_int_var_t gas_var = {
2123 (int*) &be_gas_object_file_format, gas_items
2126 #ifdef FIRM_GRGEN_BE
2127 static const lc_opt_enum_int_items_t transformer_items[] = {
2128 { "default", TRANSFORMER_DEFAULT },
2129 { "pbqp", TRANSFORMER_PBQP },
2130 { "random", TRANSFORMER_RAND },
2134 static lc_opt_enum_int_var_t transformer_var = {
2135 (int*)&be_transformer, transformer_items
2139 static const lc_opt_table_entry_t ia32_options[] = {
2140 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2141 #ifdef FIRM_GRGEN_BE
2142 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2144 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2145 &ia32_isa_template.base.stack_alignment),
2146 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2150 const arch_isa_if_t ia32_isa_if = {
2152 ia32_lower_for_target,
2154 ia32_handle_intrinsics,
2155 ia32_get_reg_class_for_mode,
2157 ia32_get_reg_class_alignment,
2158 ia32_get_libfirm_params,
2161 ia32_parse_asm_constraint,
2162 ia32_is_valid_clobber,
2165 ia32_get_pic_base, /* return node used as base in pic code addresses */
2166 ia32_before_abi, /* before abi introduce hook */
2168 ia32_before_ra, /* before register allocation hook */
2169 ia32_after_ra, /* after register allocation hook */
2170 ia32_finish, /* called before codegen */
2171 ia32_emit, /* emit && done */
2174 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2175 void be_init_arch_ia32(void)
2177 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2178 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2180 lc_opt_add_table(ia32_grp, ia32_options);
2181 be_register_isa_if("ia32", &ia32_isa_if);
2183 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2185 ia32_init_emitter();
2187 ia32_init_optimize();
2188 ia32_init_transform();
2190 ia32_init_architecture();