11 #include "pseudo_irg.h"
15 #include "iredges_t.h"
22 #include "../beabi.h" /* the general register allocator interface */
23 #include "../benode_t.h"
24 #include "../belower.h"
25 #include "../besched_t.h"
27 #include "bearch_ia32_t.h"
29 #include "ia32_new_nodes.h" /* ia32 nodes interface */
30 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
31 #include "ia32_gen_decls.h" /* interface declaration emitter */
32 #include "ia32_transform.h"
33 #include "ia32_emitter.h"
34 #include "ia32_map_regs.h"
35 #include "ia32_optimize.h"
37 #define DEBUG_MODULE "firm.be.ia32.isa"
40 static set *cur_reg_set = NULL;
43 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
45 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
46 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_XXX]);
49 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
50 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_fp_regs[REG_XXXX]);
53 /**************************************************
56 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
57 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
58 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
59 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
62 **************************************************/
64 static ir_node *my_skip_proj(const ir_node *n) {
71 * Return register requirements for an ia32 node.
72 * If the node returns a tuple (mode_T) then the proj's
73 * will be asked for this information.
75 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
76 const ia32_register_req_t *irn_req;
77 long node_pos = pos == -1 ? 0 : pos;
78 ir_mode *mode = get_irn_mode(irn);
79 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
80 const ia32_irn_ops_t *ops = self;
82 if (mode == mode_T || mode == mode_M) {
83 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
87 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
92 node_pos = ia32_translate_proj_pos(irn);
98 irn = my_skip_proj(irn);
100 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
103 if (is_ia32_irn(irn)) {
105 irn_req = get_ia32_in_req(irn, pos);
108 irn_req = get_ia32_out_req(irn, node_pos);
111 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
113 memcpy(req, &(irn_req->req), sizeof(*req));
115 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
116 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
117 req->other_same = get_irn_n(irn, irn_req->same_pos);
120 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
121 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
122 req->other_different = get_irn_n(irn, irn_req->different_pos);
126 /* treat Phi like Const with default requirements */
128 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
129 if (mode_is_float(mode))
130 memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req));
131 else if (mode_is_int(mode) || mode_is_reference(mode))
132 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
133 else if (mode == mode_T || mode == mode_M) {
134 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
138 assert(0 && "unsupported Phi-Mode");
141 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
149 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
153 pos = ia32_translate_proj_pos(irn);
154 irn = my_skip_proj(irn);
157 if (is_ia32_irn(irn)) {
158 const arch_register_t **slots;
160 slots = get_ia32_slots(irn);
164 ia32_set_firm_reg(irn, reg, cur_reg_set);
168 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
170 const arch_register_t *reg = NULL;
173 pos = ia32_translate_proj_pos(irn);
174 irn = my_skip_proj(irn);
177 if (is_ia32_irn(irn)) {
178 const arch_register_t **slots;
179 slots = get_ia32_slots(irn);
183 reg = ia32_get_firm_reg(irn, cur_reg_set);
189 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
190 irn = my_skip_proj(irn);
192 return arch_irn_class_branch;
193 else if (is_ia32_Call(irn))
194 return arch_irn_class_call;
195 else if (is_ia32_irn(irn))
196 return arch_irn_class_normal;
201 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
202 irn = my_skip_proj(irn);
203 if (is_ia32_irn(irn))
204 return get_ia32_flags(irn);
210 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn)
212 /* TODO: Implement */
216 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
217 if (is_ia32_use_frame(irn)) {
218 /* TODO: correct offset */
222 /* fill register allocator interface */
224 static const arch_irn_ops_if_t ia32_irn_ops_if = {
225 ia32_get_irn_reg_req,
230 ia32_get_frame_entity,
234 ia32_irn_ops_t ia32_irn_ops = {
241 /**************************************************
244 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
245 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
246 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
247 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
250 **************************************************/
253 * Transforms the standard firm graph into
256 static void ia32_prepare_graph(void *self) {
257 ia32_code_gen_t *cg = self;
259 irg_walk_blkwise_graph(cg->irg, ia32_place_consts, ia32_transform_node, cg);
260 dump_ir_block_graph_sched(cg->irg, "-transformed");
261 edges_deactivate(cg->irg);
262 edges_activate(cg->irg);
263 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
264 dump_ir_block_graph_sched(cg->irg, "-am");
270 * Stack reservation and StackParam lowering.
272 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
279 * Dummy functions for hooks we don't need but which must be filled.
281 static void ia32_before_sched(void *self) {
284 static void ia32_before_ra(void *self) {
289 * Creates a Store for a Spill
291 static ir_node *ia32_lower_spill(void *self, ir_node *spill) {
292 ia32_code_gen_t *cg = self;
293 ir_graph *irg = cg->irg;
294 dbg_info *dbg = get_irn_dbg_info(spill);
295 ir_node *block = get_nodes_block(spill);
296 ir_node *ptr = get_irg_frame(irg);
297 ir_node *val = be_get_Spill_context(spill);
298 ir_node *mem = new_rd_NoMem(irg);
299 ir_mode *mode = get_irn_mode(spill);
300 entity *ent = be_get_spill_entity(spill);
301 unsigned offs = get_entity_offset_bytes(ent);
302 ir_node *noreg, *res;
305 DB((cg->mod, LEVEL_1, "lower_spill: got offset %d for %+F\n", offs, ent));
307 if (mode_is_float(mode)) {
308 noreg = ia32_new_NoReg_fp(cg);
309 res = new_rd_ia32_fStore(dbg, irg, block, ptr, noreg, val, mem, mode);
312 noreg = ia32_new_NoReg_gp(cg);
313 res = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, mem, mode);
316 snprintf(buf, sizeof(buf), "%d", offs);
317 add_ia32_am_offs(res, buf);
323 * Create a Load for a Spill
325 static ir_node *ia32_lower_reload(void *self, ir_node *reload) {
326 ia32_code_gen_t *cg = self;
327 ir_graph *irg = cg->irg;
328 dbg_info *dbg = get_irn_dbg_info(reload);
329 ir_node *block = get_nodes_block(reload);
330 ir_node *ptr = get_irg_frame(irg);
331 ir_mode *mode = get_irn_mode(reload);
332 ir_node *pred = get_irn_n(reload, 0);
335 ir_node *noreg, *res;
337 /* Get the offset to Load from. It can either be a Spill or a Store. */
338 if (be_is_Spill(pred)) {
339 entity *ent = be_get_spill_entity(pred);
340 unsigned offs = get_entity_offset_bytes(ent);
341 DB((cg->mod, LEVEL_1, "lower_reload: got offset %d for %+F\n", offs, ent));
343 snprintf(buf, sizeof(buf), "%d", offs);
345 else if (is_ia32_Store(pred) || is_ia32_fStore(pred)) {
346 ofs = get_ia32_am_offs(pred);
347 strncpy(buf, ofs, sizeof(buf));
351 assert(0 && "unsupported Reload predecessor");
354 /* Create the Load */
355 if (mode_is_float(mode)) {
356 noreg = ia32_new_NoReg_fp(cg);
357 res = new_rd_ia32_fLoad(dbg, irg, block, ptr, noreg, pred, mode_T);
360 noreg = ia32_new_NoReg_gp(cg);
361 res = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, pred, mode_T);
365 add_ia32_am_offs(res, buf);
367 /* Return the result Proj */
368 return new_rd_Proj(dbg, irg, block, res, mode, 0);
372 * Emits the code, closes the output file and frees
373 * the code generator interface.
375 static void ia32_codegen(void *self) {
376 ia32_code_gen_t *cg = self;
377 ir_graph *irg = cg->irg;
380 if (cg->emit_decls) {
381 ia32_gen_decls(cg->out);
385 ia32_finish_irg(irg, cg);
386 //dump_ir_block_graph_sched(irg, "-finished");
387 ia32_gen_routine(out, irg, cg);
391 pmap_destroy(cg->tv_ent);
392 pmap_destroy(cg->types);
394 /* de-allocate code generator */
395 del_set(cg->reg_set);
399 static void *ia32_cg_init(FILE *F, const be_irg_t *birg);
401 static const arch_code_generator_if_t ia32_code_gen_if = {
404 ia32_before_sched, /* before scheduling hook */
405 ia32_before_ra, /* before register allocation hook */
408 ia32_codegen /* emit && done */
412 * Initializes the code generator.
414 static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
415 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
416 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
418 cg->impl = &ia32_code_gen_if;
420 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
421 cg->mod = firm_dbg_register("firm.be.ia32.cg");
423 cg->arch_env = birg->main_env->arch_env;
424 cg->types = pmap_create();
425 cg->tv_ent = pmap_create();
430 if (isa->num_codegens > 1)
435 cur_reg_set = cg->reg_set;
437 ia32_irn_ops.cg = cg;
439 return (arch_code_generator_t *)cg;
444 /*****************************************************************
445 * ____ _ _ _____ _____
446 * | _ \ | | | | |_ _|/ ____| /\
447 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
448 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
449 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
450 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
452 *****************************************************************/
454 static ia32_isa_t ia32_isa_template = {
456 &ia32_gp_regs[REG_ESP],
457 &ia32_gp_regs[REG_EBP],
463 * Initializes the backend ISA.
465 static void *ia32_init(void) {
466 static int inited = 0;
472 isa = xcalloc(1, sizeof(*isa));
473 memcpy(isa, &ia32_isa_template, sizeof(*isa));
475 ia32_register_init(isa);
476 ia32_create_opcodes();
486 * Closes the output file and frees the ISA structure.
488 static void ia32_done(void *self) {
494 static int ia32_get_n_reg_class(const void *self) {
498 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
499 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
500 return &ia32_reg_classes[i];
504 * Get the register class which shall be used to store a value of a given mode.
505 * @param self The this pointer.
506 * @param mode The mode in question.
507 * @return A register class which can hold values of the given mode.
509 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
510 if (mode_is_float(mode))
511 return &ia32_reg_classes[CLASS_ia32_fp];
513 return &ia32_reg_classes[CLASS_ia32_gp];
517 * Produces the type which sits between the stack args and the locals on the stack.
518 * it will contain the return address and space to store the old base pointer.
519 * @return The Firm type modelling the ABI between type.
521 static ir_type *get_between_type(void)
523 static ir_type *between_type = NULL;
524 static entity *old_bp_ent = NULL;
527 entity *ret_addr_ent;
528 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
529 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
531 between_type = new_type_class(new_id_from_str("ia32_between_type"));
532 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
533 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
535 set_entity_offset_bytes(old_bp_ent, 0);
536 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
537 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
544 * Get the ABI restrictions for procedure calls.
545 * @param self The this pointer.
546 * @param method_type The type of the method (procedure) in question.
547 * @param abi The abi object to be modified
549 void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
550 ir_type *between_type;
553 unsigned cc = get_method_calling_convention(method_type);
554 int n = get_method_n_params(method_type);
559 const arch_register_t *reg;
561 /* get the between type and the frame pointer save entity */
562 between_type = get_between_type();
564 /* set stack parameter passing style */
565 be_abi_call_set_flags(abi, BE_ABI_NONE, between_type);
567 /* collect the mode for each type */
568 modes = alloca(n * sizeof(modes[0]));
570 for (i = 0; i < n; i++) {
571 tp = get_method_param_type(method_type, i);
572 modes[i] = get_type_mode(tp);
575 /* set register parameters */
576 if (cc & cc_reg_param) {
577 /* determine the number of parameters passed via registers */
578 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore, &ignore);
580 /* loop over all parameters and set the register requirements */
581 for (i = 0; i <= biggest_n; i++) {
582 reg = ia32_get_RegParam_reg(n, modes, i, cc);
583 assert(reg && "kaputt");
584 be_abi_call_param_reg(abi, i, reg);
591 /* set stack parameters */
592 for (i = stack_idx; i < n; i++) {
593 be_abi_call_param_stack(abi, i);
597 /* set return registers */
598 n = get_method_n_ress(method_type);
600 assert(n <= 2 && "more than two results not supported");
602 /* In case of 64bit returns, we will have two 32bit values */
604 tp = get_method_res_type(method_type, 0);
605 mode = get_type_mode(tp);
607 assert(!mode_is_float(mode) && "two FP results not supported");
609 tp = get_method_res_type(method_type, 1);
610 mode = get_type_mode(tp);
612 assert(!mode_is_float(mode) && "two FP results not supported");
614 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
615 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
618 tp = get_method_res_type(method_type, 0);
619 mode = get_type_mode(tp);
621 be_abi_call_res_reg(abi, 0, &ia32_fp_regs[mode_is_float(mode) ? REG_XMM0 : REG_EAX]);
626 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
627 return &ia32_irn_ops;
630 const arch_irn_handler_t ia32_irn_handler = {
634 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
635 return &ia32_irn_handler;
638 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
639 return is_ia32_irn(irn);
643 * Initializes the code generator interface.
645 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
646 return &ia32_code_gen_if;
649 list_sched_selector_t ia32_sched_selector;
652 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
654 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
655 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
656 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
657 return &ia32_sched_selector;
661 static void ia32_register_options(lc_opt_entry_t *ent)
664 #endif /* WITH_LIBCORE */
666 const arch_isa_if_t ia32_isa_if = {
668 ia32_register_options,
672 ia32_get_n_reg_class,
674 ia32_get_reg_class_for_mode,
676 ia32_get_irn_handler,
677 ia32_get_code_generator_if,
678 ia32_get_list_sched_selector