2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
57 #include "../benode.h"
58 #include "../belower.h"
59 #include "../besched.h"
62 #include "../beirgmod.h"
63 #include "../be_dbgout.h"
64 #include "../beblocksched.h"
65 #include "../bemachine.h"
66 #include "../beilpsched.h"
67 #include "../bespillslots.h"
68 #include "../bemodule.h"
69 #include "../begnuas.h"
70 #include "../bestate.h"
71 #include "../beflags.h"
72 #include "../betranshlp.h"
73 #include "../belistsched.h"
74 #include "../beabihelper.h"
76 #include "bearch_ia32_t.h"
78 #include "ia32_new_nodes.h"
79 #include "gen_ia32_regalloc_if.h"
80 #include "gen_ia32_machine.h"
81 #include "ia32_common_transform.h"
82 #include "ia32_transform.h"
83 #include "ia32_emitter.h"
84 #include "ia32_map_regs.h"
85 #include "ia32_optimize.h"
87 #include "ia32_dbg_stat.h"
88 #include "ia32_finish.h"
89 #include "ia32_util.h"
91 #include "ia32_architecture.h"
94 #include "ia32_pbqp_transform.h"
96 transformer_t be_transformer = TRANSFORMER_DEFAULT;
99 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
101 ir_mode *mode_fpcw = NULL;
102 ia32_code_gen_t *ia32_current_cg = NULL;
104 /** The current omit-fp state */
105 static unsigned ia32_curr_fp_ommitted = 0;
106 static ir_type *omit_fp_between_type = NULL;
107 static ir_type *between_type = NULL;
108 static ir_entity *old_bp_ent = NULL;
109 static ir_entity *ret_addr_ent = NULL;
110 static ir_entity *omit_fp_ret_addr_ent = NULL;
113 * The environment for the intrinsic mapping.
115 static ia32_intrinsic_env_t intrinsic_env = {
117 NULL, /* the irg, these entities belong to */
118 NULL, /* entity for __divdi3 library call */
119 NULL, /* entity for __moddi3 library call */
120 NULL, /* entity for __udivdi3 library call */
121 NULL, /* entity for __umoddi3 library call */
125 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
128 * Used to create per-graph unique pseudo nodes.
130 static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
131 create_const_node_func func,
132 const arch_register_t* reg)
134 ir_node *block, *res;
139 block = get_irg_start_block(cg->irg);
140 res = func(NULL, block);
141 arch_set_irn_register(res, reg);
147 /* Creates the unique per irg GP NoReg node. */
148 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg)
150 return create_const(cg, &cg->noreg_gp, new_bd_ia32_NoReg_GP,
151 &ia32_gp_regs[REG_GP_NOREG]);
154 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg)
156 return create_const(cg, &cg->noreg_vfp, new_bd_ia32_NoReg_VFP,
157 &ia32_vfp_regs[REG_VFP_NOREG]);
160 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg)
162 return create_const(cg, &cg->noreg_xmm, new_bd_ia32_NoReg_XMM,
163 &ia32_xmm_regs[REG_XMM_NOREG]);
166 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg)
168 return create_const(cg, &cg->fpu_trunc_mode, new_bd_ia32_ChangeCW,
169 &ia32_fp_cw_regs[REG_FPCW]);
174 * Returns the admissible noreg register node for input register pos of node irn.
176 static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
178 const arch_register_req_t *req = arch_get_register_req(irn, pos);
180 assert(req != NULL && "Missing register requirements");
181 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
182 return ia32_new_NoReg_gp(cg);
184 if (ia32_cg_config.use_sse2) {
185 return ia32_new_NoReg_xmm(cg);
187 return ia32_new_NoReg_vfp(cg);
192 static const arch_register_req_t *get_ia32_SwitchJmp_out_req(
193 const ir_node *node, int pos)
197 return arch_no_register_req;
200 static arch_irn_class_t ia32_classify(const ir_node *irn)
202 arch_irn_class_t classification = 0;
204 assert(is_ia32_irn(irn));
206 if (is_ia32_is_reload(irn))
207 classification |= arch_irn_class_reload;
209 if (is_ia32_is_spill(irn))
210 classification |= arch_irn_class_spill;
212 if (is_ia32_is_remat(irn))
213 classification |= arch_irn_class_remat;
215 return classification;
219 * The IA32 ABI callback object.
222 be_abi_call_flags_bits_t flags; /**< The call flags. */
223 ir_graph *irg; /**< The associated graph. */
226 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
228 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
231 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
233 if (is_be_node(node))
234 be_node_set_frame_entity(node, entity);
236 set_ia32_frame_ent(node, entity);
239 static void ia32_set_frame_offset(ir_node *irn, int bias)
241 if (get_ia32_frame_ent(irn) == NULL)
244 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
245 ir_graph *irg = get_irn_irg(irn);
246 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
247 if (layout->sp_relative) {
248 /* Pop nodes modify the stack pointer before calculating the
249 * destination address, so fix this here
254 add_ia32_am_offs_int(irn, bias);
257 static int ia32_get_sp_bias(const ir_node *node)
259 if (is_ia32_Call(node))
260 return -(int)get_ia32_call_attr_const(node)->pop;
262 if (is_ia32_Push(node))
265 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
272 * Generate the routine prologue.
274 * @param self The callback object.
275 * @param mem A pointer to the mem node. Update this if you define new memory.
276 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
277 * @param stack_bias Points to the current stack bias, can be modified if needed.
279 * @return The register which shall be used as a stack frame base.
281 * All nodes which define registers in @p reg_map must keep @p reg_map current.
283 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
285 ia32_abi_env_t *env = self;
286 ia32_code_gen_t *cg = ia32_current_cg;
287 const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
289 ia32_curr_fp_ommitted = env->flags.try_omit_fp;
290 if (! env->flags.try_omit_fp) {
291 ir_node *bl = get_irg_start_block(env->irg);
292 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
293 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
294 ir_node *noreg = ia32_new_NoReg_gp(cg);
297 /* mark bp register as ignore */
298 be_set_constr_single_reg_out(get_Proj_pred(curr_bp),
299 get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
302 push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
303 curr_sp = new_r_Proj(push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
304 *mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
306 /* the push must have SP out register */
307 arch_set_irn_register(curr_sp, arch_env->sp);
309 /* this modifies the stack bias, because we pushed 32bit */
312 /* move esp to ebp */
313 curr_bp = be_new_Copy(arch_env->bp->reg_class, bl, curr_sp);
314 be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
315 arch_register_req_type_ignore);
317 /* beware: the copy must be done before any other sp use */
318 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
319 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
320 arch_register_req_type_produces_sp);
322 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
323 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
332 * Generate the routine epilogue.
333 * @param self The callback object.
334 * @param bl The block for the epilog
335 * @param mem A pointer to the mem node. Update this if you define new memory.
336 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
337 * @return The register which shall be used as a stack frame base.
339 * All nodes which define registers in @p reg_map must keep @p reg_map current.
341 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
343 ia32_abi_env_t *env = self;
344 const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
345 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
346 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
348 if (env->flags.try_omit_fp) {
349 /* simply remove the stack frame here */
350 curr_sp = be_new_IncSP(arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
352 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
354 if (ia32_cg_config.use_leave) {
358 leave = new_bd_ia32_Leave(NULL, bl, curr_bp);
359 curr_bp = new_r_Proj(leave, mode_bp, pn_ia32_Leave_frame);
360 curr_sp = new_r_Proj(leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
364 /* the old SP is not needed anymore (kill the proj) */
365 assert(is_Proj(curr_sp));
368 /* copy ebp to esp */
369 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], bl, curr_bp);
370 arch_set_irn_register(curr_sp, arch_env->sp);
371 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
372 arch_register_req_type_ignore);
375 pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
376 curr_bp = new_r_Proj(pop, mode_bp, pn_ia32_Pop_res);
377 curr_sp = new_r_Proj(pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
379 *mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
381 arch_set_irn_register(curr_sp, arch_env->sp);
382 arch_set_irn_register(curr_bp, arch_env->bp);
385 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
386 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
390 * Initialize the callback object.
391 * @param call The call object.
392 * @param irg The graph with the method.
393 * @return Some pointer. This pointer is passed to all other callback functions as self object.
395 static void *ia32_abi_init(const be_abi_call_t *call, ir_graph *irg)
397 ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
398 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
399 env->flags = fl.bits;
405 * Destroy the callback object.
406 * @param self The callback object.
408 static void ia32_abi_done(void *self)
414 * Build the between type and entities if not already build.
416 static void ia32_build_between_type(void)
418 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
419 if (! between_type) {
420 ir_type *old_bp_type = new_type_primitive(mode_Iu);
421 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
423 between_type = new_type_struct(IDENT("ia32_between_type"));
424 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
425 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
427 set_entity_offset(old_bp_ent, 0);
428 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
429 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
430 set_type_state(between_type, layout_fixed);
432 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
433 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
435 set_entity_offset(omit_fp_ret_addr_ent, 0);
436 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
437 set_type_state(omit_fp_between_type, layout_fixed);
443 * Produces the type which sits between the stack args and the locals on the stack.
444 * it will contain the return address and space to store the old base pointer.
445 * @return The Firm type modeling the ABI between type.
447 static ir_type *ia32_abi_get_between_type(void *self)
449 ia32_abi_env_t *env = self;
451 ia32_build_between_type();
452 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
456 * Return the stack entity that contains the return address.
458 ir_entity *ia32_get_return_address_entity(void)
460 ia32_build_between_type();
461 return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent;
465 * Return the stack entity that contains the frame address.
467 ir_entity *ia32_get_frame_address_entity(void)
469 ia32_build_between_type();
470 return ia32_curr_fp_ommitted ? NULL : old_bp_ent;
474 * Get the estimated cycle count for @p irn.
476 * @param self The this pointer.
477 * @param irn The node.
479 * @return The estimated cycle count for this operation
481 static int ia32_get_op_estimated_cost(const ir_node *irn)
484 ia32_op_type_t op_tp;
488 if (!is_ia32_irn(irn))
491 assert(is_ia32_irn(irn));
493 cost = get_ia32_latency(irn);
494 op_tp = get_ia32_op_type(irn);
496 if (is_ia32_CopyB(irn)) {
499 else if (is_ia32_CopyB_i(irn)) {
500 int size = get_ia32_copyb_size(irn);
501 cost = 20 + (int)ceil((4/3) * size);
503 /* in case of address mode operations add additional cycles */
504 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
506 In case of stack access and access to fixed addresses add 5 cycles
507 (we assume they are in cache), other memory operations cost 20
510 if (is_ia32_use_frame(irn) || (
511 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
512 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
524 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
526 * @param irn The original operation
527 * @param i Index of the argument we want the inverse operation to yield
528 * @param inverse struct to be filled with the resulting inverse op
529 * @param obstack The obstack to use for allocation of the returned nodes array
530 * @return The inverse operation or NULL if operation invertible
532 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
543 ir_node *block, *noreg, *nomem;
546 /* we cannot invert non-ia32 irns */
547 if (! is_ia32_irn(irn))
550 /* operand must always be a real operand (not base, index or mem) */
551 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
554 /* we don't invert address mode operations */
555 if (get_ia32_op_type(irn) != ia32_Normal)
558 /* TODO: adjust for new immediates... */
559 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
563 block = get_nodes_block(irn);
564 mode = get_irn_mode(irn);
565 irn_mode = get_irn_mode(irn);
566 noreg = get_irn_n(irn, 0);
568 dbg = get_irn_dbg_info(irn);
570 /* initialize structure */
571 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
575 switch (get_ia32_irn_opcode(irn)) {
578 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
579 /* we have an add with a const here */
580 /* invers == add with negated const */
581 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
583 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
584 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
585 set_ia32_commutative(inverse->nodes[0]);
587 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
588 /* we have an add with a symconst here */
589 /* invers == sub with const */
590 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
592 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
595 /* normal add: inverse == sub */
596 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
603 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
604 /* we have a sub with a const/symconst here */
605 /* invers == add with this const */
606 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
607 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
608 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
612 if (i == n_ia32_binary_left) {
613 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
616 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
624 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
625 /* xor with const: inverse = xor */
626 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
627 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
628 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
632 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
638 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
643 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
648 /* inverse operation not supported */
656 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
658 if (mode_is_float(mode))
665 * Get the mode that should be used for spilling value node
667 static ir_mode *get_spill_mode(const ir_node *node)
669 ir_mode *mode = get_irn_mode(node);
670 return get_spill_mode_mode(mode);
674 * Checks whether an addressmode reload for a node with mode mode is compatible
675 * with a spillslot of mode spill_mode
677 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
679 return !mode_is_float(mode) || mode == spillmode;
683 * Check if irn can load its operand at position i from memory (source addressmode).
684 * @param irn The irn to be checked
685 * @param i The operands position
686 * @return Non-Zero if operand can be loaded
688 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
690 ir_node *op = get_irn_n(irn, i);
691 const ir_mode *mode = get_irn_mode(op);
692 const ir_mode *spillmode = get_spill_mode(op);
694 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
695 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
696 !ia32_is_spillmode_compatible(mode, spillmode) ||
697 is_ia32_use_frame(irn)) /* must not already use frame */
700 switch (get_ia32_am_support(irn)) {
705 if (i != n_ia32_unary_op)
711 case n_ia32_binary_left: {
712 const arch_register_req_t *req;
713 if (!is_ia32_commutative(irn))
716 /* we can't swap left/right for limited registers
717 * (As this (currently) breaks constraint handling copies)
719 req = get_ia32_in_req(irn, n_ia32_binary_left);
720 if (req->type & arch_register_req_type_limited)
725 case n_ia32_binary_right:
734 panic("Unknown AM type");
737 /* HACK: must not already use "real" memory.
738 * This can happen for Call and Div */
739 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
745 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
749 ir_mode *dest_op_mode;
751 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
753 set_ia32_op_type(irn, ia32_AddrModeS);
755 load_mode = get_irn_mode(get_irn_n(irn, i));
756 dest_op_mode = get_ia32_ls_mode(irn);
757 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
758 set_ia32_ls_mode(irn, load_mode);
760 set_ia32_use_frame(irn);
761 set_ia32_need_stackent(irn);
763 if (i == n_ia32_binary_left &&
764 get_ia32_am_support(irn) == ia32_am_binary &&
765 /* immediates are only allowed on the right side */
766 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
767 ia32_swap_left_right(irn);
768 i = n_ia32_binary_right;
771 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
773 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
774 set_irn_n(irn, n_ia32_mem, spill);
775 set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i));
776 set_ia32_is_reload(irn);
779 static const be_abi_callbacks_t ia32_abi_callbacks = {
782 ia32_abi_get_between_type,
787 /* register allocator interface */
788 static const arch_irn_ops_t ia32_irn_ops = {
791 ia32_get_frame_entity,
792 ia32_set_frame_offset,
795 ia32_get_op_estimated_cost,
796 ia32_possible_memory_operand,
797 ia32_perform_memory_operand,
800 /* special register allocator interface for SwitchJmp
801 as it possibly has a WIDE range of Proj numbers.
802 We don't want to allocate output for register constraints for
804 static const arch_irn_ops_t ia32_SwitchJmp_irn_ops = {
805 /* Note: we also use SwitchJmp_out_req for the inputs too:
806 This is because the bearch API has a conceptual problem at the moment.
807 Querying for negative proj numbers which can happen for switchs
808 isn't possible and will result in inputs getting queried */
809 get_ia32_SwitchJmp_out_req,
811 ia32_get_frame_entity,
812 ia32_set_frame_offset,
815 ia32_get_op_estimated_cost,
816 ia32_possible_memory_operand,
817 ia32_perform_memory_operand,
821 static ir_entity *mcount = NULL;
823 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
825 static void ia32_before_abi(void *self)
827 ia32_code_gen_t *cg = self;
829 if (mcount == NULL) {
830 ir_type *tp = new_type_method(0, 0);
831 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
832 /* FIXME: enter the right ld_ident here */
833 set_entity_ld_ident(mcount, get_entity_ident(mcount));
834 set_entity_visibility(mcount, ir_visibility_external);
836 instrument_initcall(cg->irg, mcount);
841 * Transforms the standard firm graph into
844 static void ia32_prepare_graph(void *self)
846 ia32_code_gen_t *cg = self;
849 switch (be_transformer) {
850 case TRANSFORMER_DEFAULT:
851 /* transform remaining nodes into assembler instructions */
852 ia32_transform_graph(cg);
855 case TRANSFORMER_PBQP:
856 case TRANSFORMER_RAND:
857 /* transform nodes into assembler instructions by PBQP magic */
858 ia32_transform_graph_by_pbqp(cg);
862 panic("invalid transformer");
865 ia32_transform_graph(cg);
868 /* do local optimizations (mainly CSE) */
869 optimize_graph_df(cg->irg);
872 dump_ir_graph(cg->irg, "transformed");
874 /* optimize address mode */
875 ia32_optimize_graph(cg);
877 /* do code placement, to optimize the position of constants */
881 dump_ir_graph(cg->irg, "place");
884 ir_node *turn_back_am(ir_node *node)
886 dbg_info *dbgi = get_irn_dbg_info(node);
887 ir_node *block = get_nodes_block(node);
888 ir_node *base = get_irn_n(node, n_ia32_base);
889 ir_node *index = get_irn_n(node, n_ia32_index);
890 ir_node *mem = get_irn_n(node, n_ia32_mem);
893 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
894 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
896 ia32_copy_am_attrs(load, node);
897 if (is_ia32_is_reload(node))
898 set_ia32_is_reload(load);
899 set_irn_n(node, n_ia32_mem, new_NoMem());
901 switch (get_ia32_am_support(node)) {
903 set_irn_n(node, n_ia32_unary_op, load_res);
907 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
908 set_irn_n(node, n_ia32_binary_left, load_res);
910 set_irn_n(node, n_ia32_binary_right, load_res);
915 panic("Unknown AM type");
917 noreg = ia32_new_NoReg_gp(ia32_current_cg);
918 set_irn_n(node, n_ia32_base, noreg);
919 set_irn_n(node, n_ia32_index, noreg);
920 set_ia32_am_offs_int(node, 0);
921 set_ia32_am_sc(node, NULL);
922 set_ia32_am_scale(node, 0);
923 clear_ia32_am_sc_sign(node);
925 /* rewire mem-proj */
926 if (get_irn_mode(node) == mode_T) {
927 const ir_edge_t *edge;
928 foreach_out_edge(node, edge) {
929 ir_node *out = get_edge_src_irn(edge);
930 if (get_irn_mode(out) == mode_M) {
931 set_Proj_pred(out, load);
932 set_Proj_proj(out, pn_ia32_Load_M);
938 set_ia32_op_type(node, ia32_Normal);
939 if (sched_is_scheduled(node))
940 sched_add_before(node, load);
945 static ir_node *flags_remat(ir_node *node, ir_node *after)
947 /* we should turn back source address mode when rematerializing nodes */
952 if (is_Block(after)) {
955 block = get_nodes_block(after);
958 type = get_ia32_op_type(node);
965 /* TODO implement this later... */
966 panic("found DestAM with flag user %+F this should not happen", node);
969 default: assert(type == ia32_Normal); break;
972 copy = exact_copy(node);
973 set_nodes_block(copy, block);
974 sched_add_after(after, copy);
980 * Called before the register allocator.
982 static void ia32_before_ra(void *self)
984 ia32_code_gen_t *cg = self;
986 /* setup fpu rounding modes */
987 ia32_setup_fpu_mode(cg);
990 be_sched_fix_flags(cg->irg, &ia32_reg_classes[CLASS_ia32_flags],
993 be_add_missing_keeps(cg->irg);
998 * Transforms a be_Reload into a ia32 Load.
1000 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node)
1002 ir_graph *irg = get_irn_irg(node);
1003 dbg_info *dbg = get_irn_dbg_info(node);
1004 ir_node *block = get_nodes_block(node);
1005 ir_entity *ent = be_get_frame_entity(node);
1006 ir_mode *mode = get_irn_mode(node);
1007 ir_mode *spillmode = get_spill_mode(node);
1008 ir_node *noreg = ia32_new_NoReg_gp(cg);
1009 ir_node *sched_point = NULL;
1010 ir_node *ptr = get_irg_frame(irg);
1011 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1012 ir_node *new_op, *proj;
1013 const arch_register_t *reg;
1015 if (sched_is_scheduled(node)) {
1016 sched_point = sched_prev(node);
1019 if (mode_is_float(spillmode)) {
1020 if (ia32_cg_config.use_sse2)
1021 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
1023 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
1025 else if (get_mode_size_bits(spillmode) == 128) {
1026 /* Reload 128 bit SSE registers */
1027 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
1030 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
1032 set_ia32_op_type(new_op, ia32_AddrModeS);
1033 set_ia32_ls_mode(new_op, spillmode);
1034 set_ia32_frame_ent(new_op, ent);
1035 set_ia32_use_frame(new_op);
1036 set_ia32_is_reload(new_op);
1038 DBG_OPT_RELOAD2LD(node, new_op);
1040 proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
1043 sched_add_after(sched_point, new_op);
1047 /* copy the register from the old node to the new Load */
1048 reg = arch_get_irn_register(node);
1049 arch_set_irn_register(proj, reg);
1051 SET_IA32_ORIG_NODE(new_op, node);
1053 exchange(node, proj);
1057 * Transforms a be_Spill node into a ia32 Store.
1059 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node)
1061 ir_graph *irg = get_irn_irg(node);
1062 dbg_info *dbg = get_irn_dbg_info(node);
1063 ir_node *block = get_nodes_block(node);
1064 ir_entity *ent = be_get_frame_entity(node);
1065 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1066 ir_mode *mode = get_spill_mode(spillval);
1067 ir_node *noreg = ia32_new_NoReg_gp(cg);
1068 ir_node *nomem = new_NoMem();
1069 ir_node *ptr = get_irg_frame(irg);
1070 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1072 ir_node *sched_point = NULL;
1074 if (sched_is_scheduled(node)) {
1075 sched_point = sched_prev(node);
1078 if (mode_is_float(mode)) {
1079 if (ia32_cg_config.use_sse2)
1080 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
1082 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
1083 } else if (get_mode_size_bits(mode) == 128) {
1084 /* Spill 128 bit SSE registers */
1085 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
1086 } else if (get_mode_size_bits(mode) == 8) {
1087 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
1089 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
1092 set_ia32_op_type(store, ia32_AddrModeD);
1093 set_ia32_ls_mode(store, mode);
1094 set_ia32_frame_ent(store, ent);
1095 set_ia32_use_frame(store);
1096 set_ia32_is_spill(store);
1097 SET_IA32_ORIG_NODE(store, node);
1098 DBG_OPT_SPILL2ST(node, store);
1101 sched_add_after(sched_point, store);
1105 exchange(node, store);
1108 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
1110 dbg_info *dbg = get_irn_dbg_info(node);
1111 ir_node *block = get_nodes_block(node);
1112 ir_node *noreg = ia32_new_NoReg_gp(cg);
1113 ir_graph *irg = get_irn_irg(node);
1114 ir_node *frame = get_irg_frame(irg);
1116 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
1118 set_ia32_frame_ent(push, ent);
1119 set_ia32_use_frame(push);
1120 set_ia32_op_type(push, ia32_AddrModeS);
1121 set_ia32_ls_mode(push, mode_Is);
1122 set_ia32_is_spill(push);
1124 sched_add_before(schedpoint, push);
1128 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
1130 dbg_info *dbg = get_irn_dbg_info(node);
1131 ir_node *block = get_nodes_block(node);
1132 ir_node *noreg = ia32_new_NoReg_gp(cg);
1133 ir_graph *irg = get_irn_irg(node);
1134 ir_node *frame = get_irg_frame(irg);
1136 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
1138 set_ia32_frame_ent(pop, ent);
1139 set_ia32_use_frame(pop);
1140 set_ia32_op_type(pop, ia32_AddrModeD);
1141 set_ia32_ls_mode(pop, mode_Is);
1142 set_ia32_is_reload(pop);
1144 sched_add_before(schedpoint, pop);
1149 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1151 dbg_info *dbg = get_irn_dbg_info(node);
1152 ir_mode *spmode = mode_Iu;
1153 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1156 sp = new_rd_Proj(dbg, pred, spmode, pos);
1157 arch_set_irn_register(sp, spreg);
1163 * Transform MemPerm, currently we do this the ugly way and produce
1164 * push/pop into/from memory cascades. This is possible without using
1167 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
1169 ir_node *block = get_nodes_block(node);
1170 ir_node *sp = be_abi_get_ignore_irn(be_get_irg_abi(cg->irg), &ia32_gp_regs[REG_ESP]);
1171 int arity = be_get_MemPerm_entity_arity(node);
1172 ir_node **pops = ALLOCAN(ir_node*, arity);
1176 const ir_edge_t *edge;
1177 const ir_edge_t *next;
1180 for (i = 0; i < arity; ++i) {
1181 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1182 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1183 ir_type *enttype = get_entity_type(inent);
1184 unsigned entsize = get_type_size_bytes(enttype);
1185 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1186 ir_node *mem = get_irn_n(node, i + 1);
1189 /* work around cases where entities have different sizes */
1190 if (entsize2 < entsize)
1192 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1194 push = create_push(cg, node, node, sp, mem, inent);
1195 sp = create_spproj(node, push, pn_ia32_Push_stack);
1197 /* add another push after the first one */
1198 push = create_push(cg, node, node, sp, mem, inent);
1199 add_ia32_am_offs_int(push, 4);
1200 sp = create_spproj(node, push, pn_ia32_Push_stack);
1203 set_irn_n(node, i, new_Bad());
1207 for (i = arity - 1; i >= 0; --i) {
1208 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1209 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1210 ir_type *enttype = get_entity_type(outent);
1211 unsigned entsize = get_type_size_bytes(enttype);
1212 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1215 /* work around cases where entities have different sizes */
1216 if (entsize2 < entsize)
1218 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1220 pop = create_pop(cg, node, node, sp, outent);
1221 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1223 add_ia32_am_offs_int(pop, 4);
1225 /* add another pop after the first one */
1226 pop = create_pop(cg, node, node, sp, outent);
1227 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1234 keep = be_new_Keep(block, 1, in);
1235 sched_add_before(node, keep);
1237 /* exchange memprojs */
1238 foreach_out_edge_safe(node, edge, next) {
1239 ir_node *proj = get_edge_src_irn(edge);
1240 int p = get_Proj_proj(proj);
1244 set_Proj_pred(proj, pops[p]);
1245 set_Proj_proj(proj, pn_ia32_Pop_M);
1248 /* remove memperm */
1249 arity = get_irn_arity(node);
1250 for (i = 0; i < arity; ++i) {
1251 set_irn_n(node, i, new_Bad());
1257 * Block-Walker: Calls the transform functions Spill and Reload.
1259 static void ia32_after_ra_walker(ir_node *block, void *env)
1261 ir_node *node, *prev;
1262 ia32_code_gen_t *cg = env;
1264 /* beware: the schedule is changed here */
1265 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1266 prev = sched_prev(node);
1268 if (be_is_Reload(node)) {
1269 transform_to_Load(cg, node);
1270 } else if (be_is_Spill(node)) {
1271 transform_to_Store(cg, node);
1272 } else if (be_is_MemPerm(node)) {
1273 transform_MemPerm(cg, node);
1279 * Collects nodes that need frame entities assigned.
1281 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1283 be_fec_env_t *env = data;
1284 const ir_mode *mode;
1287 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1288 mode = get_spill_mode_mode(get_irn_mode(node));
1289 align = get_mode_size_bytes(mode);
1290 } else if (is_ia32_irn(node) &&
1291 get_ia32_frame_ent(node) == NULL &&
1292 is_ia32_use_frame(node)) {
1293 if (is_ia32_need_stackent(node))
1296 switch (get_ia32_irn_opcode(node)) {
1298 case iro_ia32_Load: {
1299 const ia32_attr_t *attr = get_ia32_attr_const(node);
1301 if (attr->data.need_32bit_stackent) {
1303 } else if (attr->data.need_64bit_stackent) {
1306 mode = get_ia32_ls_mode(node);
1307 if (is_ia32_is_reload(node))
1308 mode = get_spill_mode_mode(mode);
1310 align = get_mode_size_bytes(mode);
1314 case iro_ia32_vfild:
1316 case iro_ia32_xLoad: {
1317 mode = get_ia32_ls_mode(node);
1322 case iro_ia32_FldCW: {
1323 /* although 2 byte would be enough 4 byte performs best */
1331 panic("unexpected frame user while collection frame entity nodes");
1333 case iro_ia32_FnstCW:
1334 case iro_ia32_Store8Bit:
1335 case iro_ia32_Store:
1338 case iro_ia32_vfist:
1339 case iro_ia32_vfisttp:
1341 case iro_ia32_xStore:
1342 case iro_ia32_xStoreSimple:
1349 be_node_needs_frame_entity(env, node, mode, align);
1353 * We transform Spill and Reload here. This needs to be done before
1354 * stack biasing otherwise we would miss the corrected offset for these nodes.
1356 static void ia32_after_ra(void *self)
1358 ia32_code_gen_t *cg = self;
1359 ir_graph *irg = cg->irg;
1360 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->irg);
1362 /* create and coalesce frame entities */
1363 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1364 be_assign_entities(fec_env, ia32_set_frame_entity);
1365 be_free_frame_entity_coalescer(fec_env);
1367 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1371 * Last touchups for the graph before emit: x87 simulation to replace the
1372 * virtual with real x87 instructions, creating a block schedule and peephole
1375 static void ia32_finish(void *self)
1377 ia32_code_gen_t *cg = self;
1378 ir_graph *irg = cg->irg;
1380 ia32_finish_irg(irg, cg);
1382 /* we might have to rewrite x87 virtual registers */
1383 if (cg->do_x87_sim) {
1384 x87_simulate_graph(cg->irg);
1387 /* do peephole optimisations */
1388 ia32_peephole_optimization(cg);
1390 /* create block schedule, this also removes empty blocks which might
1391 * produce critical edges */
1392 cg->blk_sched = be_create_block_schedule(irg);
1396 * Emits the code, closes the output file and frees
1397 * the code generator interface.
1399 static void ia32_codegen(void *self)
1401 ia32_code_gen_t *cg = self;
1402 ir_graph *irg = cg->irg;
1404 if (ia32_cg_config.emit_machcode) {
1405 ia32_gen_binary_routine(cg, irg);
1407 ia32_gen_routine(cg, irg);
1410 /* remove it from the isa */
1413 assert(ia32_current_cg == cg);
1414 ia32_current_cg = NULL;
1416 /* de-allocate code generator */
1421 * Returns the node representing the PIC base.
1423 static ir_node *ia32_get_pic_base(void *self)
1426 ia32_code_gen_t *cg = self;
1427 ir_node *get_eip = cg->get_eip;
1428 if (get_eip != NULL)
1431 block = get_irg_start_block(cg->irg);
1432 get_eip = new_bd_ia32_GetEIP(NULL, block);
1433 cg->get_eip = get_eip;
1435 be_dep_on_frame(get_eip);
1439 static void *ia32_cg_init(ir_graph *irg);
1441 static const arch_code_generator_if_t ia32_code_gen_if = {
1443 ia32_get_pic_base, /* return node used as base in pic code addresses */
1444 ia32_before_abi, /* before abi introduce hook */
1447 ia32_before_ra, /* before register allocation hook */
1448 ia32_after_ra, /* after register allocation hook */
1449 ia32_finish, /* called before codegen */
1450 ia32_codegen /* emit && done */
1454 * Initializes a IA32 code generator.
1456 static void *ia32_cg_init(ir_graph *irg)
1458 ia32_isa_t *isa = (ia32_isa_t *)be_get_irg_arch_env(irg);
1459 ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t);
1461 cg->impl = &ia32_code_gen_if;
1464 cg->blk_sched = NULL;
1465 cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1466 cg->gprof = (be_get_irg_options(irg)->gprof) ? 1 : 0;
1469 /* Linux gprof implementation needs base pointer */
1470 be_get_irg_options(irg)->omit_fp = 0;
1477 if (isa->name_obst) {
1478 obstack_free(isa->name_obst, NULL);
1479 obstack_init(isa->name_obst);
1483 assert(ia32_current_cg == NULL);
1484 ia32_current_cg = cg;
1486 return (arch_code_generator_t *)cg;
1491 * Set output modes for GCC
1493 static const tarval_mode_info mo_integer = {
1500 * set the tarval output mode of all integer modes to decimal
1502 static void set_tarval_output_modes(void)
1506 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1507 ir_mode *mode = get_irp_mode(i);
1509 if (mode_is_int(mode))
1510 set_tarval_mode_output_option(mode, &mo_integer);
1514 const arch_isa_if_t ia32_isa_if;
1517 * The template that generates a new ISA object.
1518 * Note that this template can be changed by command line
1521 static ia32_isa_t ia32_isa_template = {
1523 &ia32_isa_if, /* isa interface implementation */
1524 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1525 &ia32_gp_regs[REG_EBP], /* base pointer register */
1526 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1527 -1, /* stack direction */
1528 2, /* power of two stack alignment, 2^2 == 4 */
1529 NULL, /* main environment */
1530 7, /* costs for a spill instruction */
1531 5, /* costs for a reload instruction */
1532 false, /* no custom abi handling */
1534 NULL, /* 16bit register names */
1535 NULL, /* 8bit register names */
1536 NULL, /* 8bit register names high */
1539 NULL, /* current code generator */
1540 NULL, /* abstract machine */
1542 NULL, /* name obstack */
1546 static void init_asm_constraints(void)
1548 be_init_default_asm_constraint_flags();
1550 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1551 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1552 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1553 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1554 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1555 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1556 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1557 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1558 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1559 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1560 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1561 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1562 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1563 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1564 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1565 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1566 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1567 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1568 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1569 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1571 /* no support for autodecrement/autoincrement */
1572 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1573 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1574 /* no float consts */
1575 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1576 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1577 /* makes no sense on x86 */
1578 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1579 /* no support for sse consts yet */
1580 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1581 /* no support for x87 consts yet */
1582 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1583 /* no support for mmx registers yet */
1584 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1585 /* not available in 32bit mode */
1586 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1587 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1589 /* no code yet to determine register class needed... */
1590 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1594 * Initializes the backend ISA.
1596 static arch_env_t *ia32_init(FILE *file_handle)
1598 static int inited = 0;
1606 set_tarval_output_modes();
1608 isa = XMALLOC(ia32_isa_t);
1609 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1611 if (mode_fpcw == NULL) {
1612 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1615 ia32_register_init();
1616 ia32_create_opcodes(&ia32_irn_ops);
1617 /* special handling for SwitchJmp */
1618 op_ia32_SwitchJmp->ops.be_ops = &ia32_SwitchJmp_irn_ops;
1620 be_emit_init(file_handle);
1621 isa->regs_16bit = pmap_create();
1622 isa->regs_8bit = pmap_create();
1623 isa->regs_8bit_high = pmap_create();
1624 isa->types = pmap_create();
1625 isa->tv_ent = pmap_create();
1626 isa->cpu = ia32_init_machine_description();
1628 ia32_build_16bit_reg_map(isa->regs_16bit);
1629 ia32_build_8bit_reg_map(isa->regs_8bit);
1630 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1633 isa->name_obst = XMALLOC(struct obstack);
1634 obstack_init(isa->name_obst);
1637 /* enter the ISA object into the intrinsic environment */
1638 intrinsic_env.isa = isa;
1640 /* emit asm includes */
1641 n = get_irp_n_asms();
1642 for (i = 0; i < n; ++i) {
1643 be_emit_cstring("#APP\n");
1644 be_emit_ident(get_irp_asm(i));
1645 be_emit_cstring("\n#NO_APP\n");
1648 /* needed for the debug support */
1649 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1650 be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
1651 be_emit_write_line();
1659 * Closes the output file and frees the ISA structure.
1661 static void ia32_done(void *self)
1663 ia32_isa_t *isa = self;
1665 /* emit now all global declarations */
1666 be_gas_emit_decls(isa->base.main_env);
1668 pmap_destroy(isa->regs_16bit);
1669 pmap_destroy(isa->regs_8bit);
1670 pmap_destroy(isa->regs_8bit_high);
1671 pmap_destroy(isa->tv_ent);
1672 pmap_destroy(isa->types);
1675 obstack_free(isa->name_obst, NULL);
1685 * Return the number of register classes for this architecture.
1686 * We report always these:
1687 * - the general purpose registers
1688 * - the SSE floating point register set
1689 * - the virtual floating point registers
1690 * - the SSE vector register set
1692 static unsigned ia32_get_n_reg_class(void)
1698 * Return the register class for index i.
1700 static const arch_register_class_t *ia32_get_reg_class(unsigned i)
1702 assert(i < N_CLASSES);
1703 return &ia32_reg_classes[i];
1707 * Get the register class which shall be used to store a value of a given mode.
1708 * @param self The this pointer.
1709 * @param mode The mode in question.
1710 * @return A register class which can hold values of the given mode.
1712 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1714 if (mode_is_float(mode)) {
1715 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1718 return &ia32_reg_classes[CLASS_ia32_gp];
1722 * Returns the register for parameter nr.
1724 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1725 const ir_mode *mode)
1727 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1728 &ia32_gp_regs[REG_ECX],
1729 &ia32_gp_regs[REG_EDX],
1732 static const unsigned MAXNUM_GPREG_ARGS = 3;
1734 static const arch_register_t *gpreg_param_reg_regparam[] = {
1735 &ia32_gp_regs[REG_EAX],
1736 &ia32_gp_regs[REG_EDX],
1737 &ia32_gp_regs[REG_ECX]
1740 static const arch_register_t *gpreg_param_reg_this[] = {
1741 &ia32_gp_regs[REG_ECX],
1746 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1747 &ia32_xmm_regs[REG_XMM0],
1748 &ia32_xmm_regs[REG_XMM1],
1749 &ia32_xmm_regs[REG_XMM2],
1750 &ia32_xmm_regs[REG_XMM3],
1751 &ia32_xmm_regs[REG_XMM4],
1752 &ia32_xmm_regs[REG_XMM5],
1753 &ia32_xmm_regs[REG_XMM6],
1754 &ia32_xmm_regs[REG_XMM7]
1757 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1758 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1760 static const unsigned MAXNUM_SSE_ARGS = 8;
1762 if ((cc & cc_this_call) && nr == 0)
1763 return gpreg_param_reg_this[0];
1765 if (! (cc & cc_reg_param))
1768 if (mode_is_float(mode)) {
1769 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1771 if (nr >= MAXNUM_SSE_ARGS)
1774 if (cc & cc_this_call) {
1775 return fpreg_sse_param_reg_this[nr];
1777 return fpreg_sse_param_reg_std[nr];
1778 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1779 unsigned num_regparam;
1781 if (get_mode_size_bits(mode) > 32)
1784 if (nr >= MAXNUM_GPREG_ARGS)
1787 if (cc & cc_this_call) {
1788 return gpreg_param_reg_this[nr];
1790 num_regparam = cc & ~cc_bits;
1791 if (num_regparam == 0) {
1792 /* default fastcall */
1793 return gpreg_param_reg_fastcall[nr];
1795 if (nr < num_regparam)
1796 return gpreg_param_reg_regparam[nr];
1800 panic("unknown argument mode");
1804 * Get the ABI restrictions for procedure calls.
1805 * @param self The this pointer.
1806 * @param method_type The type of the method (procedure) in question.
1807 * @param abi The abi object to be modified
1809 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1817 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1821 /* set abi flags for calls */
1822 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1823 call_flags.bits.store_args_sequential = 0;
1824 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1825 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1826 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1828 /* set parameter passing style */
1829 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1831 cc = get_method_calling_convention(method_type);
1832 if (get_method_variadicity(method_type) == variadicity_variadic) {
1833 /* pass all parameters of a variadic function on the stack */
1834 cc = cc_cdecl_set | (cc & cc_this_call);
1836 if (get_method_additional_properties(method_type) & mtp_property_private &&
1837 ia32_cg_config.optimize_cc) {
1838 /* set the fast calling conventions (allowing up to 3) */
1839 cc = SET_FASTCALL(cc) | 3;
1843 /* we have to pop the shadow parameter ourself for compound calls */
1844 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1845 && !(cc & cc_reg_param)) {
1846 pop_amount += get_mode_size_bytes(mode_P_data);
1849 n = get_method_n_params(method_type);
1850 for (i = regnum = 0; i < n; i++) {
1852 const arch_register_t *reg = NULL;
1854 tp = get_method_param_type(method_type, i);
1855 mode = get_type_mode(tp);
1857 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1860 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1863 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1864 * movl has a shorter opcode than mov[sz][bw]l */
1865 ir_mode *load_mode = mode;
1868 unsigned size = get_mode_size_bytes(mode);
1870 if (cc & cc_callee_clear_stk) {
1871 pop_amount += (size + 3U) & ~3U;
1874 if (size < 4) load_mode = mode_Iu;
1877 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1881 be_abi_call_set_pop(abi, pop_amount);
1883 /* set return registers */
1884 n = get_method_n_ress(method_type);
1886 assert(n <= 2 && "more than two results not supported");
1888 /* In case of 64bit returns, we will have two 32bit values */
1890 tp = get_method_res_type(method_type, 0);
1891 mode = get_type_mode(tp);
1893 assert(!mode_is_float(mode) && "two FP results not supported");
1895 tp = get_method_res_type(method_type, 1);
1896 mode = get_type_mode(tp);
1898 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1900 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX], ABI_CONTEXT_BOTH);
1901 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX], ABI_CONTEXT_BOTH);
1904 const arch_register_t *reg;
1906 tp = get_method_res_type(method_type, 0);
1907 assert(is_atomic_type(tp));
1908 mode = get_type_mode(tp);
1910 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1912 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1916 static int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1920 if (!is_ia32_irn(irn)) {
1924 if (is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1925 || is_ia32_ChangeCW(irn) || is_ia32_Immediate(irn))
1932 * Initializes the code generator interface.
1934 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1937 return &ia32_code_gen_if;
1941 * Returns the estimated execution time of an ia32 irn.
1943 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn)
1946 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
1949 list_sched_selector_t ia32_sched_selector;
1952 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1954 static const list_sched_selector_t *ia32_get_list_sched_selector(
1955 const void *self, list_sched_selector_t *selector)
1958 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1959 ia32_sched_selector.exectime = ia32_sched_exectime;
1960 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1961 return &ia32_sched_selector;
1964 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1971 * Returns the necessary byte alignment for storing a register of given class.
1973 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1975 ir_mode *mode = arch_register_class_mode(cls);
1976 int bytes = get_mode_size_bytes(mode);
1978 if (mode_is_float(mode) && bytes > 8)
1983 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1986 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1987 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1988 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1991 static const be_execution_unit_t *_allowed_units_GP[] = {
1992 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1993 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1994 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1995 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1996 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1997 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1998 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2001 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2002 &be_machine_execution_units_DUMMY[0],
2005 static const be_execution_unit_t **_units_callret[] = {
2006 _allowed_units_BRANCH,
2009 static const be_execution_unit_t **_units_other[] = {
2013 static const be_execution_unit_t **_units_dummy[] = {
2014 _allowed_units_DUMMY,
2017 const be_execution_unit_t ***ret;
2019 if (is_ia32_irn(irn)) {
2020 ret = get_ia32_exec_units(irn);
2021 } else if (is_be_node(irn)) {
2022 if (be_is_Return(irn)) {
2023 ret = _units_callret;
2024 } else if (be_is_Barrier(irn)) {
2038 * Return the abstract ia32 machine.
2040 static const be_machine_t *ia32_get_machine(const void *self)
2042 const ia32_isa_t *isa = self;
2047 * Return irp irgs in the desired order.
2049 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2056 static void ia32_mark_remat(ir_node *node)
2058 if (is_ia32_irn(node)) {
2059 set_ia32_is_remat(node);
2064 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
2066 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
2076 cmp = get_Proj_pred(sel);
2080 cmp_l = get_Cmp_left(cmp);
2081 cmp_r = get_Cmp_right(cmp);
2082 if (!mode_is_float(get_irn_mode(cmp_l)))
2085 /* check for min/max. They're defined as (C-Semantik):
2086 * min(a, b) = a < b ? a : b
2087 * or min(a, b) = a <= b ? a : b
2088 * max(a, b) = a > b ? a : b
2089 * or max(a, b) = a >= b ? a : b
2090 * (Note we only handle float min/max here)
2092 pnc = get_Proj_proj(sel);
2097 if (cmp_l == mux_true && cmp_r == mux_false)
2103 if (cmp_l == mux_true && cmp_r == mux_false)
2109 if (cmp_l == mux_false && cmp_r == mux_true)
2115 if (cmp_l == mux_false && cmp_r == mux_true)
2126 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
2128 ir_mode *mode = get_irn_mode(mux_true);
2131 if (!mode_is_int(mode) && !mode_is_reference(mode)
2135 if (is_Const(mux_true) && is_Const(mux_false)) {
2136 /* we can create a set plus up two 3 instructions for any combination of constants */
2143 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
2148 if (!mode_is_float(get_irn_mode(mux_true)))
2151 return is_Const(mux_true) && is_Const(mux_false);
2154 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
2167 cmp = get_Proj_pred(sel);
2171 mode = get_irn_mode(mux_true);
2172 if (mode_is_signed(mode) || mode_is_float(mode))
2175 pn = get_Proj_proj(sel);
2176 cmp_left = get_Cmp_left(cmp);
2177 cmp_right = get_Cmp_right(cmp);
2179 /* "move" zero constant to false input */
2180 if (is_Const(mux_true) && is_Const_null(mux_true)) {
2181 ir_node *tmp = mux_false;
2182 mux_false = mux_true;
2184 pn = get_negated_pnc(pn, mode);
2186 if (!is_Const(mux_false) || !is_Const_null(mux_false))
2188 if (!is_Sub(mux_true))
2190 sub_left = get_Sub_left(mux_true);
2191 sub_right = get_Sub_right(mux_true);
2193 /* Mux(a >=u b, 0, a-b) */
2194 if ((pn == pn_Cmp_Gt || pn == pn_Cmp_Ge)
2195 && sub_left == cmp_left && sub_right == cmp_right)
2197 /* Mux(a <=u b, 0, b-a) */
2198 if ((pn == pn_Cmp_Lt || pn == pn_Cmp_Le)
2199 && sub_left == cmp_right && sub_right == cmp_left)
2205 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
2210 /* we can handle Set for all modes and compares */
2211 if (mux_is_set(sel, mux_true, mux_false))
2213 /* SSE has own min/max operations */
2214 if (ia32_cg_config.use_sse2
2215 && mux_is_float_min_max(sel, mux_true, mux_false))
2217 /* we can handle Mux(?, Const[f], Const[f]) */
2218 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
2219 #ifdef FIRM_GRGEN_BE
2220 /* well, some code selectors can't handle it */
2221 if (be_transformer != TRANSFORMER_PBQP
2222 || be_transformer != TRANSFORMER_RAND)
2229 /* no support for 64bit inputs to cmov */
2230 mode = get_irn_mode(mux_true);
2231 if (get_mode_size_bits(mode) > 32)
2233 /* we can handle Abs for all modes and compares (except 64bit) */
2234 if (be_mux_is_abs(sel, mux_true, mux_false) != 0)
2236 /* we can't handle MuxF yet */
2237 if (mode_is_float(mode))
2240 if (mux_is_doz(sel, mux_true, mux_false))
2243 /* Check Cmp before the node */
2245 ir_node *cmp = get_Proj_pred(sel);
2247 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(cmp));
2249 /* we can't handle 64bit compares */
2250 if (get_mode_size_bits(cmp_mode) > 32)
2253 /* we can't handle float compares */
2254 if (mode_is_float(cmp_mode))
2259 /* did we disable cmov generation? */
2260 if (!ia32_cg_config.use_cmov)
2263 /* we can use a cmov */
2267 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2271 /* we already added all our simple flags to the flags modifier list in
2272 * init, so this flag we don't know. */
2273 return ASM_CONSTRAINT_FLAG_INVALID;
2276 static int ia32_is_valid_clobber(const char *clobber)
2278 return ia32_get_clobber_register(clobber) != NULL;
2281 static void ia32_lower_for_target(void)
2283 int n_irgs = get_irp_n_irgs();
2285 lower_mode_b_config_t lower_mode_b_config = {
2286 mode_Iu, /* lowered mode */
2287 mode_Bu, /* preferred mode for set */
2288 0, /* don't lower direct compares */
2291 /* perform doubleword lowering */
2292 lwrdw_param_t lower_dw_params = {
2293 1, /* little endian */
2294 64, /* doubleword size */
2295 ia32_create_intrinsic_fkt,
2298 lower_dw_ops(&lower_dw_params);
2300 /* lower for mode_b stuff */
2301 for (i = 0; i < n_irgs; ++i) {
2302 ir_graph *irg = get_irp_irg(i);
2303 ir_lower_mode_b(irg, &lower_mode_b_config);
2308 * Create the trampoline code.
2310 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2312 ir_node *st, *p = trampoline;
2313 ir_mode *mode = get_irn_mode(p);
2316 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xb9), 0);
2317 mem = new_r_Proj(st, mode_M, pn_Store_M);
2318 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2319 st = new_r_Store(block, mem, p, env, 0);
2320 mem = new_r_Proj(st, mode_M, pn_Store_M);
2321 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2323 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xe9), 0);
2324 mem = new_r_Proj(st, mode_M, pn_Store_M);
2325 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2326 st = new_r_Store(block, mem, p, callee, 0);
2327 mem = new_r_Proj(st, mode_M, pn_Store_M);
2328 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2334 * Returns the libFirm configuration parameter for this backend.
2336 static const backend_params *ia32_get_libfirm_params(void)
2338 static const ir_settings_arch_dep_t ad = {
2339 1, /* also use subs */
2340 4, /* maximum shifts */
2341 31, /* maximum shift amount */
2342 ia32_evaluate_insn, /* evaluate the instruction sequence */
2344 1, /* allow Mulhs */
2345 1, /* allow Mulus */
2346 32, /* Mulh allowed up to 32 bit */
2348 static backend_params p = {
2349 1, /* support inline assembly */
2350 1, /* support Rotl nodes */
2351 0, /* little endian */
2352 ia32_lower_for_target,
2353 NULL, /* will be set later */
2354 ia32_is_mux_allowed,
2355 NULL, /* float arithmetic mode, will be set below */
2356 12, /* size of trampoline code */
2357 4, /* alignment of trampoline code */
2358 ia32_create_trampoline_fkt,
2359 4 /* alignment of stack parameter */
2362 ia32_setup_cg_config();
2364 /* doesn't really belong here, but this is the earliest place the backend
2366 init_asm_constraints();
2369 if (! ia32_cg_config.use_sse2)
2370 p.mode_float_arithmetic = mode_E;
2374 static const lc_opt_enum_int_items_t gas_items[] = {
2375 { "elf", OBJECT_FILE_FORMAT_ELF },
2376 { "mingw", OBJECT_FILE_FORMAT_COFF },
2377 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2381 static lc_opt_enum_int_var_t gas_var = {
2382 (int*) &be_gas_object_file_format, gas_items
2385 #ifdef FIRM_GRGEN_BE
2386 static const lc_opt_enum_int_items_t transformer_items[] = {
2387 { "default", TRANSFORMER_DEFAULT },
2388 { "pbqp", TRANSFORMER_PBQP },
2389 { "random", TRANSFORMER_RAND },
2393 static lc_opt_enum_int_var_t transformer_var = {
2394 (int*)&be_transformer, transformer_items
2398 static const lc_opt_table_entry_t ia32_options[] = {
2399 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2400 #ifdef FIRM_GRGEN_BE
2401 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2403 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2404 &ia32_isa_template.base.stack_alignment),
2408 const arch_isa_if_t ia32_isa_if = {
2411 ia32_handle_intrinsics,
2412 ia32_get_n_reg_class,
2414 ia32_get_reg_class_for_mode,
2416 ia32_get_code_generator_if,
2417 ia32_get_list_sched_selector,
2418 ia32_get_ilp_sched_selector,
2419 ia32_get_reg_class_alignment,
2420 ia32_get_libfirm_params,
2421 ia32_get_allowed_execution_units,
2425 ia32_parse_asm_constraint,
2426 ia32_is_valid_clobber
2429 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
2430 void be_init_arch_ia32(void)
2432 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2433 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2435 lc_opt_add_table(ia32_grp, ia32_options);
2436 be_register_isa_if("ia32", &ia32_isa_if);
2438 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2440 ia32_init_emitter();
2442 ia32_init_optimize();
2443 ia32_init_transform();
2445 ia32_init_architecture();