2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
26 #include "pseudo_irg.h"
30 #include "iredges_t.h"
38 #include "../beabi.h" /* the general register allocator interface */
39 #include "../benode_t.h"
40 #include "../belower.h"
41 #include "../besched_t.h"
44 #include "../beirgmod.h"
45 #include "../be_dbgout.h"
46 #include "../beblocksched.h"
47 #include "bearch_ia32_t.h"
49 #include "ia32_new_nodes.h" /* ia32 nodes interface */
50 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
51 #include "ia32_gen_decls.h" /* interface declaration emitter */
52 #include "ia32_transform.h"
53 #include "ia32_emitter.h"
54 #include "ia32_map_regs.h"
55 #include "ia32_optimize.h"
57 #include "ia32_dbg_stat.h"
58 #include "ia32_finish.h"
59 #include "ia32_util.h"
61 #define DEBUG_MODULE "firm.be.ia32.isa"
64 static set *cur_reg_set = NULL;
66 /* Creates the unique per irg GP NoReg node. */
67 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
68 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
71 /* Creates the unique per irg FP NoReg node. */
72 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
73 return be_abi_get_callee_save_irn(cg->birg->abi,
74 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
78 * Returns gp_noreg or fp_noreg, depending in input requirements.
80 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
81 arch_register_req_t req;
82 const arch_register_req_t *p_req;
84 p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
85 assert(p_req && "Missing register requirements");
86 if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
87 return ia32_new_NoReg_gp(cg);
89 return ia32_new_NoReg_fp(cg);
92 /**************************************************
95 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
96 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
97 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
98 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
101 **************************************************/
104 * Return register requirements for an ia32 node.
105 * If the node returns a tuple (mode_T) then the proj's
106 * will be asked for this information.
108 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
109 const ia32_irn_ops_t *ops = self;
110 const ia32_register_req_t *irn_req;
111 long node_pos = pos == -1 ? 0 : pos;
112 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
113 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
115 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
116 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
120 if (mode == mode_T && pos < 0) {
121 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
125 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
129 DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
133 node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
134 irn = skip_Proj(irn);
136 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
139 if (is_ia32_irn(irn)) {
140 irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
141 if (irn_req == NULL) {
142 /* no requirements */
146 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
148 memcpy(req, &(irn_req->req), sizeof(*req));
150 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
151 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
152 req->other_same = get_irn_n(irn, irn_req->same_pos);
155 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
156 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
157 req->other_different = get_irn_n(irn, irn_req->different_pos);
161 /* treat Unknowns like Const with default requirements */
162 if (is_Unknown(irn)) {
163 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
164 if (mode_is_float(mode)) {
165 if (USE_SSE2(ops->cg))
166 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
168 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
170 else if (mode_is_int(mode) || mode_is_reference(mode))
171 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
172 else if (mode == mode_T || mode == mode_M) {
173 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
177 assert(0 && "unsupported Unknown-Mode");
180 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
188 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
190 const ia32_irn_ops_t *ops = self;
192 if (get_irn_mode(irn) == mode_X) {
196 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
199 pos = get_Proj_proj(irn);
200 irn = skip_Proj(irn);
203 if (is_ia32_irn(irn)) {
204 const arch_register_t **slots;
206 slots = get_ia32_slots(irn);
210 ia32_set_firm_reg(irn, reg, cur_reg_set);
214 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
216 const arch_register_t *reg = NULL;
220 if (get_irn_mode(irn) == mode_X) {
224 pos = get_Proj_proj(irn);
225 irn = skip_Proj(irn);
228 if (is_ia32_irn(irn)) {
229 const arch_register_t **slots;
230 slots = get_ia32_slots(irn);
234 reg = ia32_get_firm_reg(irn, cur_reg_set);
240 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
241 arch_irn_class_t classification = arch_irn_class_normal;
243 irn = skip_Proj(irn);
246 classification |= arch_irn_class_branch;
248 if (! is_ia32_irn(irn))
249 return classification & ~arch_irn_class_normal;
251 if (is_ia32_Cnst(irn))
252 classification |= arch_irn_class_const;
255 classification |= arch_irn_class_load;
257 if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
258 classification |= arch_irn_class_store;
260 if (is_ia32_got_reload(irn))
261 classification |= arch_irn_class_reload;
263 return classification;
266 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
267 arch_irn_flags_t flags;
268 ir_node *pred = is_Proj(irn) && mode_is_datab(get_irn_mode(irn)) ? get_Proj_pred(irn) : NULL;
271 flags = arch_irn_flags_ignore;
273 /* pred is only set, if we have a Proj */
274 flags = pred && is_ia32_irn(pred) ? get_ia32_out_flags(pred, get_Proj_proj(irn)) : arch_irn_flags_none;
276 irn = skip_Proj(irn);
277 if (is_ia32_irn(irn))
278 flags |= get_ia32_flags(irn);
285 * The IA32 ABI callback object.
288 be_abi_call_flags_bits_t flags; /**< The call flags. */
289 const arch_isa_t *isa; /**< The ISA handle. */
290 const arch_env_t *aenv; /**< The architecture environment. */
291 ir_graph *irg; /**< The associated graph. */
294 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
295 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
298 static void ia32_set_frame_entity(const void *self, ir_node *irn, entity *ent) {
299 set_ia32_frame_ent(irn, ent);
302 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
304 const ia32_irn_ops_t *ops = self;
306 if (get_ia32_frame_ent(irn)) {
307 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
309 if(is_ia32_Pop(irn)) {
310 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
312 /* Pop nodes modify the stack pointer before calculating the destination
313 * address, so fix this here
319 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
321 snprintf(buf, sizeof(buf), "%d", bias);
323 if (get_ia32_op_type(irn) == ia32_Normal) {
324 set_ia32_cnst(irn, buf);
326 add_ia32_am_offs(irn, buf);
328 set_ia32_am_flavour(irn, am_flav);
333 static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
335 long proj = get_Proj_proj(irn);
336 ir_node *pred = get_Proj_pred(irn);
338 if (proj == pn_ia32_Push_stack && is_ia32_Push(pred))
340 if (proj == pn_ia32_Pop_stack && is_ia32_Pop(pred))
348 * Put all registers which are saved by the prologue/epilogue in a set.
350 * @param self The callback object.
351 * @param s The result set.
353 static void ia32_abi_dont_save_regs(void *self, pset *s)
355 ia32_abi_env_t *env = self;
356 if(env->flags.try_omit_fp)
357 pset_insert_ptr(s, env->isa->bp);
361 * Generate the routine prologue.
363 * @param self The callback object.
364 * @param mem A pointer to the mem node. Update this if you define new memory.
365 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
367 * @return The register which shall be used as a stack frame base.
369 * All nodes which define registers in @p reg_map must keep @p reg_map current.
371 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
373 ia32_abi_env_t *env = self;
375 if (! env->flags.try_omit_fp) {
376 ir_node *bl = get_irg_start_block(env->irg);
377 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
378 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
379 ir_node *noreg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
383 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
384 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
385 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
387 /* the push must have SP out register */
388 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
389 set_ia32_flags(push, arch_irn_flags_ignore);
391 /* move esp to ebp */
392 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
393 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
394 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
395 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
397 /* beware: the copy must be done before any other sp use */
398 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
399 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
400 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
401 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
403 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
404 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
413 * Generate the routine epilogue.
414 * @param self The callback object.
415 * @param bl The block for the epilog
416 * @param mem A pointer to the mem node. Update this if you define new memory.
417 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
418 * @return The register which shall be used as a stack frame base.
420 * All nodes which define registers in @p reg_map must keep @p reg_map current.
422 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
424 ia32_abi_env_t *env = self;
425 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
426 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
428 if (env->flags.try_omit_fp) {
429 /* simply remove the stack frame here */
430 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
431 add_irn_dep(curr_sp, *mem);
434 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
435 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
437 /* gcc always emits a leave at the end of a routine */
438 if (1 || ARCH_AMD(isa->opt_arch)) {
442 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
443 set_ia32_flags(leave, arch_irn_flags_ignore);
444 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
445 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
446 *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
449 ir_node *noreg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
452 /* copy ebp to esp */
453 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
456 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
457 set_ia32_flags(pop, arch_irn_flags_ignore);
458 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
459 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
460 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
462 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
463 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
466 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
467 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
471 * Initialize the callback object.
472 * @param call The call object.
473 * @param aenv The architecture environment.
474 * @param irg The graph with the method.
475 * @return Some pointer. This pointer is passed to all other callback functions as self object.
477 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
479 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
480 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
481 env->flags = fl.bits;
484 env->isa = aenv->isa;
489 * Destroy the callback object.
490 * @param self The callback object.
492 static void ia32_abi_done(void *self) {
497 * Produces the type which sits between the stack args and the locals on the stack.
498 * it will contain the return address and space to store the old base pointer.
499 * @return The Firm type modeling the ABI between type.
501 static ir_type *ia32_abi_get_between_type(void *self)
503 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
504 static ir_type *omit_fp_between_type = NULL;
505 static ir_type *between_type = NULL;
507 ia32_abi_env_t *env = self;
509 if ( !between_type) {
511 entity *ret_addr_ent;
512 entity *omit_fp_ret_addr_ent;
514 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_P);
515 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_P);
517 between_type = new_type_struct(IDENT("ia32_between_type"));
518 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
519 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
521 set_entity_offset_bytes(old_bp_ent, 0);
522 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
523 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
524 set_type_state(between_type, layout_fixed);
526 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
527 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
529 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
530 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
531 set_type_state(omit_fp_between_type, layout_fixed);
534 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
539 * Get the estimated cycle count for @p irn.
541 * @param self The this pointer.
542 * @param irn The node.
544 * @return The estimated cycle count for this operation
546 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
549 ia32_op_type_t op_tp;
550 const ia32_irn_ops_t *ops = self;
555 assert(is_ia32_irn(irn));
557 cost = get_ia32_latency(irn);
558 op_tp = get_ia32_op_type(irn);
560 if (is_ia32_CopyB(irn)) {
562 if (ARCH_INTEL(ops->cg->arch))
565 else if (is_ia32_CopyB_i(irn)) {
566 int size = get_tarval_long(get_ia32_Immop_tarval(irn));
567 cost = 20 + (int)ceil((4/3) * size);
568 if (ARCH_INTEL(ops->cg->arch))
571 /* in case of address mode operations add additional cycles */
572 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
574 In case of stack access add 5 cycles (we assume stack is in cache),
575 other memory operations cost 20 cycles.
577 cost += is_ia32_use_frame(irn) ? 5 : 20;
584 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
586 * @param irn The original operation
587 * @param i Index of the argument we want the inverse operation to yield
588 * @param inverse struct to be filled with the resulting inverse op
589 * @param obstack The obstack to use for allocation of the returned nodes array
590 * @return The inverse operation or NULL if operation invertible
592 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
595 ir_node *block, *noreg, *nomem;
598 /* we cannot invert non-ia32 irns */
599 if (! is_ia32_irn(irn))
602 /* operand must always be a real operand (not base, index or mem) */
603 if (i != 2 && i != 3)
606 /* we don't invert address mode operations */
607 if (get_ia32_op_type(irn) != ia32_Normal)
610 irg = get_irn_irg(irn);
611 block = get_nodes_block(irn);
612 mode = get_ia32_res_mode(irn);
613 noreg = get_irn_n(irn, 0);
614 nomem = new_r_NoMem(irg);
616 /* initialize structure */
617 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
621 switch (get_ia32_irn_opcode(irn)) {
623 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
624 /* we have an add with a const here */
625 /* invers == add with negated const */
626 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
627 pnc = pn_ia32_Add_res;
629 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
630 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
631 set_ia32_commutative(inverse->nodes[0]);
633 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
634 /* we have an add with a symconst here */
635 /* invers == sub with const */
636 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
637 pnc = pn_ia32_Sub_res;
639 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
642 /* normal add: inverse == sub */
643 ir_node *proj = ia32_get_res_proj(irn);
646 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, i ^ 1), nomem);
647 pnc = pn_ia32_Sub_res;
652 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
653 /* we have a sub with a const/symconst here */
654 /* invers == add with this const */
655 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
656 pnc = pn_ia32_Add_res;
657 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
658 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
662 ir_node *proj = ia32_get_res_proj(irn);
666 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, 3), nomem);
669 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, 2), proj, nomem);
671 pnc = pn_ia32_Sub_res;
676 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
677 /* xor with const: inverse = xor */
678 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
679 pnc = pn_ia32_Eor_res;
680 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
681 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
685 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, (ir_node *)irn, get_irn_n(irn, i), nomem);
686 pnc = pn_ia32_Eor_res;
691 ir_node *proj = ia32_get_res_proj(irn);
694 inverse->nodes[0] = new_rd_ia32_Not(NULL, irg, block, noreg, noreg, proj, nomem);
695 pnc = pn_ia32_Not_res;
699 case iro_ia32_Minus: {
700 ir_node *proj = ia32_get_res_proj(irn);
703 inverse->nodes[0] = new_rd_ia32_Minus(NULL, irg, block, noreg, noreg, proj, nomem);
704 pnc = pn_ia32_Minus_res;
709 /* inverse operation not supported */
713 set_ia32_res_mode(inverse->nodes[0], mode);
714 inverse->nodes[1] = new_r_Proj(irg, block, inverse->nodes[0], mode, pnc);
720 * Check if irn can load it's operand at position i from memory (source addressmode).
721 * @param self Pointer to irn ops itself
722 * @param irn The irn to be checked
723 * @param i The operands position
724 * @return Non-Zero if operand can be loaded
726 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
727 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
728 get_irn_arity(irn) != 5 || /* must be a binary operation */
729 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
730 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
731 (i != 2 && i != 3) || /* a "real" operand position must be requested */
732 (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
733 is_ia32_use_frame(irn)) /* must not already use frame */
739 static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
740 const ia32_irn_ops_t *ops = self;
741 ia32_code_gen_t *cg = ops->cg;
743 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
746 ir_node *tmp = get_irn_n(irn, 3);
747 set_irn_n(irn, 3, get_irn_n(irn, 2));
748 set_irn_n(irn, 2, tmp);
751 set_ia32_am_support(irn, ia32_am_Source);
752 set_ia32_op_type(irn, ia32_AddrModeS);
753 set_ia32_am_flavour(irn, ia32_B);
754 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
755 set_ia32_use_frame(irn);
756 set_ia32_got_reload(irn);
758 set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
759 set_irn_n(irn, 4, spill);
762 Input at position one is index register, which is NoReg.
763 We would need cg object to get a real noreg, but we cannot
766 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
768 //FIXME DBG_OPT_AM_S(reload, irn);
771 static const be_abi_callbacks_t ia32_abi_callbacks = {
774 ia32_abi_get_between_type,
775 ia32_abi_dont_save_regs,
780 /* fill register allocator interface */
782 static const arch_irn_ops_if_t ia32_irn_ops_if = {
783 ia32_get_irn_reg_req,
788 ia32_get_frame_entity,
789 ia32_set_frame_entity,
790 ia32_set_frame_offset,
793 ia32_get_op_estimated_cost,
794 ia32_possible_memory_operand,
795 ia32_perform_memory_operand,
798 ia32_irn_ops_t ia32_irn_ops = {
805 /**************************************************
808 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
809 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
810 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
811 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
814 **************************************************/
816 static void ia32_kill_convs(ia32_code_gen_t *cg) {
819 /* BEWARE: the Projs are inserted in the set */
820 foreach_nodeset(cg->kill_conv, irn) {
821 ir_node *in = get_irn_n(get_Proj_pred(irn), 2);
822 edges_reroute(irn, in, cg->birg->irg);
827 * Transform the Thread Local Store base.
829 static void transform_tls(ir_graph *irg) {
830 ir_node *irn = get_irg_tls(irg);
833 dbg_info *dbg = get_irn_dbg_info(irn);
834 ir_node *blk = get_nodes_block(irn);
836 newn = new_rd_ia32_LdTls(dbg, irg, blk, get_irn_mode(irn));
843 * Transforms the standard firm graph into
846 static void ia32_prepare_graph(void *self) {
847 ia32_code_gen_t *cg = self;
848 dom_front_info_t *dom;
849 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
851 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
853 /* 1st: transform constants and psi condition trees */
854 ia32_pre_transform_phase(cg);
856 /* 2nd: transform all remaining nodes */
857 ia32_register_transformers();
858 dom = be_compute_dominance_frontiers(cg->irg);
860 cg->kill_conv = new_nodeset(5);
861 transform_tls(cg->irg);
862 edges_deactivate(cg->irg);
863 edges_activate(cg->irg);
864 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
866 del_nodeset(cg->kill_conv);
868 be_free_dominance_frontiers(dom);
871 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
873 /* 3rd: optimize address mode */
874 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
875 ia32_optimize_addressmode(cg);
878 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
880 DEBUG_ONLY(cg->mod = old_mod;)
884 * Dummy functions for hooks we don't need but which must be filled.
886 static void ia32_before_sched(void *self) {
889 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
892 ir_node *mem_proj = NULL;
897 mode = get_irn_mode(irn);
899 /* check if we already saw this node or the node has more than one user */
900 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) {
904 /* mark irn visited */
905 bitset_add_irn(already_visited, irn);
907 /* non-Tuple nodes with one user: ok, return */
908 if (get_irn_n_edges(irn) >= 1 && mode != mode_T) {
912 /* tuple node has one user which is not the mem proj-> ok */
913 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
914 mem_proj = ia32_get_proj_for_mode(irn, mode_M);
915 if (mem_proj == NULL) {
920 arity = get_irn_arity(irn);
921 for (i = 0; i < arity; ++i) {
922 ir_node *pred = get_irn_n(irn, i);
924 /* do not follow memory edges or we will accidentally remove stores */
925 if (get_irn_mode(pred) == mode_M) {
926 if(mem_proj != NULL) {
927 edges_reroute(mem_proj, pred, get_irn_irg(mem_proj));
933 set_irn_n(irn, i, new_Bad());
936 The current node is about to be removed: if the predecessor
937 has only this node as user, it need to be removed as well.
939 if (get_irn_n_edges(pred) <= 1)
940 remove_unused_nodes(pred, already_visited);
943 // we need to set the presd to Bad again to also get the memory edges
944 arity = get_irn_arity(irn);
945 for (i = 0; i < arity; ++i) {
946 set_irn_n(irn, i, new_Bad());
949 if (sched_is_scheduled(irn)) {
954 static void remove_unused_loads_walker(ir_node *irn, void *env) {
955 bitset_t *already_visited = env;
956 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
957 remove_unused_nodes(irn, env);
961 * Called before the register allocator.
962 * Calculate a block schedule here. We need it for the x87
963 * simulator and the emitter.
965 static void ia32_before_ra(void *self) {
966 ia32_code_gen_t *cg = self;
967 bitset_t *already_visited = bitset_irg_alloca(cg->irg);
971 There are sometimes unused loads, only pinned by memory.
972 We need to remove those Loads and all other nodes which won't be used
973 after removing the Load from schedule.
975 irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
980 * Transforms a be node into a Load.
982 static void transform_to_Load(ia32_transform_env_t *env) {
983 ir_node *irn = env->irn;
984 entity *ent = be_get_frame_entity(irn);
985 ir_mode *mode = env->mode;
986 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
987 ir_node *nomem = new_rd_NoMem(env->irg);
988 ir_node *sched_point = NULL;
989 ir_node *ptr = get_irn_n(irn, 0);
990 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
991 ir_node *new_op, *proj;
992 const arch_register_t *reg;
994 if (sched_is_scheduled(irn)) {
995 sched_point = sched_prev(irn);
998 if (mode_is_float(mode)) {
999 if (USE_SSE2(env->cg))
1000 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1002 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1005 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1007 set_ia32_am_support(new_op, ia32_am_Source);
1008 set_ia32_op_type(new_op, ia32_AddrModeS);
1009 set_ia32_am_flavour(new_op, ia32_B);
1010 set_ia32_ls_mode(new_op, mode);
1011 set_ia32_frame_ent(new_op, ent);
1012 set_ia32_use_frame(new_op);
1014 DBG_OPT_RELOAD2LD(irn, new_op);
1016 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1019 sched_add_after(sched_point, new_op);
1020 sched_add_after(new_op, proj);
1025 /* copy the register from the old node to the new Load */
1026 reg = arch_get_irn_register(env->cg->arch_env, irn);
1027 arch_set_irn_register(env->cg->arch_env, new_op, reg);
1029 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
1031 exchange(irn, proj);
1035 * Transforms a be node into a Store.
1037 static void transform_to_Store(ia32_transform_env_t *env) {
1038 ir_node *irn = env->irn;
1039 entity *ent = be_get_frame_entity(irn);
1040 ir_mode *mode = env->mode;
1041 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1042 ir_node *nomem = new_rd_NoMem(env->irg);
1043 ir_node *ptr = get_irn_n(irn, 0);
1044 ir_node *val = get_irn_n(irn, 1);
1045 ir_node *new_op, *proj;
1046 ir_node *sched_point = NULL;
1048 if (sched_is_scheduled(irn)) {
1049 sched_point = sched_prev(irn);
1052 if (mode_is_float(mode)) {
1053 if (USE_SSE2(env->cg))
1054 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1056 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1058 else if (get_mode_size_bits(mode) == 8) {
1059 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1062 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1065 set_ia32_am_support(new_op, ia32_am_Dest);
1066 set_ia32_op_type(new_op, ia32_AddrModeD);
1067 set_ia32_am_flavour(new_op, ia32_B);
1068 set_ia32_ls_mode(new_op, mode);
1069 set_ia32_frame_ent(new_op, ent);
1070 set_ia32_use_frame(new_op);
1072 DBG_OPT_SPILL2ST(irn, new_op);
1074 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
1077 sched_add_after(sched_point, new_op);
1081 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
1083 exchange(irn, proj);
1086 static ir_node *create_push(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, ir_node *mem, entity *ent) {
1087 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1088 ir_node *frame = get_irg_frame(env->irg);
1090 ir_node *push = new_rd_ia32_Push(env->dbg, env->irg, env->block, frame, noreg, noreg, sp, mem);
1092 set_ia32_frame_ent(push, ent);
1093 set_ia32_use_frame(push);
1094 set_ia32_op_type(push, ia32_AddrModeS);
1095 set_ia32_am_flavour(push, ia32_B);
1096 set_ia32_ls_mode(push, mode_Is);
1098 sched_add_before(schedpoint, push);
1102 static ir_node *create_pop(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, entity *ent) {
1103 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1104 ir_node *frame = get_irg_frame(env->irg);
1106 ir_node *pop = new_rd_ia32_Pop(env->dbg, env->irg, env->block, frame, noreg, sp, new_NoMem());
1108 set_ia32_frame_ent(pop, ent);
1109 set_ia32_use_frame(pop);
1110 set_ia32_op_type(pop, ia32_AddrModeD);
1111 set_ia32_am_flavour(pop, ia32_B);
1112 set_ia32_ls_mode(pop, mode_Is);
1114 sched_add_before(schedpoint, pop);
1119 static ir_node* create_spproj(ia32_transform_env_t *env, ir_node *pred, int pos, ir_node *schedpoint) {
1120 ir_mode *spmode = mode_Iu;
1121 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1124 sp = new_rd_Proj(env->dbg, env->irg, env->block, pred, spmode, pos);
1125 arch_set_irn_register(env->cg->arch_env, sp, spreg);
1126 sched_add_before(schedpoint, sp);
1132 * Transform memperm, currently we do this the ugly way and produce
1133 * push/pop into/from memory cascades. This is possible without using
1136 static void transform_MemPerm(ia32_transform_env_t *env) {
1137 ir_node *node = env->irn;
1139 ir_node *sp = be_abi_get_ignore_irn(env->cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1140 const ir_edge_t *edge;
1141 const ir_edge_t *next;
1144 arity = be_get_MemPerm_entity_arity(node);
1145 pops = alloca(arity * sizeof(pops[0]));
1148 for(i = 0; i < arity; ++i) {
1149 entity *ent = be_get_MemPerm_in_entity(node, i);
1150 ir_type *enttype = get_entity_type(ent);
1151 int entbits = get_type_size_bits(enttype);
1152 ir_node *mem = get_irn_n(node, i + 1);
1155 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1157 push = create_push(env, node, sp, mem, ent);
1158 sp = create_spproj(env, push, 0, node);
1160 // add another push after the first one
1161 push = create_push(env, node, sp, mem, ent);
1162 add_ia32_am_offs_int(push, 4);
1163 sp = create_spproj(env, push, 0, node);
1166 set_irn_n(node, i, new_Bad());
1170 for(i = arity - 1; i >= 0; --i) {
1171 entity *ent = be_get_MemPerm_out_entity(node, i);
1172 ir_type *enttype = get_entity_type(ent);
1173 int entbits = get_type_size_bits(enttype);
1177 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1179 pop = create_pop(env, node, sp, ent);
1181 // add another pop after the first one
1182 sp = create_spproj(env, pop, 1, node);
1183 pop = create_pop(env, node, sp, ent);
1184 add_ia32_am_offs_int(pop, 4);
1186 sp = create_spproj(env, pop, 1, node);
1191 // exchange memprojs
1192 foreach_out_edge_safe(node, edge, next) {
1193 ir_node *proj = get_edge_src_irn(edge);
1194 int p = get_Proj_proj(proj);
1198 set_Proj_pred(proj, pops[p]);
1199 set_Proj_proj(proj, 3);
1203 arity = get_irn_arity(node);
1204 for(i = 0; i < arity; ++i) {
1205 set_irn_n(node, i, new_Bad());
1211 * Fix the mode of Spill/Reload
1213 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
1215 if (mode_is_float(mode)) {
1227 * Block-Walker: Calls the transform functions Spill and Reload.
1229 static void ia32_after_ra_walker(ir_node *block, void *env) {
1230 ir_node *node, *prev;
1231 ia32_code_gen_t *cg = env;
1232 ia32_transform_env_t tenv;
1235 tenv.irg = current_ir_graph;
1237 DEBUG_ONLY(tenv.mod = cg->mod;)
1239 /* beware: the schedule is changed here */
1240 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1241 prev = sched_prev(node);
1242 if (be_is_Reload(node)) {
1243 /* we always reload the whole register */
1244 tenv.dbg = get_irn_dbg_info(node);
1246 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
1247 transform_to_Load(&tenv);
1249 else if (be_is_Spill(node)) {
1250 ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1251 /* we always spill the whole register */
1252 tenv.dbg = get_irn_dbg_info(node);
1254 tenv.mode = fix_spill_mode(cg, get_irn_mode(spillval));
1255 transform_to_Store(&tenv);
1257 else if(be_is_MemPerm(node)) {
1258 tenv.dbg = get_irn_dbg_info(node);
1260 transform_MemPerm(&tenv);
1266 * We transform Spill and Reload here. This needs to be done before
1267 * stack biasing otherwise we would miss the corrected offset for these nodes.
1269 * If x87 instruction should be emitted, run the x87 simulator and patch
1270 * the virtual instructions. This must obviously be done after register allocation.
1272 static void ia32_after_ra(void *self) {
1273 ia32_code_gen_t *cg = self;
1274 ir_graph *irg = cg->irg;
1276 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1278 ia32_finish_irg(irg, cg);
1282 * Last touchups for the graph before emit
1284 static void ia32_finish(void *self) {
1285 ia32_code_gen_t *cg = self;
1286 ir_graph *irg = cg->irg;
1288 //be_remove_empty_blocks(irg);
1289 cg->blk_sched = be_create_block_schedule(irg, cg->birg->execfreqs);
1291 //cg->blk_sched = sched_create_block_schedule(cg->irg, cg->birg->execfreqs);
1293 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1294 if (cg->used_fp == fp_x87 || cg->force_sim) {
1295 x87_simulate_graph(cg->arch_env, irg, cg->blk_sched);
1298 ia32_peephole_optimization(irg, cg);
1302 * Emits the code, closes the output file and frees
1303 * the code generator interface.
1305 static void ia32_codegen(void *self) {
1306 ia32_code_gen_t *cg = self;
1307 ir_graph *irg = cg->irg;
1309 ia32_gen_routine(cg->isa->out, irg, cg);
1313 /* remove it from the isa */
1316 /* de-allocate code generator */
1317 del_set(cg->reg_set);
1321 static void *ia32_cg_init(const be_irg_t *birg);
1323 static const arch_code_generator_if_t ia32_code_gen_if = {
1325 NULL, /* before abi introduce hook */
1327 ia32_before_sched, /* before scheduling hook */
1328 ia32_before_ra, /* before register allocation hook */
1329 ia32_after_ra, /* after register allocation hook */
1330 ia32_finish, /* called before codegen */
1331 ia32_codegen /* emit && done */
1335 * Initializes a IA32 code generator.
1337 static void *ia32_cg_init(const be_irg_t *birg) {
1338 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1339 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1341 cg->impl = &ia32_code_gen_if;
1342 cg->irg = birg->irg;
1343 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1344 cg->arch_env = birg->main_env->arch_env;
1347 cg->blk_sched = NULL;
1348 cg->fp_to_gp = NULL;
1349 cg->gp_to_fp = NULL;
1350 cg->fp_kind = isa->fp_kind;
1351 cg->used_fp = fp_none;
1352 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1354 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1356 /* copy optimizations from isa for easier access */
1358 cg->arch = isa->arch;
1359 cg->opt_arch = isa->opt_arch;
1365 if (isa->name_obst_size) {
1366 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
1367 isa->name_obst_size = 0;
1368 obstack_free(isa->name_obst, NULL);
1369 obstack_init(isa->name_obst);
1373 cur_reg_set = cg->reg_set;
1375 ia32_irn_ops.cg = cg;
1377 return (arch_code_generator_t *)cg;
1382 /*****************************************************************
1383 * ____ _ _ _____ _____
1384 * | _ \ | | | | |_ _|/ ____| /\
1385 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1386 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1387 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1388 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1390 *****************************************************************/
1393 * Set output modes for GCC
1395 static const tarval_mode_info mo_integer = {
1402 * set the tarval output mode of all integer modes to decimal
1404 static void set_tarval_output_modes(void)
1408 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1409 ir_mode *mode = get_irp_mode(i);
1411 if (mode_is_int(mode))
1412 set_tarval_mode_output_option(mode, &mo_integer);
1418 * The template that generates a new ISA object.
1419 * Note that this template can be changed by command line
1422 static ia32_isa_t ia32_isa_template = {
1424 &ia32_isa_if, /* isa interface implementation */
1425 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1426 &ia32_gp_regs[REG_EBP], /* base pointer register */
1427 -1, /* stack direction */
1428 NULL, /* main environment */
1430 NULL, /* 16bit register names */
1431 NULL, /* 8bit register names */
1435 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1436 IA32_OPT_DOAM | /* optimize address mode default: on */
1437 IA32_OPT_LEA | /* optimize for LEAs default: on */
1438 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1439 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1440 IA32_OPT_EXTBB | /* use extended basic block scheduling, default: on */
1441 IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
1442 arch_pentium_4, /* instruction architecture */
1443 arch_pentium_4, /* optimize for architecture */
1444 fp_sse2, /* use sse2 unit */
1445 NULL, /* current code generator */
1446 NULL, /* output file */
1448 NULL, /* name obstack */
1449 0 /* name obst size */
1454 * Initializes the backend ISA.
1456 static void *ia32_init(FILE *file_handle) {
1457 static int inited = 0;
1463 set_tarval_output_modes();
1465 isa = xmalloc(sizeof(*isa));
1466 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1468 ia32_register_init(isa);
1469 ia32_create_opcodes();
1471 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1472 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1473 /* no SSE2 for these cpu's */
1474 isa->fp_kind = fp_x87;
1476 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1477 /* Pentium 4 don't like inc and dec instructions */
1478 isa->opt &= ~IA32_OPT_INCDEC;
1481 isa->regs_16bit = pmap_create();
1482 isa->regs_8bit = pmap_create();
1483 isa->types = pmap_create();
1484 isa->tv_ent = pmap_create();
1485 isa->out = file_handle;
1487 ia32_build_16bit_reg_map(isa->regs_16bit);
1488 ia32_build_8bit_reg_map(isa->regs_8bit);
1490 /* patch register names of x87 registers */
1491 ia32_st_regs[0].name = "st";
1492 ia32_st_regs[1].name = "st(1)";
1493 ia32_st_regs[2].name = "st(2)";
1494 ia32_st_regs[3].name = "st(3)";
1495 ia32_st_regs[4].name = "st(4)";
1496 ia32_st_regs[5].name = "st(5)";
1497 ia32_st_regs[6].name = "st(6)";
1498 ia32_st_regs[7].name = "st(7)";
1501 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1502 obstack_init(isa->name_obst);
1503 isa->name_obst_size = 0;
1506 ia32_handle_intrinsics();
1507 ia32_switch_section(isa->out, NO_SECTION);
1508 fprintf(isa->out, "\t.intel_syntax\n");
1510 /* needed for the debug support */
1511 ia32_switch_section(isa->out, SECTION_TEXT);
1512 fprintf(isa->out, ".Ltext0:\n");
1522 * Closes the output file and frees the ISA structure.
1524 static void ia32_done(void *self) {
1525 ia32_isa_t *isa = self;
1527 /* emit now all global declarations */
1528 ia32_gen_decls(isa->out, isa->arch_isa.main_env);
1530 pmap_destroy(isa->regs_16bit);
1531 pmap_destroy(isa->regs_8bit);
1532 pmap_destroy(isa->tv_ent);
1533 pmap_destroy(isa->types);
1536 //printf("name obst size = %d bytes\n", isa->name_obst_size);
1537 obstack_free(isa->name_obst, NULL);
1545 * Return the number of register classes for this architecture.
1546 * We report always these:
1547 * - the general purpose registers
1548 * - the SSE floating point register set
1549 * - the virtual floating point registers
1551 static int ia32_get_n_reg_class(const void *self) {
1556 * Return the register class for index i.
1558 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1559 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1561 return &ia32_reg_classes[CLASS_ia32_gp];
1563 return &ia32_reg_classes[CLASS_ia32_xmm];
1565 return &ia32_reg_classes[CLASS_ia32_vfp];
1569 * Get the register class which shall be used to store a value of a given mode.
1570 * @param self The this pointer.
1571 * @param mode The mode in question.
1572 * @return A register class which can hold values of the given mode.
1574 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1575 const ia32_isa_t *isa = self;
1576 if (mode_is_float(mode)) {
1577 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1580 return &ia32_reg_classes[CLASS_ia32_gp];
1584 * Get the ABI restrictions for procedure calls.
1585 * @param self The this pointer.
1586 * @param method_type The type of the method (procedure) in question.
1587 * @param abi The abi object to be modified
1589 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1590 const ia32_isa_t *isa = self;
1593 unsigned cc = get_method_calling_convention(method_type);
1594 int n = get_method_n_params(method_type);
1597 int i, ignore_1, ignore_2;
1599 const arch_register_t *reg;
1600 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1602 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1604 /* set abi flags for calls */
1605 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1606 call_flags.bits.store_args_sequential = use_push;
1607 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1608 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1609 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1611 /* set stack parameter passing style */
1612 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1614 /* collect the mode for each type */
1615 modes = alloca(n * sizeof(modes[0]));
1617 for (i = 0; i < n; i++) {
1618 tp = get_method_param_type(method_type, i);
1619 modes[i] = get_type_mode(tp);
1622 /* set register parameters */
1623 if (cc & cc_reg_param) {
1624 /* determine the number of parameters passed via registers */
1625 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1627 /* loop over all parameters and set the register requirements */
1628 for (i = 0; i <= biggest_n; i++) {
1629 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1630 assert(reg && "kaputt");
1631 be_abi_call_param_reg(abi, i, reg);
1638 /* set stack parameters */
1639 for (i = stack_idx; i < n; i++) {
1640 /* parameters on the stack are 32 bit aligned */
1641 be_abi_call_param_stack(abi, i, 4, 0, 0);
1645 /* set return registers */
1646 n = get_method_n_ress(method_type);
1648 assert(n <= 2 && "more than two results not supported");
1650 /* In case of 64bit returns, we will have two 32bit values */
1652 tp = get_method_res_type(method_type, 0);
1653 mode = get_type_mode(tp);
1655 assert(!mode_is_float(mode) && "two FP results not supported");
1657 tp = get_method_res_type(method_type, 1);
1658 mode = get_type_mode(tp);
1660 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1662 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1663 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1666 const arch_register_t *reg;
1668 tp = get_method_res_type(method_type, 0);
1669 assert(is_atomic_type(tp));
1670 mode = get_type_mode(tp);
1672 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1674 be_abi_call_res_reg(abi, 0, reg);
1679 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1680 return &ia32_irn_ops;
1683 const arch_irn_handler_t ia32_irn_handler = {
1687 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1688 return &ia32_irn_handler;
1691 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1692 return is_ia32_irn(irn) ? 1 : -1;
1696 * Initializes the code generator interface.
1698 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1699 return &ia32_code_gen_if;
1703 * Returns the estimated execution time of an ia32 irn.
1705 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1706 const arch_env_t *arch_env = env;
1707 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1710 list_sched_selector_t ia32_sched_selector;
1713 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1715 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1716 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1717 ia32_sched_selector.exectime = ia32_sched_exectime;
1718 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1719 return &ia32_sched_selector;
1723 * Returns the necessary byte alignment for storing a register of given class.
1725 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1726 ir_mode *mode = arch_register_class_mode(cls);
1727 int bytes = get_mode_size_bytes(mode);
1729 if (mode_is_float(mode) && bytes > 8)
1735 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1736 * @return 1 if allowed, 0 otherwise
1738 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
1740 ir_node *cmp, *cmp_a, *phi;
1743 /* we don't want long long an floating point Psi */
1744 #define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
1746 if (get_irn_mode(sel) != mode_b)
1749 cmp = get_Proj_pred(sel);
1750 cmp_a = get_Cmp_left(cmp);
1751 mode = get_irn_mode(cmp_a);
1753 if (IS_BAD_PSI_MODE(mode))
1756 /* check the Phi nodes */
1757 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1758 ir_node *pred_i = get_irn_n(phi, i);
1759 ir_node *pred_j = get_irn_n(phi, j);
1760 ir_mode *mode_i = get_irn_mode(pred_i);
1761 ir_mode *mode_j = get_irn_mode(pred_j);
1763 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1767 #undef IS_BAD_PSI_MODE
1772 static ia32_intrinsic_env_t intrinsic_env = {
1773 NULL, /**< the irg, these entities belong to */
1774 NULL, /**< entity for first div operand (move into FPU) */
1775 NULL, /**< entity for second div operand (move into FPU) */
1776 NULL, /**< entity for converts ll -> d */
1777 NULL, /**< entity for converts d -> ll */
1781 * Returns the libFirm configuration parameter for this backend.
1783 static const backend_params *ia32_get_libfirm_params(void) {
1784 static const opt_if_conv_info_t ifconv = {
1785 4, /* maxdepth, doesn't matter for Psi-conversion */
1786 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
1788 static const arch_dep_params_t ad = {
1789 1, /* also use subs */
1790 4, /* maximum shifts */
1791 31, /* maximum shift amount */
1793 1, /* allow Mulhs */
1794 1, /* allow Mulus */
1795 32 /* Mulh allowed up to 32 bit */
1797 static backend_params p = {
1798 NULL, /* no additional opcodes */
1799 NULL, /* will be set later */
1800 1, /* need dword lowering */
1801 ia32_create_intrinsic_fkt,
1802 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1803 NULL, /* will be set later */
1807 p.if_conv_info = &ifconv;
1812 /* instruction set architectures. */
1813 static const lc_opt_enum_int_items_t arch_items[] = {
1814 { "386", arch_i386, },
1815 { "486", arch_i486, },
1816 { "pentium", arch_pentium, },
1817 { "586", arch_pentium, },
1818 { "pentiumpro", arch_pentium_pro, },
1819 { "686", arch_pentium_pro, },
1820 { "pentiummmx", arch_pentium_mmx, },
1821 { "pentium2", arch_pentium_2, },
1822 { "p2", arch_pentium_2, },
1823 { "pentium3", arch_pentium_3, },
1824 { "p3", arch_pentium_3, },
1825 { "pentium4", arch_pentium_4, },
1826 { "p4", arch_pentium_4, },
1827 { "pentiumm", arch_pentium_m, },
1828 { "pm", arch_pentium_m, },
1829 { "core", arch_core, },
1831 { "athlon", arch_athlon, },
1832 { "athlon64", arch_athlon_64, },
1833 { "opteron", arch_opteron, },
1837 static lc_opt_enum_int_var_t arch_var = {
1838 &ia32_isa_template.arch, arch_items
1841 static lc_opt_enum_int_var_t opt_arch_var = {
1842 &ia32_isa_template.opt_arch, arch_items
1845 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1847 { "sse2", fp_sse2 },
1851 static lc_opt_enum_int_var_t fp_unit_var = {
1852 &ia32_isa_template.fp_kind, fp_unit_items
1855 static const lc_opt_enum_int_items_t gas_items[] = {
1856 { "linux", ASM_LINUX_GAS },
1857 { "mingw", ASM_MINGW_GAS },
1861 static lc_opt_enum_int_var_t gas_var = {
1862 (int *)&asm_flavour, gas_items
1865 static const lc_opt_table_entry_t ia32_options[] = {
1866 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1867 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1868 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1869 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1870 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
1871 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1872 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1873 LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
1874 LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
1875 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
1880 * Register command line options for the ia32 backend.
1884 * ia32-arch=arch create instruction for arch
1885 * ia32-opt=arch optimize for run on arch
1886 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1887 * ia32-incdec optimize for inc/dec
1888 * ia32-noaddrmode do not use address mode
1889 * ia32-nolea do not optimize for LEAs
1890 * ia32-noplacecnst do not place constants,
1891 * ia32-noimmop no operations with immediates
1892 * ia32-noextbb do not use extended basic block scheduling
1893 * ia32-nopushargs do not create pushs for function argument passing
1894 * ia32-gasmode set the GAS compatibility mode
1896 static void ia32_register_options(lc_opt_entry_t *ent)
1898 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1899 lc_opt_add_table(be_grp_ia32, ia32_options);
1901 #endif /* WITH_LIBCORE */
1903 const arch_isa_if_t ia32_isa_if = {
1906 ia32_get_n_reg_class,
1908 ia32_get_reg_class_for_mode,
1910 ia32_get_irn_handler,
1911 ia32_get_code_generator_if,
1912 ia32_get_list_sched_selector,
1913 ia32_get_reg_class_alignment,
1914 ia32_get_libfirm_params,
1916 ia32_register_options