2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
33 #include "pseudo_irg.h"
38 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
55 #include "../beirg_t.h"
56 #include "../benode_t.h"
57 #include "../belower.h"
58 #include "../besched_t.h"
61 #include "../beirgmod.h"
62 #include "../be_dbgout.h"
63 #include "../beblocksched.h"
64 #include "../bemachine.h"
65 #include "../beilpsched.h"
66 #include "../bespillslots.h"
67 #include "../bemodule.h"
68 #include "../begnuas.h"
69 #include "../bestate.h"
70 #include "../beflags.h"
71 #include "../betranshlp.h"
73 #include "bearch_ia32_t.h"
75 #include "ia32_new_nodes.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "gen_ia32_machine.h"
78 #include "ia32_common_transform.h"
79 #include "ia32_transform.h"
80 #include "ia32_emitter.h"
81 #include "ia32_map_regs.h"
82 #include "ia32_optimize.h"
84 #include "ia32_dbg_stat.h"
85 #include "ia32_finish.h"
86 #include "ia32_util.h"
88 #include "ia32_architecture.h"
91 #include "ia32_pbqp_transform.h"
93 transformer_t be_transformer = TRANSFORMER_DEFAULT;
96 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
99 static set *cur_reg_set = NULL;
101 ir_mode *mode_fpcw = NULL;
102 ia32_code_gen_t *ia32_current_cg = NULL;
104 /** The current omit-fp state */
105 static unsigned ia32_curr_fp_ommitted = 0;
106 static ir_type *omit_fp_between_type = NULL;
107 static ir_type *between_type = NULL;
108 static ir_entity *old_bp_ent = NULL;
109 static ir_entity *ret_addr_ent = NULL;
110 static ir_entity *omit_fp_ret_addr_ent = NULL;
113 * The environment for the intrinsic mapping.
115 static ia32_intrinsic_env_t intrinsic_env = {
117 NULL, /* the irg, these entities belong to */
118 NULL, /* entity for __divdi3 library call */
119 NULL, /* entity for __moddi3 library call */
120 NULL, /* entity for __udivdi3 library call */
121 NULL, /* entity for __umoddi3 library call */
125 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
128 * Used to create per-graph unique pseudo nodes.
130 static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
131 create_const_node_func func,
132 const arch_register_t* reg)
134 ir_node *block, *res;
139 block = get_irg_start_block(cg->irg);
140 res = func(NULL, block);
141 arch_set_irn_register(res, reg);
147 /* Creates the unique per irg GP NoReg node. */
148 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
149 return create_const(cg, &cg->noreg_gp, new_bd_ia32_NoReg_GP,
150 &ia32_gp_regs[REG_GP_NOREG]);
153 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
154 return create_const(cg, &cg->noreg_vfp, new_bd_ia32_NoReg_VFP,
155 &ia32_vfp_regs[REG_VFP_NOREG]);
158 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
159 return create_const(cg, &cg->noreg_xmm, new_bd_ia32_NoReg_XMM,
160 &ia32_xmm_regs[REG_XMM_NOREG]);
163 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
164 return create_const(cg, &cg->unknown_gp, new_bd_ia32_Unknown_GP,
165 &ia32_gp_regs[REG_GP_UKNWN]);
168 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
169 return create_const(cg, &cg->unknown_vfp, new_bd_ia32_Unknown_VFP,
170 &ia32_vfp_regs[REG_VFP_UKNWN]);
173 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
174 return create_const(cg, &cg->unknown_xmm, new_bd_ia32_Unknown_XMM,
175 &ia32_xmm_regs[REG_XMM_UKNWN]);
178 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
179 return create_const(cg, &cg->fpu_trunc_mode, new_bd_ia32_ChangeCW,
180 &ia32_fp_cw_regs[REG_FPCW]);
185 * Returns the admissible noreg register node for input register pos of node irn.
187 static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
189 const arch_register_req_t *req = arch_get_register_req(irn, pos);
191 assert(req != NULL && "Missing register requirements");
192 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
193 return ia32_new_NoReg_gp(cg);
195 if (ia32_cg_config.use_sse2) {
196 return ia32_new_NoReg_xmm(cg);
198 return ia32_new_NoReg_vfp(cg);
202 /**************************************************
205 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
206 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
207 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
208 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
211 **************************************************/
214 * Return register requirements for an ia32 node.
215 * If the node returns a tuple (mode_T) then the proj's
216 * will be asked for this information.
218 static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node,
221 ir_mode *mode = get_irn_mode(node);
224 if (mode == mode_X || is_Block(node)) {
225 return arch_no_register_req;
228 if (mode == mode_T && pos < 0) {
229 return arch_no_register_req;
232 node_pos = pos == -1 ? 0 : pos;
234 if (mode == mode_M || pos >= 0) {
235 return arch_no_register_req;
238 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
239 node = skip_Proj_const(node);
242 if (is_ia32_irn(node)) {
243 const arch_register_req_t *req;
245 req = get_ia32_in_req(node, pos);
247 req = get_ia32_out_req(node, node_pos);
254 /* unknowns should be transformed already */
255 return arch_no_register_req;
258 static arch_irn_class_t ia32_classify(const ir_node *irn) {
259 arch_irn_class_t classification = 0;
261 irn = skip_Proj_const(irn);
264 classification |= arch_irn_class_branch;
266 if (! is_ia32_irn(irn))
267 return classification;
269 if (is_ia32_is_reload(irn))
270 classification |= arch_irn_class_reload;
272 if (is_ia32_is_spill(irn))
273 classification |= arch_irn_class_spill;
275 if (is_ia32_is_remat(irn))
276 classification |= arch_irn_class_remat;
278 return classification;
282 * The IA32 ABI callback object.
285 be_abi_call_flags_bits_t flags; /**< The call flags. */
286 const arch_env_t *aenv; /**< The architecture environment. */
287 ir_graph *irg; /**< The associated graph. */
290 static ir_entity *ia32_get_frame_entity(const ir_node *irn) {
291 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
294 static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) {
295 set_ia32_frame_ent(irn, ent);
298 static void ia32_set_frame_offset(ir_node *irn, int bias)
300 if (get_ia32_frame_ent(irn) == NULL)
303 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
304 ia32_code_gen_t *cg = ia32_current_cg;
305 int omit_fp = be_abi_omit_fp(cg->birg->abi);
307 /* Pop nodes modify the stack pointer before calculating the
308 * destination address, so fix this here
313 add_ia32_am_offs_int(irn, bias);
316 static int ia32_get_sp_bias(const ir_node *node)
318 if (is_ia32_Call(node))
319 return -(int)get_ia32_call_attr_const(node)->pop;
321 if (is_ia32_Push(node))
324 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
331 * Generate the routine prologue.
333 * @param self The callback object.
334 * @param mem A pointer to the mem node. Update this if you define new memory.
335 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
336 * @param stack_bias Points to the current stack bias, can be modified if needed.
338 * @return The register which shall be used as a stack frame base.
340 * All nodes which define registers in @p reg_map must keep @p reg_map current.
342 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
344 ia32_abi_env_t *env = self;
345 ia32_code_gen_t *cg = ia32_current_cg;
346 const arch_env_t *arch_env = env->aenv;
348 ia32_curr_fp_ommitted = env->flags.try_omit_fp;
349 if (! env->flags.try_omit_fp) {
350 ir_graph *irg = env->irg;
351 ir_node *bl = get_irg_start_block(irg);
352 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
353 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
354 ir_node *noreg = ia32_new_NoReg_gp(cg);
357 /* mark bp register as ignore */
358 be_set_constr_single_reg_out(get_Proj_pred(curr_bp),
359 get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
362 push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
363 curr_sp = new_r_Proj(irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
364 *mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M);
366 /* the push must have SP out register */
367 arch_set_irn_register(curr_sp, arch_env->sp);
369 /* this modifies the stack bias, because we pushed 32bit */
372 /* move esp to ebp */
373 curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp);
374 be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
375 arch_register_req_type_ignore);
377 /* beware: the copy must be done before any other sp use */
378 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
379 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
380 arch_register_req_type_produces_sp);
382 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
383 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
392 * Generate the routine epilogue.
393 * @param self The callback object.
394 * @param bl The block for the epilog
395 * @param mem A pointer to the mem node. Update this if you define new memory.
396 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
397 * @return The register which shall be used as a stack frame base.
399 * All nodes which define registers in @p reg_map must keep @p reg_map current.
401 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
403 ia32_abi_env_t *env = self;
404 const arch_env_t *arch_env = env->aenv;
405 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
406 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
407 ir_graph *irg = env->irg;
409 if (env->flags.try_omit_fp) {
410 /* simply remove the stack frame here */
411 curr_sp = be_new_IncSP(arch_env->sp, irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
413 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
415 if (ia32_cg_config.use_leave) {
419 leave = new_bd_ia32_Leave(NULL, bl, curr_bp);
420 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
421 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
425 /* the old SP is not needed anymore (kill the proj) */
426 assert(is_Proj(curr_sp));
429 /* copy ebp to esp */
430 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
431 arch_set_irn_register(curr_sp, arch_env->sp);
432 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
433 arch_register_req_type_ignore);
436 pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
437 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
438 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
440 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
442 arch_set_irn_register(curr_sp, arch_env->sp);
443 arch_set_irn_register(curr_bp, arch_env->bp);
446 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
447 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
451 * Initialize the callback object.
452 * @param call The call object.
453 * @param aenv The architecture environment.
454 * @param irg The graph with the method.
455 * @return Some pointer. This pointer is passed to all other callback functions as self object.
457 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
459 ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
460 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
461 env->flags = fl.bits;
468 * Destroy the callback object.
469 * @param self The callback object.
471 static void ia32_abi_done(void *self) {
476 * Build the between type and entities if not already build.
478 static void ia32_build_between_type(void) {
479 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
480 if (! between_type) {
481 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
482 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
484 between_type = new_type_struct(IDENT("ia32_between_type"));
485 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
486 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
488 set_entity_offset(old_bp_ent, 0);
489 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
490 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
491 set_type_state(between_type, layout_fixed);
493 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
494 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
496 set_entity_offset(omit_fp_ret_addr_ent, 0);
497 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
498 set_type_state(omit_fp_between_type, layout_fixed);
504 * Produces the type which sits between the stack args and the locals on the stack.
505 * it will contain the return address and space to store the old base pointer.
506 * @return The Firm type modeling the ABI between type.
508 static ir_type *ia32_abi_get_between_type(void *self)
510 ia32_abi_env_t *env = self;
512 ia32_build_between_type();
513 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
517 * Return the stack entity that contains the return address.
519 ir_entity *ia32_get_return_address_entity(void) {
520 ia32_build_between_type();
521 return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent;
525 * Return the stack entity that contains the frame address.
527 ir_entity *ia32_get_frame_address_entity(void) {
528 ia32_build_between_type();
529 return ia32_curr_fp_ommitted ? NULL : old_bp_ent;
533 * Get the estimated cycle count for @p irn.
535 * @param self The this pointer.
536 * @param irn The node.
538 * @return The estimated cycle count for this operation
540 static int ia32_get_op_estimated_cost(const ir_node *irn)
543 ia32_op_type_t op_tp;
547 if (!is_ia32_irn(irn))
550 assert(is_ia32_irn(irn));
552 cost = get_ia32_latency(irn);
553 op_tp = get_ia32_op_type(irn);
555 if (is_ia32_CopyB(irn)) {
558 else if (is_ia32_CopyB_i(irn)) {
559 int size = get_ia32_copyb_size(irn);
560 cost = 20 + (int)ceil((4/3) * size);
562 /* in case of address mode operations add additional cycles */
563 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
565 In case of stack access and access to fixed addresses add 5 cycles
566 (we assume they are in cache), other memory operations cost 20
569 if (is_ia32_use_frame(irn) || (
570 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
571 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
583 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
585 * @param irn The original operation
586 * @param i Index of the argument we want the inverse operation to yield
587 * @param inverse struct to be filled with the resulting inverse op
588 * @param obstack The obstack to use for allocation of the returned nodes array
589 * @return The inverse operation or NULL if operation invertible
591 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
594 ir_node *block, *noreg, *nomem;
597 /* we cannot invert non-ia32 irns */
598 if (! is_ia32_irn(irn))
601 /* operand must always be a real operand (not base, index or mem) */
602 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
605 /* we don't invert address mode operations */
606 if (get_ia32_op_type(irn) != ia32_Normal)
609 /* TODO: adjust for new immediates... */
610 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
614 block = get_nodes_block(irn);
615 mode = get_irn_mode(irn);
616 irn_mode = get_irn_mode(irn);
617 noreg = get_irn_n(irn, 0);
619 dbg = get_irn_dbg_info(irn);
621 /* initialize structure */
622 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
626 switch (get_ia32_irn_opcode(irn)) {
629 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
630 /* we have an add with a const here */
631 /* invers == add with negated const */
632 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
634 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
635 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
636 set_ia32_commutative(inverse->nodes[0]);
638 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
639 /* we have an add with a symconst here */
640 /* invers == sub with const */
641 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
643 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
646 /* normal add: inverse == sub */
647 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
654 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
655 /* we have a sub with a const/symconst here */
656 /* invers == add with this const */
657 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
658 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
659 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
663 if (i == n_ia32_binary_left) {
664 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
667 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
675 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
676 /* xor with const: inverse = xor */
677 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
678 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
679 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
683 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
689 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
694 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
699 /* inverse operation not supported */
706 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
708 if(mode_is_float(mode))
715 * Get the mode that should be used for spilling value node
717 static ir_mode *get_spill_mode(const ir_node *node)
719 ir_mode *mode = get_irn_mode(node);
720 return get_spill_mode_mode(mode);
724 * Checks whether an addressmode reload for a node with mode mode is compatible
725 * with a spillslot of mode spill_mode
727 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
729 return !mode_is_float(mode) || mode == spillmode;
733 * Check if irn can load its operand at position i from memory (source addressmode).
734 * @param irn The irn to be checked
735 * @param i The operands position
736 * @return Non-Zero if operand can be loaded
738 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
740 ir_node *op = get_irn_n(irn, i);
741 const ir_mode *mode = get_irn_mode(op);
742 const ir_mode *spillmode = get_spill_mode(op);
744 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
745 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
746 !ia32_is_spillmode_compatible(mode, spillmode) ||
747 is_ia32_use_frame(irn)) /* must not already use frame */
750 switch (get_ia32_am_support(irn)) {
755 if (i != n_ia32_unary_op)
761 case n_ia32_binary_left: {
762 const arch_register_req_t *req;
763 if (!is_ia32_commutative(irn))
766 /* we can't swap left/right for limited registers
767 * (As this (currently) breaks constraint handling copies)
769 req = get_ia32_in_req(irn, n_ia32_binary_left);
770 if (req->type & arch_register_req_type_limited)
775 case n_ia32_binary_right:
784 panic("Unknown AM type");
787 /* HACK: must not already use "real" memory.
788 * This can happen for Call and Div */
789 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
795 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
799 ir_mode *dest_op_mode;
801 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
803 set_ia32_op_type(irn, ia32_AddrModeS);
805 load_mode = get_irn_mode(get_irn_n(irn, i));
806 dest_op_mode = get_ia32_ls_mode(irn);
807 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
808 set_ia32_ls_mode(irn, load_mode);
810 set_ia32_use_frame(irn);
811 set_ia32_need_stackent(irn);
813 if (i == n_ia32_binary_left &&
814 get_ia32_am_support(irn) == ia32_am_binary &&
815 /* immediates are only allowed on the right side */
816 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
817 ia32_swap_left_right(irn);
818 i = n_ia32_binary_right;
821 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
823 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
824 set_irn_n(irn, n_ia32_mem, spill);
825 set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i));
826 set_ia32_is_reload(irn);
829 static const be_abi_callbacks_t ia32_abi_callbacks = {
832 ia32_abi_get_between_type,
837 /* fill register allocator interface */
839 static const arch_irn_ops_t ia32_irn_ops = {
840 ia32_get_irn_reg_req,
842 ia32_get_frame_entity,
843 ia32_set_frame_entity,
844 ia32_set_frame_offset,
847 ia32_get_op_estimated_cost,
848 ia32_possible_memory_operand,
849 ia32_perform_memory_operand,
852 /**************************************************
855 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
856 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
857 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
858 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
861 **************************************************/
863 static ir_entity *mcount = NULL;
865 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
867 static void ia32_before_abi(void *self) {
868 lower_mode_b_config_t lower_mode_b_config = {
869 mode_Iu, /* lowered mode */
870 mode_Bu, /* preferred mode for set */
871 0, /* don't lower direct compares */
873 ia32_code_gen_t *cg = self;
875 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
877 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
879 if (mcount == NULL) {
880 ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
881 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
882 /* FIXME: enter the right ld_ident here */
883 set_entity_ld_ident(mcount, get_entity_ident(mcount));
884 set_entity_visibility(mcount, visibility_external_allocated);
886 instrument_initcall(cg->irg, mcount);
891 * Transforms the standard firm graph into
894 static void ia32_prepare_graph(void *self)
896 ia32_code_gen_t *cg = self;
897 ir_graph *irg = cg->irg;
899 /* do local optimizations */
900 optimize_graph_df(irg);
902 /* we have to do cfopt+remove_critical_edges as we can't have Bad-blocks
903 * or critical edges in the backend */
905 remove_critical_cf_edges(irg);
907 /* TODO: we often have dead code reachable through out-edges here. So for
908 * now we rebuild edges (as we need correct user count for code selection)
911 edges_deactivate(cg->irg);
912 edges_activate(cg->irg);
916 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
918 switch (be_transformer) {
919 case TRANSFORMER_DEFAULT:
920 /* transform remaining nodes into assembler instructions */
921 ia32_transform_graph(cg);
925 case TRANSFORMER_PBQP:
926 case TRANSFORMER_RAND:
927 /* transform nodes into assembler instructions by PBQP magic */
928 ia32_transform_graph_by_pbqp(cg);
933 panic("invalid transformer");
936 /* do local optimizations (mainly CSE) */
937 optimize_graph_df(cg->irg);
940 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
942 /* optimize address mode */
943 ia32_optimize_graph(cg);
945 /* do code placement, to optimize the position of constants */
949 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
952 ir_node *turn_back_am(ir_node *node)
954 ir_graph *irg = current_ir_graph;
955 dbg_info *dbgi = get_irn_dbg_info(node);
956 ir_node *block = get_nodes_block(node);
957 ir_node *base = get_irn_n(node, n_ia32_base);
958 ir_node *index = get_irn_n(node, n_ia32_index);
959 ir_node *mem = get_irn_n(node, n_ia32_mem);
962 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
963 ir_node *load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
965 ia32_copy_am_attrs(load, node);
966 if (is_ia32_is_reload(node))
967 set_ia32_is_reload(load);
968 set_irn_n(node, n_ia32_mem, new_NoMem());
970 switch (get_ia32_am_support(node)) {
972 set_irn_n(node, n_ia32_unary_op, load_res);
976 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
977 set_irn_n(node, n_ia32_binary_left, load_res);
979 set_irn_n(node, n_ia32_binary_right, load_res);
984 panic("Unknown AM type");
986 noreg = ia32_new_NoReg_gp(ia32_current_cg);
987 set_irn_n(node, n_ia32_base, noreg);
988 set_irn_n(node, n_ia32_index, noreg);
989 set_ia32_am_offs_int(node, 0);
990 set_ia32_am_sc(node, NULL);
991 set_ia32_am_scale(node, 0);
992 clear_ia32_am_sc_sign(node);
994 /* rewire mem-proj */
995 if (get_irn_mode(node) == mode_T) {
996 const ir_edge_t *edge;
997 foreach_out_edge(node, edge) {
998 ir_node *out = get_edge_src_irn(edge);
999 if (get_irn_mode(out) == mode_M) {
1000 set_Proj_pred(out, load);
1001 set_Proj_proj(out, pn_ia32_Load_M);
1007 set_ia32_op_type(node, ia32_Normal);
1008 if (sched_is_scheduled(node))
1009 sched_add_before(node, load);
1014 static ir_node *flags_remat(ir_node *node, ir_node *after)
1016 /* we should turn back source address mode when rematerializing nodes */
1017 ia32_op_type_t type;
1021 if (is_Block(after)) {
1024 block = get_nodes_block(after);
1027 type = get_ia32_op_type(node);
1029 case ia32_AddrModeS:
1033 case ia32_AddrModeD:
1034 /* TODO implement this later... */
1035 panic("found DestAM with flag user %+F this should not happen", node);
1038 default: assert(type == ia32_Normal); break;
1041 copy = exact_copy(node);
1042 set_nodes_block(copy, block);
1043 sched_add_after(after, copy);
1049 * Called before the register allocator.
1051 static void ia32_before_ra(void *self) {
1052 ia32_code_gen_t *cg = self;
1054 /* setup fpu rounding modes */
1055 ia32_setup_fpu_mode(cg);
1058 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1061 ia32_add_missing_keeps(cg);
1066 * Transforms a be_Reload into a ia32 Load.
1068 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1069 ir_graph *irg = get_irn_irg(node);
1070 dbg_info *dbg = get_irn_dbg_info(node);
1071 ir_node *block = get_nodes_block(node);
1072 ir_entity *ent = be_get_frame_entity(node);
1073 ir_mode *mode = get_irn_mode(node);
1074 ir_mode *spillmode = get_spill_mode(node);
1075 ir_node *noreg = ia32_new_NoReg_gp(cg);
1076 ir_node *sched_point = NULL;
1077 ir_node *ptr = get_irg_frame(irg);
1078 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1079 ir_node *new_op, *proj;
1080 const arch_register_t *reg;
1082 if (sched_is_scheduled(node)) {
1083 sched_point = sched_prev(node);
1086 if (mode_is_float(spillmode)) {
1087 if (ia32_cg_config.use_sse2)
1088 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
1090 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
1092 else if (get_mode_size_bits(spillmode) == 128) {
1093 /* Reload 128 bit SSE registers */
1094 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
1097 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
1099 set_ia32_op_type(new_op, ia32_AddrModeS);
1100 set_ia32_ls_mode(new_op, spillmode);
1101 set_ia32_frame_ent(new_op, ent);
1102 set_ia32_use_frame(new_op);
1103 set_ia32_is_reload(new_op);
1105 DBG_OPT_RELOAD2LD(node, new_op);
1107 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1110 sched_add_after(sched_point, new_op);
1114 /* copy the register from the old node to the new Load */
1115 reg = arch_get_irn_register(node);
1116 arch_set_irn_register(proj, reg);
1118 SET_IA32_ORIG_NODE(new_op, node);
1120 exchange(node, proj);
1124 * Transforms a be_Spill node into a ia32 Store.
1126 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1127 ir_graph *irg = get_irn_irg(node);
1128 dbg_info *dbg = get_irn_dbg_info(node);
1129 ir_node *block = get_nodes_block(node);
1130 ir_entity *ent = be_get_frame_entity(node);
1131 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1132 ir_mode *mode = get_spill_mode(spillval);
1133 ir_node *noreg = ia32_new_NoReg_gp(cg);
1134 ir_node *nomem = new_NoMem();
1135 ir_node *ptr = get_irg_frame(irg);
1136 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1138 ir_node *sched_point = NULL;
1140 if (sched_is_scheduled(node)) {
1141 sched_point = sched_prev(node);
1144 /* No need to spill unknown values... */
1145 if(is_ia32_Unknown_GP(val) ||
1146 is_ia32_Unknown_VFP(val) ||
1147 is_ia32_Unknown_XMM(val)) {
1152 exchange(node, store);
1156 if (mode_is_float(mode)) {
1157 if (ia32_cg_config.use_sse2)
1158 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
1160 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
1161 } else if (get_mode_size_bits(mode) == 128) {
1162 /* Spill 128 bit SSE registers */
1163 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
1164 } else if (get_mode_size_bits(mode) == 8) {
1165 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
1167 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
1170 set_ia32_op_type(store, ia32_AddrModeD);
1171 set_ia32_ls_mode(store, mode);
1172 set_ia32_frame_ent(store, ent);
1173 set_ia32_use_frame(store);
1174 set_ia32_is_spill(store);
1175 SET_IA32_ORIG_NODE(store, node);
1176 DBG_OPT_SPILL2ST(node, store);
1179 sched_add_after(sched_point, store);
1183 exchange(node, store);
1186 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1187 dbg_info *dbg = get_irn_dbg_info(node);
1188 ir_node *block = get_nodes_block(node);
1189 ir_node *noreg = ia32_new_NoReg_gp(cg);
1190 ir_graph *irg = get_irn_irg(node);
1191 ir_node *frame = get_irg_frame(irg);
1193 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
1195 set_ia32_frame_ent(push, ent);
1196 set_ia32_use_frame(push);
1197 set_ia32_op_type(push, ia32_AddrModeS);
1198 set_ia32_ls_mode(push, mode_Is);
1199 set_ia32_is_spill(push);
1201 sched_add_before(schedpoint, push);
1205 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1206 dbg_info *dbg = get_irn_dbg_info(node);
1207 ir_node *block = get_nodes_block(node);
1208 ir_node *noreg = ia32_new_NoReg_gp(cg);
1209 ir_graph *irg = get_irn_irg(node);
1210 ir_node *frame = get_irg_frame(irg);
1212 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
1214 set_ia32_frame_ent(pop, ent);
1215 set_ia32_use_frame(pop);
1216 set_ia32_op_type(pop, ia32_AddrModeD);
1217 set_ia32_ls_mode(pop, mode_Is);
1218 set_ia32_is_reload(pop);
1220 sched_add_before(schedpoint, pop);
1225 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1227 ir_graph *irg = get_irn_irg(node);
1228 dbg_info *dbg = get_irn_dbg_info(node);
1229 ir_node *block = get_nodes_block(node);
1230 ir_mode *spmode = mode_Iu;
1231 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1234 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1235 arch_set_irn_register(sp, spreg);
1241 * Transform MemPerm, currently we do this the ugly way and produce
1242 * push/pop into/from memory cascades. This is possible without using
1245 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
1247 ir_graph *irg = get_irn_irg(node);
1248 ir_node *block = get_nodes_block(node);
1249 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1250 int arity = be_get_MemPerm_entity_arity(node);
1251 ir_node **pops = ALLOCAN(ir_node*, arity);
1255 const ir_edge_t *edge;
1256 const ir_edge_t *next;
1259 for(i = 0; i < arity; ++i) {
1260 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1261 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1262 ir_type *enttype = get_entity_type(inent);
1263 unsigned entsize = get_type_size_bytes(enttype);
1264 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1265 ir_node *mem = get_irn_n(node, i + 1);
1268 /* work around cases where entities have different sizes */
1269 if(entsize2 < entsize)
1271 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1273 push = create_push(cg, node, node, sp, mem, inent);
1274 sp = create_spproj(node, push, pn_ia32_Push_stack);
1276 /* add another push after the first one */
1277 push = create_push(cg, node, node, sp, mem, inent);
1278 add_ia32_am_offs_int(push, 4);
1279 sp = create_spproj(node, push, pn_ia32_Push_stack);
1282 set_irn_n(node, i, new_Bad());
1286 for(i = arity - 1; i >= 0; --i) {
1287 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1288 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1289 ir_type *enttype = get_entity_type(outent);
1290 unsigned entsize = get_type_size_bytes(enttype);
1291 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1294 /* work around cases where entities have different sizes */
1295 if(entsize2 < entsize)
1297 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1299 pop = create_pop(cg, node, node, sp, outent);
1300 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1302 add_ia32_am_offs_int(pop, 4);
1304 /* add another pop after the first one */
1305 pop = create_pop(cg, node, node, sp, outent);
1306 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1313 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1314 sched_add_before(node, keep);
1316 /* exchange memprojs */
1317 foreach_out_edge_safe(node, edge, next) {
1318 ir_node *proj = get_edge_src_irn(edge);
1319 int p = get_Proj_proj(proj);
1323 set_Proj_pred(proj, pops[p]);
1324 set_Proj_proj(proj, pn_ia32_Pop_M);
1327 /* remove memperm */
1328 arity = get_irn_arity(node);
1329 for(i = 0; i < arity; ++i) {
1330 set_irn_n(node, i, new_Bad());
1336 * Block-Walker: Calls the transform functions Spill and Reload.
1338 static void ia32_after_ra_walker(ir_node *block, void *env) {
1339 ir_node *node, *prev;
1340 ia32_code_gen_t *cg = env;
1342 /* beware: the schedule is changed here */
1343 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1344 prev = sched_prev(node);
1346 if (be_is_Reload(node)) {
1347 transform_to_Load(cg, node);
1348 } else if (be_is_Spill(node)) {
1349 transform_to_Store(cg, node);
1350 } else if (be_is_MemPerm(node)) {
1351 transform_MemPerm(cg, node);
1357 * Collects nodes that need frame entities assigned.
1359 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1361 be_fec_env_t *env = data;
1362 const ir_mode *mode;
1365 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1366 mode = get_spill_mode_mode(get_irn_mode(node));
1367 align = get_mode_size_bytes(mode);
1368 } else if (is_ia32_irn(node) &&
1369 get_ia32_frame_ent(node) == NULL &&
1370 is_ia32_use_frame(node)) {
1371 if (is_ia32_need_stackent(node))
1374 switch (get_ia32_irn_opcode(node)) {
1376 case iro_ia32_Load: {
1377 const ia32_attr_t *attr = get_ia32_attr_const(node);
1379 if (attr->data.need_32bit_stackent) {
1381 } else if (attr->data.need_64bit_stackent) {
1384 mode = get_ia32_ls_mode(node);
1385 if (is_ia32_is_reload(node))
1386 mode = get_spill_mode_mode(mode);
1388 align = get_mode_size_bytes(mode);
1392 case iro_ia32_vfild:
1394 case iro_ia32_xLoad: {
1395 mode = get_ia32_ls_mode(node);
1400 case iro_ia32_FldCW: {
1401 /* although 2 byte would be enough 4 byte performs best */
1409 panic("unexpected frame user while collection frame entity nodes");
1411 case iro_ia32_FnstCW:
1412 case iro_ia32_Store8Bit:
1413 case iro_ia32_Store:
1416 case iro_ia32_vfist:
1417 case iro_ia32_vfisttp:
1419 case iro_ia32_xStore:
1420 case iro_ia32_xStoreSimple:
1427 be_node_needs_frame_entity(env, node, mode, align);
1431 * We transform Spill and Reload here. This needs to be done before
1432 * stack biasing otherwise we would miss the corrected offset for these nodes.
1434 static void ia32_after_ra(void *self) {
1435 ia32_code_gen_t *cg = self;
1436 ir_graph *irg = cg->irg;
1437 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1439 /* create and coalesce frame entities */
1440 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1441 be_assign_entities(fec_env);
1442 be_free_frame_entity_coalescer(fec_env);
1444 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1448 * Last touchups for the graph before emit: x87 simulation to replace the
1449 * virtual with real x87 instructions, creating a block schedule and peephole
1452 static void ia32_finish(void *self) {
1453 ia32_code_gen_t *cg = self;
1454 ir_graph *irg = cg->irg;
1456 ia32_finish_irg(irg, cg);
1458 /* we might have to rewrite x87 virtual registers */
1459 if (cg->do_x87_sim) {
1460 x87_simulate_graph(cg->birg);
1463 /* do peephole optimisations */
1464 ia32_peephole_optimization(cg);
1466 /* create block schedule, this also removes empty blocks which might
1467 * produce critical edges */
1468 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1472 * Emits the code, closes the output file and frees
1473 * the code generator interface.
1475 static void ia32_codegen(void *self) {
1476 ia32_code_gen_t *cg = self;
1477 ir_graph *irg = cg->irg;
1479 ia32_gen_routine(cg, irg);
1483 /* remove it from the isa */
1486 assert(ia32_current_cg == cg);
1487 ia32_current_cg = NULL;
1489 /* de-allocate code generator */
1490 del_set(cg->reg_set);
1495 * Returns the node representing the PIC base.
1497 static ir_node *ia32_get_pic_base(void *self) {
1499 ia32_code_gen_t *cg = self;
1500 ir_node *get_eip = cg->get_eip;
1501 if (get_eip != NULL)
1504 block = get_irg_start_block(cg->irg);
1505 get_eip = new_bd_ia32_GetEIP(NULL, block);
1506 cg->get_eip = get_eip;
1508 be_dep_on_frame(get_eip);
1512 static void *ia32_cg_init(be_irg_t *birg);
1514 static const arch_code_generator_if_t ia32_code_gen_if = {
1516 ia32_get_pic_base, /* return node used as base in pic code addresses */
1517 ia32_before_abi, /* before abi introduce hook */
1520 ia32_before_ra, /* before register allocation hook */
1521 ia32_after_ra, /* after register allocation hook */
1522 ia32_finish, /* called before codegen */
1523 ia32_codegen /* emit && done */
1527 * Initializes a IA32 code generator.
1529 static void *ia32_cg_init(be_irg_t *birg) {
1530 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
1531 ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t);
1533 cg->impl = &ia32_code_gen_if;
1534 cg->irg = birg->irg;
1535 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1538 cg->blk_sched = NULL;
1539 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1540 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1543 /* Linux gprof implementation needs base pointer */
1544 birg->main_env->options->omit_fp = 0;
1551 if (isa->name_obst) {
1552 obstack_free(isa->name_obst, NULL);
1553 obstack_init(isa->name_obst);
1557 cur_reg_set = cg->reg_set;
1559 assert(ia32_current_cg == NULL);
1560 ia32_current_cg = cg;
1562 return (arch_code_generator_t *)cg;
1567 /*****************************************************************
1568 * ____ _ _ _____ _____
1569 * | _ \ | | | | |_ _|/ ____| /\
1570 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1571 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1572 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1573 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1575 *****************************************************************/
1578 * Set output modes for GCC
1580 static const tarval_mode_info mo_integer = {
1587 * set the tarval output mode of all integer modes to decimal
1589 static void set_tarval_output_modes(void)
1593 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1594 ir_mode *mode = get_irp_mode(i);
1596 if (mode_is_int(mode))
1597 set_tarval_mode_output_option(mode, &mo_integer);
1601 const arch_isa_if_t ia32_isa_if;
1604 * The template that generates a new ISA object.
1605 * Note that this template can be changed by command line
1608 static ia32_isa_t ia32_isa_template = {
1610 &ia32_isa_if, /* isa interface implementation */
1611 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1612 &ia32_gp_regs[REG_EBP], /* base pointer register */
1613 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1614 -1, /* stack direction */
1615 2, /* power of two stack alignment, 2^2 == 4 */
1616 NULL, /* main environment */
1617 7, /* costs for a spill instruction */
1618 5, /* costs for a reload instruction */
1620 NULL, /* 16bit register names */
1621 NULL, /* 8bit register names */
1622 NULL, /* 8bit register names high */
1625 NULL, /* current code generator */
1626 NULL, /* abstract machine */
1628 NULL, /* name obstack */
1632 static void init_asm_constraints(void)
1634 be_init_default_asm_constraint_flags();
1636 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1637 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1638 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1639 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1640 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1641 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1642 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1643 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1644 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1645 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1646 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1647 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1648 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1649 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1650 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1651 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1652 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1653 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1654 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1655 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1657 /* no support for autodecrement/autoincrement */
1658 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1659 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1660 /* no float consts */
1661 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1662 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1663 /* makes no sense on x86 */
1664 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1665 /* no support for sse consts yet */
1666 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1667 /* no support for x87 consts yet */
1668 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1669 /* no support for mmx registers yet */
1670 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1671 /* not available in 32bit mode */
1672 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1673 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1675 /* no code yet to determine register class needed... */
1676 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1680 * Initializes the backend ISA.
1682 static arch_env_t *ia32_init(FILE *file_handle) {
1683 static int inited = 0;
1691 set_tarval_output_modes();
1693 isa = XMALLOC(ia32_isa_t);
1694 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1696 if(mode_fpcw == NULL) {
1697 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1700 ia32_register_init();
1701 ia32_create_opcodes(&ia32_irn_ops);
1703 be_emit_init(file_handle);
1704 isa->regs_16bit = pmap_create();
1705 isa->regs_8bit = pmap_create();
1706 isa->regs_8bit_high = pmap_create();
1707 isa->types = pmap_create();
1708 isa->tv_ent = pmap_create();
1709 isa->cpu = ia32_init_machine_description();
1711 ia32_build_16bit_reg_map(isa->regs_16bit);
1712 ia32_build_8bit_reg_map(isa->regs_8bit);
1713 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1716 isa->name_obst = XMALLOC(struct obstack);
1717 obstack_init(isa->name_obst);
1720 /* enter the ISA object into the intrinsic environment */
1721 intrinsic_env.isa = isa;
1723 /* emit asm includes */
1724 n = get_irp_n_asms();
1725 for (i = 0; i < n; ++i) {
1726 be_emit_cstring("#APP\n");
1727 be_emit_ident(get_irp_asm(i));
1728 be_emit_cstring("\n#NO_APP\n");
1731 /* needed for the debug support */
1732 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1733 be_emit_cstring(".Ltext0:\n");
1734 be_emit_write_line();
1736 /* we mark referenced global entities, so we can only emit those which
1737 * are actually referenced. (Note: you mustn't use the type visited flag
1738 * elsewhere in the backend)
1740 inc_master_type_visited();
1742 return &isa->arch_env;
1748 * Closes the output file and frees the ISA structure.
1750 static void ia32_done(void *self) {
1751 ia32_isa_t *isa = self;
1753 /* emit now all global declarations */
1754 be_gas_emit_decls(isa->arch_env.main_env, 1);
1756 pmap_destroy(isa->regs_16bit);
1757 pmap_destroy(isa->regs_8bit);
1758 pmap_destroy(isa->regs_8bit_high);
1759 pmap_destroy(isa->tv_ent);
1760 pmap_destroy(isa->types);
1763 obstack_free(isa->name_obst, NULL);
1773 * Return the number of register classes for this architecture.
1774 * We report always these:
1775 * - the general purpose registers
1776 * - the SSE floating point register set
1777 * - the virtual floating point registers
1778 * - the SSE vector register set
1780 static unsigned ia32_get_n_reg_class(const void *self) {
1786 * Return the register class for index i.
1788 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1792 assert(i < N_CLASSES);
1793 return &ia32_reg_classes[i];
1797 * Get the register class which shall be used to store a value of a given mode.
1798 * @param self The this pointer.
1799 * @param mode The mode in question.
1800 * @return A register class which can hold values of the given mode.
1802 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1803 const ir_mode *mode)
1807 if (mode_is_float(mode)) {
1808 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1811 return &ia32_reg_classes[CLASS_ia32_gp];
1815 * Get the ABI restrictions for procedure calls.
1816 * @param self The this pointer.
1817 * @param method_type The type of the method (procedure) in question.
1818 * @param abi The abi object to be modified
1820 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1828 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1832 /* set abi flags for calls */
1833 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1834 call_flags.bits.store_args_sequential = 0;
1835 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1836 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1837 call_flags.bits.call_has_imm = 0; /* No call immediates, we handle this by ourselves */
1839 /* set parameter passing style */
1840 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1842 cc = get_method_calling_convention(method_type);
1843 if (get_method_variadicity(method_type) == variadicity_variadic) {
1844 /* pass all parameters of a variadic function on the stack */
1845 cc = cc_cdecl_set | (cc & cc_this_call);
1847 if (get_method_additional_properties(method_type) & mtp_property_private &&
1848 ia32_cg_config.optimize_cc) {
1849 /* set the regparam calling conventions (allowing up to 3) */
1850 cc = (cc & ~(cc_bits|cc_this_call)) | cc_reg_param | 3;
1854 /* we have to pop the shadow parameter ourself for compound calls */
1855 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1856 && !(cc & cc_reg_param)) {
1857 pop_amount += get_mode_size_bytes(mode_P_data);
1860 n = get_method_n_params(method_type);
1861 for (i = regnum = 0; i < n; i++) {
1863 const arch_register_t *reg = NULL;
1865 tp = get_method_param_type(method_type, i);
1866 mode = get_type_mode(tp);
1868 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1871 be_abi_call_param_reg(abi, i, reg);
1874 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1875 * movl has a shorter opcode than mov[sz][bw]l */
1876 ir_mode *load_mode = mode;
1879 unsigned size = get_mode_size_bytes(mode);
1881 if (cc & cc_callee_clear_stk) {
1882 pop_amount += (size + 3U) & ~3U;
1885 if (size < 4) load_mode = mode_Iu;
1888 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1892 be_abi_call_set_pop(abi, pop_amount);
1894 /* set return registers */
1895 n = get_method_n_ress(method_type);
1897 assert(n <= 2 && "more than two results not supported");
1899 /* In case of 64bit returns, we will have two 32bit values */
1901 tp = get_method_res_type(method_type, 0);
1902 mode = get_type_mode(tp);
1904 assert(!mode_is_float(mode) && "two FP results not supported");
1906 tp = get_method_res_type(method_type, 1);
1907 mode = get_type_mode(tp);
1909 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1911 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1912 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1915 const arch_register_t *reg;
1917 tp = get_method_res_type(method_type, 0);
1918 assert(is_atomic_type(tp));
1919 mode = get_type_mode(tp);
1921 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1923 be_abi_call_res_reg(abi, 0, reg);
1927 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1931 if(!is_ia32_irn(irn)) {
1935 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1936 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1937 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1938 || is_ia32_Immediate(irn))
1945 * Initializes the code generator interface.
1947 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1950 return &ia32_code_gen_if;
1954 * Returns the estimated execution time of an ia32 irn.
1956 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1958 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
1961 list_sched_selector_t ia32_sched_selector;
1964 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1966 static const list_sched_selector_t *ia32_get_list_sched_selector(
1967 const void *self, list_sched_selector_t *selector)
1970 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1971 ia32_sched_selector.exectime = ia32_sched_exectime;
1972 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1973 return &ia32_sched_selector;
1976 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1983 * Returns the necessary byte alignment for storing a register of given class.
1985 static int ia32_get_reg_class_alignment(const void *self,
1986 const arch_register_class_t *cls)
1988 ir_mode *mode = arch_register_class_mode(cls);
1989 int bytes = get_mode_size_bytes(mode);
1992 if (mode_is_float(mode) && bytes > 8)
1997 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1998 const void *self, const ir_node *irn)
2000 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
2001 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
2002 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
2005 static const be_execution_unit_t *_allowed_units_GP[] = {
2006 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
2007 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
2008 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
2009 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
2010 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
2011 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
2012 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2015 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2016 &be_machine_execution_units_DUMMY[0],
2019 static const be_execution_unit_t **_units_callret[] = {
2020 _allowed_units_BRANCH,
2023 static const be_execution_unit_t **_units_other[] = {
2027 static const be_execution_unit_t **_units_dummy[] = {
2028 _allowed_units_DUMMY,
2031 const be_execution_unit_t ***ret;
2034 if (is_ia32_irn(irn)) {
2035 ret = get_ia32_exec_units(irn);
2036 } else if (is_be_node(irn)) {
2037 if (be_is_Return(irn)) {
2038 ret = _units_callret;
2039 } else if (be_is_Barrier(irn)) {
2053 * Return the abstract ia32 machine.
2055 static const be_machine_t *ia32_get_machine(const void *self) {
2056 const ia32_isa_t *isa = self;
2061 * Return irp irgs in the desired order.
2063 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2070 static void ia32_mark_remat(const void *self, ir_node *node) {
2072 if (is_ia32_irn(node)) {
2073 set_ia32_is_remat(node);
2078 * Check for Abs or -Abs.
2080 static int psi_is_Abs_or_Nabs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f) {
2087 /* must be <, <=, >=, > */
2088 pnc = get_Proj_proj(sel);
2089 if (pnc != pn_Cmp_Ge && pnc != pn_Cmp_Gt &&
2090 pnc != pn_Cmp_Le && pnc != pn_Cmp_Lt)
2093 l = get_Cmp_left(cmp);
2094 r = get_Cmp_right(cmp);
2096 /* must be x cmp 0 */
2097 if ((l != t && l != f) || !is_Const(r) || !is_Const_null(r))
2100 if ((!is_Minus(t) || get_Minus_op(t) != f) &&
2101 (!is_Minus(f) || get_Minus_op(f) != t))
2107 * Check for Abs only
2109 static int psi_is_Abs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f) {
2116 /* must be <, <=, >=, > */
2117 pnc = get_Proj_proj(sel);
2118 if (pnc != pn_Cmp_Ge && pnc != pn_Cmp_Gt &&
2119 pnc != pn_Cmp_Le && pnc != pn_Cmp_Lt)
2122 l = get_Cmp_left(cmp);
2123 r = get_Cmp_right(cmp);
2125 /* must be x cmp 0 */
2126 if ((l != t && l != f) || !is_Const(r) || !is_Const_null(r))
2129 if ((!is_Minus(t) || get_Minus_op(t) != f) &&
2130 (!is_Minus(f) || get_Minus_op(f) != t))
2133 if (pnc & pn_Cmp_Gt) {
2134 /* x >= 0 ? -x : x is NABS */
2138 /* x < 0 ? x : -x is NABS */
2147 * Allows or disallows the creation of Mux nodes for the given Phi nodes.
2149 * @param sel A selector of a Cond.
2150 * @param phi_list List of Phi nodes about to be converted (linked via get_Phi_next() field)
2151 * @param i First data predecessor involved in if conversion
2152 * @param j Second data predecessor involved in if conversion
2154 * @return 1 if allowed, 0 otherwise
2156 static int ia32_is_mux_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2163 /* we can't handle Muxs with 64bit compares yet */
2165 cmp = get_Proj_pred(sel);
2167 ir_node *left = get_Cmp_left(cmp);
2168 ir_mode *cmp_mode = get_irn_mode(left);
2169 if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32) {
2170 /* 64bit Abs IS supported */
2171 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2172 ir_node *t = get_Phi_pred(phi, i);
2173 ir_node *f = get_Phi_pred(phi, j);
2175 if (! psi_is_Abs(cmp, sel, t, f))
2181 /* we do not support nodes without Cmp yet */
2185 /* we do not support nodes without Cmp yet */
2189 pn = get_Proj_proj(sel);
2190 cl = get_Cmp_left(cmp);
2191 cr = get_Cmp_right(cmp);
2193 if (ia32_cg_config.use_cmov) {
2194 if (ia32_cg_config.use_sse2) {
2195 /* check the Phi nodes: no 64bit and no floating point cmov */
2196 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2197 ir_mode *mode = get_irn_mode(phi);
2199 if (mode_is_float(mode)) {
2200 /* check for Min, Max */
2201 ir_node *t = get_Phi_pred(phi, i);
2202 ir_node *f = get_Phi_pred(phi, j);
2204 /* SSE2 supports Min & Max */
2205 if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2206 if (cl == t && cr == f) {
2207 /* Mux(a <=/>= b, a, b) => MIN, MAX */
2209 } else if (cl == f && cr == t) {
2210 /* Mux(a <=/>= b, b, a) => MAX, MIN */
2215 } else if (get_mode_size_bits(mode) > 32) {
2221 /* check the Phi nodes: no 64bit and no floating point cmov */
2222 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2223 ir_mode *mode = get_irn_mode(phi);
2225 if (mode_is_float(mode)) {
2226 ir_node *t = get_Phi_pred(phi, i);
2227 ir_node *f = get_Phi_pred(phi, j);
2229 /* always support Mux(!float, C1, C2) */
2230 if (is_Const(t) && is_Const(f) && !mode_is_float(get_irn_mode(cl))) {
2231 switch (be_transformer) {
2232 case TRANSFORMER_DEFAULT:
2233 /* always support Mux(!float, C1, C2) */
2235 #ifdef FIRM_GRGEN_BE
2236 case TRANSFORMER_PBQP:
2237 case TRANSFORMER_RAND:
2238 /* no support for Mux(*, C1, C2) */
2242 panic("invalid transformer");
2245 /* only abs or nabs supported */
2246 if (! psi_is_Abs_or_Nabs(cmp, sel, t, f))
2248 } else if (get_mode_size_bits(mode) > 32)
2254 } else { /* No Cmov, only some special cases */
2256 /* Now some supported cases here */
2257 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2258 ir_mode *mode = get_irn_mode(phi);
2261 t = get_Phi_pred(phi, i);
2262 f = get_Phi_pred(phi, j);
2264 if (mode_is_float(mode)) {
2265 /* always support Mux(!float, C1, C2) */
2266 if (is_Const(t) && is_Const(f) &&
2267 !mode_is_float(get_irn_mode(cl))) {
2268 switch (be_transformer) {
2269 case TRANSFORMER_DEFAULT:
2270 /* always support Mux(!float, C1, C2) */
2272 #ifdef FIRM_GRGEN_BE
2273 case TRANSFORMER_PBQP:
2274 case TRANSFORMER_RAND:
2275 /* no support for Mux(*, C1, C2) */
2279 panic("invalid transformer");
2282 /* only abs or nabs supported */
2283 if (! psi_is_Abs_or_Nabs(cmp, sel, t, f))
2285 } else if (get_mode_size_bits(mode) > 32) {
2290 if (is_Const(t) && is_Const(f)) {
2291 if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
2292 /* always support Mux(x, C1, C2) */
2295 } else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2297 if (cl == t && cr == f) {
2298 /* Mux(a <=/>= b, a, b) => Min, Max */
2301 if (cl == f && cr == t) {
2302 /* Mux(a <=/>= b, b, a) => Max, Min */
2306 if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
2307 is_Const(f) && is_Const_null(f) && is_Sub(t) &&
2308 get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
2309 /* Mux(a >=u b, a - b, 0) unsigned Doz */
2312 if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
2313 is_Const(t) && is_Const_null(t) && is_Sub(f) &&
2314 get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
2315 /* Mux(a <=u b, 0, a - b) unsigned Doz */
2318 if (is_Const(cr) && is_Const_null(cr)) {
2319 if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
2320 /* Mux(a <=/>= 0 ? a : -a) Nabs/Abs */
2322 } else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
2323 /* Mux(a <=/>= 0 ? -a : a) Abs/Nabs */
2330 /* all checks passed */
2336 static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const char **c)
2341 /* we already added all our simple flags to the flags modifier list in
2342 * init, so this flag we don't know. */
2343 return ASM_CONSTRAINT_FLAG_INVALID;
2346 static int ia32_is_valid_clobber(const void *self, const char *clobber)
2350 return ia32_get_clobber_register(clobber) != NULL;
2354 * Create the trampoline code.
2356 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2358 ir_graph *irg = get_Block_irg(block);
2359 ir_node *st, *p = trampoline;
2360 ir_mode *mode = get_irn_mode(p);
2363 st = new_r_Store(irg, block, mem, p, new_Const_long(mode_Bu, 0xb9), 0);
2364 mem = new_r_Proj(irg, block, st, mode_M, pn_Store_M);
2365 p = new_r_Add(irg, block, p, new_Const_long(mode_Iu, 1), mode);
2366 st = new_r_Store(irg, block, mem, p, env, 0);
2367 mem = new_r_Proj(irg, block, st, mode_M, pn_Store_M);
2368 p = new_r_Add(irg, block, p, new_Const_long(mode_Iu, 4), mode);
2370 st = new_r_Store(irg, block, mem, p, new_Const_long(mode_Bu, 0xe9), 0);
2371 mem = new_r_Proj(irg, block, st, mode_M, pn_Store_M);
2372 p = new_r_Add(irg, block, p, new_Const_long(mode_Iu, 1), mode);
2373 st = new_r_Store(irg, block, mem, p, callee, 0);
2374 mem = new_r_Proj(irg, block, st, mode_M, pn_Store_M);
2375 p = new_r_Add(irg, block, p, new_Const_long(mode_Iu, 4), mode);
2381 * Returns the libFirm configuration parameter for this backend.
2383 static const backend_params *ia32_get_libfirm_params(void) {
2384 static const ir_settings_if_conv_t ifconv = {
2385 4, /* maxdepth, doesn't matter for Mux-conversion */
2386 ia32_is_mux_allowed /* allows or disallows Mux creation for given selector */
2388 static const ir_settings_arch_dep_t ad = {
2389 1, /* also use subs */
2390 4, /* maximum shifts */
2391 31, /* maximum shift amount */
2392 ia32_evaluate_insn, /* evaluate the instruction sequence */
2394 1, /* allow Mulhs */
2395 1, /* allow Mulus */
2396 32, /* Mulh allowed up to 32 bit */
2398 static backend_params p = {
2399 1, /* need dword lowering */
2400 1, /* support inline assembly */
2401 NULL, /* will be set later */
2402 ia32_create_intrinsic_fkt,
2403 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2404 NULL, /* ifconv info will be set below */
2405 NULL, /* float arithmetic mode, will be set below */
2406 12, /* size of trampoline code */
2407 4, /* alignment of trampoline code */
2408 ia32_create_trampoline_fkt,
2409 4 /* alignment of stack parameter */
2412 ia32_setup_cg_config();
2414 /* doesn't really belong here, but this is the earliest place the backend
2416 init_asm_constraints();
2419 p.if_conv_info = &ifconv;
2420 if (! ia32_cg_config.use_sse2)
2421 p.mode_float_arithmetic = mode_E;
2425 static const lc_opt_enum_int_items_t gas_items[] = {
2426 { "elf", GAS_FLAVOUR_ELF },
2427 { "mingw", GAS_FLAVOUR_MINGW },
2428 { "yasm", GAS_FLAVOUR_YASM },
2429 { "macho", GAS_FLAVOUR_MACH_O },
2433 static lc_opt_enum_int_var_t gas_var = {
2434 (int*) &be_gas_flavour, gas_items
2437 #ifdef FIRM_GRGEN_BE
2438 static const lc_opt_enum_int_items_t transformer_items[] = {
2439 { "default", TRANSFORMER_DEFAULT },
2440 { "pbqp", TRANSFORMER_PBQP },
2441 { "random", TRANSFORMER_RAND },
2445 static lc_opt_enum_int_var_t transformer_var = {
2446 (int*)&be_transformer, transformer_items
2450 static const lc_opt_table_entry_t ia32_options[] = {
2451 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2452 #ifdef FIRM_GRGEN_BE
2453 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2455 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2456 &ia32_isa_template.arch_env.stack_alignment),
2460 const arch_isa_if_t ia32_isa_if = {
2463 ia32_handle_intrinsics,
2464 ia32_get_n_reg_class,
2466 ia32_get_reg_class_for_mode,
2468 ia32_get_code_generator_if,
2469 ia32_get_list_sched_selector,
2470 ia32_get_ilp_sched_selector,
2471 ia32_get_reg_class_alignment,
2472 ia32_get_libfirm_params,
2473 ia32_get_allowed_execution_units,
2477 ia32_parse_asm_constraint,
2478 ia32_is_valid_clobber
2481 void be_init_arch_ia32(void)
2483 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2484 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2486 lc_opt_add_table(ia32_grp, ia32_options);
2487 be_register_isa_if("ia32", &ia32_isa_if);
2489 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2491 ia32_init_emitter();
2493 ia32_init_optimize();
2494 ia32_init_transform();
2496 ia32_init_architecture();
2499 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);