11 #include "pseudo_irg.h"
15 #include "iredges_t.h"
22 #include "../beabi.h" /* the general register allocator interface */
23 #include "../benode_t.h"
24 #include "../belower.h"
25 #include "../besched_t.h"
27 #include "bearch_ia32_t.h"
29 #include "ia32_new_nodes.h" /* ia32 nodes interface */
30 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
31 #include "ia32_gen_decls.h" /* interface declaration emitter */
32 #include "ia32_transform.h"
33 #include "ia32_emitter.h"
34 #include "ia32_map_regs.h"
35 #include "ia32_optimize.h"
37 #define DEBUG_MODULE "firm.be.ia32.isa"
40 static set *cur_reg_set = NULL;
43 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
45 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
46 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_XXX]);
49 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
50 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_fp_regs[REG_XXXX]);
53 /**************************************************
56 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
57 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
58 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
59 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
62 **************************************************/
64 static ir_node *my_skip_proj(const ir_node *n) {
71 * Return register requirements for an ia32 node.
72 * If the node returns a tuple (mode_T) then the proj's
73 * will be asked for this information.
75 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
76 const ia32_register_req_t *irn_req;
77 long node_pos = pos == -1 ? 0 : pos;
78 ir_mode *mode = get_irn_mode(irn);
79 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
81 if (mode == mode_T || mode == mode_M) {
82 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
86 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
91 node_pos = ia32_translate_proj_pos(irn);
97 irn = my_skip_proj(irn);
99 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
102 if (is_ia32_irn(irn)) {
104 irn_req = get_ia32_in_req(irn, pos);
107 irn_req = get_ia32_out_req(irn, node_pos);
110 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
112 memcpy(req, &(irn_req->req), sizeof(*req));
114 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
115 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
116 req->other_same = get_irn_n(irn, irn_req->same_pos);
119 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
120 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
121 req->other_different = get_irn_n(irn, irn_req->different_pos);
125 /* treat Phi like Const with default requirements */
127 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
128 if (mode_is_float(mode))
129 memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req));
130 else if (mode_is_int(mode) || mode_is_reference(mode))
131 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
132 else if (mode == mode_T || mode == mode_M) {
133 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
137 assert(0 && "unsupported Phi-Mode");
140 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
148 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
152 pos = ia32_translate_proj_pos(irn);
153 irn = my_skip_proj(irn);
156 if (is_ia32_irn(irn)) {
157 const arch_register_t **slots;
159 slots = get_ia32_slots(irn);
163 ia32_set_firm_reg(irn, reg, cur_reg_set);
167 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
169 const arch_register_t *reg = NULL;
172 pos = ia32_translate_proj_pos(irn);
173 irn = my_skip_proj(irn);
176 if (is_ia32_irn(irn)) {
177 const arch_register_t **slots;
178 slots = get_ia32_slots(irn);
182 reg = ia32_get_firm_reg(irn, cur_reg_set);
188 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
189 irn = my_skip_proj(irn);
191 return arch_irn_class_branch;
192 else if (is_ia32_irn(irn))
193 return arch_irn_class_normal;
198 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
199 irn = my_skip_proj(irn);
200 if (is_ia32_irn(irn))
201 return get_ia32_flags(irn);
207 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
208 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
211 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
213 const ia32_irn_ops_t *ops = self;
215 if (is_ia32_use_frame(irn) && bias != 0) {
216 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
218 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
219 snprintf(buf, sizeof(buf), "%d", bias);
220 add_ia32_am_offs(irn, buf);
222 set_ia32_am_flavour(irn, am_flav);
226 /* fill register allocator interface */
228 static const arch_irn_ops_if_t ia32_irn_ops_if = {
229 ia32_get_irn_reg_req,
234 ia32_get_frame_entity,
238 ia32_irn_ops_t ia32_irn_ops = {
245 /**************************************************
248 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
249 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
250 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
251 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
254 **************************************************/
257 * Transforms the standard firm graph into
260 static void ia32_prepare_graph(void *self) {
261 ia32_code_gen_t *cg = self;
263 irg_walk_blkwise_graph(cg->irg, ia32_place_consts, ia32_transform_node, cg);
264 dump_ir_block_graph_sched(cg->irg, "-transformed");
265 edges_deactivate(cg->irg);
266 edges_activate(cg->irg);
269 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
270 dump_ir_block_graph_sched(cg->irg, "-am");
276 * Insert copies for all ia32 nodes where the should_be_same requirement
279 static void ia32_finish_irg_walker(ir_node *irn, void *env) {
280 ia32_code_gen_t *cg = env;
281 const ia32_register_req_t **reqs;
282 const arch_register_t *out_reg, *in_reg;
284 ir_node *copy, *in_node, *block;
286 if (! is_ia32_irn(irn))
289 /* nodes with destination address mode don't produce values */
290 if (get_ia32_op_type(irn) == ia32_AddrModeD)
293 reqs = get_ia32_out_req_all(irn);
294 n_res = get_ia32_n_res(irn);
295 block = get_nodes_block(irn);
297 /* check all OUT requirements, if there is a should_be_same */
298 for (i = 0; i < n_res; i++) {
299 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
300 /* get in and out register */
301 out_reg = get_ia32_out_reg(irn, i);
302 in_node = get_irn_n(irn, reqs[i]->same_pos);
303 in_reg = arch_get_irn_register(cg->arch_env, in_node);
305 /* check if in and out register are equal */
306 if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
307 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
309 /* create copy from in register */
310 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
312 /* destination is the out register */
313 arch_set_irn_register(cg->arch_env, copy, out_reg);
315 /* insert copy before the node into the schedule */
316 sched_add_before(irn, copy);
319 set_irn_n(irn, reqs[i]->same_pos, copy);
326 * Add Copy nodes for not fulfilled should_be_equal constraints
328 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
329 irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
335 * Dummy functions for hooks we don't need but which must be filled.
337 static void ia32_before_sched(void *self) {
340 static void ia32_before_ra(void *self) {
346 * Transforms a be node into a Load.
348 static void transform_to_Load(ia32_transform_env_t *env) {
349 ir_node *irn = env->irn;
350 entity *ent = be_get_frame_entity(irn);
351 ir_mode *mode = env->mode;
352 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
353 ir_node *nomem = new_rd_NoMem(env->irg);
354 ir_node *sched_point = NULL;
355 ir_node *ptr = get_irn_n(irn, 0);
356 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
357 ir_node *new_op, *proj;
358 const arch_register_t *reg;
360 if (sched_is_scheduled(irn)) {
361 sched_point = sched_prev(irn);
364 if (mode_is_float(mode)) {
365 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
368 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
371 set_ia32_am_support(new_op, ia32_am_Source);
372 set_ia32_op_type(new_op, ia32_AddrModeS);
373 set_ia32_am_flavour(new_op, ia32_B);
374 set_ia32_ls_mode(new_op, mode);
375 set_ia32_frame_ent(new_op, ent);
376 set_ia32_use_frame(new_op);
378 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
381 sched_add_after(sched_point, new_op);
382 sched_add_after(new_op, proj);
387 /* copy the register from the old node to the new Load */
388 reg = arch_get_irn_register(env->cg->arch_env, irn);
389 arch_set_irn_register(env->cg->arch_env, new_op, reg);
396 * Transforms a be node into a Store.
398 static void transform_to_Store(ia32_transform_env_t *env) {
399 ir_node *irn = env->irn;
400 entity *ent = be_get_frame_entity(irn);
401 ir_mode *mode = env->mode;
402 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
403 ir_node *nomem = new_rd_NoMem(env->irg);
404 ir_node *ptr = get_irn_n(irn, 0);
405 ir_node *val = get_irn_n(irn, 1);
406 ir_node *new_op, *proj;
407 ir_node *sched_point = NULL;
409 if (sched_is_scheduled(irn)) {
410 sched_point = sched_prev(irn);
413 if (mode_is_float(mode)) {
414 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
417 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
420 set_ia32_am_support(new_op, ia32_am_Dest);
421 set_ia32_op_type(new_op, ia32_AddrModeD);
422 set_ia32_am_flavour(new_op, ia32_B);
423 set_ia32_ls_mode(new_op, get_irn_mode(val));
424 set_ia32_frame_ent(new_op, ent);
425 set_ia32_use_frame(new_op);
427 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
430 sched_add_after(sched_point, new_op);
431 sched_add_after(new_op, proj);
441 * Calls the transform functions for StackParam, Spill and Reload.
443 static void ia32_after_ra_walker(ir_node *node, void *env) {
444 ia32_code_gen_t *cg = env;
445 ia32_transform_env_t tenv;
450 tenv.block = get_nodes_block(node);
451 tenv.dbg = get_irn_dbg_info(node);
452 tenv.irg = current_ir_graph;
455 tenv.mode = get_irn_mode(node);
458 if (be_is_StackParam(node) || be_is_Reload(node)) {
459 transform_to_Load(&tenv);
461 else if (be_is_Spill(node)) {
462 transform_to_Store(&tenv);
467 * We transform StackParam, Spill and Reload here. This needs to be done before
468 * stack biasing otherwise we would miss the corrected offset for these nodes.
470 static void ia32_after_ra(void *self) {
471 ia32_code_gen_t *cg = self;
472 irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
477 * Emits the code, closes the output file and frees
478 * the code generator interface.
480 static void ia32_codegen(void *self) {
481 ia32_code_gen_t *cg = self;
482 ir_graph *irg = cg->irg;
485 if (cg->emit_decls) {
486 ia32_gen_decls(cg->out);
490 ia32_finish_irg(irg, cg);
491 dump_ir_block_graph_sched(irg, "-finished");
492 ia32_gen_routine(out, irg, cg);
496 pmap_destroy(cg->tv_ent);
497 pmap_destroy(cg->types);
499 /* de-allocate code generator */
500 del_set(cg->reg_set);
504 static void *ia32_cg_init(FILE *F, const be_irg_t *birg);
506 static const arch_code_generator_if_t ia32_code_gen_if = {
509 ia32_before_sched, /* before scheduling hook */
510 ia32_before_ra, /* before register allocation hook */
511 ia32_after_ra, /* after register allocation hook */
512 ia32_codegen /* emit && done */
516 * Initializes the code generator.
518 static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
519 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
520 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
522 cg->impl = &ia32_code_gen_if;
524 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
525 cg->mod = firm_dbg_register("firm.be.ia32.cg");
527 cg->arch_env = birg->main_env->arch_env;
528 cg->types = pmap_create();
529 cg->tv_ent = pmap_create();
532 /* set optimizations */
535 cg->opt.placecnst = 1;
540 if (isa->num_codegens > 1)
545 cur_reg_set = cg->reg_set;
547 ia32_irn_ops.cg = cg;
549 return (arch_code_generator_t *)cg;
554 /*****************************************************************
555 * ____ _ _ _____ _____
556 * | _ \ | | | | |_ _|/ ____| /\
557 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
558 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
559 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
560 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
562 *****************************************************************/
564 static ia32_isa_t ia32_isa_template = {
566 &ia32_gp_regs[REG_ESP],
567 &ia32_gp_regs[REG_EBP],
573 * Initializes the backend ISA.
575 static void *ia32_init(void) {
576 static int inited = 0;
582 isa = xcalloc(1, sizeof(*isa));
583 memcpy(isa, &ia32_isa_template, sizeof(*isa));
585 ia32_register_init(isa);
586 ia32_create_opcodes();
596 * Closes the output file and frees the ISA structure.
598 static void ia32_done(void *self) {
604 static int ia32_get_n_reg_class(const void *self) {
608 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
609 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
610 return &ia32_reg_classes[i];
614 * Get the register class which shall be used to store a value of a given mode.
615 * @param self The this pointer.
616 * @param mode The mode in question.
617 * @return A register class which can hold values of the given mode.
619 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
620 if (mode_is_float(mode))
621 return &ia32_reg_classes[CLASS_ia32_fp];
623 return &ia32_reg_classes[CLASS_ia32_gp];
627 * Produces the type which sits between the stack args and the locals on the stack.
628 * it will contain the return address and space to store the old base pointer.
629 * @return The Firm type modelling the ABI between type.
631 static ir_type *get_between_type(void)
633 static ir_type *between_type = NULL;
634 static entity *old_bp_ent = NULL;
637 entity *ret_addr_ent;
638 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
639 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
641 between_type = new_type_class(new_id_from_str("ia32_between_type"));
642 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
643 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
645 set_entity_offset_bytes(old_bp_ent, 0);
646 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
647 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
654 * Get the ABI restrictions for procedure calls.
655 * @param self The this pointer.
656 * @param method_type The type of the method (procedure) in question.
657 * @param abi The abi object to be modified
659 void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
660 ir_type *between_type;
663 unsigned cc = get_method_calling_convention(method_type);
664 int n = get_method_n_params(method_type);
669 const arch_register_t *reg;
670 be_abi_call_flags_t call_flags;
672 /* set abi flags for calls */
673 call_flags.bits.left_to_right = 0;
674 call_flags.bits.store_args_sequential = 0;
675 call_flags.bits.try_omit_fp = 1;
676 call_flags.bits.fp_free = 0;
677 call_flags.bits.call_has_imm = 1;
679 /* get the between type and the frame pointer save entity */
680 between_type = get_between_type();
682 /* set stack parameter passing style */
683 be_abi_call_set_flags(abi, call_flags, between_type);
685 /* collect the mode for each type */
686 modes = alloca(n * sizeof(modes[0]));
688 for (i = 0; i < n; i++) {
689 tp = get_method_param_type(method_type, i);
690 modes[i] = get_type_mode(tp);
693 /* set register parameters */
694 if (cc & cc_reg_param) {
695 /* determine the number of parameters passed via registers */
696 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore, &ignore);
698 /* loop over all parameters and set the register requirements */
699 for (i = 0; i <= biggest_n; i++) {
700 reg = ia32_get_RegParam_reg(n, modes, i, cc);
701 assert(reg && "kaputt");
702 be_abi_call_param_reg(abi, i, reg);
709 /* set stack parameters */
710 for (i = stack_idx; i < n; i++) {
711 be_abi_call_param_stack(abi, i);
715 /* set return registers */
716 n = get_method_n_ress(method_type);
718 assert(n <= 2 && "more than two results not supported");
720 /* In case of 64bit returns, we will have two 32bit values */
722 tp = get_method_res_type(method_type, 0);
723 mode = get_type_mode(tp);
725 assert(!mode_is_float(mode) && "two FP results not supported");
727 tp = get_method_res_type(method_type, 1);
728 mode = get_type_mode(tp);
730 assert(!mode_is_float(mode) && "two FP results not supported");
732 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
733 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
736 tp = get_method_res_type(method_type, 0);
737 assert(is_atomic_type(tp));
738 mode = get_type_mode(tp);
740 be_abi_call_res_reg(abi, 0, mode_is_float(mode) ? &ia32_fp_regs[REG_XMM0] : &ia32_gp_regs[REG_EAX]);
745 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
746 return &ia32_irn_ops;
749 const arch_irn_handler_t ia32_irn_handler = {
753 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
754 return &ia32_irn_handler;
757 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
758 return is_ia32_irn(irn);
762 * Initializes the code generator interface.
764 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
765 return &ia32_code_gen_if;
768 list_sched_selector_t ia32_sched_selector;
771 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
773 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
774 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
775 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
776 return &ia32_sched_selector;
780 static void ia32_register_options(lc_opt_entry_t *ent)
783 #endif /* WITH_LIBCORE */
785 const arch_isa_if_t ia32_isa_if = {
787 ia32_register_options,
791 ia32_get_n_reg_class,
793 ia32_get_reg_class_for_mode,
795 ia32_get_irn_handler,
796 ia32_get_code_generator_if,
797 ia32_get_list_sched_selector