2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
31 #include "lc_opts_enum.h"
35 #include "pseudo_irg.h"
40 #include "iredges_t.h"
46 #include "irdump_grgen.h"
53 #include "iroptimize.h"
56 #include "../beirg_t.h"
57 #include "../benode_t.h"
58 #include "../belower.h"
59 #include "../besched_t.h"
62 #include "../beirgmod.h"
63 #include "../be_dbgout.h"
64 #include "../beblocksched.h"
65 #include "../bemachine.h"
66 #include "../beilpsched.h"
67 #include "../bespillslots.h"
68 #include "../bemodule.h"
69 #include "../begnuas.h"
70 #include "../bestate.h"
71 #include "../beflags.h"
73 #include "bearch_ia32_t.h"
75 #include "ia32_new_nodes.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "gen_ia32_machine.h"
78 #include "ia32_transform.h"
79 #include "ia32_pbqp_transform.h"
80 #include "ia32_emitter.h"
81 #include "ia32_map_regs.h"
82 #include "ia32_optimize.h"
84 #include "ia32_dbg_stat.h"
85 #include "ia32_finish.h"
86 #include "ia32_util.h"
88 #include "ia32_architecture.h"
90 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
93 static set *cur_reg_set = NULL;
95 ir_mode *mode_fpcw = NULL;
96 ia32_code_gen_t *ia32_current_cg = NULL;
99 * The environment for the intrinsic mapping.
101 static ia32_intrinsic_env_t intrinsic_env = {
103 NULL, /* the irg, these entities belong to */
104 NULL, /* entity for first div operand (move into FPU) */
105 NULL, /* entity for second div operand (move into FPU) */
106 NULL, /* entity for converts ll -> d */
107 NULL, /* entity for converts d -> ll */
108 NULL, /* entity for __divdi3 library call */
109 NULL, /* entity for __moddi3 library call */
110 NULL, /* entity for __udivdi3 library call */
111 NULL, /* entity for __umoddi3 library call */
112 NULL, /* bias value for conversion from float to unsigned 64 */
116 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
118 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
119 create_const_node_func func,
120 const arch_register_t* reg)
122 ir_node *block, *res;
127 block = get_irg_start_block(cg->irg);
128 res = func(NULL, cg->irg, block);
129 arch_set_irn_register(cg->arch_env, res, reg);
132 add_irn_dep(get_irg_end(cg->irg), res);
133 /* add_irn_dep(get_irg_start(cg->irg), res); */
138 /* Creates the unique per irg GP NoReg node. */
139 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
140 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
141 &ia32_gp_regs[REG_GP_NOREG]);
144 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
145 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
146 &ia32_vfp_regs[REG_VFP_NOREG]);
149 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
150 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
151 &ia32_xmm_regs[REG_XMM_NOREG]);
154 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
155 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
156 &ia32_gp_regs[REG_GP_UKNWN]);
159 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
160 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
161 &ia32_vfp_regs[REG_VFP_UKNWN]);
164 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
165 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
166 &ia32_xmm_regs[REG_XMM_UKNWN]);
169 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
170 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
171 &ia32_fp_cw_regs[REG_FPCW]);
176 * Returns gp_noreg or fp_noreg, depending in input requirements.
178 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
179 const arch_register_req_t *req;
181 req = arch_get_register_req(cg->arch_env, irn, pos);
182 assert(req != NULL && "Missing register requirements");
183 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
184 return ia32_new_NoReg_gp(cg);
186 if (ia32_cg_config.use_sse2) {
187 return ia32_new_NoReg_xmm(cg);
189 return ia32_new_NoReg_vfp(cg);
193 /**************************************************
196 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
197 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
198 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
199 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
202 **************************************************/
205 * Return register requirements for an ia32 node.
206 * If the node returns a tuple (mode_T) then the proj's
207 * will be asked for this information.
209 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
213 long node_pos = pos == -1 ? 0 : pos;
214 ir_mode *mode = is_Block(node) ? NULL : get_irn_mode(node);
217 if (is_Block(node) || mode == mode_X) {
218 return arch_no_register_req;
221 if (mode == mode_T && pos < 0) {
222 return arch_no_register_req;
227 return arch_no_register_req;
230 return arch_no_register_req;
233 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
234 node = skip_Proj_const(node);
237 if (is_ia32_irn(node)) {
238 const arch_register_req_t *req;
240 req = get_ia32_in_req(node, pos);
242 req = get_ia32_out_req(node, node_pos);
249 /* unknowns should be transformed already */
250 assert(!is_Unknown(node));
252 return arch_no_register_req;
255 static void ia32_set_irn_reg(const void *self, ir_node *irn,
256 const arch_register_t *reg)
261 if (get_irn_mode(irn) == mode_X) {
266 pos = get_Proj_proj(irn);
267 irn = skip_Proj(irn);
270 if (is_ia32_irn(irn)) {
271 const arch_register_t **slots;
273 slots = get_ia32_slots(irn);
276 ia32_set_firm_reg(irn, reg, cur_reg_set);
280 static const arch_register_t *ia32_get_irn_reg(const void *self,
284 const arch_register_t *reg = NULL;
289 if (get_irn_mode(irn) == mode_X) {
293 pos = get_Proj_proj(irn);
294 irn = skip_Proj_const(irn);
297 if (is_ia32_irn(irn)) {
298 const arch_register_t **slots;
299 slots = get_ia32_slots(irn);
300 assert(pos < get_ia32_n_res(irn));
303 reg = ia32_get_firm_reg(irn, cur_reg_set);
309 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
310 arch_irn_class_t classification = arch_irn_class_normal;
313 irn = skip_Proj_const(irn);
316 classification |= arch_irn_class_branch;
318 if (! is_ia32_irn(irn))
319 return classification & ~arch_irn_class_normal;
322 classification |= arch_irn_class_load;
325 classification |= arch_irn_class_store;
327 if (is_ia32_need_stackent(irn))
328 classification |= arch_irn_class_reload;
330 return classification;
333 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
334 arch_irn_flags_t flags = arch_irn_flags_none;
338 return arch_irn_flags_ignore;
340 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
341 ir_node *pred = get_Proj_pred(irn);
343 if(is_ia32_irn(pred)) {
344 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
350 if (is_ia32_irn(irn)) {
351 flags |= get_ia32_flags(irn);
358 * The IA32 ABI callback object.
361 be_abi_call_flags_bits_t flags; /**< The call flags. */
362 const arch_isa_t *isa; /**< The ISA handle. */
363 const arch_env_t *aenv; /**< The architecture environment. */
364 ir_graph *irg; /**< The associated graph. */
367 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
369 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
372 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
374 set_ia32_frame_ent(irn, ent);
377 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
378 const ia32_irn_ops_t *ops = self;
380 if (get_ia32_frame_ent(irn)) {
381 if (is_ia32_Pop(irn)) {
382 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
384 /* Pop nodes modify the stack pointer before calculating the destination
385 * address, so fix this here
391 add_ia32_am_offs_int(irn, bias);
395 static int ia32_get_sp_bias(const void *self, const ir_node *node)
399 if (is_ia32_Push(node))
402 if (is_ia32_Pop(node))
409 * Put all registers which are saved by the prologue/epilogue in a set.
411 * @param self The callback object.
412 * @param s The result set.
414 static void ia32_abi_dont_save_regs(void *self, pset *s)
416 ia32_abi_env_t *env = self;
417 if(env->flags.try_omit_fp)
418 pset_insert_ptr(s, env->isa->bp);
422 * Generate the routine prologue.
424 * @param self The callback object.
425 * @param mem A pointer to the mem node. Update this if you define new memory.
426 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
428 * @return The register which shall be used as a stack frame base.
430 * All nodes which define registers in @p reg_map must keep @p reg_map current.
432 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
434 ia32_abi_env_t *env = self;
435 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
436 ia32_code_gen_t *cg = isa->cg;
438 if (! env->flags.try_omit_fp) {
439 ir_node *bl = get_irg_start_block(env->irg);
440 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
441 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
442 ir_node *noreg = ia32_new_NoReg_gp(cg);
445 /* ALL nodes representing bp must be set to ignore. */
446 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
449 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp, curr_bp);
450 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
451 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
453 /* the push must have SP out register */
454 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
455 set_ia32_flags(push, arch_irn_flags_ignore);
457 /* move esp to ebp */
458 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
459 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
460 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
461 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
463 /* beware: the copy must be done before any other sp use */
464 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
465 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
466 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
467 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
469 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
470 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
479 * Generate the routine epilogue.
480 * @param self The callback object.
481 * @param bl The block for the epilog
482 * @param mem A pointer to the mem node. Update this if you define new memory.
483 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
484 * @return The register which shall be used as a stack frame base.
486 * All nodes which define registers in @p reg_map must keep @p reg_map current.
488 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
490 ia32_abi_env_t *env = self;
491 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
492 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
494 if (env->flags.try_omit_fp) {
495 /* simply remove the stack frame here */
496 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
497 add_irn_dep(curr_sp, *mem);
499 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
500 ia32_code_gen_t *cg = isa->cg;
501 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
502 ir_graph *irg = current_ir_graph;
504 if (ia32_cg_config.use_leave) {
508 leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
509 set_ia32_flags(leave, arch_irn_flags_ignore);
510 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
511 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
513 ir_node *noreg = ia32_new_NoReg_gp(cg);
516 /* the old SP is not needed anymore (kill the proj) */
517 assert(is_Proj(curr_sp));
518 be_kill_node(curr_sp);
520 /* copy ebp to esp */
521 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
522 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
523 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
526 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp);
527 set_ia32_flags(pop, arch_irn_flags_ignore);
528 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
529 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
531 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
533 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
534 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
537 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
538 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
542 * Initialize the callback object.
543 * @param call The call object.
544 * @param aenv The architecture environment.
545 * @param irg The graph with the method.
546 * @return Some pointer. This pointer is passed to all other callback functions as self object.
548 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
550 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
551 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
552 env->flags = fl.bits;
555 env->isa = aenv->isa;
560 * Destroy the callback object.
561 * @param self The callback object.
563 static void ia32_abi_done(void *self) {
568 * Produces the type which sits between the stack args and the locals on the stack.
569 * it will contain the return address and space to store the old base pointer.
570 * @return The Firm type modeling the ABI between type.
572 static ir_type *ia32_abi_get_between_type(void *self)
574 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
575 static ir_type *omit_fp_between_type = NULL;
576 static ir_type *between_type = NULL;
578 ia32_abi_env_t *env = self;
580 if (! between_type) {
581 ir_entity *old_bp_ent;
582 ir_entity *ret_addr_ent;
583 ir_entity *omit_fp_ret_addr_ent;
585 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
586 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
588 between_type = new_type_struct(IDENT("ia32_between_type"));
589 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
590 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
592 set_entity_offset(old_bp_ent, 0);
593 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
594 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
595 set_type_state(between_type, layout_fixed);
597 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
598 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
600 set_entity_offset(omit_fp_ret_addr_ent, 0);
601 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
602 set_type_state(omit_fp_between_type, layout_fixed);
605 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
610 * Get the estimated cycle count for @p irn.
612 * @param self The this pointer.
613 * @param irn The node.
615 * @return The estimated cycle count for this operation
617 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
620 ia32_op_type_t op_tp;
625 if (!is_ia32_irn(irn))
628 assert(is_ia32_irn(irn));
630 cost = get_ia32_latency(irn);
631 op_tp = get_ia32_op_type(irn);
633 if (is_ia32_CopyB(irn)) {
636 else if (is_ia32_CopyB_i(irn)) {
637 int size = get_ia32_copyb_size(irn);
638 cost = 20 + (int)ceil((4/3) * size);
640 /* in case of address mode operations add additional cycles */
641 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
643 In case of stack access and access to fixed addresses add 5 cycles
644 (we assume they are in cache), other memory operations cost 20
647 if(is_ia32_use_frame(irn) ||
648 (is_ia32_NoReg_GP(get_irn_n(irn, 0)) &&
649 is_ia32_NoReg_GP(get_irn_n(irn, 1)))) {
660 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
662 * @param irn The original operation
663 * @param i Index of the argument we want the inverse operation to yield
664 * @param inverse struct to be filled with the resulting inverse op
665 * @param obstack The obstack to use for allocation of the returned nodes array
666 * @return The inverse operation or NULL if operation invertible
668 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
672 ir_node *block, *noreg, *nomem;
676 /* we cannot invert non-ia32 irns */
677 if (! is_ia32_irn(irn))
680 /* operand must always be a real operand (not base, index or mem) */
681 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
684 /* we don't invert address mode operations */
685 if (get_ia32_op_type(irn) != ia32_Normal)
688 /* TODO: adjust for new immediates... */
689 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
693 irg = get_irn_irg(irn);
694 block = get_nodes_block(irn);
695 mode = get_irn_mode(irn);
696 irn_mode = get_irn_mode(irn);
697 noreg = get_irn_n(irn, 0);
698 nomem = new_r_NoMem(irg);
699 dbg = get_irn_dbg_info(irn);
701 /* initialize structure */
702 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
706 switch (get_ia32_irn_opcode(irn)) {
709 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
710 /* we have an add with a const here */
711 /* invers == add with negated const */
712 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
714 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
715 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
716 set_ia32_commutative(inverse->nodes[0]);
718 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
719 /* we have an add with a symconst here */
720 /* invers == sub with const */
721 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
723 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
726 /* normal add: inverse == sub */
727 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
734 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
735 /* we have a sub with a const/symconst here */
736 /* invers == add with this const */
737 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
738 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
739 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
743 if (i == n_ia32_binary_left) {
744 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
747 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
755 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
756 /* xor with const: inverse = xor */
757 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
758 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
759 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
763 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
769 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
774 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
779 /* inverse operation not supported */
786 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
788 if(mode_is_float(mode))
795 * Get the mode that should be used for spilling value node
797 static ir_mode *get_spill_mode(const ir_node *node)
799 ir_mode *mode = get_irn_mode(node);
800 return get_spill_mode_mode(mode);
804 * Checks whether an addressmode reload for a node with mode mode is compatible
805 * with a spillslot of mode spill_mode
807 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
809 if(mode_is_float(mode)) {
810 return mode == spillmode;
817 * Check if irn can load it's operand at position i from memory (source addressmode).
818 * @param self Pointer to irn ops itself
819 * @param irn The irn to be checked
820 * @param i The operands position
821 * @return Non-Zero if operand can be loaded
823 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
824 ir_node *op = get_irn_n(irn, i);
825 const ir_mode *mode = get_irn_mode(op);
826 const ir_mode *spillmode = get_spill_mode(op);
829 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
830 get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */
831 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
832 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
833 ! ia32_is_spillmode_compatible(mode, spillmode) ||
834 (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
835 is_ia32_use_frame(irn)) /* must not already use frame */
838 if (i == n_ia32_binary_left) {
839 const arch_register_req_t *req;
840 if(!is_ia32_commutative(irn))
842 /* we can't swap left/right for limited registers
843 * (As this (currently) breaks constraint handling copies)
845 req = get_ia32_in_req(irn, n_ia32_binary_left);
846 if(req->type & arch_register_req_type_limited) {
854 static void ia32_perform_memory_operand(const void *self, ir_node *irn,
855 ir_node *spill, unsigned int i)
857 const ia32_irn_ops_t *ops = self;
858 ia32_code_gen_t *cg = ops->cg;
860 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
862 if (i == n_ia32_binary_left) {
863 ia32_swap_left_right(irn);
866 set_ia32_op_type(irn, ia32_AddrModeS);
867 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
868 set_ia32_use_frame(irn);
869 set_ia32_need_stackent(irn);
871 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
872 set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
873 set_irn_n(irn, n_ia32_mem, spill);
875 /* immediates are only allowed on the right side */
876 if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
877 ia32_swap_left_right(irn);
881 static const be_abi_callbacks_t ia32_abi_callbacks = {
884 ia32_abi_get_between_type,
885 ia32_abi_dont_save_regs,
890 /* fill register allocator interface */
892 static const arch_irn_ops_if_t ia32_irn_ops_if = {
893 ia32_get_irn_reg_req,
898 ia32_get_frame_entity,
899 ia32_set_frame_entity,
900 ia32_set_frame_offset,
903 ia32_get_op_estimated_cost,
904 ia32_possible_memory_operand,
905 ia32_perform_memory_operand,
908 static ia32_irn_ops_t ia32_irn_ops = {
915 /**************************************************
918 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
919 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
920 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
921 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
924 **************************************************/
926 static void ia32_before_abi(void *self) {
927 lower_mode_b_config_t lower_mode_b_config = {
928 mode_Iu, /* lowered mode */
929 mode_Bu, /* prefered mode for set */
930 0, /* don't lower direct compares */
932 ia32_code_gen_t *cg = self;
934 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
936 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
940 * Transforms the standard firm graph into
943 static void ia32_prepare_graph(void *self) {
944 ia32_code_gen_t *cg = self;
946 /* do local optimisations */
947 optimize_graph_df(cg->irg);
949 /* TODO: we often have dead code reachable through out-edges here. So for
950 * now we rebuild edges (as we need correct user count for code selection)
953 edges_deactivate(cg->irg);
954 edges_activate(cg->irg);
958 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
960 /* used for examination purposes only
962 dump_irg_grgen(cg->irg, "-pre_transform");
965 /* transform nodes into assembler instructions by PBQP magic */
966 ia32_transform_graph_by_pbqp(cg);
969 be_dump(cg->irg, "-after_pbqp_transform", dump_ir_block_graph_sched);
971 /* transform remaining nodes into assembler instructions */
972 ia32_transform_graph(cg);
974 /* do local optimisations (mainly CSE) */
975 optimize_graph_df(cg->irg);
978 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
980 /* optimize address mode */
981 ia32_optimize_graph(cg);
984 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
986 /* do code placement, to optimize the position of constants */
990 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
994 * Dummy functions for hooks we don't need but which must be filled.
996 static void ia32_before_sched(void *self) {
1000 static void turn_back_am(ir_node *node)
1002 ir_graph *irg = current_ir_graph;
1003 dbg_info *dbgi = get_irn_dbg_info(node);
1004 ir_node *block = get_nodes_block(node);
1005 ir_node *base = get_irn_n(node, n_ia32_base);
1006 ir_node *index = get_irn_n(node, n_ia32_index);
1007 ir_node *mem = get_irn_n(node, n_ia32_mem);
1008 ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg);
1012 const ir_edge_t *edge;
1014 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1015 load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1017 ia32_copy_am_attrs(load, node);
1018 set_irn_n(node, n_ia32_mem, new_NoMem());
1020 switch (get_ia32_am_arity(node)) {
1022 set_irn_n(node, n_ia32_unary_op, load_res);
1025 case ia32_am_binary:
1026 if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
1027 assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) ||
1028 is_ia32_Test(node) || is_ia32_Test8Bit(node));
1029 set_irn_n(node, n_ia32_binary_left, load_res);
1031 set_irn_n(node, n_ia32_binary_right, load_res);
1035 case ia32_am_ternary:
1036 set_irn_n(node, n_ia32_binary_right, load_res);
1041 set_irn_n(node, n_ia32_base, noreg);
1042 set_irn_n(node, n_ia32_index, noreg);
1043 set_ia32_am_offs_int(node, 0);
1044 set_ia32_am_sc(node, NULL);
1045 set_ia32_am_scale(node, 0);
1046 clear_ia32_am_sc_sign(node);
1048 /* rewire mem-proj */
1049 if(get_irn_mode(node) == mode_T) {
1051 foreach_out_edge(node, edge) {
1052 ir_node *out = get_edge_src_irn(edge);
1053 if(get_Proj_proj(out) == pn_ia32_mem) {
1059 if(mem_proj != NULL) {
1060 set_Proj_pred(mem_proj, load);
1061 set_Proj_proj(mem_proj, pn_ia32_Load_M);
1065 set_ia32_op_type(node, ia32_Normal);
1066 if(sched_is_scheduled(node))
1067 sched_add_before(node, load);
1070 static ir_node *flags_remat(ir_node *node, ir_node *after)
1072 /* we should turn back source address mode when rematerializing nodes */
1073 ia32_op_type_t type = get_ia32_op_type(node);
1077 if(is_Block(after)) {
1080 block = get_nodes_block(after);
1084 case ia32_AddrModeS: turn_back_am(node); break;
1086 case ia32_AddrModeD:
1087 /* TODO implement this later... */
1088 panic("found DestAM with flag user %+F this should not happen", node);
1091 default: assert(type == ia32_Normal); break;
1094 copy = exact_copy(node);
1095 set_nodes_block(copy, block);
1096 sched_add_after(after, copy);
1102 * Called before the register allocator.
1103 * Calculate a block schedule here. We need it for the x87
1104 * simulator and the emitter.
1106 static void ia32_before_ra(void *self) {
1107 ia32_code_gen_t *cg = self;
1109 /* setup fpu rounding modes */
1110 ia32_setup_fpu_mode(cg);
1113 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1116 ia32_add_missing_keeps(cg);
1121 * Transforms a be_Reload into a ia32 Load.
1123 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1124 ir_graph *irg = get_irn_irg(node);
1125 dbg_info *dbg = get_irn_dbg_info(node);
1126 ir_node *block = get_nodes_block(node);
1127 ir_entity *ent = be_get_frame_entity(node);
1128 ir_mode *mode = get_irn_mode(node);
1129 ir_mode *spillmode = get_spill_mode(node);
1130 ir_node *noreg = ia32_new_NoReg_gp(cg);
1131 ir_node *sched_point = NULL;
1132 ir_node *ptr = get_irg_frame(irg);
1133 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1134 ir_node *new_op, *proj;
1135 const arch_register_t *reg;
1137 if (sched_is_scheduled(node)) {
1138 sched_point = sched_prev(node);
1141 if (mode_is_float(spillmode)) {
1142 if (ia32_cg_config.use_sse2)
1143 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
1145 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
1147 else if (get_mode_size_bits(spillmode) == 128) {
1148 // Reload 128 bit sse registers
1149 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1152 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1154 set_ia32_op_type(new_op, ia32_AddrModeS);
1155 set_ia32_ls_mode(new_op, spillmode);
1156 set_ia32_frame_ent(new_op, ent);
1157 set_ia32_use_frame(new_op);
1159 DBG_OPT_RELOAD2LD(node, new_op);
1161 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1164 sched_add_after(sched_point, new_op);
1168 /* copy the register from the old node to the new Load */
1169 reg = arch_get_irn_register(cg->arch_env, node);
1170 arch_set_irn_register(cg->arch_env, new_op, reg);
1172 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1174 exchange(node, proj);
1178 * Transforms a be_Spill node into a ia32 Store.
1180 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1181 ir_graph *irg = get_irn_irg(node);
1182 dbg_info *dbg = get_irn_dbg_info(node);
1183 ir_node *block = get_nodes_block(node);
1184 ir_entity *ent = be_get_frame_entity(node);
1185 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1186 ir_mode *mode = get_spill_mode(spillval);
1187 ir_node *noreg = ia32_new_NoReg_gp(cg);
1188 ir_node *nomem = new_rd_NoMem(irg);
1189 ir_node *ptr = get_irg_frame(irg);
1190 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1192 ir_node *sched_point = NULL;
1194 if (sched_is_scheduled(node)) {
1195 sched_point = sched_prev(node);
1198 /* No need to spill unknown values... */
1199 if(is_ia32_Unknown_GP(val) ||
1200 is_ia32_Unknown_VFP(val) ||
1201 is_ia32_Unknown_XMM(val)) {
1206 exchange(node, store);
1210 if (mode_is_float(mode)) {
1211 if (ia32_cg_config.use_sse2)
1212 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
1214 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
1215 } else if (get_mode_size_bits(mode) == 128) {
1216 // Spill 128 bit SSE registers
1217 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
1218 } else if (get_mode_size_bits(mode) == 8) {
1219 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
1221 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
1224 set_ia32_op_type(store, ia32_AddrModeD);
1225 set_ia32_ls_mode(store, mode);
1226 set_ia32_frame_ent(store, ent);
1227 set_ia32_use_frame(store);
1228 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1229 DBG_OPT_SPILL2ST(node, store);
1232 sched_add_after(sched_point, store);
1236 exchange(node, store);
1239 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1240 ir_graph *irg = get_irn_irg(node);
1241 dbg_info *dbg = get_irn_dbg_info(node);
1242 ir_node *block = get_nodes_block(node);
1243 ir_node *noreg = ia32_new_NoReg_gp(cg);
1244 ir_node *frame = get_irg_frame(irg);
1246 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, sp, noreg);
1248 set_ia32_frame_ent(push, ent);
1249 set_ia32_use_frame(push);
1250 set_ia32_op_type(push, ia32_AddrModeS);
1251 set_ia32_ls_mode(push, mode_Is);
1253 sched_add_before(schedpoint, push);
1257 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1258 ir_graph *irg = get_irn_irg(node);
1259 dbg_info *dbg = get_irn_dbg_info(node);
1260 ir_node *block = get_nodes_block(node);
1261 ir_node *noreg = ia32_new_NoReg_gp(cg);
1262 ir_node *frame = get_irg_frame(irg);
1264 ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, new_NoMem(), sp);
1266 set_ia32_frame_ent(pop, ent);
1267 set_ia32_use_frame(pop);
1268 set_ia32_op_type(pop, ia32_AddrModeD);
1269 set_ia32_ls_mode(pop, mode_Is);
1271 sched_add_before(schedpoint, pop);
1276 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
1277 ir_graph *irg = get_irn_irg(node);
1278 dbg_info *dbg = get_irn_dbg_info(node);
1279 ir_node *block = get_nodes_block(node);
1280 ir_mode *spmode = mode_Iu;
1281 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1284 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1285 arch_set_irn_register(cg->arch_env, sp, spreg);
1291 * Transform memperm, currently we do this the ugly way and produce
1292 * push/pop into/from memory cascades. This is possible without using
1295 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1296 ir_graph *irg = get_irn_irg(node);
1297 ir_node *block = get_nodes_block(node);
1301 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1302 const ir_edge_t *edge;
1303 const ir_edge_t *next;
1306 arity = be_get_MemPerm_entity_arity(node);
1307 pops = alloca(arity * sizeof(pops[0]));
1310 for(i = 0; i < arity; ++i) {
1311 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1312 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1313 ir_type *enttype = get_entity_type(inent);
1314 unsigned entsize = get_type_size_bytes(enttype);
1315 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1316 ir_node *mem = get_irn_n(node, i + 1);
1319 /* work around cases where entities have different sizes */
1320 if(entsize2 < entsize)
1322 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1324 push = create_push(cg, node, node, sp, mem, inent);
1325 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1327 /* add another push after the first one */
1328 push = create_push(cg, node, node, sp, mem, inent);
1329 add_ia32_am_offs_int(push, 4);
1330 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1333 set_irn_n(node, i, new_Bad());
1337 for(i = arity - 1; i >= 0; --i) {
1338 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1339 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1340 ir_type *enttype = get_entity_type(outent);
1341 unsigned entsize = get_type_size_bytes(enttype);
1342 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1345 /* work around cases where entities have different sizes */
1346 if(entsize2 < entsize)
1348 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1350 pop = create_pop(cg, node, node, sp, outent);
1351 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1353 add_ia32_am_offs_int(pop, 4);
1355 /* add another pop after the first one */
1356 pop = create_pop(cg, node, node, sp, outent);
1357 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1364 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1365 sched_add_before(node, keep);
1367 /* exchange memprojs */
1368 foreach_out_edge_safe(node, edge, next) {
1369 ir_node *proj = get_edge_src_irn(edge);
1370 int p = get_Proj_proj(proj);
1374 set_Proj_pred(proj, pops[p]);
1375 set_Proj_proj(proj, pn_ia32_Pop_M);
1378 /* remove memperm */
1379 arity = get_irn_arity(node);
1380 for(i = 0; i < arity; ++i) {
1381 set_irn_n(node, i, new_Bad());
1387 * Block-Walker: Calls the transform functions Spill and Reload.
1389 static void ia32_after_ra_walker(ir_node *block, void *env) {
1390 ir_node *node, *prev;
1391 ia32_code_gen_t *cg = env;
1393 /* beware: the schedule is changed here */
1394 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1395 prev = sched_prev(node);
1397 if (be_is_Reload(node)) {
1398 transform_to_Load(cg, node);
1399 } else if (be_is_Spill(node)) {
1400 transform_to_Store(cg, node);
1401 } else if(be_is_MemPerm(node)) {
1402 transform_MemPerm(cg, node);
1408 * Collects nodes that need frame entities assigned.
1410 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1412 be_fec_env_t *env = data;
1414 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1415 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1416 int align = get_mode_size_bytes(mode);
1417 be_node_needs_frame_entity(env, node, mode, align);
1418 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1419 && is_ia32_use_frame(node)) {
1420 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1421 const ir_mode *mode = get_ia32_ls_mode(node);
1422 const ia32_attr_t *attr = get_ia32_attr_const(node);
1423 int align = get_mode_size_bytes(mode);
1425 if(attr->data.need_64bit_stackent) {
1428 if(attr->data.need_32bit_stackent) {
1431 be_node_needs_frame_entity(env, node, mode, align);
1432 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
1433 || is_ia32_vfld(node)) {
1434 const ir_mode *mode = get_ia32_ls_mode(node);
1436 be_node_needs_frame_entity(env, node, mode, align);
1437 } else if(is_ia32_FldCW(node)) {
1438 /* although 2 byte would be enough 4 byte performs best */
1439 const ir_mode *mode = mode_Iu;
1441 be_node_needs_frame_entity(env, node, mode, align);
1444 assert(is_ia32_St(node) ||
1445 is_ia32_xStoreSimple(node) ||
1446 is_ia32_vfst(node) ||
1447 is_ia32_vfist(node) ||
1448 is_ia32_FnstCW(node));
1455 * We transform Spill and Reload here. This needs to be done before
1456 * stack biasing otherwise we would miss the corrected offset for these nodes.
1458 static void ia32_after_ra(void *self) {
1459 ia32_code_gen_t *cg = self;
1460 ir_graph *irg = cg->irg;
1461 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1463 /* create and coalesce frame entities */
1464 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1465 be_assign_entities(fec_env);
1466 be_free_frame_entity_coalescer(fec_env);
1468 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1472 * Last touchups for the graph before emit: x87 simulation to replace the
1473 * virtual with real x87 instructions, creating a block schedule and peephole
1476 static void ia32_finish(void *self) {
1477 ia32_code_gen_t *cg = self;
1478 ir_graph *irg = cg->irg;
1480 ia32_finish_irg(irg, cg);
1482 /* we might have to rewrite x87 virtual registers */
1483 if (cg->do_x87_sim) {
1484 x87_simulate_graph(cg->arch_env, cg->birg);
1487 /* do peephole optimisations */
1488 ia32_peephole_optimization(cg);
1490 /* create block schedule, this also removes empty blocks which might
1491 * produce critical edges */
1492 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1496 * Emits the code, closes the output file and frees
1497 * the code generator interface.
1499 static void ia32_codegen(void *self) {
1500 ia32_code_gen_t *cg = self;
1501 ir_graph *irg = cg->irg;
1503 ia32_gen_routine(cg, irg);
1507 /* remove it from the isa */
1510 assert(ia32_current_cg == cg);
1511 ia32_current_cg = NULL;
1513 /* de-allocate code generator */
1514 del_set(cg->reg_set);
1518 static void *ia32_cg_init(be_irg_t *birg);
1520 static const arch_code_generator_if_t ia32_code_gen_if = {
1522 ia32_before_abi, /* before abi introduce hook */
1525 ia32_before_sched, /* before scheduling hook */
1526 ia32_before_ra, /* before register allocation hook */
1527 ia32_after_ra, /* after register allocation hook */
1528 ia32_finish, /* called before codegen */
1529 ia32_codegen /* emit && done */
1533 * Initializes a IA32 code generator.
1535 static void *ia32_cg_init(be_irg_t *birg) {
1536 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1537 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1539 cg->impl = &ia32_code_gen_if;
1540 cg->irg = birg->irg;
1541 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1542 cg->arch_env = birg->main_env->arch_env;
1545 cg->blk_sched = NULL;
1546 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1552 if (isa->name_obst) {
1553 obstack_free(isa->name_obst, NULL);
1554 obstack_init(isa->name_obst);
1558 cur_reg_set = cg->reg_set;
1560 ia32_irn_ops.cg = cg;
1562 assert(ia32_current_cg == NULL);
1563 ia32_current_cg = cg;
1565 return (arch_code_generator_t *)cg;
1570 /*****************************************************************
1571 * ____ _ _ _____ _____
1572 * | _ \ | | | | |_ _|/ ____| /\
1573 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1574 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1575 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1576 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1578 *****************************************************************/
1581 * Set output modes for GCC
1583 static const tarval_mode_info mo_integer = {
1590 * set the tarval output mode of all integer modes to decimal
1592 static void set_tarval_output_modes(void)
1596 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1597 ir_mode *mode = get_irp_mode(i);
1599 if (mode_is_int(mode))
1600 set_tarval_mode_output_option(mode, &mo_integer);
1604 const arch_isa_if_t ia32_isa_if;
1607 * The template that generates a new ISA object.
1608 * Note that this template can be changed by command line
1611 static ia32_isa_t ia32_isa_template = {
1613 &ia32_isa_if, /* isa interface implementation */
1614 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1615 &ia32_gp_regs[REG_EBP], /* base pointer register */
1616 -1, /* stack direction */
1617 NULL, /* main environment */
1618 7, /* costs for a spill instruction */
1619 5, /* costs for a reload instruction */
1621 NULL, /* 16bit register names */
1622 NULL, /* 8bit register names */
1623 NULL, /* 8bit register names high */
1626 NULL, /* current code generator */
1627 NULL, /* abstract machine */
1629 NULL, /* name obstack */
1634 * Initializes the backend ISA.
1636 static void *ia32_init(FILE *file_handle) {
1637 static int inited = 0;
1644 set_tarval_output_modes();
1646 isa = xmalloc(sizeof(*isa));
1647 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1649 if(mode_fpcw == NULL) {
1650 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1653 ia32_register_init();
1654 ia32_create_opcodes();
1656 be_emit_init(file_handle);
1657 isa->regs_16bit = pmap_create();
1658 isa->regs_8bit = pmap_create();
1659 isa->regs_8bit_high = pmap_create();
1660 isa->types = pmap_create();
1661 isa->tv_ent = pmap_create();
1662 isa->cpu = ia32_init_machine_description();
1664 ia32_build_16bit_reg_map(isa->regs_16bit);
1665 ia32_build_8bit_reg_map(isa->regs_8bit);
1666 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1669 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1670 obstack_init(isa->name_obst);
1673 /* enter the ISA object into the intrinsic environment */
1674 intrinsic_env.isa = isa;
1675 ia32_handle_intrinsics();
1677 /* needed for the debug support */
1678 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1679 be_emit_cstring(".Ltext0:\n");
1680 be_emit_write_line();
1682 /* we mark referenced global entities, so we can only emit those which
1683 * are actually referenced. (Note: you mustn't use the type visited flag
1684 * elsewhere in the backend)
1686 inc_master_type_visited();
1694 * Closes the output file and frees the ISA structure.
1696 static void ia32_done(void *self) {
1697 ia32_isa_t *isa = self;
1699 /* emit now all global declarations */
1700 be_gas_emit_decls(isa->arch_isa.main_env, 1);
1702 pmap_destroy(isa->regs_16bit);
1703 pmap_destroy(isa->regs_8bit);
1704 pmap_destroy(isa->regs_8bit_high);
1705 pmap_destroy(isa->tv_ent);
1706 pmap_destroy(isa->types);
1709 obstack_free(isa->name_obst, NULL);
1719 * Return the number of register classes for this architecture.
1720 * We report always these:
1721 * - the general purpose registers
1722 * - the SSE floating point register set
1723 * - the virtual floating point registers
1724 * - the SSE vector register set
1726 static unsigned ia32_get_n_reg_class(const void *self) {
1732 * Return the register class for index i.
1734 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1738 assert(i < N_CLASSES);
1739 return &ia32_reg_classes[i];
1743 * Get the register class which shall be used to store a value of a given mode.
1744 * @param self The this pointer.
1745 * @param mode The mode in question.
1746 * @return A register class which can hold values of the given mode.
1748 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1749 const ir_mode *mode)
1753 if (mode_is_float(mode)) {
1754 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1757 return &ia32_reg_classes[CLASS_ia32_gp];
1761 * Get the ABI restrictions for procedure calls.
1762 * @param self The this pointer.
1763 * @param method_type The type of the method (procedure) in question.
1764 * @param abi The abi object to be modified
1766 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1773 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1776 /* set abi flags for calls */
1777 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1778 call_flags.bits.store_args_sequential = 0;
1779 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1780 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1781 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1783 /* set parameter passing style */
1784 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1786 if (get_method_variadicity(method_type) == variadicity_variadic) {
1787 /* pass all parameters of a variadic function on the stack */
1790 cc = get_method_calling_convention(method_type);
1791 if (get_method_additional_properties(method_type) & mtp_property_private
1792 && (ia32_cg_config.optimize_cc)) {
1793 /* set the calling conventions to register parameter */
1794 cc = (cc & ~cc_bits) | cc_reg_param;
1798 /* we have to pop the shadow parameter ourself for compound calls */
1799 if( (get_method_calling_convention(method_type) & cc_compound_ret)
1800 && !(cc & cc_reg_param)) {
1801 be_abi_call_set_pop(abi, get_mode_size_bytes(mode_P_data));
1804 n = get_method_n_params(method_type);
1805 for (i = regnum = 0; i < n; i++) {
1807 const arch_register_t *reg = NULL;
1809 tp = get_method_param_type(method_type, i);
1810 mode = get_type_mode(tp);
1812 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1815 be_abi_call_param_reg(abi, i, reg);
1818 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1819 * movl has a shorter opcode than mov[sz][bw]l */
1820 ir_mode *load_mode = mode;
1821 if (mode != NULL && get_mode_size_bytes(mode) < 4) load_mode = mode_Iu;
1822 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1826 /* set return registers */
1827 n = get_method_n_ress(method_type);
1829 assert(n <= 2 && "more than two results not supported");
1831 /* In case of 64bit returns, we will have two 32bit values */
1833 tp = get_method_res_type(method_type, 0);
1834 mode = get_type_mode(tp);
1836 assert(!mode_is_float(mode) && "two FP results not supported");
1838 tp = get_method_res_type(method_type, 1);
1839 mode = get_type_mode(tp);
1841 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1843 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1844 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1847 const arch_register_t *reg;
1849 tp = get_method_res_type(method_type, 0);
1850 assert(is_atomic_type(tp));
1851 mode = get_type_mode(tp);
1853 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1855 be_abi_call_res_reg(abi, 0, reg);
1860 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self,
1865 return &ia32_irn_ops;
1868 const arch_irn_handler_t ia32_irn_handler = {
1872 const arch_irn_handler_t *ia32_get_irn_handler(const void *self)
1875 return &ia32_irn_handler;
1878 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1882 if(!is_ia32_irn(irn)) {
1886 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1887 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1888 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1889 || is_ia32_Immediate(irn))
1896 * Initializes the code generator interface.
1898 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1901 return &ia32_code_gen_if;
1905 * Returns the estimated execution time of an ia32 irn.
1907 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1908 const arch_env_t *arch_env = env;
1909 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1912 list_sched_selector_t ia32_sched_selector;
1915 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1917 static const list_sched_selector_t *ia32_get_list_sched_selector(
1918 const void *self, list_sched_selector_t *selector)
1921 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1922 ia32_sched_selector.exectime = ia32_sched_exectime;
1923 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1924 return &ia32_sched_selector;
1927 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1934 * Returns the necessary byte alignment for storing a register of given class.
1936 static int ia32_get_reg_class_alignment(const void *self,
1937 const arch_register_class_t *cls)
1939 ir_mode *mode = arch_register_class_mode(cls);
1940 int bytes = get_mode_size_bytes(mode);
1943 if (mode_is_float(mode) && bytes > 8)
1948 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1949 const void *self, const ir_node *irn)
1951 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1952 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1953 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1956 static const be_execution_unit_t *_allowed_units_GP[] = {
1957 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1958 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1959 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1960 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1961 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1962 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1963 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1966 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1967 &be_machine_execution_units_DUMMY[0],
1970 static const be_execution_unit_t **_units_callret[] = {
1971 _allowed_units_BRANCH,
1974 static const be_execution_unit_t **_units_other[] = {
1978 static const be_execution_unit_t **_units_dummy[] = {
1979 _allowed_units_DUMMY,
1982 const be_execution_unit_t ***ret;
1985 if (is_ia32_irn(irn)) {
1986 ret = get_ia32_exec_units(irn);
1988 else if (is_be_node(irn)) {
1989 if (be_is_Call(irn) || be_is_Return(irn)) {
1990 ret = _units_callret;
1992 else if (be_is_Barrier(irn)) {
2007 * Return the abstract ia32 machine.
2009 static const be_machine_t *ia32_get_machine(const void *self) {
2010 const ia32_isa_t *isa = self;
2015 * Return irp irgs in the desired order.
2017 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2025 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2026 * @return 1 if allowed, 0 otherwise
2028 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2036 if(!ia32_cg_config.use_cmov) {
2037 /* TODO: we could still handle abs(x)... */
2041 /* we can't handle psis with 64bit compares yet */
2043 ir_node *pred = get_Proj_pred(sel);
2045 ir_node *left = get_Cmp_left(pred);
2046 ir_mode *cmp_mode = get_irn_mode(left);
2047 if(!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
2052 /* check the Phi nodes */
2053 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
2054 ir_mode *mode = get_irn_mode(phi);
2056 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2064 * Returns the libFirm configuration parameter for this backend.
2066 static const backend_params *ia32_get_libfirm_params(void) {
2067 static const ir_settings_if_conv_t ifconv = {
2068 4, /* maxdepth, doesn't matter for Psi-conversion */
2069 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2071 static const ir_settings_arch_dep_t ad = {
2072 1, /* also use subs */
2073 4, /* maximum shifts */
2074 31, /* maximum shift amount */
2075 ia32_evaluate_insn, /* evaluate the instruction sequence */
2077 1, /* allow Mulhs */
2078 1, /* allow Mulus */
2079 32 /* Mulh allowed up to 32 bit */
2081 static backend_params p = {
2082 1, /* need dword lowering */
2083 1, /* support inline assembly */
2084 NULL, /* no additional opcodes */
2085 NULL, /* will be set later */
2086 ia32_create_intrinsic_fkt,
2087 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2088 NULL, /* will be set below */
2091 ia32_setup_cg_config();
2094 p.if_conv_info = &ifconv;
2098 static const lc_opt_enum_int_items_t gas_items[] = {
2099 { "elf", GAS_FLAVOUR_ELF },
2100 { "mingw", GAS_FLAVOUR_MINGW },
2101 { "yasm", GAS_FLAVOUR_YASM },
2102 { "macho", GAS_FLAVOUR_MACH_O },
2106 static lc_opt_enum_int_var_t gas_var = {
2107 (int*) &be_gas_flavour, gas_items
2110 static const lc_opt_table_entry_t ia32_options[] = {
2111 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2115 const arch_isa_if_t ia32_isa_if = {
2118 ia32_get_n_reg_class,
2120 ia32_get_reg_class_for_mode,
2122 ia32_get_irn_handler,
2123 ia32_get_code_generator_if,
2124 ia32_get_list_sched_selector,
2125 ia32_get_ilp_sched_selector,
2126 ia32_get_reg_class_alignment,
2127 ia32_get_libfirm_params,
2128 ia32_get_allowed_execution_units,
2133 void ia32_init_emitter(void);
2134 void ia32_init_finish(void);
2135 void ia32_init_optimize(void);
2136 void ia32_init_transform(void);
2137 void ia32_init_x87(void);
2139 void be_init_arch_ia32(void)
2141 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2142 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2144 lc_opt_add_table(ia32_grp, ia32_options);
2145 be_register_isa_if("ia32", &ia32_isa_if);
2147 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2149 ia32_init_emitter();
2151 ia32_init_optimize();
2152 ia32_init_transform();
2154 ia32_init_architecture();
2157 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);