2 * This is the main ia32 firm backend driver.
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
24 #include "pseudo_irg.h"
28 #include "iredges_t.h"
36 #include "../beabi.h" /* the general register allocator interface */
37 #include "../benode_t.h"
38 #include "../belower.h"
39 #include "../besched_t.h"
41 #include "bearch_ia32_t.h"
43 #include "ia32_new_nodes.h" /* ia32 nodes interface */
44 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
45 #include "ia32_gen_decls.h" /* interface declaration emitter */
46 #include "ia32_transform.h"
47 #include "ia32_emitter.h"
48 #include "ia32_map_regs.h"
49 #include "ia32_optimize.h"
51 #include "ia32_dbg_stat.h"
53 #define DEBUG_MODULE "firm.be.ia32.isa"
56 static set *cur_reg_set = NULL;
59 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
61 /* Creates the unique per irg GP NoReg node. */
62 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
63 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
66 /* Creates the unique per irg FP NoReg node. */
67 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
68 return be_abi_get_callee_save_irn(cg->birg->abi,
69 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
72 /**************************************************
75 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
76 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
77 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
78 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
81 **************************************************/
83 static ir_node *my_skip_proj(const ir_node *n) {
91 * Return register requirements for an ia32 node.
92 * If the node returns a tuple (mode_T) then the proj's
93 * will be asked for this information.
95 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
96 const ia32_irn_ops_t *ops = self;
97 const ia32_register_req_t *irn_req;
98 long node_pos = pos == -1 ? 0 : pos;
99 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
100 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
102 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
103 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
107 if (mode == mode_T && pos < 0) {
108 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
112 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
116 node_pos = ia32_translate_proj_pos(irn);
122 irn = my_skip_proj(irn);
124 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
127 if (is_ia32_irn(irn)) {
129 irn_req = get_ia32_in_req(irn, pos);
132 irn_req = get_ia32_out_req(irn, node_pos);
135 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
137 memcpy(req, &(irn_req->req), sizeof(*req));
139 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
140 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
141 req->other_same = get_irn_n(irn, irn_req->same_pos);
144 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
145 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
146 req->other_different = get_irn_n(irn, irn_req->different_pos);
150 /* treat Phi like Const with default requirements */
152 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
153 if (mode_is_float(mode)) {
154 if (USE_SSE2(ops->cg))
155 memcpy(req, &(ia32_default_req_ia32_xmm.req), sizeof(*req));
157 memcpy(req, &(ia32_default_req_ia32_vfp.req), sizeof(*req));
159 else if (mode_is_int(mode) || mode_is_reference(mode))
160 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
161 else if (mode == mode_T || mode == mode_M) {
162 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
166 assert(0 && "unsupported Phi-Mode");
169 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
177 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
179 const ia32_irn_ops_t *ops = self;
181 if (get_irn_mode(irn) == mode_X) {
185 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
188 pos = ia32_translate_proj_pos(irn);
189 irn = my_skip_proj(irn);
192 if (is_ia32_irn(irn)) {
193 const arch_register_t **slots;
195 slots = get_ia32_slots(irn);
199 ia32_set_firm_reg(irn, reg, cur_reg_set);
203 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
205 const arch_register_t *reg = NULL;
209 if (get_irn_mode(irn) == mode_X) {
213 pos = ia32_translate_proj_pos(irn);
214 irn = my_skip_proj(irn);
217 if (is_ia32_irn(irn)) {
218 const arch_register_t **slots;
219 slots = get_ia32_slots(irn);
223 reg = ia32_get_firm_reg(irn, cur_reg_set);
229 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
230 irn = my_skip_proj(irn);
232 return arch_irn_class_branch;
233 else if (is_ia32_irn(irn))
234 return arch_irn_class_normal;
239 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
240 irn = my_skip_proj(irn);
241 if (is_ia32_irn(irn))
242 return get_ia32_flags(irn);
248 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
249 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
252 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
254 const ia32_irn_ops_t *ops = self;
256 if (get_ia32_frame_ent(irn)) {
257 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
259 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
260 snprintf(buf, sizeof(buf), "%d", bias);
262 if (get_ia32_op_type(irn) == ia32_Normal) {
263 set_ia32_cnst(irn, buf);
266 add_ia32_am_offs(irn, buf);
268 set_ia32_am_flavour(irn, am_flav);
274 be_abi_call_flags_bits_t flags;
275 const arch_isa_t *isa;
276 const arch_env_t *aenv;
280 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
282 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
283 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
284 env->flags = fl.bits;
287 env->isa = aenv->isa;
291 static void ia32_abi_dont_save_regs(void *self, pset *s)
293 ia32_abi_env_t *env = self;
294 if(env->flags.try_omit_fp)
295 pset_insert_ptr(s, env->isa->bp);
299 * Generate the prologue.
300 * @param self The callback object.
301 * @param mem A pointer to the mem node. Update this if you define new memory.
302 * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
303 * @return The register which shall be used as a stack frame base.
305 * All nodes which define registers in @p reg_map must keep @p reg_map current.
307 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
309 ia32_abi_env_t *env = self;
311 if (!env->flags.try_omit_fp) {
312 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
313 ir_node *bl = get_irg_start_block(env->irg);
314 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
315 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
316 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
320 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_expand);
321 store_bp = new_rd_ia32_Store(NULL, env->irg, bl, curr_sp, curr_no_reg, curr_bp, *mem, mode_T);
322 set_ia32_am_support(store_bp, ia32_am_Dest);
323 set_ia32_am_flavour(store_bp, ia32_B);
324 set_ia32_op_type(store_bp, ia32_AddrModeD);
325 set_ia32_ls_mode(store_bp, env->isa->bp->reg_class->mode);
326 *mem = new_r_Proj(env->irg, bl, store_bp, mode_M, 0);
328 /* move esp to ebp */
329 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
330 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
331 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
332 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
334 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
335 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
343 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
345 ia32_abi_env_t *env = self;
346 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
347 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
348 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
350 if (env->flags.try_omit_fp) {
351 /* simply remove the stack frame here */
352 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
357 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
358 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
360 /* copy ebp to esp */
361 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
364 load_bp = new_rd_ia32_Load(NULL, env->irg, bl, curr_sp, curr_no_reg, *mem, mode_T);
365 set_ia32_am_support(load_bp, ia32_am_Source);
366 set_ia32_am_flavour(load_bp, ia32_B);
367 set_ia32_op_type(load_bp, ia32_AddrModeS);
368 set_ia32_ls_mode(load_bp, mode_bp);
369 curr_bp = new_r_Proj(env->irg, bl, load_bp, mode_bp, 0);
370 *mem = new_r_Proj(env->irg, bl, load_bp, mode_M, 1);
371 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
373 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_shrink);
376 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
377 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
381 * Produces the type which sits between the stack args and the locals on the stack.
382 * it will contain the return address and space to store the old base pointer.
383 * @return The Firm type modeling the ABI between type.
385 static ir_type *ia32_abi_get_between_type(void *self)
387 static ir_type *omit_fp_between_type = NULL;
388 static ir_type *between_type = NULL;
390 ia32_abi_env_t *env = self;
394 entity *ret_addr_ent;
395 entity *omit_fp_ret_addr_ent;
397 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
398 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
400 between_type = new_type_class(new_id_from_str("ia32_between_type"));
401 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
402 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
404 set_entity_offset_bytes(old_bp_ent, 0);
405 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
406 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
408 omit_fp_between_type = new_type_class(new_id_from_str("ia32_between_type_omit_fp"));
409 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, new_id_from_str("ret_addr"), ret_addr_type);
411 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
412 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
415 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
418 static const be_abi_callbacks_t ia32_abi_callbacks = {
421 ia32_abi_get_between_type,
422 ia32_abi_dont_save_regs,
427 /* fill register allocator interface */
429 static const arch_irn_ops_if_t ia32_irn_ops_if = {
430 ia32_get_irn_reg_req,
435 ia32_get_frame_entity,
439 ia32_irn_ops_t ia32_irn_ops = {
446 /**************************************************
449 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
450 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
451 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
452 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
455 **************************************************/
458 * Transforms the standard firm graph into
461 static void ia32_prepare_graph(void *self) {
462 ia32_code_gen_t *cg = self;
463 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
465 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
466 ia32_register_transformers();
467 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
468 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
470 if (cg->opt & IA32_OPT_DOAM) {
471 edges_deactivate(cg->irg);
472 //dead_node_elimination(cg->irg);
473 edges_activate(cg->irg);
475 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
477 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
478 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
481 DEBUG_ONLY(cg->mod = old_mod;)
486 * Insert copies for all ia32 nodes where the should_be_same requirement
488 * Transform Sub into Neg -- Add if IN2 == OUT
490 static void ia32_finish_node(ir_node *irn, void *env) {
491 ia32_code_gen_t *cg = env;
492 const ia32_register_req_t **reqs;
493 const arch_register_t *out_reg, *in_reg, *in2_reg;
495 ir_node *copy, *in_node, *block, *in2_node;
496 ia32_op_type_t op_tp;
498 if (is_ia32_irn(irn)) {
499 /* AM Dest nodes don't produce any values */
500 op_tp = get_ia32_op_type(irn);
501 if (op_tp == ia32_AddrModeD)
504 reqs = get_ia32_out_req_all(irn);
505 n_res = get_ia32_n_res(irn);
506 block = get_nodes_block(irn);
508 /* check all OUT requirements, if there is a should_be_same */
509 if (op_tp == ia32_Normal && ! is_ia32_Lea(irn)) {
510 for (i = 0; i < n_res; i++) {
511 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
512 /* get in and out register */
513 out_reg = get_ia32_out_reg(irn, i);
514 in_node = get_irn_n(irn, reqs[i]->same_pos);
515 in_reg = arch_get_irn_register(cg->arch_env, in_node);
517 /* don't copy ignore nodes */
518 if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
521 /* check if in and out register are equal */
522 if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
523 /* in case of a commutative op: just exchange the in's */
524 /* beware: the current op could be everything, so test for ia32 */
525 /* commutativity first before getting the second in */
526 if (is_ia32_commutative(irn)) {
527 in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
528 in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
530 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
531 set_irn_n(irn, reqs[i]->same_pos, in2_node);
532 set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
539 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
540 /* create copy from in register */
541 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
543 DBG_OPT_2ADDRCPY(copy);
545 /* destination is the out register */
546 arch_set_irn_register(cg->arch_env, copy, out_reg);
548 /* insert copy before the node into the schedule */
549 sched_add_before(irn, copy);
552 set_irn_n(irn, reqs[i]->same_pos, copy);
559 /* If we have a CondJmp with immediate, we need to */
560 /* check if it's the right operand, otherwise we have */
561 /* to change it, as CMP doesn't support immediate as */
563 if (is_ia32_CondJmp(irn) && (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) && op_tp == ia32_AddrModeS) {
564 long pnc = get_negated_pnc(get_ia32_pncode(irn), get_ia32_res_mode(irn));
565 set_ia32_op_type(irn, ia32_AddrModeD);
566 set_ia32_pncode(irn, pnc);
569 /* check if there is a sub which need to be transformed */
570 ia32_transform_sub_to_neg_add(irn, cg);
572 /* transform a LEA into an Add if possible */
573 ia32_transform_lea_to_add(irn, cg);
577 /* check for peephole optimization */
578 ia32_peephole_optimization(irn, cg);
581 static void ia32_finish_irg_walker(ir_node *block, void *env) {
584 for (irn = sched_first(block); !sched_is_end(irn); irn = next) {
585 next = sched_next(irn);
586 ia32_finish_node(irn, env);
591 * Add Copy nodes for not fulfilled should_be_equal constraints
593 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
594 irg_block_walk_graph(irg, NULL, ia32_finish_irg_walker, cg);
600 * Dummy functions for hooks we don't need but which must be filled.
602 static void ia32_before_sched(void *self) {
606 * Called before the register allocator.
607 * Calculate a block schedule here. We need it for the x87
608 * simulator and the emitter.
610 static void ia32_before_ra(void *self) {
611 ia32_code_gen_t *cg = self;
613 cg->blk_sched = sched_create_block_schedule(cg->irg);
618 * Transforms a be node into a Load.
620 static void transform_to_Load(ia32_transform_env_t *env) {
621 ir_node *irn = env->irn;
622 entity *ent = be_get_frame_entity(irn);
623 ir_mode *mode = env->mode;
624 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
625 ir_node *nomem = new_rd_NoMem(env->irg);
626 ir_node *sched_point = NULL;
627 ir_node *ptr = get_irn_n(irn, 0);
628 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
629 ir_node *new_op, *proj;
630 const arch_register_t *reg;
632 if (sched_is_scheduled(irn)) {
633 sched_point = sched_prev(irn);
636 if (mode_is_float(mode)) {
637 if (USE_SSE2(env->cg))
638 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
640 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
643 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
646 set_ia32_am_support(new_op, ia32_am_Source);
647 set_ia32_op_type(new_op, ia32_AddrModeS);
648 set_ia32_am_flavour(new_op, ia32_B);
649 set_ia32_ls_mode(new_op, mode);
650 set_ia32_frame_ent(new_op, ent);
651 set_ia32_use_frame(new_op);
653 DBG_OPT_RELOAD2LD(irn, new_op);
655 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
658 sched_add_after(sched_point, new_op);
659 sched_add_after(new_op, proj);
664 /* copy the register from the old node to the new Load */
665 reg = arch_get_irn_register(env->cg->arch_env, irn);
666 arch_set_irn_register(env->cg->arch_env, new_op, reg);
668 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
674 * Transforms a be node into a Store.
676 static void transform_to_Store(ia32_transform_env_t *env) {
677 ir_node *irn = env->irn;
678 entity *ent = be_get_frame_entity(irn);
679 ir_mode *mode = env->mode;
680 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
681 ir_node *nomem = new_rd_NoMem(env->irg);
682 ir_node *ptr = get_irn_n(irn, 0);
683 ir_node *val = get_irn_n(irn, 1);
684 ir_node *new_op, *proj;
685 ir_node *sched_point = NULL;
687 if (sched_is_scheduled(irn)) {
688 sched_point = sched_prev(irn);
691 if (mode_is_float(mode)) {
692 if (USE_SSE2(env->cg))
693 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
695 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
697 else if (get_mode_size_bits(mode) == 8) {
698 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
701 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
704 set_ia32_am_support(new_op, ia32_am_Dest);
705 set_ia32_op_type(new_op, ia32_AddrModeD);
706 set_ia32_am_flavour(new_op, ia32_B);
707 set_ia32_ls_mode(new_op, mode);
708 set_ia32_frame_ent(new_op, ent);
709 set_ia32_use_frame(new_op);
711 DBG_OPT_SPILL2ST(irn, new_op);
713 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, 0);
716 sched_add_after(sched_point, new_op);
717 sched_add_after(new_op, proj);
722 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
728 * Fix the mode of Spill/Reload
730 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
732 if (mode_is_float(mode)) {
744 * Block-Walker: Calls the transform functions Spill and Reload.
746 static void ia32_after_ra_walker(ir_node *block, void *env) {
747 ir_node *node, *prev;
748 ia32_code_gen_t *cg = env;
749 ia32_transform_env_t tenv;
752 tenv.irg = current_ir_graph;
754 DEBUG_ONLY(tenv.mod = cg->mod;)
756 /* beware: the schedule is changed here */
757 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
758 prev = sched_prev(node);
759 if (be_is_Reload(node)) {
760 /* we always reload the whole register */
761 tenv.dbg = get_irn_dbg_info(node);
763 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
764 transform_to_Load(&tenv);
766 else if (be_is_Spill(node)) {
767 /* we always spill the whole register */
768 tenv.dbg = get_irn_dbg_info(node);
770 tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node)));
771 transform_to_Store(&tenv);
777 * We transform Spill and Reload here. This needs to be done before
778 * stack biasing otherwise we would miss the corrected offset for these nodes.
780 * If x87 instruction should be emitted, run the x87 simulator and patch
781 * the virtual instructions. This must obviously be done after register allocation.
783 static void ia32_after_ra(void *self) {
784 ia32_code_gen_t *cg = self;
785 irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self);
787 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
788 if (cg->used_fp == fp_x87) {
789 x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
795 * Emits the code, closes the output file and frees
796 * the code generator interface.
798 static void ia32_codegen(void *self) {
799 ia32_code_gen_t *cg = self;
800 ir_graph *irg = cg->irg;
802 ia32_finish_irg(irg, cg);
803 be_dump(irg, "-finished", dump_ir_block_graph_sched);
804 ia32_gen_routine(cg->isa->out, irg, cg);
808 /* remove it from the isa */
811 /* de-allocate code generator */
812 del_set(cg->reg_set);
817 static void *ia32_cg_init(const be_irg_t *birg);
819 static const arch_code_generator_if_t ia32_code_gen_if = {
821 NULL, /* before abi introduce hook */
823 ia32_before_sched, /* before scheduling hook */
824 ia32_before_ra, /* before register allocation hook */
825 ia32_after_ra, /* after register allocation hook */
826 ia32_codegen /* emit && done */
830 * Initializes a IA32 code generator.
832 static void *ia32_cg_init(const be_irg_t *birg) {
833 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
834 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
836 cg->impl = &ia32_code_gen_if;
838 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
839 cg->arch_env = birg->main_env->arch_env;
842 cg->blk_sched = NULL;
845 cg->fp_kind = isa->fp_kind;
846 cg->used_fp = fp_none;
848 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
850 /* copy optimizations from isa for easier access */
857 if (isa->name_obst_size) {
858 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
859 isa->name_obst_size = 0;
860 obstack_free(isa->name_obst, NULL);
861 obstack_init(isa->name_obst);
867 if (isa->num_codegens > 1)
872 cur_reg_set = cg->reg_set;
874 ia32_irn_ops.cg = cg;
876 return (arch_code_generator_t *)cg;
881 /*****************************************************************
882 * ____ _ _ _____ _____
883 * | _ \ | | | | |_ _|/ ____| /\
884 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
885 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
886 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
887 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
889 *****************************************************************/
892 * The template that generates a new ISA object.
893 * Note that this template can be changed by command line
896 static ia32_isa_t ia32_isa_template = {
897 &ia32_isa_if, /* isa interface implementation */
898 &ia32_gp_regs[REG_ESP], /* stack pointer register */
899 &ia32_gp_regs[REG_EBP], /* base pointer register */
900 -1, /* stack direction */
901 0, /* number of code generator objects so far */
902 NULL, /* 16bit register names */
903 NULL, /* 8bit register names */
907 IA32_OPT_DOAM | /* optimize address mode default: on */
908 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
909 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
910 IA32_OPT_EXTBB), /* use extended basic block scheduling, default: on */
911 arch_pentium_4, /* instruction architecture */
912 arch_pentium_4, /* optimize for architecture */
913 fp_sse2, /* use sse2 unit */
914 NULL, /* current code generator */
916 NULL, /* name obstack */
917 0 /* name obst size */
922 * Initializes the backend ISA.
924 static void *ia32_init(FILE *file_handle) {
925 static int inited = 0;
931 isa = xmalloc(sizeof(*isa));
932 memcpy(isa, &ia32_isa_template, sizeof(*isa));
934 ia32_register_init(isa);
935 ia32_create_opcodes();
936 ia32_register_copy_attr_func();
938 isa->regs_16bit = pmap_create();
939 isa->regs_8bit = pmap_create();
940 isa->types = pmap_create();
941 isa->tv_ent = pmap_create();
942 isa->out = file_handle;
944 ia32_build_16bit_reg_map(isa->regs_16bit);
945 ia32_build_8bit_reg_map(isa->regs_8bit);
947 /* patch register names of x87 registers */
949 ia32_st_regs[0].name = "st";
950 ia32_st_regs[1].name = "st(1)";
951 ia32_st_regs[2].name = "st(2)";
952 ia32_st_regs[3].name = "st(3)";
953 ia32_st_regs[4].name = "st(4)";
954 ia32_st_regs[5].name = "st(5)";
955 ia32_st_regs[6].name = "st(6)";
956 ia32_st_regs[7].name = "st(7)";
960 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
961 obstack_init(isa->name_obst);
962 isa->name_obst_size = 0;
965 fprintf(isa->out, "\t.intel_syntax\n");
975 * Closes the output file and frees the ISA structure.
977 static void ia32_done(void *self) {
978 ia32_isa_t *isa = self;
980 /* emit now all global declarations */
981 ia32_gen_decls(isa->out);
983 pmap_destroy(isa->regs_16bit);
984 pmap_destroy(isa->regs_8bit);
985 pmap_destroy(isa->tv_ent);
986 pmap_destroy(isa->types);
989 //printf("name obst size = %d bytes\n", isa->name_obst_size);
990 obstack_free(isa->name_obst, NULL);
998 * Return the number of register classes for this architecture.
999 * We report always these:
1000 * - the general purpose registers
1001 * - the floating point register set (depending on the unit used for FP)
1002 * - MMX/SSE registers (currently not supported)
1004 static int ia32_get_n_reg_class(const void *self) {
1009 * Return the register class for index i.
1011 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1012 const ia32_isa_t *isa = self;
1013 assert(i >= 0 && i < 2 && "Invalid ia32 register class requested.");
1015 return &ia32_reg_classes[CLASS_ia32_gp];
1016 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1020 * Get the register class which shall be used to store a value of a given mode.
1021 * @param self The this pointer.
1022 * @param mode The mode in question.
1023 * @return A register class which can hold values of the given mode.
1025 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1026 const ia32_isa_t *isa = self;
1027 if (mode_is_float(mode)) {
1028 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1031 return &ia32_reg_classes[CLASS_ia32_gp];
1035 * Get the ABI restrictions for procedure calls.
1036 * @param self The this pointer.
1037 * @param method_type The type of the method (procedure) in question.
1038 * @param abi The abi object to be modified
1040 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1041 const ia32_isa_t *isa = self;
1044 unsigned cc = get_method_calling_convention(method_type);
1045 int n = get_method_n_params(method_type);
1048 int i, ignore_1, ignore_2;
1050 const arch_register_t *reg;
1051 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1053 /* set abi flags for calls */
1054 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1055 call_flags.bits.store_args_sequential = 0; /* use stores instead of push */
1056 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1057 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1058 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1060 /* set stack parameter passing style */
1061 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1063 /* collect the mode for each type */
1064 modes = alloca(n * sizeof(modes[0]));
1066 for (i = 0; i < n; i++) {
1067 tp = get_method_param_type(method_type, i);
1068 modes[i] = get_type_mode(tp);
1071 /* set register parameters */
1072 if (cc & cc_reg_param) {
1073 /* determine the number of parameters passed via registers */
1074 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1076 /* loop over all parameters and set the register requirements */
1077 for (i = 0; i <= biggest_n; i++) {
1078 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1079 assert(reg && "kaputt");
1080 be_abi_call_param_reg(abi, i, reg);
1087 /* set stack parameters */
1088 for (i = stack_idx; i < n; i++) {
1089 be_abi_call_param_stack(abi, i, 1, 0, 0);
1093 /* set return registers */
1094 n = get_method_n_ress(method_type);
1096 assert(n <= 2 && "more than two results not supported");
1098 /* In case of 64bit returns, we will have two 32bit values */
1100 tp = get_method_res_type(method_type, 0);
1101 mode = get_type_mode(tp);
1103 assert(!mode_is_float(mode) && "two FP results not supported");
1105 tp = get_method_res_type(method_type, 1);
1106 mode = get_type_mode(tp);
1108 assert(!mode_is_float(mode) && "two FP results not supported");
1110 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1111 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1114 const arch_register_t *reg;
1116 tp = get_method_res_type(method_type, 0);
1117 assert(is_atomic_type(tp));
1118 mode = get_type_mode(tp);
1120 reg = mode_is_float(mode) ?
1121 (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
1122 &ia32_gp_regs[REG_EAX];
1124 be_abi_call_res_reg(abi, 0, reg);
1129 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1130 return &ia32_irn_ops;
1133 const arch_irn_handler_t ia32_irn_handler = {
1137 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1138 return &ia32_irn_handler;
1141 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1142 return is_ia32_irn(irn);
1146 * Initializes the code generator interface.
1148 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1149 return &ia32_code_gen_if;
1152 list_sched_selector_t ia32_sched_selector;
1155 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1157 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
1158 // memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1159 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
1160 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1161 return &ia32_sched_selector;
1165 * Returns the necessary byte alignment for storing a register of given class.
1167 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1168 ir_mode *mode = arch_register_class_mode(cls);
1169 int bytes = get_mode_size_bytes(mode);
1171 if (mode_is_float(mode) && bytes > 8)
1178 /* instruction set architectures. */
1179 static const lc_opt_enum_int_items_t arch_items[] = {
1180 { "386", arch_i386, },
1181 { "486", arch_i486, },
1182 { "pentium", arch_pentium, },
1183 { "586", arch_pentium, },
1184 { "pentiumpro", arch_pentium_pro, },
1185 { "686", arch_pentium_pro, },
1186 { "pentiummmx", arch_pentium_mmx, },
1187 { "pentium2", arch_pentium_2, },
1188 { "p2", arch_pentium_2, },
1189 { "pentium3", arch_pentium_3, },
1190 { "p3", arch_pentium_3, },
1191 { "pentium4", arch_pentium_4, },
1192 { "p4", arch_pentium_4, },
1193 { "pentiumm", arch_pentium_m, },
1194 { "pm", arch_pentium_m, },
1195 { "core", arch_core, },
1197 { "athlon", arch_athlon, },
1198 { "athlon64", arch_athlon_64, },
1199 { "opteron", arch_opteron, },
1203 static lc_opt_enum_int_var_t arch_var = {
1204 &ia32_isa_template.arch, arch_items
1207 static lc_opt_enum_int_var_t opt_arch_var = {
1208 &ia32_isa_template.opt_arch, arch_items
1211 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1213 { "sse2", fp_sse2 },
1217 static lc_opt_enum_int_var_t fp_unit_var = {
1218 &ia32_isa_template.fp_kind, fp_unit_items
1221 static const lc_opt_table_entry_t ia32_options[] = {
1222 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1223 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1224 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1225 LC_OPT_ENT_BIT("incdec", "optimize for inc/dec", &ia32_isa_template.opt, IA32_OPT_INCDEC),
1226 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1227 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1228 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1229 LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
1234 * Register command line options for the ia32 backend.
1238 * ia32-arch=arch create instruction for arch
1239 * ia32-opt=arch optimize for run on arch
1240 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1241 * ia32-incdec optimize for inc/dec
1242 * ia32-noaddrmode do not use address mode
1243 * ia32-noplacecnst do not place constants,
1244 * ia32-noimmop no operations with immediates
1245 * ia32-noextbb do not use extended basic block scheduling
1247 static void ia32_register_options(lc_opt_entry_t *ent)
1249 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1250 lc_opt_add_table(be_grp_ia32, ia32_options);
1252 #endif /* WITH_LIBCORE */
1254 const arch_isa_if_t ia32_isa_if = {
1257 ia32_get_n_reg_class,
1259 ia32_get_reg_class_for_mode,
1261 ia32_get_irn_handler,
1262 ia32_get_code_generator_if,
1263 ia32_get_list_sched_selector,
1264 ia32_get_reg_class_alignment,
1266 ia32_register_options