2 * This is the main ia32 firm backend driver.
17 #include "pseudo_irg.h"
21 #include "iredges_t.h"
28 #include "../beabi.h" /* the general register allocator interface */
29 #include "../benode_t.h"
30 #include "../belower.h"
31 #include "../besched_t.h"
33 #include "bearch_ia32_t.h"
35 #include "ia32_new_nodes.h" /* ia32 nodes interface */
36 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
37 #include "ia32_gen_decls.h" /* interface declaration emitter */
38 #include "ia32_transform.h"
39 #include "ia32_emitter.h"
40 #include "ia32_map_regs.h"
41 #include "ia32_optimize.h"
43 #define DEBUG_MODULE "firm.be.ia32.isa"
46 static set *cur_reg_set = NULL;
49 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
51 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
52 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_XXX]);
55 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
56 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_fp_regs[REG_XXXX]);
59 /**************************************************
62 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
63 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
64 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
65 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
68 **************************************************/
70 static ir_node *my_skip_proj(const ir_node *n) {
77 * Return register requirements for an ia32 node.
78 * If the node returns a tuple (mode_T) then the proj's
79 * will be asked for this information.
81 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
82 const ia32_register_req_t *irn_req;
83 long node_pos = pos == -1 ? 0 : pos;
84 ir_mode *mode = get_irn_mode(irn);
85 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
87 if (mode == mode_T || mode == mode_M) {
88 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
92 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
97 node_pos = ia32_translate_proj_pos(irn);
103 irn = my_skip_proj(irn);
105 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
108 if (is_ia32_irn(irn)) {
110 irn_req = get_ia32_in_req(irn, pos);
113 irn_req = get_ia32_out_req(irn, node_pos);
116 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
118 memcpy(req, &(irn_req->req), sizeof(*req));
120 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
121 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
122 req->other_same = get_irn_n(irn, irn_req->same_pos);
125 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
126 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
127 req->other_different = get_irn_n(irn, irn_req->different_pos);
131 /* treat Phi like Const with default requirements */
133 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
134 if (mode_is_float(mode))
135 memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req));
136 else if (mode_is_int(mode) || mode_is_reference(mode))
137 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
138 else if (mode == mode_T || mode == mode_M) {
139 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
143 assert(0 && "unsupported Phi-Mode");
146 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
154 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
156 const ia32_irn_ops_t *ops = self;
158 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
161 pos = ia32_translate_proj_pos(irn);
162 irn = my_skip_proj(irn);
165 if (is_ia32_irn(irn)) {
166 const arch_register_t **slots;
168 slots = get_ia32_slots(irn);
172 ia32_set_firm_reg(irn, reg, cur_reg_set);
176 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
178 const arch_register_t *reg = NULL;
181 pos = ia32_translate_proj_pos(irn);
182 irn = my_skip_proj(irn);
185 if (is_ia32_irn(irn)) {
186 const arch_register_t **slots;
187 slots = get_ia32_slots(irn);
191 reg = ia32_get_firm_reg(irn, cur_reg_set);
197 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
198 irn = my_skip_proj(irn);
200 return arch_irn_class_branch;
201 else if (is_ia32_irn(irn))
202 return arch_irn_class_normal;
207 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
208 irn = my_skip_proj(irn);
209 if (is_ia32_irn(irn))
210 return get_ia32_flags(irn);
216 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
217 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
220 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
222 const ia32_irn_ops_t *ops = self;
224 if (is_ia32_use_frame(irn) && bias != 0) {
225 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
227 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
228 snprintf(buf, sizeof(buf), "%d", bias);
229 add_ia32_am_offs(irn, buf);
231 set_ia32_am_flavour(irn, am_flav);
235 /* fill register allocator interface */
237 static const arch_irn_ops_if_t ia32_irn_ops_if = {
238 ia32_get_irn_reg_req,
243 ia32_get_frame_entity,
247 ia32_irn_ops_t ia32_irn_ops = {
254 /**************************************************
257 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
258 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
259 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
260 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
263 **************************************************/
266 * Transforms the standard firm graph into
269 static void ia32_prepare_graph(void *self) {
270 ia32_code_gen_t *cg = self;
271 firm_dbg_module_t *old_mod = cg->mod;
273 cg->mod = firm_dbg_register("firm.be.ia32.transform");
274 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
275 dump_ir_block_graph_sched(cg->irg, "-transformed");
280 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
281 dump_ir_block_graph_sched(cg->irg, "-am");
287 * Insert copies for all ia32 nodes where the should_be_same requirement
290 static void ia32_finish_irg_walker(ir_node *irn, void *env) {
291 ia32_code_gen_t *cg = env;
292 const ia32_register_req_t **reqs;
293 const arch_register_t *out_reg, *in_reg;
295 ir_node *copy, *in_node, *block;
297 if (! is_ia32_irn(irn))
300 /* nodes with destination address mode don't produce values */
301 if (get_ia32_op_type(irn) == ia32_AddrModeD)
304 reqs = get_ia32_out_req_all(irn);
305 n_res = get_ia32_n_res(irn);
306 block = get_nodes_block(irn);
308 /* check all OUT requirements, if there is a should_be_same */
309 for (i = 0; i < n_res; i++) {
310 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
311 /* get in and out register */
312 out_reg = get_ia32_out_reg(irn, i);
313 in_node = get_irn_n(irn, reqs[i]->same_pos);
314 in_reg = arch_get_irn_register(cg->arch_env, in_node);
316 /* check if in and out register are equal */
317 if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
318 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
320 /* create copy from in register */
321 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
323 /* destination is the out register */
324 arch_set_irn_register(cg->arch_env, copy, out_reg);
326 /* insert copy before the node into the schedule */
327 sched_add_before(irn, copy);
330 set_irn_n(irn, reqs[i]->same_pos, copy);
337 * Add Copy nodes for not fulfilled should_be_equal constraints
339 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
340 irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
346 * Dummy functions for hooks we don't need but which must be filled.
348 static void ia32_before_sched(void *self) {
351 static void ia32_before_ra(void *self) {
357 * Transforms a be node into a Load.
359 static void transform_to_Load(ia32_transform_env_t *env) {
360 ir_node *irn = env->irn;
361 entity *ent = be_get_frame_entity(irn);
362 ir_mode *mode = env->mode;
363 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
364 ir_node *nomem = new_rd_NoMem(env->irg);
365 ir_node *sched_point = NULL;
366 ir_node *ptr = get_irn_n(irn, 0);
367 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
368 ir_node *new_op, *proj;
369 const arch_register_t *reg;
371 if (sched_is_scheduled(irn)) {
372 sched_point = sched_prev(irn);
375 if (mode_is_float(mode)) {
376 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
379 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
382 set_ia32_am_support(new_op, ia32_am_Source);
383 set_ia32_op_type(new_op, ia32_AddrModeS);
384 set_ia32_am_flavour(new_op, ia32_B);
385 set_ia32_ls_mode(new_op, mode);
386 set_ia32_frame_ent(new_op, ent);
387 set_ia32_use_frame(new_op);
389 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
392 sched_add_after(sched_point, new_op);
393 sched_add_after(new_op, proj);
398 /* copy the register from the old node to the new Load */
399 reg = arch_get_irn_register(env->cg->arch_env, irn);
400 arch_set_irn_register(env->cg->arch_env, new_op, reg);
407 * Transforms a be node into a Store.
409 static void transform_to_Store(ia32_transform_env_t *env) {
410 ir_node *irn = env->irn;
411 entity *ent = be_get_frame_entity(irn);
412 ir_mode *mode = env->mode;
413 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
414 ir_node *nomem = new_rd_NoMem(env->irg);
415 ir_node *ptr = get_irn_n(irn, 0);
416 ir_node *val = get_irn_n(irn, 1);
417 ir_node *new_op, *proj;
418 ir_node *sched_point = NULL;
420 if (sched_is_scheduled(irn)) {
421 sched_point = sched_prev(irn);
424 if (mode_is_float(mode)) {
425 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
428 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
431 set_ia32_am_support(new_op, ia32_am_Dest);
432 set_ia32_op_type(new_op, ia32_AddrModeD);
433 set_ia32_am_flavour(new_op, ia32_B);
434 set_ia32_ls_mode(new_op, get_irn_mode(val));
435 set_ia32_frame_ent(new_op, ent);
436 set_ia32_use_frame(new_op);
438 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
441 sched_add_after(sched_point, new_op);
442 sched_add_after(new_op, proj);
452 * Calls the transform functions for StackParam, Spill and Reload.
454 static void ia32_after_ra_walker(ir_node *node, void *env) {
455 ia32_code_gen_t *cg = env;
456 ia32_transform_env_t tenv;
461 tenv.block = get_nodes_block(node);
462 tenv.dbg = get_irn_dbg_info(node);
463 tenv.irg = current_ir_graph;
466 tenv.mode = get_irn_mode(node);
469 if (be_is_StackParam(node) || be_is_Reload(node)) {
470 transform_to_Load(&tenv);
472 else if (be_is_Spill(node)) {
473 transform_to_Store(&tenv);
478 * We transform StackParam, Spill and Reload here. This needs to be done before
479 * stack biasing otherwise we would miss the corrected offset for these nodes.
481 static void ia32_after_ra(void *self) {
482 ia32_code_gen_t *cg = self;
483 irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
488 * Emits the code, closes the output file and frees
489 * the code generator interface.
491 static void ia32_codegen(void *self) {
492 ia32_code_gen_t *cg = self;
493 ir_graph *irg = cg->irg;
496 if (cg->emit_decls) {
497 ia32_gen_decls(cg->out);
501 ia32_finish_irg(irg, cg);
502 dump_ir_block_graph_sched(irg, "-finished");
503 ia32_gen_routine(out, irg, cg);
507 pmap_destroy(cg->tv_ent);
508 pmap_destroy(cg->types);
510 /* de-allocate code generator */
511 del_set(cg->reg_set);
515 static void *ia32_cg_init(FILE *F, const be_irg_t *birg);
517 static const arch_code_generator_if_t ia32_code_gen_if = {
519 NULL, /* before abi introduce hook */
521 ia32_before_sched, /* before scheduling hook */
522 ia32_before_ra, /* before register allocation hook */
523 ia32_after_ra, /* after register allocation hook */
524 ia32_codegen /* emit && done */
528 * Initializes the code generator.
530 static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
531 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
532 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
534 cg->impl = &ia32_code_gen_if;
536 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
537 cg->mod = firm_dbg_register("firm.be.ia32.cg");
539 cg->arch_env = birg->main_env->arch_env;
540 cg->types = pmap_create();
541 cg->tv_ent = pmap_create();
544 /* set optimizations */
547 cg->opt.placecnst = 1;
551 if (isa->name_obst_size) {
552 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
553 isa->name_obst_size = 0;
554 obstack_free(isa->name_obst, NULL);
555 obstack_init(isa->name_obst);
561 if (isa->num_codegens > 1)
566 cur_reg_set = cg->reg_set;
568 ia32_irn_ops.cg = cg;
570 return (arch_code_generator_t *)cg;
575 /*****************************************************************
576 * ____ _ _ _____ _____
577 * | _ \ | | | | |_ _|/ ____| /\
578 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
579 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
580 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
581 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
583 *****************************************************************/
585 static ia32_isa_t ia32_isa_template = {
586 &ia32_isa_if, /* isa interface implementation */
587 &ia32_gp_regs[REG_ESP], /* stack pointer register */
588 &ia32_gp_regs[REG_EBP], /* base pointer register */
589 -1, /* stack direction */
590 0, /* number of code generator objects so far */
591 NULL /* name obstack */
595 * Initializes the backend ISA.
597 static void *ia32_init(void) {
598 static int inited = 0;
604 isa = xcalloc(1, sizeof(*isa));
605 memcpy(isa, &ia32_isa_template, sizeof(*isa));
607 ia32_register_init(isa);
608 ia32_create_opcodes();
611 isa->name_obst = xcalloc(1, sizeof(*(isa->name_obst)));
612 obstack_init(isa->name_obst);
613 isa->name_obst_size = 0;
624 * Closes the output file and frees the ISA structure.
626 static void ia32_done(void *self) {
627 ia32_isa_t *isa = self;
630 //printf("name obst size = %d bytes\n", isa->name_obst_size);
631 obstack_free(isa->name_obst, NULL);
639 static int ia32_get_n_reg_class(const void *self) {
643 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
644 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
645 return &ia32_reg_classes[i];
649 * Get the register class which shall be used to store a value of a given mode.
650 * @param self The this pointer.
651 * @param mode The mode in question.
652 * @return A register class which can hold values of the given mode.
654 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
655 if (mode_is_float(mode))
656 return &ia32_reg_classes[CLASS_ia32_fp];
658 return &ia32_reg_classes[CLASS_ia32_gp];
662 * Produces the type which sits between the stack args and the locals on the stack.
663 * it will contain the return address and space to store the old base pointer.
664 * @return The Firm type modeling the ABI between type.
666 static ir_type *get_between_type(void)
668 static ir_type *between_type = NULL;
669 static entity *old_bp_ent = NULL;
672 entity *ret_addr_ent;
673 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
674 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
676 between_type = new_type_class(new_id_from_str("ia32_between_type"));
677 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
678 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
680 set_entity_offset_bytes(old_bp_ent, 0);
681 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
682 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
689 * Get the ABI restrictions for procedure calls.
690 * @param self The this pointer.
691 * @param method_type The type of the method (procedure) in question.
692 * @param abi The abi object to be modified
694 void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
695 ir_type *between_type;
698 unsigned cc = get_method_calling_convention(method_type);
699 int n = get_method_n_params(method_type);
704 const arch_register_t *reg;
705 be_abi_call_flags_t call_flags;
707 /* set abi flags for calls */
708 call_flags.bits.left_to_right = 0;
709 call_flags.bits.store_args_sequential = 0;
710 call_flags.bits.try_omit_fp = 1;
711 call_flags.bits.fp_free = 0;
712 call_flags.bits.call_has_imm = 1;
714 /* get the between type and the frame pointer save entity */
715 between_type = get_between_type();
717 /* set stack parameter passing style */
718 be_abi_call_set_flags(abi, call_flags, between_type);
720 /* collect the mode for each type */
721 modes = alloca(n * sizeof(modes[0]));
723 for (i = 0; i < n; i++) {
724 tp = get_method_param_type(method_type, i);
725 modes[i] = get_type_mode(tp);
728 /* set register parameters */
729 if (cc & cc_reg_param) {
730 /* determine the number of parameters passed via registers */
731 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore, &ignore);
733 /* loop over all parameters and set the register requirements */
734 for (i = 0; i <= biggest_n; i++) {
735 reg = ia32_get_RegParam_reg(n, modes, i, cc);
736 assert(reg && "kaputt");
737 be_abi_call_param_reg(abi, i, reg);
744 /* set stack parameters */
745 for (i = stack_idx; i < n; i++) {
746 be_abi_call_param_stack(abi, i);
750 /* set return registers */
751 n = get_method_n_ress(method_type);
753 assert(n <= 2 && "more than two results not supported");
755 /* In case of 64bit returns, we will have two 32bit values */
757 tp = get_method_res_type(method_type, 0);
758 mode = get_type_mode(tp);
760 assert(!mode_is_float(mode) && "two FP results not supported");
762 tp = get_method_res_type(method_type, 1);
763 mode = get_type_mode(tp);
765 assert(!mode_is_float(mode) && "two FP results not supported");
767 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
768 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
771 tp = get_method_res_type(method_type, 0);
772 assert(is_atomic_type(tp));
773 mode = get_type_mode(tp);
775 be_abi_call_res_reg(abi, 0, mode_is_float(mode) ? &ia32_fp_regs[REG_XMM0] : &ia32_gp_regs[REG_EAX]);
780 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
781 return &ia32_irn_ops;
784 const arch_irn_handler_t ia32_irn_handler = {
788 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
789 return &ia32_irn_handler;
792 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
793 return is_ia32_irn(irn);
797 * Initializes the code generator interface.
799 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
800 return &ia32_code_gen_if;
803 list_sched_selector_t ia32_sched_selector;
806 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
808 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
809 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
810 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
811 return &ia32_sched_selector;
815 static void ia32_register_options(lc_opt_entry_t *ent)
818 #endif /* WITH_LIBCORE */
820 const arch_isa_if_t ia32_isa_if = {
822 ia32_register_options,
826 ia32_get_n_reg_class,
828 ia32_get_reg_class_for_mode,
830 ia32_get_irn_handler,
831 ia32_get_code_generator_if,
832 ia32_get_list_sched_selector