2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
55 #include "lower_calls.h"
56 #include "lower_softfloat.h"
60 #include "../benode.h"
61 #include "../belower.h"
62 #include "../besched.h"
65 #include "../beirgmod.h"
66 #include "../be_dbgout.h"
67 #include "../beblocksched.h"
68 #include "../bemachine.h"
69 #include "../bespillutil.h"
70 #include "../bespillslots.h"
71 #include "../bemodule.h"
72 #include "../begnuas.h"
73 #include "../bestate.h"
74 #include "../beflags.h"
75 #include "../betranshlp.h"
76 #include "../belistsched.h"
77 #include "../beabihelper.h"
78 #include "../bestack.h"
80 #include "bearch_ia32_t.h"
82 #include "ia32_new_nodes.h"
83 #include "gen_ia32_regalloc_if.h"
84 #include "gen_ia32_machine.h"
85 #include "ia32_common_transform.h"
86 #include "ia32_transform.h"
87 #include "ia32_emitter.h"
88 #include "ia32_optimize.h"
90 #include "ia32_dbg_stat.h"
91 #include "ia32_finish.h"
93 #include "ia32_architecture.h"
96 #include "ia32_pbqp_transform.h"
98 transformer_t be_transformer = TRANSFORMER_DEFAULT;
101 ir_mode *ia32_mode_fpcw = NULL;
103 /** The current omit-fp state */
104 static ir_type *omit_fp_between_type = NULL;
105 static ir_type *between_type = NULL;
106 static ir_entity *old_bp_ent = NULL;
107 static ir_entity *ret_addr_ent = NULL;
108 static ir_entity *omit_fp_ret_addr_ent = NULL;
111 * The environment for the intrinsic mapping.
113 static ia32_intrinsic_env_t intrinsic_env = {
115 NULL, /* the irg, these entities belong to */
116 NULL, /* entity for __divdi3 library call */
117 NULL, /* entity for __moddi3 library call */
118 NULL, /* entity for __udivdi3 library call */
119 NULL, /* entity for __umoddi3 library call */
123 typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
126 * Used to create per-graph unique pseudo nodes.
128 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
129 create_const_node_func func,
130 const arch_register_t* reg)
132 ir_node *block, *res;
137 block = get_irg_start_block(irg);
138 res = func(NULL, block);
139 arch_set_irn_register(res, reg);
145 /* Creates the unique per irg GP NoReg node. */
146 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
148 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
149 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
150 &ia32_registers[REG_GP_NOREG]);
153 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
155 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
156 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
157 &ia32_registers[REG_VFP_NOREG]);
160 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
162 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
163 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
164 &ia32_registers[REG_XMM_NOREG]);
167 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
169 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
170 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
171 &ia32_registers[REG_FPCW]);
176 * Returns the admissible noreg register node for input register pos of node irn.
178 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
180 ir_graph *irg = get_irn_irg(irn);
181 const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
183 assert(req != NULL && "Missing register requirements");
184 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
185 return ia32_new_NoReg_gp(irg);
187 if (ia32_cg_config.use_sse2) {
188 return ia32_new_NoReg_xmm(irg);
190 return ia32_new_NoReg_vfp(irg);
194 static arch_irn_class_t ia32_classify(const ir_node *irn)
196 arch_irn_class_t classification = arch_irn_class_none;
198 assert(is_ia32_irn(irn));
200 if (is_ia32_is_reload(irn))
201 classification |= arch_irn_class_reload;
203 if (is_ia32_is_spill(irn))
204 classification |= arch_irn_class_spill;
206 if (is_ia32_is_remat(irn))
207 classification |= arch_irn_class_remat;
209 return classification;
213 * The IA32 ABI callback object.
216 be_abi_call_flags_bits_t flags; /**< The call flags. */
217 ir_graph *irg; /**< The associated graph. */
220 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
222 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
225 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
227 if (is_be_node(node))
228 be_node_set_frame_entity(node, entity);
230 set_ia32_frame_ent(node, entity);
233 static void ia32_set_frame_offset(ir_node *irn, int bias)
235 if (get_ia32_frame_ent(irn) == NULL)
238 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
239 ir_graph *irg = get_irn_irg(irn);
240 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
241 if (layout->sp_relative) {
242 /* Pop nodes modify the stack pointer before calculating the
243 * destination address, so fix this here
248 add_ia32_am_offs_int(irn, bias);
251 static int ia32_get_sp_bias(const ir_node *node)
253 if (is_ia32_Call(node))
254 return -(int)get_ia32_call_attr_const(node)->pop;
256 if (is_ia32_Push(node))
259 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
262 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
263 return SP_BIAS_RESET;
270 * Build the between type and entities if not already build.
272 static void ia32_build_between_type(void)
274 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
275 if (! between_type) {
276 ir_type *old_bp_type = new_type_primitive(mode_Iu);
277 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
279 between_type = new_type_struct(IDENT("ia32_between_type"));
280 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
281 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
283 set_entity_offset(old_bp_ent, 0);
284 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
285 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
286 set_type_state(between_type, layout_fixed);
288 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
289 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
291 set_entity_offset(omit_fp_ret_addr_ent, 0);
292 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
293 set_type_state(omit_fp_between_type, layout_fixed);
299 * Produces the type which sits between the stack args and the locals on the stack.
300 * it will contain the return address and space to store the old base pointer.
301 * @return The Firm type modeling the ABI between type.
303 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
305 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
306 ia32_build_between_type();
307 return layout->sp_relative ? omit_fp_between_type : between_type;
311 * Return the stack entity that contains the return address.
313 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
315 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
316 ia32_build_between_type();
317 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
321 * Return the stack entity that contains the frame address.
323 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
325 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
326 ia32_build_between_type();
327 return layout->sp_relative ? NULL : old_bp_ent;
331 * Get the estimated cycle count for @p irn.
333 * @param self The this pointer.
334 * @param irn The node.
336 * @return The estimated cycle count for this operation
338 static int ia32_get_op_estimated_cost(const ir_node *irn)
341 ia32_op_type_t op_tp;
345 if (!is_ia32_irn(irn))
348 assert(is_ia32_irn(irn));
350 cost = get_ia32_latency(irn);
351 op_tp = get_ia32_op_type(irn);
353 if (is_ia32_CopyB(irn)) {
356 else if (is_ia32_CopyB_i(irn)) {
357 int size = get_ia32_copyb_size(irn);
358 cost = 20 + (int)ceil((4/3) * size);
360 /* in case of address mode operations add additional cycles */
361 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
363 In case of stack access and access to fixed addresses add 5 cycles
364 (we assume they are in cache), other memory operations cost 20
367 if (is_ia32_use_frame(irn) || (
368 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
369 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
381 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
383 * @param irn The original operation
384 * @param i Index of the argument we want the inverse operation to yield
385 * @param inverse struct to be filled with the resulting inverse op
386 * @param obstack The obstack to use for allocation of the returned nodes array
387 * @return The inverse operation or NULL if operation invertible
389 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
400 ir_node *block, *noreg, *nomem;
403 /* we cannot invert non-ia32 irns */
404 if (! is_ia32_irn(irn))
407 /* operand must always be a real operand (not base, index or mem) */
408 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
411 /* we don't invert address mode operations */
412 if (get_ia32_op_type(irn) != ia32_Normal)
415 /* TODO: adjust for new immediates... */
416 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
420 block = get_nodes_block(irn);
421 mode = get_irn_mode(irn);
422 irn_mode = get_irn_mode(irn);
423 noreg = get_irn_n(irn, 0);
424 nomem = get_irg_no_mem(irg);
425 dbgi = get_irn_dbg_info(irn);
427 /* initialize structure */
428 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
432 switch (get_ia32_irn_opcode(irn)) {
434 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
435 /* we have an add with a const here */
436 /* invers == add with negated const */
437 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
439 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
440 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
441 set_ia32_commutative(inverse->nodes[0]);
443 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
444 /* we have an add with a symconst here */
445 /* invers == sub with const */
446 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
448 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
451 /* normal add: inverse == sub */
452 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
457 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
458 /* we have a sub with a const/symconst here */
459 /* invers == add with this const */
460 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
461 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
462 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
466 if (i == n_ia32_binary_left) {
467 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
470 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
476 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
477 /* xor with const: inverse = xor */
478 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
479 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
480 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
484 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
489 inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
494 inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
499 /* inverse operation not supported */
507 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
509 if (mode_is_float(mode))
516 * Get the mode that should be used for spilling value node
518 static ir_mode *get_spill_mode(const ir_node *node)
520 ir_mode *mode = get_irn_mode(node);
521 return get_spill_mode_mode(mode);
525 * Checks whether an addressmode reload for a node with mode mode is compatible
526 * with a spillslot of mode spill_mode
528 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
530 return !mode_is_float(mode) || mode == spillmode;
534 * Check if irn can load its operand at position i from memory (source addressmode).
535 * @param irn The irn to be checked
536 * @param i The operands position
537 * @return Non-Zero if operand can be loaded
539 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
541 ir_node *op = get_irn_n(irn, i);
542 const ir_mode *mode = get_irn_mode(op);
543 const ir_mode *spillmode = get_spill_mode(op);
545 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
546 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
547 !ia32_is_spillmode_compatible(mode, spillmode) ||
548 is_ia32_use_frame(irn)) /* must not already use frame */
551 switch (get_ia32_am_support(irn)) {
556 if (i != n_ia32_unary_op)
562 case n_ia32_binary_left: {
563 const arch_register_req_t *req;
564 if (!is_ia32_commutative(irn))
567 /* we can't swap left/right for limited registers
568 * (As this (currently) breaks constraint handling copies)
570 req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
571 if (req->type & arch_register_req_type_limited)
576 case n_ia32_binary_right:
585 panic("Unknown AM type");
588 /* HACK: must not already use "real" memory.
589 * This can happen for Call and Div */
590 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
596 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
600 ir_mode *dest_op_mode;
602 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
604 set_ia32_op_type(irn, ia32_AddrModeS);
606 load_mode = get_irn_mode(get_irn_n(irn, i));
607 dest_op_mode = get_ia32_ls_mode(irn);
608 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
609 set_ia32_ls_mode(irn, load_mode);
611 set_ia32_use_frame(irn);
612 set_ia32_need_stackent(irn);
614 if (i == n_ia32_binary_left &&
615 get_ia32_am_support(irn) == ia32_am_binary &&
616 /* immediates are only allowed on the right side */
617 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
618 ia32_swap_left_right(irn);
619 i = n_ia32_binary_right;
622 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
624 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
625 set_irn_n(irn, n_ia32_mem, spill);
626 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
627 set_ia32_is_reload(irn);
630 static const be_abi_callbacks_t ia32_abi_callbacks = {
631 ia32_abi_get_between_type,
634 /* register allocator interface */
635 static const arch_irn_ops_t ia32_irn_ops = {
637 ia32_get_frame_entity,
638 ia32_set_frame_offset,
641 ia32_get_op_estimated_cost,
642 ia32_possible_memory_operand,
643 ia32_perform_memory_operand,
646 static ir_entity *mcount = NULL;
647 static int gprof = 0;
649 static void ia32_before_abi(ir_graph *irg)
652 if (mcount == NULL) {
653 ir_type *tp = new_type_method(0, 0);
654 ident *id = new_id_from_str("mcount");
655 mcount = new_entity(get_glob_type(), id, tp);
656 /* FIXME: enter the right ld_ident here */
657 set_entity_ld_ident(mcount, get_entity_ident(mcount));
658 set_entity_visibility(mcount, ir_visibility_external);
660 instrument_initcall(irg, mcount);
665 * Transforms the standard firm graph into
668 static void ia32_prepare_graph(ir_graph *irg)
670 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
673 switch (be_transformer) {
674 case TRANSFORMER_DEFAULT:
675 /* transform remaining nodes into assembler instructions */
676 ia32_transform_graph(irg);
679 case TRANSFORMER_PBQP:
680 case TRANSFORMER_RAND:
681 /* transform nodes into assembler instructions by PBQP magic */
682 ia32_transform_graph_by_pbqp(irg);
686 panic("invalid transformer");
689 ia32_transform_graph(irg);
692 /* do local optimizations (mainly CSE) */
693 optimize_graph_df(irg);
696 dump_ir_graph(irg, "transformed");
698 /* optimize address mode */
699 ia32_optimize_graph(irg);
701 /* do code placement, to optimize the position of constants */
705 dump_ir_graph(irg, "place");
708 ir_node *ia32_turn_back_am(ir_node *node)
710 dbg_info *dbgi = get_irn_dbg_info(node);
711 ir_graph *irg = get_irn_irg(node);
712 ir_node *block = get_nodes_block(node);
713 ir_node *base = get_irn_n(node, n_ia32_base);
714 ir_node *idx = get_irn_n(node, n_ia32_index);
715 ir_node *mem = get_irn_n(node, n_ia32_mem);
718 ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
719 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
721 ia32_copy_am_attrs(load, node);
722 if (is_ia32_is_reload(node))
723 set_ia32_is_reload(load);
724 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
726 switch (get_ia32_am_support(node)) {
728 set_irn_n(node, n_ia32_unary_op, load_res);
732 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
733 set_irn_n(node, n_ia32_binary_left, load_res);
735 set_irn_n(node, n_ia32_binary_right, load_res);
740 panic("Unknown AM type");
742 noreg = ia32_new_NoReg_gp(current_ir_graph);
743 set_irn_n(node, n_ia32_base, noreg);
744 set_irn_n(node, n_ia32_index, noreg);
745 set_ia32_am_offs_int(node, 0);
746 set_ia32_am_sc(node, NULL);
747 set_ia32_am_scale(node, 0);
748 clear_ia32_am_sc_sign(node);
750 /* rewire mem-proj */
751 if (get_irn_mode(node) == mode_T) {
752 const ir_edge_t *edge;
753 foreach_out_edge(node, edge) {
754 ir_node *out = get_edge_src_irn(edge);
755 if (get_irn_mode(out) == mode_M) {
756 set_Proj_pred(out, load);
757 set_Proj_proj(out, pn_ia32_Load_M);
763 set_ia32_op_type(node, ia32_Normal);
764 if (sched_is_scheduled(node))
765 sched_add_before(node, load);
770 static ir_node *flags_remat(ir_node *node, ir_node *after)
772 /* we should turn back source address mode when rematerializing nodes */
777 if (is_Block(after)) {
780 block = get_nodes_block(after);
783 type = get_ia32_op_type(node);
786 ia32_turn_back_am(node);
790 /* TODO implement this later... */
791 panic("found DestAM with flag user %+F this should not happen", node);
793 default: assert(type == ia32_Normal); break;
796 copy = exact_copy(node);
797 set_nodes_block(copy, block);
798 sched_add_after(after, copy);
804 * Called before the register allocator.
806 static void ia32_before_ra(ir_graph *irg)
808 /* setup fpu rounding modes */
809 ia32_setup_fpu_mode(irg);
812 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
815 be_add_missing_keeps(irg);
820 * Transforms a be_Reload into a ia32 Load.
822 static void transform_to_Load(ir_node *node)
824 ir_graph *irg = get_irn_irg(node);
825 dbg_info *dbgi = get_irn_dbg_info(node);
826 ir_node *block = get_nodes_block(node);
827 ir_entity *ent = be_get_frame_entity(node);
828 ir_mode *mode = get_irn_mode(node);
829 ir_mode *spillmode = get_spill_mode(node);
830 ir_node *noreg = ia32_new_NoReg_gp(irg);
831 ir_node *sched_point = NULL;
832 ir_node *ptr = get_irg_frame(irg);
833 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
834 ir_node *new_op, *proj;
835 const arch_register_t *reg;
837 if (sched_is_scheduled(node)) {
838 sched_point = sched_prev(node);
841 if (mode_is_float(spillmode)) {
842 if (ia32_cg_config.use_sse2)
843 new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
845 new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
847 else if (get_mode_size_bits(spillmode) == 128) {
848 /* Reload 128 bit SSE registers */
849 new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
852 new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
854 set_ia32_op_type(new_op, ia32_AddrModeS);
855 set_ia32_ls_mode(new_op, spillmode);
856 set_ia32_frame_ent(new_op, ent);
857 set_ia32_use_frame(new_op);
858 set_ia32_is_reload(new_op);
860 DBG_OPT_RELOAD2LD(node, new_op);
862 proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
865 sched_add_after(sched_point, new_op);
869 /* copy the register from the old node to the new Load */
870 reg = arch_get_irn_register(node);
871 arch_set_irn_register(proj, reg);
873 SET_IA32_ORIG_NODE(new_op, node);
875 exchange(node, proj);
879 * Transforms a be_Spill node into a ia32 Store.
881 static void transform_to_Store(ir_node *node)
883 ir_graph *irg = get_irn_irg(node);
884 dbg_info *dbgi = get_irn_dbg_info(node);
885 ir_node *block = get_nodes_block(node);
886 ir_entity *ent = be_get_frame_entity(node);
887 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
888 ir_mode *mode = get_spill_mode(spillval);
889 ir_node *noreg = ia32_new_NoReg_gp(irg);
890 ir_node *nomem = get_irg_no_mem(irg);
891 ir_node *ptr = get_irg_frame(irg);
892 ir_node *val = get_irn_n(node, n_be_Spill_val);
895 ir_node *sched_point = NULL;
897 if (sched_is_scheduled(node)) {
898 sched_point = sched_prev(node);
901 if (mode_is_float(mode)) {
902 if (ia32_cg_config.use_sse2) {
903 store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
904 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
906 store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
907 res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
909 } else if (get_mode_size_bits(mode) == 128) {
910 /* Spill 128 bit SSE registers */
911 store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
912 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
913 } else if (get_mode_size_bits(mode) == 8) {
914 store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
915 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
917 store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
918 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
921 set_ia32_op_type(store, ia32_AddrModeD);
922 set_ia32_ls_mode(store, mode);
923 set_ia32_frame_ent(store, ent);
924 set_ia32_use_frame(store);
925 set_ia32_is_spill(store);
926 SET_IA32_ORIG_NODE(store, node);
927 DBG_OPT_SPILL2ST(node, store);
930 sched_add_after(sched_point, store);
937 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
939 dbg_info *dbgi = get_irn_dbg_info(node);
940 ir_node *block = get_nodes_block(node);
941 ir_graph *irg = get_irn_irg(node);
942 ir_node *noreg = ia32_new_NoReg_gp(irg);
943 ir_node *frame = get_irg_frame(irg);
945 ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
947 set_ia32_frame_ent(push, ent);
948 set_ia32_use_frame(push);
949 set_ia32_op_type(push, ia32_AddrModeS);
950 set_ia32_ls_mode(push, mode_Is);
951 set_ia32_is_spill(push);
953 sched_add_before(schedpoint, push);
957 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
959 dbg_info *dbgi = get_irn_dbg_info(node);
960 ir_node *block = get_nodes_block(node);
961 ir_graph *irg = get_irn_irg(node);
962 ir_node *noreg = ia32_new_NoReg_gp(irg);
963 ir_node *frame = get_irg_frame(irg);
965 ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
966 get_irg_no_mem(irg), sp);
968 set_ia32_frame_ent(pop, ent);
969 set_ia32_use_frame(pop);
970 set_ia32_op_type(pop, ia32_AddrModeD);
971 set_ia32_ls_mode(pop, mode_Is);
972 set_ia32_is_reload(pop);
974 sched_add_before(schedpoint, pop);
979 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
981 dbg_info *dbgi = get_irn_dbg_info(node);
982 ir_mode *spmode = mode_Iu;
983 const arch_register_t *spreg = &ia32_registers[REG_ESP];
986 sp = new_rd_Proj(dbgi, pred, spmode, pos);
987 arch_set_irn_register(sp, spreg);
993 * Transform MemPerm, currently we do this the ugly way and produce
994 * push/pop into/from memory cascades. This is possible without using
997 static void transform_MemPerm(ir_node *node)
999 ir_node *block = get_nodes_block(node);
1000 ir_graph *irg = get_irn_irg(node);
1001 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
1002 int arity = be_get_MemPerm_entity_arity(node);
1003 ir_node **pops = ALLOCAN(ir_node*, arity);
1007 const ir_edge_t *edge;
1008 const ir_edge_t *next;
1011 for (i = 0; i < arity; ++i) {
1012 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1013 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1014 ir_type *enttype = get_entity_type(inent);
1015 unsigned entsize = get_type_size_bytes(enttype);
1016 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1017 ir_node *mem = get_irn_n(node, i + 1);
1020 /* work around cases where entities have different sizes */
1021 if (entsize2 < entsize)
1023 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1025 push = create_push(node, node, sp, mem, inent);
1026 sp = create_spproj(node, push, pn_ia32_Push_stack);
1028 /* add another push after the first one */
1029 push = create_push(node, node, sp, mem, inent);
1030 add_ia32_am_offs_int(push, 4);
1031 sp = create_spproj(node, push, pn_ia32_Push_stack);
1034 set_irn_n(node, i, new_r_Bad(irg, mode_X));
1038 for (i = arity - 1; i >= 0; --i) {
1039 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1040 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1041 ir_type *enttype = get_entity_type(outent);
1042 unsigned entsize = get_type_size_bytes(enttype);
1043 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1046 /* work around cases where entities have different sizes */
1047 if (entsize2 < entsize)
1049 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1051 pop = create_pop(node, node, sp, outent);
1052 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1054 add_ia32_am_offs_int(pop, 4);
1056 /* add another pop after the first one */
1057 pop = create_pop(node, node, sp, outent);
1058 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1065 keep = be_new_Keep(block, 1, in);
1066 sched_add_before(node, keep);
1068 /* exchange memprojs */
1069 foreach_out_edge_safe(node, edge, next) {
1070 ir_node *proj = get_edge_src_irn(edge);
1071 int p = get_Proj_proj(proj);
1075 set_Proj_pred(proj, pops[p]);
1076 set_Proj_proj(proj, pn_ia32_Pop_M);
1079 /* remove memperm */
1085 * Block-Walker: Calls the transform functions Spill and Reload.
1087 static void ia32_after_ra_walker(ir_node *block, void *env)
1089 ir_node *node, *prev;
1092 /* beware: the schedule is changed here */
1093 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1094 prev = sched_prev(node);
1096 if (be_is_Reload(node)) {
1097 transform_to_Load(node);
1098 } else if (be_is_Spill(node)) {
1099 transform_to_Store(node);
1100 } else if (be_is_MemPerm(node)) {
1101 transform_MemPerm(node);
1107 * Collects nodes that need frame entities assigned.
1109 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1111 be_fec_env_t *env = (be_fec_env_t*)data;
1112 const ir_mode *mode;
1115 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1116 mode = get_spill_mode_mode(get_irn_mode(node));
1117 align = get_mode_size_bytes(mode);
1118 } else if (is_ia32_irn(node) &&
1119 get_ia32_frame_ent(node) == NULL &&
1120 is_ia32_use_frame(node)) {
1121 if (is_ia32_need_stackent(node))
1124 switch (get_ia32_irn_opcode(node)) {
1126 case iro_ia32_Load: {
1127 const ia32_attr_t *attr = get_ia32_attr_const(node);
1129 if (attr->data.need_32bit_stackent) {
1131 } else if (attr->data.need_64bit_stackent) {
1134 mode = get_ia32_ls_mode(node);
1135 if (is_ia32_is_reload(node))
1136 mode = get_spill_mode_mode(mode);
1138 align = get_mode_size_bytes(mode);
1142 case iro_ia32_vfild:
1144 case iro_ia32_xLoad: {
1145 mode = get_ia32_ls_mode(node);
1150 case iro_ia32_FldCW: {
1151 /* although 2 byte would be enough 4 byte performs best */
1159 panic("unexpected frame user while collection frame entity nodes");
1161 case iro_ia32_FnstCW:
1162 case iro_ia32_Store8Bit:
1163 case iro_ia32_Store:
1166 case iro_ia32_vfist:
1167 case iro_ia32_vfisttp:
1169 case iro_ia32_xStore:
1170 case iro_ia32_xStoreSimple:
1177 be_node_needs_frame_entity(env, node, mode, align);
1180 static int determine_ebp_input(ir_node *ret)
1182 const arch_register_t *bp = &ia32_registers[REG_EBP];
1183 int arity = get_irn_arity(ret);
1186 for (i = 0; i < arity; ++i) {
1187 ir_node *input = get_irn_n(ret, i);
1188 if (arch_get_irn_register(input) == bp)
1191 panic("no ebp input found at %+F", ret);
1194 static void introduce_epilog(ir_node *ret)
1196 const arch_register_t *sp = &ia32_registers[REG_ESP];
1197 const arch_register_t *bp = &ia32_registers[REG_EBP];
1198 ir_graph *irg = get_irn_irg(ret);
1199 ir_type *frame_type = get_irg_frame_type(irg);
1200 unsigned frame_size = get_type_size_bytes(frame_type);
1201 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1202 ir_node *block = get_nodes_block(ret);
1203 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1204 ir_node *curr_sp = first_sp;
1205 ir_mode *mode_gp = mode_Iu;
1207 if (!layout->sp_relative) {
1208 int n_ebp = determine_ebp_input(ret);
1209 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1210 if (ia32_cg_config.use_leave) {
1211 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1212 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1213 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1214 arch_set_irn_register(curr_bp, bp);
1215 arch_set_irn_register(curr_sp, sp);
1216 sched_add_before(ret, leave);
1219 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1220 /* copy ebp to esp */
1221 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1222 arch_set_irn_register(curr_sp, sp);
1223 sched_add_before(ret, curr_sp);
1226 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1227 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1228 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1229 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1230 arch_set_irn_register(curr_bp, bp);
1231 arch_set_irn_register(curr_sp, sp);
1232 sched_add_before(ret, pop);
1234 set_irn_n(ret, n_be_Return_mem, curr_mem);
1236 set_irn_n(ret, n_ebp, curr_bp);
1238 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1239 sched_add_before(ret, incsp);
1242 set_irn_n(ret, n_be_Return_sp, curr_sp);
1244 /* keep verifier happy... */
1245 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1246 kill_node(first_sp);
1251 * put the Prolog code at the beginning, epilog code before each return
1253 static void introduce_prolog_epilog(ir_graph *irg)
1255 const arch_register_t *sp = &ia32_registers[REG_ESP];
1256 const arch_register_t *bp = &ia32_registers[REG_EBP];
1257 ir_node *start = get_irg_start(irg);
1258 ir_node *block = get_nodes_block(start);
1259 ir_type *frame_type = get_irg_frame_type(irg);
1260 unsigned frame_size = get_type_size_bytes(frame_type);
1261 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1262 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1263 ir_node *curr_sp = initial_sp;
1264 ir_mode *mode_gp = mode_Iu;
1266 if (!layout->sp_relative) {
1268 ir_node *mem = get_irg_initial_mem(irg);
1269 ir_node *noreg = ia32_new_NoReg_gp(irg);
1270 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1271 ir_node *curr_bp = initial_bp;
1272 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
1275 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1276 mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
1277 arch_set_irn_register(curr_sp, sp);
1278 sched_add_after(start, push);
1280 /* move esp to ebp */
1281 curr_bp = be_new_Copy(block, curr_sp);
1282 sched_add_after(push, curr_bp);
1283 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1284 curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
1285 sched_add_after(curr_bp, curr_sp);
1286 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1287 edges_reroute(initial_bp, curr_bp);
1288 set_irn_n(push, n_ia32_Push_val, initial_bp);
1290 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1291 edges_reroute(initial_sp, incsp);
1292 set_irn_n(push, n_ia32_Push_stack, initial_sp);
1293 sched_add_after(curr_sp, incsp);
1295 /* make sure the initial IncSP is really used by someone */
1296 if (get_irn_n_edges(incsp) <= 1) {
1297 ir_node *in[] = { incsp };
1298 ir_node *keep = be_new_Keep(block, 1, in);
1299 sched_add_after(incsp, keep);
1302 layout->initial_bias = -4;
1304 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1305 edges_reroute(initial_sp, incsp);
1306 be_set_IncSP_pred(incsp, curr_sp);
1307 sched_add_after(start, incsp);
1310 /* introduce epilog for every return node */
1312 ir_node *end_block = get_irg_end_block(irg);
1313 int arity = get_irn_arity(end_block);
1316 for (i = 0; i < arity; ++i) {
1317 ir_node *ret = get_irn_n(end_block, i);
1318 assert(be_is_Return(ret));
1319 introduce_epilog(ret);
1325 * Last touchups for the graph before emit: x87 simulation to replace the
1326 * virtual with real x87 instructions, creating a block schedule and peephole
1329 static void ia32_finish(ir_graph *irg)
1331 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1332 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1333 bool at_begin = stack_layout->sp_relative ? true : false;
1334 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1336 /* create and coalesce frame entities */
1337 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1338 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1339 be_free_frame_entity_coalescer(fec_env);
1341 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1343 introduce_prolog_epilog(irg);
1345 /* fix stack entity offsets */
1346 be_abi_fix_stack_nodes(irg);
1347 be_abi_fix_stack_bias(irg);
1349 /* fix 2-address code constraints */
1350 ia32_finish_irg(irg);
1352 /* we might have to rewrite x87 virtual registers */
1353 if (irg_data->do_x87_sim) {
1354 ia32_x87_simulate_graph(irg);
1357 /* do peephole optimisations */
1358 ia32_peephole_optimization(irg);
1360 be_remove_dead_nodes_from_schedule(irg);
1362 /* create block schedule, this also removes empty blocks which might
1363 * produce critical edges */
1364 irg_data->blk_sched = be_create_block_schedule(irg);
1368 * Emits the code, closes the output file and frees
1369 * the code generator interface.
1371 static void ia32_emit(ir_graph *irg)
1373 if (ia32_cg_config.emit_machcode) {
1374 ia32_gen_binary_routine(irg);
1376 ia32_gen_routine(irg);
1381 * Returns the node representing the PIC base.
1383 static ir_node *ia32_get_pic_base(ir_graph *irg)
1385 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1387 ir_node *get_eip = irg_data->get_eip;
1388 if (get_eip != NULL)
1391 block = get_irg_start_block(irg);
1392 get_eip = new_bd_ia32_GetEIP(NULL, block);
1393 irg_data->get_eip = get_eip;
1399 * Initializes a IA32 code generator.
1401 static void ia32_init_graph(ir_graph *irg)
1403 struct obstack *obst = be_get_be_obst(irg);
1404 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1406 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1409 /* Linux gprof implementation needs base pointer */
1410 be_get_irg_options(irg)->omit_fp = 0;
1413 be_birg_from_irg(irg)->isa_link = irg_data;
1418 * Set output modes for GCC
1420 static const tarval_mode_info mo_integer = {
1427 * set the tarval output mode of all integer modes to decimal
1429 static void set_tarval_output_modes(void)
1433 for (i = get_irp_n_modes(); i > 0;) {
1434 ir_mode *mode = get_irp_mode(--i);
1436 if (mode_is_int(mode))
1437 set_tarval_mode_output_option(mode, &mo_integer);
1441 extern const arch_isa_if_t ia32_isa_if;
1444 * The template that generates a new ISA object.
1445 * Note that this template can be changed by command line
1448 static ia32_isa_t ia32_isa_template = {
1450 &ia32_isa_if, /* isa interface implementation */
1455 &ia32_registers[REG_ESP], /* stack pointer register */
1456 &ia32_registers[REG_EBP], /* base pointer register */
1457 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1458 2, /* power of two stack alignment, 2^2 == 4 */
1459 NULL, /* main environment */
1460 7, /* costs for a spill instruction */
1461 5, /* costs for a reload instruction */
1462 false, /* no custom abi handling */
1466 NULL, /* abstract machine */
1467 IA32_FPU_ARCH_X87, /* FPU architecture */
1470 static void init_asm_constraints(void)
1472 be_init_default_asm_constraint_flags();
1474 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1475 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1476 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1477 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1478 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1479 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1480 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1481 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1482 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1483 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1484 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1485 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1486 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1487 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1488 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1489 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1490 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1491 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1492 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1493 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1495 /* no support for autodecrement/autoincrement */
1496 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1497 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1498 /* no float consts */
1499 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1500 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1501 /* makes no sense on x86 */
1502 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1503 /* no support for sse consts yet */
1504 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1505 /* no support for x87 consts yet */
1506 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1507 /* no support for mmx registers yet */
1508 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1509 /* not available in 32bit mode */
1510 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1511 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1513 /* no code yet to determine register class needed... */
1514 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1518 * Initializes the backend ISA.
1520 static arch_env_t *ia32_init(FILE *file_handle)
1522 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1524 set_tarval_output_modes();
1526 *isa = ia32_isa_template;
1528 if (ia32_mode_fpcw == NULL) {
1529 ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1532 ia32_register_init();
1533 ia32_create_opcodes(&ia32_irn_ops);
1535 be_emit_init(file_handle);
1536 isa->types = pmap_create();
1537 isa->tv_ent = pmap_create();
1538 isa->cpu = ia32_init_machine_description();
1540 /* enter the ISA object into the intrinsic environment */
1541 intrinsic_env.isa = isa;
1549 * Closes the output file and frees the ISA structure.
1551 static void ia32_done(void *self)
1553 ia32_isa_t *isa = (ia32_isa_t*)self;
1555 /* emit now all global declarations */
1556 be_gas_emit_decls(isa->base.main_env);
1558 pmap_destroy(isa->tv_ent);
1559 pmap_destroy(isa->types);
1568 * Get the register class which shall be used to store a value of a given mode.
1569 * @param self The this pointer.
1570 * @param mode The mode in question.
1571 * @return A register class which can hold values of the given mode.
1573 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1575 if (mode_is_float(mode)) {
1576 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1579 return &ia32_reg_classes[CLASS_ia32_gp];
1583 * Returns the register for parameter nr.
1585 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1586 const ir_mode *mode)
1588 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1589 &ia32_registers[REG_ECX],
1590 &ia32_registers[REG_EDX],
1593 static const unsigned MAXNUM_GPREG_ARGS = 3;
1595 static const arch_register_t *gpreg_param_reg_regparam[] = {
1596 &ia32_registers[REG_EAX],
1597 &ia32_registers[REG_EDX],
1598 &ia32_registers[REG_ECX]
1601 static const arch_register_t *gpreg_param_reg_this[] = {
1602 &ia32_registers[REG_ECX],
1607 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1608 &ia32_registers[REG_XMM0],
1609 &ia32_registers[REG_XMM1],
1610 &ia32_registers[REG_XMM2],
1611 &ia32_registers[REG_XMM3],
1612 &ia32_registers[REG_XMM4],
1613 &ia32_registers[REG_XMM5],
1614 &ia32_registers[REG_XMM6],
1615 &ia32_registers[REG_XMM7]
1618 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1619 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1621 static const unsigned MAXNUM_SSE_ARGS = 8;
1623 if ((cc & cc_this_call) && nr == 0)
1624 return gpreg_param_reg_this[0];
1626 if (! (cc & cc_reg_param))
1629 if (mode_is_float(mode)) {
1630 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1632 if (nr >= MAXNUM_SSE_ARGS)
1635 if (cc & cc_this_call) {
1636 return fpreg_sse_param_reg_this[nr];
1638 return fpreg_sse_param_reg_std[nr];
1639 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1640 unsigned num_regparam;
1642 if (get_mode_size_bits(mode) > 32)
1645 if (nr >= MAXNUM_GPREG_ARGS)
1648 if (cc & cc_this_call) {
1649 return gpreg_param_reg_this[nr];
1651 num_regparam = cc & ~cc_bits;
1652 if (num_regparam == 0) {
1653 /* default fastcall */
1654 return gpreg_param_reg_fastcall[nr];
1656 if (nr < num_regparam)
1657 return gpreg_param_reg_regparam[nr];
1661 panic("unknown argument mode");
1665 * Get the ABI restrictions for procedure calls.
1666 * @param self The this pointer.
1667 * @param method_type The type of the method (procedure) in question.
1668 * @param abi The abi object to be modified
1670 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1676 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1680 /* set abi flags for calls */
1681 call_flags.bits.store_args_sequential = 0;
1682 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1683 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1684 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1686 /* set parameter passing style */
1687 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1689 cc = get_method_calling_convention(method_type);
1690 if (get_method_variadicity(method_type) == variadicity_variadic) {
1691 /* pass all parameters of a variadic function on the stack */
1692 cc = cc_cdecl_set | (cc & cc_this_call);
1694 if (get_method_additional_properties(method_type) & mtp_property_private &&
1695 ia32_cg_config.optimize_cc) {
1696 /* set the fast calling conventions (allowing up to 3) */
1697 cc = SET_FASTCALL(cc) | 3;
1701 /* we have to pop the shadow parameter ourself for compound calls */
1702 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1703 && !(cc & cc_reg_param)) {
1704 pop_amount += get_mode_size_bytes(mode_P_data);
1707 n = get_method_n_params(method_type);
1708 for (i = regnum = 0; i < n; i++) {
1709 const arch_register_t *reg = NULL;
1710 ir_type *tp = get_method_param_type(method_type, i);
1711 ir_mode *mode = get_type_mode(tp);
1714 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1717 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1720 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1721 * movl has a shorter opcode than mov[sz][bw]l */
1722 ir_mode *load_mode = mode;
1725 unsigned size = get_mode_size_bytes(mode);
1727 if (cc & cc_callee_clear_stk) {
1728 pop_amount += (size + 3U) & ~3U;
1731 if (size < 4) load_mode = mode_Iu;
1734 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1738 be_abi_call_set_pop(abi, pop_amount);
1740 /* set return registers */
1741 n = get_method_n_ress(method_type);
1743 assert(n <= 2 && "more than two results not supported");
1745 /* In case of 64bit returns, we will have two 32bit values */
1747 ir_type *tp = get_method_res_type(method_type, 0);
1748 ir_mode *mode = get_type_mode(tp);
1750 assert(!mode_is_float(mode) && "two FP results not supported");
1752 tp = get_method_res_type(method_type, 1);
1753 mode = get_type_mode(tp);
1755 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1757 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1758 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1761 ir_type *tp = get_method_res_type(method_type, 0);
1762 ir_mode *mode = get_type_mode(tp);
1763 const arch_register_t *reg;
1764 assert(is_atomic_type(tp));
1766 reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
1768 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1773 * Returns the necessary byte alignment for storing a register of given class.
1775 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1777 ir_mode *mode = arch_register_class_mode(cls);
1778 int bytes = get_mode_size_bytes(mode);
1780 if (mode_is_float(mode) && bytes > 8)
1786 * Return irp irgs in the desired order.
1788 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1795 static void ia32_mark_remat(ir_node *node)
1797 if (is_ia32_irn(node)) {
1798 set_ia32_is_remat(node);
1803 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1805 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1810 ir_relation relation;
1815 cmp_l = get_Cmp_left(sel);
1816 cmp_r = get_Cmp_right(sel);
1817 if (!mode_is_float(get_irn_mode(cmp_l)))
1820 /* check for min/max. They're defined as (C-Semantik):
1821 * min(a, b) = a < b ? a : b
1822 * or min(a, b) = a <= b ? a : b
1823 * max(a, b) = a > b ? a : b
1824 * or max(a, b) = a >= b ? a : b
1825 * (Note we only handle float min/max here)
1827 relation = get_Cmp_relation(sel);
1829 case ir_relation_greater_equal:
1830 case ir_relation_greater:
1832 if (cmp_l == mux_true && cmp_r == mux_false)
1835 case ir_relation_less_equal:
1836 case ir_relation_less:
1838 if (cmp_l == mux_true && cmp_r == mux_false)
1841 case ir_relation_unordered_greater_equal:
1842 case ir_relation_unordered_greater:
1844 if (cmp_l == mux_false && cmp_r == mux_true)
1847 case ir_relation_unordered_less_equal:
1848 case ir_relation_unordered_less:
1850 if (cmp_l == mux_false && cmp_r == mux_true)
1861 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1863 ir_mode *mode = get_irn_mode(mux_true);
1866 if (!mode_is_int(mode) && !mode_is_reference(mode)
1870 if (is_Const(mux_true) && is_Const(mux_false)) {
1871 /* we can create a set plus up two 3 instructions for any combination
1879 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1884 if (!mode_is_float(get_irn_mode(mux_true)))
1887 return is_Const(mux_true) && is_Const(mux_false);
1890 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1897 ir_relation relation;
1902 mode = get_irn_mode(mux_true);
1903 if (mode_is_signed(mode) || mode_is_float(mode))
1906 relation = get_Cmp_relation(sel);
1907 cmp_left = get_Cmp_left(sel);
1908 cmp_right = get_Cmp_right(sel);
1910 /* "move" zero constant to false input */
1911 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1912 ir_node *tmp = mux_false;
1913 mux_false = mux_true;
1915 relation = get_negated_relation(relation);
1917 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1919 if (!is_Sub(mux_true))
1921 sub_left = get_Sub_left(mux_true);
1922 sub_right = get_Sub_right(mux_true);
1924 /* Mux(a >=u b, 0, a-b) */
1925 if ((relation & ir_relation_greater)
1926 && sub_left == cmp_left && sub_right == cmp_right)
1928 /* Mux(a <=u b, 0, b-a) */
1929 if ((relation & ir_relation_less)
1930 && sub_left == cmp_right && sub_right == cmp_left)
1936 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1941 /* we can handle Set for all modes and compares */
1942 if (mux_is_set(sel, mux_true, mux_false))
1944 /* SSE has own min/max operations */
1945 if (ia32_cg_config.use_sse2
1946 && mux_is_float_min_max(sel, mux_true, mux_false))
1948 /* we can handle Mux(?, Const[f], Const[f]) */
1949 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1950 #ifdef FIRM_GRGEN_BE
1951 /* well, some code selectors can't handle it */
1952 if (be_transformer != TRANSFORMER_PBQP
1953 || be_transformer != TRANSFORMER_RAND)
1960 /* no support for 64bit inputs to cmov */
1961 mode = get_irn_mode(mux_true);
1962 if (get_mode_size_bits(mode) > 32)
1964 /* we can handle Abs for all modes and compares (except 64bit) */
1965 if (ir_mux_is_abs(sel, mux_true, mux_false) != 0)
1967 /* we can't handle MuxF yet */
1968 if (mode_is_float(mode))
1971 if (mux_is_doz(sel, mux_true, mux_false))
1974 /* Check Cmp before the node */
1976 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1978 /* we can't handle 64bit compares */
1979 if (get_mode_size_bits(cmp_mode) > 32)
1982 /* we can't handle float compares */
1983 if (mode_is_float(cmp_mode))
1987 /* did we disable cmov generation? */
1988 if (!ia32_cg_config.use_cmov)
1991 /* we can use a cmov */
1995 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
1999 /* we already added all our simple flags to the flags modifier list in
2000 * init, so this flag we don't know. */
2001 return ASM_CONSTRAINT_FLAG_INVALID;
2004 static int ia32_is_valid_clobber(const char *clobber)
2006 return ia32_get_clobber_register(clobber) != NULL;
2009 static ir_node *ia32_create_set(ir_node *cond)
2011 /* ia32-set function produces 8-bit results which have to be converted */
2012 ir_node *set = ir_create_mux_set(cond, mode_Bu);
2013 ir_node *block = get_nodes_block(set);
2014 return new_r_Conv(block, set, mode_Iu);
2017 static void ia32_lower_for_target(void)
2019 size_t i, n_irgs = get_irp_n_irgs();
2020 lower_mode_b_config_t lower_mode_b_config = {
2021 mode_Iu, /* lowered mode */
2023 0, /* don't lower direct compares */
2026 /* perform doubleword lowering */
2027 lwrdw_param_t lower_dw_params = {
2028 1, /* little endian */
2029 64, /* doubleword size */
2030 ia32_create_intrinsic_fkt,
2034 /* lower compound param handling */
2035 lower_calls_with_compounds(LF_RETURN_HIDDEN);
2037 /* replace floating point operations by function calls */
2038 if (ia32_cg_config.use_softfloat) {
2039 lower_floating_point();
2042 ir_prepare_dw_lowering(&lower_dw_params);
2045 for (i = 0; i < n_irgs; ++i) {
2046 ir_graph *irg = get_irp_irg(i);
2047 /* lower for mode_b stuff */
2048 ir_lower_mode_b(irg, &lower_mode_b_config);
2049 /* break up switches with wide ranges */
2050 lower_switch(irg, 4, 256, false);
2053 for (i = 0; i < n_irgs; ++i) {
2054 ir_graph *irg = get_irp_irg(i);
2055 /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
2056 * so we can generate rep movs later, and turn all big CopyBs into
2058 lower_CopyB(irg, 64, 8193);
2063 * Create the trampoline code.
2065 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2067 ir_graph *const irg = get_irn_irg(block);
2068 ir_node * p = trampoline;
2069 ir_mode *const mode = get_irn_mode(p);
2070 ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
2071 ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
2075 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
2076 mem = new_r_Proj(st, mode_M, pn_Store_M);
2077 p = new_r_Add(block, p, one, mode);
2078 st = new_r_Store(block, mem, p, env, cons_none);
2079 mem = new_r_Proj(st, mode_M, pn_Store_M);
2080 p = new_r_Add(block, p, four, mode);
2082 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
2083 mem = new_r_Proj(st, mode_M, pn_Store_M);
2084 p = new_r_Add(block, p, one, mode);
2085 st = new_r_Store(block, mem, p, callee, cons_none);
2086 mem = new_r_Proj(st, mode_M, pn_Store_M);
2087 p = new_r_Add(block, p, four, mode);
2093 * Returns the libFirm configuration parameter for this backend.
2095 static const backend_params *ia32_get_libfirm_params(void)
2097 static const ir_settings_arch_dep_t ad = {
2098 1, /* also use subs */
2099 4, /* maximum shifts */
2100 63, /* maximum shift amount */
2101 ia32_evaluate_insn, /* evaluate the instruction sequence */
2103 1, /* allow Mulhs */
2104 1, /* allow Mulus */
2105 32, /* Mulh allowed up to 32 bit */
2107 static backend_params p = {
2108 1, /* support inline assembly */
2109 1, /* support Rotl nodes */
2110 0, /* little endian */
2111 1, /* modulo shift efficient */
2112 0, /* non-modulo shift not efficient */
2113 &ad, /* will be set later */
2114 ia32_is_mux_allowed,
2115 32, /* machine_size */
2116 NULL, /* float arithmetic mode, will be set below */
2117 NULL, /* long long type */
2118 NULL, /* unsigned long long type */
2119 NULL, /* long double type */
2120 12, /* size of trampoline code */
2121 4, /* alignment of trampoline code */
2122 ia32_create_trampoline_fkt,
2123 4 /* alignment of stack parameter */
2125 ir_mode *mode_long_long
2126 = new_ir_mode("long long", irms_int_number, 64, 1, irma_twos_complement,
2128 ir_type *type_long_long = new_type_primitive(mode_long_long);
2129 ir_mode *mode_unsigned_long_long
2130 = new_ir_mode("unsigned long long", irms_int_number, 64, 0,
2131 irma_twos_complement, 64);
2132 ir_type *type_unsigned_long_long
2133 = new_type_primitive(mode_unsigned_long_long);
2135 ia32_setup_cg_config();
2137 /* doesn't really belong here, but this is the earliest place the backend
2139 init_asm_constraints();
2141 p.type_long_long = type_long_long;
2142 p.type_unsigned_long_long = type_unsigned_long_long;
2144 if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
2145 p.mode_float_arithmetic = NULL;
2146 p.type_long_double = NULL;
2148 p.mode_float_arithmetic = mode_E;
2149 ir_mode *mode = new_ir_mode("long double", irms_float_number, 80, 1,
2151 ir_type *type = new_type_primitive(mode);
2152 set_type_size_bytes(type, 12);
2153 set_type_alignment_bytes(type, 4);
2154 p.type_long_double = type;
2160 * Check if the given register is callee or caller save.
2162 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
2165 /* check for callee saved */
2166 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2167 switch (reg->index) {
2178 /* check for caller saved */
2179 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2180 switch (reg->index) {
2188 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
2189 /* all XMM registers are caller save */
2190 return reg->index != REG_XMM_NOREG;
2191 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
2192 /* all VFP registers are caller save */
2193 return reg->index != REG_VFP_NOREG;
2199 static const lc_opt_enum_int_items_t gas_items[] = {
2200 { "elf", OBJECT_FILE_FORMAT_ELF },
2201 { "mingw", OBJECT_FILE_FORMAT_COFF },
2202 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2206 static lc_opt_enum_int_var_t gas_var = {
2207 (int*) &be_gas_object_file_format, gas_items
2210 #ifdef FIRM_GRGEN_BE
2211 static const lc_opt_enum_int_items_t transformer_items[] = {
2212 { "default", TRANSFORMER_DEFAULT },
2213 { "pbqp", TRANSFORMER_PBQP },
2214 { "random", TRANSFORMER_RAND },
2218 static lc_opt_enum_int_var_t transformer_var = {
2219 (int*)&be_transformer, transformer_items
2223 static const lc_opt_table_entry_t ia32_options[] = {
2224 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2225 #ifdef FIRM_GRGEN_BE
2226 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2228 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2229 &ia32_isa_template.base.stack_alignment),
2230 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2234 const arch_isa_if_t ia32_isa_if = {
2236 ia32_lower_for_target,
2238 ia32_handle_intrinsics,
2239 ia32_get_reg_class_for_mode,
2241 ia32_get_reg_class_alignment,
2242 ia32_get_libfirm_params,
2245 ia32_parse_asm_constraint,
2246 ia32_is_valid_clobber,
2249 ia32_get_pic_base, /* return node used as base in pic code addresses */
2250 ia32_before_abi, /* before abi introduce hook */
2252 ia32_before_ra, /* before register allocation hook */
2253 ia32_finish, /* called before codegen */
2254 ia32_emit, /* emit && done */
2255 ia32_register_saved_by,
2260 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2261 void be_init_arch_ia32(void)
2263 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2264 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2266 lc_opt_add_table(ia32_grp, ia32_options);
2267 be_register_isa_if("ia32", &ia32_isa_if);
2269 ia32_init_emitter();
2271 ia32_init_optimize();
2272 ia32_init_transform();
2274 ia32_init_architecture();