2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
30 #include <libcore/lc_opts.h>
31 #include <libcore/lc_opts_enum.h>
35 #include "pseudo_irg.h"
40 #include "iredges_t.h"
54 #include "../beirg_t.h"
55 #include "../benode_t.h"
56 #include "../belower.h"
57 #include "../besched_t.h"
60 #include "../beirgmod.h"
61 #include "../be_dbgout.h"
62 #include "../beblocksched.h"
63 #include "../bemachine.h"
64 #include "../beilpsched.h"
65 #include "../bespillslots.h"
66 #include "../bemodule.h"
67 #include "../begnuas.h"
68 #include "../bestate.h"
70 #include "bearch_ia32_t.h"
72 #include "ia32_new_nodes.h"
73 #include "gen_ia32_regalloc_if.h"
74 #include "gen_ia32_machine.h"
75 #include "ia32_transform.h"
76 #include "ia32_emitter.h"
77 #include "ia32_map_regs.h"
78 #include "ia32_optimize.h"
80 #include "ia32_dbg_stat.h"
81 #include "ia32_finish.h"
82 #include "ia32_util.h"
85 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
88 static set *cur_reg_set = NULL;
90 ir_mode *mode_fpcw = NULL;
91 ia32_code_gen_t *ia32_current_cg = NULL;
93 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
95 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
96 create_const_node_func func,
97 const arch_register_t* reg)
104 block = get_irg_start_block(cg->irg);
105 res = func(NULL, cg->irg, block);
106 arch_set_irn_register(cg->arch_env, res, reg);
109 add_irn_dep(get_irg_end(cg->irg), res);
110 /* add_irn_dep(get_irg_start(cg->irg), res); */
115 /* Creates the unique per irg GP NoReg node. */
116 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
117 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
118 &ia32_gp_regs[REG_GP_NOREG]);
121 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
122 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
123 &ia32_vfp_regs[REG_VFP_NOREG]);
126 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
127 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
128 &ia32_xmm_regs[REG_XMM_NOREG]);
131 /* Creates the unique per irg FP NoReg node. */
132 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
133 return USE_SSE2(cg) ? ia32_new_NoReg_xmm(cg) : ia32_new_NoReg_vfp(cg);
136 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
137 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
138 &ia32_gp_regs[REG_GP_UKNWN]);
141 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
142 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
143 &ia32_vfp_regs[REG_VFP_UKNWN]);
146 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
147 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
148 &ia32_xmm_regs[REG_XMM_UKNWN]);
151 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
152 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
153 &ia32_fp_cw_regs[REG_FPCW]);
158 * Returns gp_noreg or fp_noreg, depending in input requirements.
160 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
161 const arch_register_req_t *req;
163 req = arch_get_register_req(cg->arch_env, irn, pos);
164 assert(req != NULL && "Missing register requirements");
165 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
166 return ia32_new_NoReg_gp(cg);
168 return ia32_new_NoReg_fp(cg);
171 /**************************************************
174 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
175 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
176 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
177 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
180 **************************************************/
183 * Return register requirements for an ia32 node.
184 * If the node returns a tuple (mode_T) then the proj's
185 * will be asked for this information.
187 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
191 long node_pos = pos == -1 ? 0 : pos;
192 ir_mode *mode = is_Block(node) ? NULL : get_irn_mode(node);
195 if (is_Block(node) || mode == mode_X) {
196 return arch_no_register_req;
199 if (mode == mode_T && pos < 0) {
200 return arch_no_register_req;
205 return arch_no_register_req;
208 return arch_no_register_req;
211 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
212 node = skip_Proj_const(node);
215 if (is_ia32_irn(node)) {
216 const arch_register_req_t *req;
218 req = get_ia32_in_req(node, pos);
220 req = get_ia32_out_req(node, node_pos);
227 /* unknowns should be transformed already */
228 assert(!is_Unknown(node));
230 return arch_no_register_req;
233 static void ia32_set_irn_reg(const void *self, ir_node *irn,
234 const arch_register_t *reg)
239 if (get_irn_mode(irn) == mode_X) {
244 pos = get_Proj_proj(irn);
245 irn = skip_Proj(irn);
248 if (is_ia32_irn(irn)) {
249 const arch_register_t **slots;
251 slots = get_ia32_slots(irn);
254 ia32_set_firm_reg(irn, reg, cur_reg_set);
258 static const arch_register_t *ia32_get_irn_reg(const void *self,
262 const arch_register_t *reg = NULL;
267 if (get_irn_mode(irn) == mode_X) {
271 pos = get_Proj_proj(irn);
272 irn = skip_Proj_const(irn);
275 if (is_ia32_irn(irn)) {
276 const arch_register_t **slots;
277 slots = get_ia32_slots(irn);
280 reg = ia32_get_firm_reg(irn, cur_reg_set);
286 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
287 arch_irn_class_t classification = arch_irn_class_normal;
290 irn = skip_Proj_const(irn);
293 classification |= arch_irn_class_branch;
295 if (! is_ia32_irn(irn))
296 return classification & ~arch_irn_class_normal;
298 if (is_ia32_Cnst(irn))
299 classification |= arch_irn_class_const;
302 classification |= arch_irn_class_load;
305 classification |= arch_irn_class_store;
307 if (is_ia32_need_stackent(irn))
308 classification |= arch_irn_class_reload;
310 return classification;
313 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
314 arch_irn_flags_t flags = arch_irn_flags_none;
318 return arch_irn_flags_ignore;
320 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
321 ir_node *pred = get_Proj_pred(irn);
323 if(is_ia32_irn(pred)) {
324 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
330 if (is_ia32_irn(irn)) {
331 flags |= get_ia32_flags(irn);
338 * The IA32 ABI callback object.
341 be_abi_call_flags_bits_t flags; /**< The call flags. */
342 const arch_isa_t *isa; /**< The ISA handle. */
343 const arch_env_t *aenv; /**< The architecture environment. */
344 ir_graph *irg; /**< The associated graph. */
347 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
349 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
352 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
354 set_ia32_frame_ent(irn, ent);
357 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
358 const ia32_irn_ops_t *ops = self;
360 if (get_ia32_frame_ent(irn)) {
361 ia32_am_flavour_t am_flav;
363 if (is_ia32_Pop(irn)) {
364 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
366 /* Pop nodes modify the stack pointer before calculating the destination
367 * address, so fix this here
373 am_flav = get_ia32_am_flavour(irn);
375 set_ia32_am_flavour(irn, am_flav);
377 add_ia32_am_offs_int(irn, bias);
381 static int ia32_get_sp_bias(const void *self, const ir_node *node)
385 if (is_ia32_Push(node))
388 if (is_ia32_Pop(node))
395 * Put all registers which are saved by the prologue/epilogue in a set.
397 * @param self The callback object.
398 * @param s The result set.
400 static void ia32_abi_dont_save_regs(void *self, pset *s)
402 ia32_abi_env_t *env = self;
403 if(env->flags.try_omit_fp)
404 pset_insert_ptr(s, env->isa->bp);
408 * Generate the routine prologue.
410 * @param self The callback object.
411 * @param mem A pointer to the mem node. Update this if you define new memory.
412 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
414 * @return The register which shall be used as a stack frame base.
416 * All nodes which define registers in @p reg_map must keep @p reg_map current.
418 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
420 ia32_abi_env_t *env = self;
421 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
422 ia32_code_gen_t *cg = isa->cg;
424 if (! env->flags.try_omit_fp) {
425 ir_node *bl = get_irg_start_block(env->irg);
426 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
427 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
428 ir_node *noreg = ia32_new_NoReg_gp(cg);
431 /* ALL nodes representing bp must be set to ignore. */
432 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
435 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
436 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
437 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
439 /* the push must have SP out register */
440 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
441 set_ia32_flags(push, arch_irn_flags_ignore);
443 /* move esp to ebp */
444 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
445 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
446 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
447 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
449 /* beware: the copy must be done before any other sp use */
450 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
451 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
452 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
453 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
455 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
456 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
465 * Generate the routine epilogue.
466 * @param self The callback object.
467 * @param bl The block for the epilog
468 * @param mem A pointer to the mem node. Update this if you define new memory.
469 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
470 * @return The register which shall be used as a stack frame base.
472 * All nodes which define registers in @p reg_map must keep @p reg_map current.
474 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
476 ia32_abi_env_t *env = self;
477 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
478 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
480 if (env->flags.try_omit_fp) {
481 /* simply remove the stack frame here */
482 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
483 add_irn_dep(curr_sp, *mem);
485 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
486 ia32_code_gen_t *cg = isa->cg;
487 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
489 /* gcc always emits a leave at the end of a routine */
490 if (1 || ARCH_AMD(isa->opt_arch)) {
494 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
495 set_ia32_flags(leave, arch_irn_flags_ignore);
496 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
497 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
499 ir_node *noreg = ia32_new_NoReg_gp(cg);
502 /* copy ebp to esp */
503 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
506 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
507 set_ia32_flags(pop, arch_irn_flags_ignore);
508 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
509 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
511 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
513 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
514 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
517 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
518 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
522 * Initialize the callback object.
523 * @param call The call object.
524 * @param aenv The architecture environment.
525 * @param irg The graph with the method.
526 * @return Some pointer. This pointer is passed to all other callback functions as self object.
528 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
530 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
531 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
532 env->flags = fl.bits;
535 env->isa = aenv->isa;
540 * Destroy the callback object.
541 * @param self The callback object.
543 static void ia32_abi_done(void *self) {
548 * Produces the type which sits between the stack args and the locals on the stack.
549 * it will contain the return address and space to store the old base pointer.
550 * @return The Firm type modeling the ABI between type.
552 static ir_type *ia32_abi_get_between_type(void *self)
554 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
555 static ir_type *omit_fp_between_type = NULL;
556 static ir_type *between_type = NULL;
558 ia32_abi_env_t *env = self;
560 if (! between_type) {
561 ir_entity *old_bp_ent;
562 ir_entity *ret_addr_ent;
563 ir_entity *omit_fp_ret_addr_ent;
565 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
566 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
568 between_type = new_type_struct(IDENT("ia32_between_type"));
569 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
570 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
572 set_entity_offset(old_bp_ent, 0);
573 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
574 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
575 set_type_state(between_type, layout_fixed);
577 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
578 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
580 set_entity_offset(omit_fp_ret_addr_ent, 0);
581 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
582 set_type_state(omit_fp_between_type, layout_fixed);
585 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
590 * Get the estimated cycle count for @p irn.
592 * @param self The this pointer.
593 * @param irn The node.
595 * @return The estimated cycle count for this operation
597 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
600 ia32_op_type_t op_tp;
601 const ia32_irn_ops_t *ops = self;
605 if (!is_ia32_irn(irn))
608 assert(is_ia32_irn(irn));
610 cost = get_ia32_latency(irn);
611 op_tp = get_ia32_op_type(irn);
613 if (is_ia32_CopyB(irn)) {
615 if (ARCH_INTEL(ops->cg->arch))
618 else if (is_ia32_CopyB_i(irn)) {
619 int size = get_tarval_long(get_ia32_Immop_tarval(irn));
620 cost = 20 + (int)ceil((4/3) * size);
621 if (ARCH_INTEL(ops->cg->arch))
624 /* in case of address mode operations add additional cycles */
625 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
627 In case of stack access and access to fixed addresses add 5 cycles
628 (we assume they are in cache), other memory operations cost 20
631 if(is_ia32_use_frame(irn) ||
632 (is_ia32_NoReg_GP(get_irn_n(irn, 0)) &&
633 is_ia32_NoReg_GP(get_irn_n(irn, 1)))) {
644 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
646 * @param irn The original operation
647 * @param i Index of the argument we want the inverse operation to yield
648 * @param inverse struct to be filled with the resulting inverse op
649 * @param obstack The obstack to use for allocation of the returned nodes array
650 * @return The inverse operation or NULL if operation invertible
652 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
656 ir_node *block, *noreg, *nomem;
660 /* we cannot invert non-ia32 irns */
661 if (! is_ia32_irn(irn))
664 /* operand must always be a real operand (not base, index or mem) */
665 if (i != 2 && i != 3)
668 /* we don't invert address mode operations */
669 if (get_ia32_op_type(irn) != ia32_Normal)
672 irg = get_irn_irg(irn);
673 block = get_nodes_block(irn);
674 mode = get_irn_mode(irn);
675 irn_mode = get_irn_mode(irn);
676 noreg = get_irn_n(irn, 0);
677 nomem = new_r_NoMem(irg);
678 dbg = get_irn_dbg_info(irn);
680 /* initialize structure */
681 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
685 switch (get_ia32_irn_opcode(irn)) {
687 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
688 /* we have an add with a const here */
689 /* invers == add with negated const */
690 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
692 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
693 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
694 set_ia32_commutative(inverse->nodes[0]);
696 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
697 /* we have an add with a symconst here */
698 /* invers == sub with const */
699 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
701 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
704 /* normal add: inverse == sub */
705 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, i ^ 1), nomem);
710 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
711 /* we have a sub with a const/symconst here */
712 /* invers == add with this const */
713 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
714 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
715 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
720 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, 3), nomem);
723 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, 2), (ir_node*) irn, nomem);
729 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
730 /* xor with const: inverse = xor */
731 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
732 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
733 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
737 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem);
742 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
747 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
752 /* inverse operation not supported */
759 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
761 if(mode_is_float(mode))
768 * Get the mode that should be used for spilling value node
770 static ir_mode *get_spill_mode(const ir_node *node)
772 ir_mode *mode = get_irn_mode(node);
773 return get_spill_mode_mode(mode);
777 * Checks whether an addressmode reload for a node with mode mode is compatible
778 * with a spillslot of mode spill_mode
780 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
782 if(mode_is_float(mode)) {
783 return mode == spillmode;
790 * Check if irn can load it's operand at position i from memory (source addressmode).
791 * @param self Pointer to irn ops itself
792 * @param irn The irn to be checked
793 * @param i The operands position
794 * @return Non-Zero if operand can be loaded
796 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
797 ir_node *op = get_irn_n(irn, i);
798 const ir_mode *mode = get_irn_mode(op);
799 const ir_mode *spillmode = get_spill_mode(op);
802 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
803 get_irn_arity(irn) != 5 || /* must be a binary operation */
804 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
805 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
806 ! ia32_is_spillmode_compatible(mode, spillmode) ||
807 (i != 2 && i != 3) || /* a "real" operand position must be requested */
808 is_ia32_use_frame(irn)) /* must not already use frame */
812 const arch_register_req_t *req;
813 if(!is_ia32_commutative(irn))
815 /* we can't swap left/right for limited registers
816 * (As this (currently) breaks constraint handling copies)
818 req = get_ia32_in_req(irn, 2);
819 if(req->type & arch_register_req_type_limited) {
827 static void ia32_perform_memory_operand(const void *self, ir_node *irn,
828 ir_node *spill, unsigned int i)
830 const ia32_irn_ops_t *ops = self;
831 ia32_code_gen_t *cg = ops->cg;
833 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
836 ia32_swap_left_right(irn);
839 set_ia32_op_type(irn, ia32_AddrModeS);
840 set_ia32_am_flavour(irn, ia32_B);
841 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
842 set_ia32_use_frame(irn);
843 set_ia32_need_stackent(irn);
845 set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
846 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
847 set_irn_n(irn, 4, spill);
849 /* immediates are only allowed on the right side */
850 if(i == 2 && is_ia32_Immediate(get_irn_n(irn, 2))) {
851 ia32_swap_left_right(irn);
855 static const be_abi_callbacks_t ia32_abi_callbacks = {
858 ia32_abi_get_between_type,
859 ia32_abi_dont_save_regs,
864 /* fill register allocator interface */
866 static const arch_irn_ops_if_t ia32_irn_ops_if = {
867 ia32_get_irn_reg_req,
872 ia32_get_frame_entity,
873 ia32_set_frame_entity,
874 ia32_set_frame_offset,
877 ia32_get_op_estimated_cost,
878 ia32_possible_memory_operand,
879 ia32_perform_memory_operand,
882 ia32_irn_ops_t ia32_irn_ops = {
889 /**************************************************
892 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
893 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
894 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
895 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
898 **************************************************/
901 * Transforms the standard firm graph into
904 static void ia32_prepare_graph(void *self) {
905 ia32_code_gen_t *cg = self;
907 ir_lower_mode_b(cg->irg, mode_Iu, 0);
908 /* do local optimisations */
909 optimize_graph_df(cg->irg);
911 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
913 /* transform nodes into assembler instructions */
914 ia32_transform_graph(cg);
916 /* do local optimisations (mainly CSE) */
917 optimize_graph_df(cg->irg);
920 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
922 /* optimize address mode */
923 ia32_optimize_graph(cg);
926 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
928 /* do code placement, to optimize the position of constants */
932 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
936 * Dummy functions for hooks we don't need but which must be filled.
938 static void ia32_before_sched(void *self) {
943 * Called before the register allocator.
944 * Calculate a block schedule here. We need it for the x87
945 * simulator and the emitter.
947 static void ia32_before_ra(void *self) {
948 ia32_code_gen_t *cg = self;
950 /* setup fpu rounding modes */
951 ia32_setup_fpu_mode(cg);
956 * Transforms a be_Reload into a ia32 Load.
958 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
959 ir_graph *irg = get_irn_irg(node);
960 dbg_info *dbg = get_irn_dbg_info(node);
961 ir_node *block = get_nodes_block(node);
962 ir_entity *ent = be_get_frame_entity(node);
963 ir_mode *mode = get_irn_mode(node);
964 ir_mode *spillmode = get_spill_mode(node);
965 ir_node *noreg = ia32_new_NoReg_gp(cg);
966 ir_node *sched_point = NULL;
967 ir_node *ptr = get_irg_frame(irg);
968 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
969 ir_node *new_op, *proj;
970 const arch_register_t *reg;
972 if (sched_is_scheduled(node)) {
973 sched_point = sched_prev(node);
976 if (mode_is_float(spillmode)) {
978 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem);
980 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
982 else if (get_mode_size_bits(spillmode) == 128) {
983 // Reload 128 bit sse registers
984 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
987 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
989 set_ia32_op_type(new_op, ia32_AddrModeS);
990 set_ia32_am_flavour(new_op, ia32_B);
991 set_ia32_ls_mode(new_op, spillmode);
992 set_ia32_frame_ent(new_op, ent);
993 set_ia32_use_frame(new_op);
995 DBG_OPT_RELOAD2LD(node, new_op);
997 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1000 sched_add_after(sched_point, new_op);
1004 /* copy the register from the old node to the new Load */
1005 reg = arch_get_irn_register(cg->arch_env, node);
1006 arch_set_irn_register(cg->arch_env, new_op, reg);
1008 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1010 exchange(node, proj);
1014 * Transforms a be_Spill node into a ia32 Store.
1016 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1017 ir_graph *irg = get_irn_irg(node);
1018 dbg_info *dbg = get_irn_dbg_info(node);
1019 ir_node *block = get_nodes_block(node);
1020 ir_entity *ent = be_get_frame_entity(node);
1021 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1022 ir_mode *mode = get_spill_mode(spillval);
1023 ir_node *noreg = ia32_new_NoReg_gp(cg);
1024 ir_node *nomem = new_rd_NoMem(irg);
1025 ir_node *ptr = get_irg_frame(irg);
1026 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1028 ir_node *sched_point = NULL;
1030 if (sched_is_scheduled(node)) {
1031 sched_point = sched_prev(node);
1034 /* No need to spill unknown values... */
1035 if(is_ia32_Unknown_GP(val) ||
1036 is_ia32_Unknown_VFP(val) ||
1037 is_ia32_Unknown_XMM(val)) {
1042 exchange(node, store);
1046 if (mode_is_float(mode)) {
1048 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem);
1050 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem, mode);
1051 } else if (get_mode_size_bits(mode) == 128) {
1052 // Spill 128 bit SSE registers
1053 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, val, nomem);
1054 } else if (get_mode_size_bits(mode) == 8) {
1055 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem);
1057 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem);
1060 set_ia32_op_type(store, ia32_AddrModeD);
1061 set_ia32_am_flavour(store, ia32_B);
1062 set_ia32_ls_mode(store, mode);
1063 set_ia32_frame_ent(store, ent);
1064 set_ia32_use_frame(store);
1065 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1066 DBG_OPT_SPILL2ST(node, store);
1069 sched_add_after(sched_point, store);
1073 exchange(node, store);
1076 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1077 ir_graph *irg = get_irn_irg(node);
1078 dbg_info *dbg = get_irn_dbg_info(node);
1079 ir_node *block = get_nodes_block(node);
1080 ir_node *noreg = ia32_new_NoReg_gp(cg);
1081 ir_node *frame = get_irg_frame(irg);
1083 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, noreg, sp, mem);
1085 set_ia32_frame_ent(push, ent);
1086 set_ia32_use_frame(push);
1087 set_ia32_op_type(push, ia32_AddrModeS);
1088 set_ia32_am_flavour(push, ia32_B);
1089 set_ia32_ls_mode(push, mode_Is);
1091 sched_add_before(schedpoint, push);
1095 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1096 ir_graph *irg = get_irn_irg(node);
1097 dbg_info *dbg = get_irn_dbg_info(node);
1098 ir_node *block = get_nodes_block(node);
1099 ir_node *noreg = ia32_new_NoReg_gp(cg);
1100 ir_node *frame = get_irg_frame(irg);
1102 ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, sp, new_NoMem());
1104 set_ia32_frame_ent(pop, ent);
1105 set_ia32_use_frame(pop);
1106 set_ia32_op_type(pop, ia32_AddrModeD);
1107 set_ia32_am_flavour(pop, ia32_am_OB);
1108 set_ia32_ls_mode(pop, mode_Is);
1110 sched_add_before(schedpoint, pop);
1115 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
1116 ir_graph *irg = get_irn_irg(node);
1117 dbg_info *dbg = get_irn_dbg_info(node);
1118 ir_node *block = get_nodes_block(node);
1119 ir_mode *spmode = mode_Iu;
1120 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1123 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1124 arch_set_irn_register(cg->arch_env, sp, spreg);
1130 * Transform memperm, currently we do this the ugly way and produce
1131 * push/pop into/from memory cascades. This is possible without using
1134 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1135 ir_graph *irg = get_irn_irg(node);
1136 ir_node *block = get_nodes_block(node);
1140 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1141 const ir_edge_t *edge;
1142 const ir_edge_t *next;
1145 arity = be_get_MemPerm_entity_arity(node);
1146 pops = alloca(arity * sizeof(pops[0]));
1149 for(i = 0; i < arity; ++i) {
1150 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1151 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1152 ir_type *enttype = get_entity_type(inent);
1153 int entbits = get_type_size_bits(enttype);
1154 int entbits2 = get_type_size_bits(get_entity_type(outent));
1155 ir_node *mem = get_irn_n(node, i + 1);
1158 /* work around cases where entities have different sizes */
1159 if(entbits2 < entbits)
1161 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1163 push = create_push(cg, node, node, sp, mem, inent);
1164 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1166 // add another push after the first one
1167 push = create_push(cg, node, node, sp, mem, inent);
1168 add_ia32_am_offs_int(push, 4);
1169 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1172 set_irn_n(node, i, new_Bad());
1176 for(i = arity - 1; i >= 0; --i) {
1177 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1178 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1179 ir_type *enttype = get_entity_type(outent);
1180 int entbits = get_type_size_bits(enttype);
1181 int entbits2 = get_type_size_bits(get_entity_type(inent));
1184 /* work around cases where entities have different sizes */
1185 if(entbits2 < entbits)
1187 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1189 pop = create_pop(cg, node, node, sp, outent);
1190 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1192 add_ia32_am_offs_int(pop, 4);
1194 // add another pop after the first one
1195 pop = create_pop(cg, node, node, sp, outent);
1196 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1203 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1204 sched_add_before(node, keep);
1206 // exchange memprojs
1207 foreach_out_edge_safe(node, edge, next) {
1208 ir_node *proj = get_edge_src_irn(edge);
1209 int p = get_Proj_proj(proj);
1213 set_Proj_pred(proj, pops[p]);
1214 set_Proj_proj(proj, pn_ia32_Pop_M);
1218 arity = get_irn_arity(node);
1219 for(i = 0; i < arity; ++i) {
1220 set_irn_n(node, i, new_Bad());
1226 * Block-Walker: Calls the transform functions Spill and Reload.
1228 static void ia32_after_ra_walker(ir_node *block, void *env) {
1229 ir_node *node, *prev;
1230 ia32_code_gen_t *cg = env;
1232 /* beware: the schedule is changed here */
1233 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1234 prev = sched_prev(node);
1236 if (be_is_Reload(node)) {
1237 transform_to_Load(cg, node);
1238 } else if (be_is_Spill(node)) {
1239 transform_to_Store(cg, node);
1240 } else if(be_is_MemPerm(node)) {
1241 transform_MemPerm(cg, node);
1247 * Collects nodes that need frame entities assigned.
1249 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1251 be_fec_env_t *env = data;
1253 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1254 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1255 int align = get_mode_size_bytes(mode);
1256 be_node_needs_frame_entity(env, node, mode, align);
1257 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1258 && is_ia32_use_frame(node)) {
1259 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1260 const ir_mode *mode = get_ia32_ls_mode(node);
1261 const ia32_attr_t *attr = get_ia32_attr_const(node);
1262 int align = get_mode_size_bytes(mode);
1264 if(attr->data.need_64bit_stackent) {
1267 be_node_needs_frame_entity(env, node, mode, align);
1268 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
1269 || is_ia32_vfld(node)) {
1270 const ir_mode *mode = get_ia32_ls_mode(node);
1272 be_node_needs_frame_entity(env, node, mode, align);
1273 } else if(is_ia32_FldCW(node)) {
1274 const ir_mode *mode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
1276 be_node_needs_frame_entity(env, node, mode, align);
1279 assert(is_ia32_St(node) ||
1280 is_ia32_xStoreSimple(node) ||
1281 is_ia32_vfst(node) ||
1282 is_ia32_vfist(node) ||
1283 is_ia32_FnstCW(node));
1290 * We transform Spill and Reload here. This needs to be done before
1291 * stack biasing otherwise we would miss the corrected offset for these nodes.
1293 static void ia32_after_ra(void *self) {
1294 ia32_code_gen_t *cg = self;
1295 ir_graph *irg = cg->irg;
1296 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1298 /* create and coalesce frame entities */
1299 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1300 be_assign_entities(fec_env);
1301 be_free_frame_entity_coalescer(fec_env);
1303 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1305 ia32_finish_irg(irg, cg);
1309 * Last touchups for the graph before emit: x87 simulation to replace the
1310 * virtual with real x87 instructions, creating a block schedule and peephole
1313 static void ia32_finish(void *self) {
1314 ia32_code_gen_t *cg = self;
1315 ir_graph *irg = cg->irg;
1317 /* we might have to rewrite x87 virtual registers */
1318 if (cg->do_x87_sim) {
1319 x87_simulate_graph(cg->arch_env, cg->birg);
1322 /* create block schedule, this also removes empty blocks which might
1323 * produce critical edges */
1324 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1326 /* do peephole optimisations */
1327 ia32_peephole_optimization(irg, cg);
1331 * Emits the code, closes the output file and frees
1332 * the code generator interface.
1334 static void ia32_codegen(void *self) {
1335 ia32_code_gen_t *cg = self;
1336 ir_graph *irg = cg->irg;
1338 ia32_gen_routine(cg, irg);
1342 /* remove it from the isa */
1345 assert(ia32_current_cg == cg);
1346 ia32_current_cg = NULL;
1348 /* de-allocate code generator */
1349 del_set(cg->reg_set);
1353 static void *ia32_cg_init(be_irg_t *birg);
1355 static const arch_code_generator_if_t ia32_code_gen_if = {
1357 NULL, /* before abi introduce hook */
1360 ia32_before_sched, /* before scheduling hook */
1361 ia32_before_ra, /* before register allocation hook */
1362 ia32_after_ra, /* after register allocation hook */
1363 ia32_finish, /* called before codegen */
1364 ia32_codegen /* emit && done */
1368 * Initializes a IA32 code generator.
1370 static void *ia32_cg_init(be_irg_t *birg) {
1371 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1372 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1374 cg->impl = &ia32_code_gen_if;
1375 cg->irg = birg->irg;
1376 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1377 cg->arch_env = birg->main_env->arch_env;
1380 cg->blk_sched = NULL;
1381 cg->fp_kind = isa->fp_kind;
1382 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1384 /* copy optimizations from isa for easier access */
1386 cg->arch = isa->arch;
1387 cg->opt_arch = isa->opt_arch;
1393 if (isa->name_obst) {
1394 obstack_free(isa->name_obst, NULL);
1395 obstack_init(isa->name_obst);
1399 cur_reg_set = cg->reg_set;
1401 ia32_irn_ops.cg = cg;
1403 assert(ia32_current_cg == NULL);
1404 ia32_current_cg = cg;
1406 return (arch_code_generator_t *)cg;
1411 /*****************************************************************
1412 * ____ _ _ _____ _____
1413 * | _ \ | | | | |_ _|/ ____| /\
1414 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1415 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1416 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1417 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1419 *****************************************************************/
1422 * Set output modes for GCC
1424 static const tarval_mode_info mo_integer = {
1431 * set the tarval output mode of all integer modes to decimal
1433 static void set_tarval_output_modes(void)
1437 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1438 ir_mode *mode = get_irp_mode(i);
1440 if (mode_is_int(mode))
1441 set_tarval_mode_output_option(mode, &mo_integer);
1445 const arch_isa_if_t ia32_isa_if;
1448 * The template that generates a new ISA object.
1449 * Note that this template can be changed by command line
1452 static ia32_isa_t ia32_isa_template = {
1454 &ia32_isa_if, /* isa interface implementation */
1455 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1456 &ia32_gp_regs[REG_EBP], /* base pointer register */
1457 -1, /* stack direction */
1458 NULL, /* main environment */
1459 7, /* costs for a spill instruction */
1460 5, /* costs for a reload instruction */
1462 NULL_EMITTER, /* emitter environment */
1463 NULL, /* 16bit register names */
1464 NULL, /* 8bit register names */
1465 NULL, /* 8bit register names high */
1469 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1470 IA32_OPT_DOAM | /* optimize address mode default: on */
1471 IA32_OPT_LEA | /* optimize for LEAs default: on */
1472 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1473 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1474 IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
1475 arch_pentium_4, /* instruction architecture */
1476 arch_pentium_4, /* optimize for architecture */
1477 fp_x87, /* floating point mode */
1478 NULL, /* current code generator */
1480 NULL, /* name obstack */
1481 0 /* name obst size */
1486 * Initializes the backend ISA.
1488 static void *ia32_init(FILE *file_handle) {
1489 static int inited = 0;
1496 set_tarval_output_modes();
1498 isa = xmalloc(sizeof(*isa));
1499 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1501 if(mode_fpcw == NULL) {
1502 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1505 ia32_register_init();
1506 ia32_create_opcodes();
1508 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1509 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1510 /* no SSE2 for these cpu's */
1511 isa->fp_kind = fp_x87;
1513 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1514 /* Pentium 4 don't like inc and dec instructions */
1515 isa->opt &= ~IA32_OPT_INCDEC;
1518 be_emit_init_env(&isa->emit, file_handle);
1519 isa->regs_16bit = pmap_create();
1520 isa->regs_8bit = pmap_create();
1521 isa->regs_8bit_high = pmap_create();
1522 isa->types = pmap_create();
1523 isa->tv_ent = pmap_create();
1524 isa->cpu = ia32_init_machine_description();
1526 ia32_build_16bit_reg_map(isa->regs_16bit);
1527 ia32_build_8bit_reg_map(isa->regs_8bit);
1528 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1531 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1532 obstack_init(isa->name_obst);
1535 ia32_handle_intrinsics();
1537 /* needed for the debug support */
1538 be_gas_emit_switch_section(&isa->emit, GAS_SECTION_TEXT);
1539 be_emit_cstring(&isa->emit, ".Ltext0:\n");
1540 be_emit_write_line(&isa->emit);
1542 /* we mark referenced global entities, so we can only emit those which
1543 * are actually referenced. (Note: you mustn't use the type visited flag
1544 * elsewhere in the backend)
1546 inc_master_type_visited();
1554 * Closes the output file and frees the ISA structure.
1556 static void ia32_done(void *self) {
1557 ia32_isa_t *isa = self;
1559 /* emit now all global declarations */
1560 be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
1562 pmap_destroy(isa->regs_16bit);
1563 pmap_destroy(isa->regs_8bit);
1564 pmap_destroy(isa->regs_8bit_high);
1565 pmap_destroy(isa->tv_ent);
1566 pmap_destroy(isa->types);
1569 obstack_free(isa->name_obst, NULL);
1572 be_emit_destroy_env(&isa->emit);
1579 * Return the number of register classes for this architecture.
1580 * We report always these:
1581 * - the general purpose registers
1582 * - the SSE floating point register set
1583 * - the virtual floating point registers
1584 * - the SSE vector register set
1586 static int ia32_get_n_reg_class(const void *self) {
1592 * Return the register class for index i.
1594 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i)
1597 assert(i >= 0 && i < N_CLASSES);
1598 return &ia32_reg_classes[i];
1602 * Get the register class which shall be used to store a value of a given mode.
1603 * @param self The this pointer.
1604 * @param mode The mode in question.
1605 * @return A register class which can hold values of the given mode.
1607 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1608 const ia32_isa_t *isa = self;
1609 if (mode_is_float(mode)) {
1610 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1613 return &ia32_reg_classes[CLASS_ia32_gp];
1617 * Get the ABI restrictions for procedure calls.
1618 * @param self The this pointer.
1619 * @param method_type The type of the method (procedure) in question.
1620 * @param abi The abi object to be modified
1622 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1623 const ia32_isa_t *isa = self;
1628 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1630 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1632 /* set abi flags for calls */
1633 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1634 call_flags.bits.store_args_sequential = use_push;
1635 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1636 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1637 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1639 /* set parameter passing style */
1640 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1642 if (get_method_variadicity(method_type) == variadicity_variadic) {
1643 /* pass all parameters of a variadic function on the stack */
1646 cc = get_method_calling_convention(method_type);
1647 if (get_method_additional_properties(method_type) & mtp_property_private) {
1648 /* set the calling conventions to register parameter */
1649 cc = (cc & ~cc_bits) | cc_reg_param;
1652 n = get_method_n_params(method_type);
1653 for (i = regnum = 0; i < n; i++) {
1654 const ir_mode *mode;
1655 const arch_register_t *reg = NULL;
1657 tp = get_method_param_type(method_type, i);
1658 mode = get_type_mode(tp);
1660 reg = ia32_get_RegParam_reg(isa->cg, cc, regnum, mode);
1663 be_abi_call_param_reg(abi, i, reg);
1666 be_abi_call_param_stack(abi, i, 4, 0, 0);
1670 /* set return registers */
1671 n = get_method_n_ress(method_type);
1673 assert(n <= 2 && "more than two results not supported");
1675 /* In case of 64bit returns, we will have two 32bit values */
1677 tp = get_method_res_type(method_type, 0);
1678 mode = get_type_mode(tp);
1680 assert(!mode_is_float(mode) && "two FP results not supported");
1682 tp = get_method_res_type(method_type, 1);
1683 mode = get_type_mode(tp);
1685 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1687 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1688 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1691 const arch_register_t *reg;
1693 tp = get_method_res_type(method_type, 0);
1694 assert(is_atomic_type(tp));
1695 mode = get_type_mode(tp);
1697 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1699 be_abi_call_res_reg(abi, 0, reg);
1704 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self,
1709 return &ia32_irn_ops;
1712 const arch_irn_handler_t ia32_irn_handler = {
1716 const arch_irn_handler_t *ia32_get_irn_handler(const void *self)
1719 return &ia32_irn_handler;
1722 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1726 if(!is_ia32_irn(irn)) {
1730 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1731 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1732 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1733 || is_ia32_Immediate(irn))
1740 * Initializes the code generator interface.
1742 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1745 return &ia32_code_gen_if;
1749 * Returns the estimated execution time of an ia32 irn.
1751 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1752 const arch_env_t *arch_env = env;
1753 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1756 list_sched_selector_t ia32_sched_selector;
1759 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1761 static const list_sched_selector_t *ia32_get_list_sched_selector(
1762 const void *self, list_sched_selector_t *selector)
1765 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1766 ia32_sched_selector.exectime = ia32_sched_exectime;
1767 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1768 return &ia32_sched_selector;
1771 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1778 * Returns the necessary byte alignment for storing a register of given class.
1780 static int ia32_get_reg_class_alignment(const void *self,
1781 const arch_register_class_t *cls)
1783 ir_mode *mode = arch_register_class_mode(cls);
1784 int bytes = get_mode_size_bytes(mode);
1787 if (mode_is_float(mode) && bytes > 8)
1792 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1793 const void *self, const ir_node *irn)
1795 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1796 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1797 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1800 static const be_execution_unit_t *_allowed_units_GP[] = {
1801 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1802 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1803 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1804 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1805 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1806 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1807 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1810 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1811 &be_machine_execution_units_DUMMY[0],
1814 static const be_execution_unit_t **_units_callret[] = {
1815 _allowed_units_BRANCH,
1818 static const be_execution_unit_t **_units_other[] = {
1822 static const be_execution_unit_t **_units_dummy[] = {
1823 _allowed_units_DUMMY,
1826 const be_execution_unit_t ***ret;
1829 if (is_ia32_irn(irn)) {
1830 ret = get_ia32_exec_units(irn);
1832 else if (is_be_node(irn)) {
1833 if (be_is_Call(irn) || be_is_Return(irn)) {
1834 ret = _units_callret;
1836 else if (be_is_Barrier(irn)) {
1851 * Return the abstract ia32 machine.
1853 static const be_machine_t *ia32_get_machine(const void *self) {
1854 const ia32_isa_t *isa = self;
1859 * Return irp irgs in the desired order.
1861 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1869 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1870 * @return 1 if allowed, 0 otherwise
1872 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
1882 ir_node *pred = get_Proj_pred(sel);
1884 ir_node *left = get_Cmp_left(pred);
1885 ir_mode *cmp_mode = get_irn_mode(left);
1886 if(mode_is_float(cmp_mode))
1892 /* check the Phi nodes */
1893 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1894 ir_mode *mode = get_irn_mode(phi);
1896 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
1903 static ia32_intrinsic_env_t intrinsic_env = {
1904 NULL, /**< the irg, these entities belong to */
1905 NULL, /**< entity for first div operand (move into FPU) */
1906 NULL, /**< entity for second div operand (move into FPU) */
1907 NULL, /**< entity for converts ll -> d */
1908 NULL, /**< entity for converts d -> ll */
1912 * Returns the libFirm configuration parameter for this backend.
1914 static const backend_params *ia32_get_libfirm_params(void) {
1915 static const ir_settings_if_conv_t ifconv = {
1916 4, /* maxdepth, doesn't matter for Psi-conversion */
1917 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
1919 static const ir_settings_arch_dep_t ad = {
1920 1, /* also use subs */
1921 4, /* maximum shifts */
1922 31, /* maximum shift amount */
1924 1, /* allow Mulhs */
1925 1, /* allow Mulus */
1926 32 /* Mulh allowed up to 32 bit */
1928 static backend_params p = {
1929 1, /* need dword lowering */
1930 1, /* support inline assembly */
1931 NULL, /* no additional opcodes */
1932 NULL, /* will be set later */
1933 ia32_create_intrinsic_fkt,
1934 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1935 NULL, /* will be set below */
1939 p.if_conv_info = &ifconv;
1943 /* instruction set architectures. */
1944 static const lc_opt_enum_int_items_t arch_items[] = {
1945 { "386", arch_i386, },
1946 { "486", arch_i486, },
1947 { "pentium", arch_pentium, },
1948 { "586", arch_pentium, },
1949 { "pentiumpro", arch_pentium_pro, },
1950 { "686", arch_pentium_pro, },
1951 { "pentiummmx", arch_pentium_mmx, },
1952 { "pentium2", arch_pentium_2, },
1953 { "p2", arch_pentium_2, },
1954 { "pentium3", arch_pentium_3, },
1955 { "p3", arch_pentium_3, },
1956 { "pentium4", arch_pentium_4, },
1957 { "p4", arch_pentium_4, },
1958 { "pentiumm", arch_pentium_m, },
1959 { "pm", arch_pentium_m, },
1960 { "core", arch_core, },
1962 { "athlon", arch_athlon, },
1963 { "athlon64", arch_athlon_64, },
1964 { "opteron", arch_opteron, },
1968 static lc_opt_enum_int_var_t arch_var = {
1969 &ia32_isa_template.arch, arch_items
1972 static lc_opt_enum_int_var_t opt_arch_var = {
1973 &ia32_isa_template.opt_arch, arch_items
1976 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1978 { "sse2", fp_sse2 },
1982 static lc_opt_enum_int_var_t fp_unit_var = {
1983 &ia32_isa_template.fp_kind, fp_unit_items
1986 static const lc_opt_enum_int_items_t gas_items[] = {
1987 { "normal", GAS_FLAVOUR_NORMAL },
1988 { "mingw", GAS_FLAVOUR_MINGW },
1992 static lc_opt_enum_int_var_t gas_var = {
1993 (int*) &be_gas_flavour, gas_items
1996 static const lc_opt_table_entry_t ia32_options[] = {
1997 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1998 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1999 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
2000 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
2001 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
2002 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
2003 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
2004 LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
2005 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2009 const arch_isa_if_t ia32_isa_if = {
2012 ia32_get_n_reg_class,
2014 ia32_get_reg_class_for_mode,
2016 ia32_get_irn_handler,
2017 ia32_get_code_generator_if,
2018 ia32_get_list_sched_selector,
2019 ia32_get_ilp_sched_selector,
2020 ia32_get_reg_class_alignment,
2021 ia32_get_libfirm_params,
2022 ia32_get_allowed_execution_units,
2027 void ia32_init_emitter(void);
2028 void ia32_init_finish(void);
2029 void ia32_init_optimize(void);
2030 void ia32_init_transform(void);
2031 void ia32_init_x87(void);
2033 void be_init_arch_ia32(void)
2035 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2036 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2038 lc_opt_add_table(ia32_grp, ia32_options);
2039 be_register_isa_if("ia32", &ia32_isa_if);
2041 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2043 ia32_init_emitter();
2045 ia32_init_optimize();
2046 ia32_init_transform();
2050 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);