2 * This is the main ia32 firm backend driver.
17 #include "pseudo_irg.h"
21 #include "iredges_t.h"
29 #include "../beabi.h" /* the general register allocator interface */
30 #include "../benode_t.h"
31 #include "../belower.h"
32 #include "../besched_t.h"
34 #include "bearch_ia32_t.h"
36 #include "ia32_new_nodes.h" /* ia32 nodes interface */
37 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
38 #include "ia32_gen_decls.h" /* interface declaration emitter */
39 #include "ia32_transform.h"
40 #include "ia32_emitter.h"
41 #include "ia32_map_regs.h"
42 #include "ia32_optimize.h"
45 #define DEBUG_MODULE "firm.be.ia32.isa"
48 static set *cur_reg_set = NULL;
51 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
53 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
54 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
57 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
58 return be_abi_get_callee_save_irn(cg->birg->abi,
59 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
62 /**************************************************
65 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
66 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
67 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
68 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
71 **************************************************/
73 static ir_node *my_skip_proj(const ir_node *n) {
81 * Return register requirements for an ia32 node.
82 * If the node returns a tuple (mode_T) then the proj's
83 * will be asked for this information.
85 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
86 const ia32_irn_ops_t *ops = self;
87 const ia32_register_req_t *irn_req;
88 long node_pos = pos == -1 ? 0 : pos;
89 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
90 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
92 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
93 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
97 if (mode == mode_T && pos < 0) {
98 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
102 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
106 node_pos = ia32_translate_proj_pos(irn);
112 irn = my_skip_proj(irn);
114 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
117 if (is_ia32_irn(irn)) {
119 irn_req = get_ia32_in_req(irn, pos);
122 irn_req = get_ia32_out_req(irn, node_pos);
125 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
127 memcpy(req, &(irn_req->req), sizeof(*req));
129 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
130 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
131 req->other_same = get_irn_n(irn, irn_req->same_pos);
134 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
135 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
136 req->other_different = get_irn_n(irn, irn_req->different_pos);
140 /* treat Phi like Const with default requirements */
142 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
143 if (mode_is_float(mode)) {
144 if (USE_SSE2(ops->cg))
145 memcpy(req, &(ia32_default_req_ia32_xmm.req), sizeof(*req));
147 memcpy(req, &(ia32_default_req_ia32_vfp.req), sizeof(*req));
149 else if (mode_is_int(mode) || mode_is_reference(mode))
150 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
151 else if (mode == mode_T || mode == mode_M) {
152 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
156 assert(0 && "unsupported Phi-Mode");
159 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
167 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
169 const ia32_irn_ops_t *ops = self;
171 if (get_irn_mode(irn) == mode_X) {
175 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
178 pos = ia32_translate_proj_pos(irn);
179 irn = my_skip_proj(irn);
182 if (is_ia32_irn(irn)) {
183 const arch_register_t **slots;
185 slots = get_ia32_slots(irn);
189 ia32_set_firm_reg(irn, reg, cur_reg_set);
193 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
195 const arch_register_t *reg = NULL;
199 if (get_irn_mode(irn) == mode_X) {
203 pos = ia32_translate_proj_pos(irn);
204 irn = my_skip_proj(irn);
207 if (is_ia32_irn(irn)) {
208 const arch_register_t **slots;
209 slots = get_ia32_slots(irn);
213 reg = ia32_get_firm_reg(irn, cur_reg_set);
219 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
220 irn = my_skip_proj(irn);
222 return arch_irn_class_branch;
223 else if (is_ia32_irn(irn))
224 return arch_irn_class_normal;
229 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
230 irn = my_skip_proj(irn);
231 if (is_ia32_irn(irn))
232 return get_ia32_flags(irn);
238 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
239 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
242 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
244 const ia32_irn_ops_t *ops = self;
246 if (get_ia32_frame_ent(irn) && bias != 0) {
247 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
249 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
250 snprintf(buf, sizeof(buf), "%d", bias);
251 add_ia32_am_offs(irn, buf);
253 set_ia32_am_flavour(irn, am_flav);
258 be_abi_call_flags_bits_t flags;
259 const arch_isa_t *isa;
263 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
265 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
266 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
267 env->flags = fl.bits;
269 env->isa = aenv->isa;
273 static void ia32_abi_dont_save_regs(void *self, pset *s)
275 ia32_abi_env_t *env = self;
276 if(env->flags.try_omit_fp)
277 pset_insert_ptr(s, env->isa->bp);
280 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
282 ia32_abi_env_t *env = self;
283 const arch_register_t *frame_reg = env->isa->sp;
285 if(!env->flags.try_omit_fp) {
286 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
287 ir_node *bl = get_irg_start_block(env->irg);
288 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
289 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
290 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
293 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_expand);
294 store_bp = new_rd_ia32_Store(NULL, env->irg, bl, curr_sp, curr_no_reg, curr_bp, *mem, mode_T);
295 set_ia32_am_support(store_bp, ia32_am_Dest);
296 set_ia32_am_flavour(store_bp, ia32_B);
297 set_ia32_op_type(store_bp, ia32_AddrModeD);
298 *mem = new_r_Proj(env->irg, bl, store_bp, mode_M, 0);
299 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
300 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
301 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
303 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
304 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
310 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
312 ia32_abi_env_t *env = self;
313 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
314 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
315 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
317 if(env->flags.try_omit_fp) {
318 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
323 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
325 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
326 load_bp = new_rd_ia32_Load(NULL, env->irg, bl, curr_sp, curr_no_reg, *mem, mode_T);
327 set_ia32_am_support(load_bp, ia32_am_Source);
328 set_ia32_am_flavour(load_bp, ia32_B);
329 set_ia32_op_type(load_bp, ia32_AddrModeS);
330 set_ia32_ls_mode(load_bp, mode_bp);
331 curr_bp = new_r_Proj(env->irg, bl, load_bp, mode_bp, 0);
332 *mem = new_r_Proj(env->irg, bl, load_bp, mode_M, 1);
335 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
336 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
340 * Produces the type which sits between the stack args and the locals on the stack.
341 * it will contain the return address and space to store the old base pointer.
342 * @return The Firm type modeling the ABI between type.
344 static ir_type *ia32_abi_get_between_type(void *self)
346 static ir_type *omit_fp_between_type = NULL;
347 static ir_type *between_type = NULL;
349 ia32_abi_env_t *env = self;
353 entity *ret_addr_ent;
354 entity *omit_fp_ret_addr_ent;
356 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
357 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
359 between_type = new_type_class(new_id_from_str("ia32_between_type"));
360 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
361 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
363 set_entity_offset_bytes(old_bp_ent, 0);
364 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
365 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
367 omit_fp_between_type = new_type_class(new_id_from_str("ia32_between_type_omit_fp"));
368 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, new_id_from_str("ret_addr"), ret_addr_type);
370 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
371 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
374 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
377 static const be_abi_callbacks_t ia32_abi_callbacks = {
380 ia32_abi_get_between_type,
381 ia32_abi_dont_save_regs,
386 /* fill register allocator interface */
388 static const arch_irn_ops_if_t ia32_irn_ops_if = {
389 ia32_get_irn_reg_req,
394 ia32_get_frame_entity,
398 ia32_irn_ops_t ia32_irn_ops = {
405 /**************************************************
408 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
409 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
410 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
411 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
414 **************************************************/
417 * Transforms the standard firm graph into
420 static void ia32_prepare_graph(void *self) {
421 ia32_code_gen_t *cg = self;
422 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
424 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
425 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
426 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
428 DEBUG_ONLY(cg->mod = old_mod;)
431 edges_deactivate(cg->irg);
432 //dead_node_elimination(cg->irg);
433 edges_activate(cg->irg);
435 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
436 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
442 * Insert copies for all ia32 nodes where the should_be_same requirement
444 * Transform Sub into Neg -- Add if IN2 == OUT
446 static void ia32_finish_irg_walker(ir_node *irn, void *env) {
447 ia32_code_gen_t *cg = env;
448 const ia32_register_req_t **reqs;
449 const arch_register_t *out_reg, *in_reg;
451 ir_node *copy, *in_node, *block;
452 ia32_op_type_t op_tp;
454 if (! is_ia32_irn(irn))
457 /* AM Dest nodes don't produce any values */
458 op_tp = get_ia32_op_type(irn);
459 if (op_tp == ia32_AddrModeD)
462 reqs = get_ia32_out_req_all(irn);
463 n_res = get_ia32_n_res(irn);
464 block = get_nodes_block(irn);
466 /* check all OUT requirements, if there is a should_be_same */
467 if (op_tp == ia32_Normal) {
468 for (i = 0; i < n_res; i++) {
469 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
470 /* get in and out register */
471 out_reg = get_ia32_out_reg(irn, i);
472 in_node = get_irn_n(irn, reqs[i]->same_pos);
473 in_reg = arch_get_irn_register(cg->arch_env, in_node);
475 /* don't copy ignore nodes */
476 if (arch_irn_is(cg->arch_env, in_node, ignore))
479 /* check if in and out register are equal */
480 if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
481 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
483 /* create copy from in register */
484 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
486 /* destination is the out register */
487 arch_set_irn_register(cg->arch_env, copy, out_reg);
489 /* insert copy before the node into the schedule */
490 sched_add_before(irn, copy);
493 set_irn_n(irn, reqs[i]->same_pos, copy);
499 /* If we have a CondJmp with immediate, we need to */
500 /* check if it's the right operand, otherwise we have */
501 /* to change it, as CMP doesn't support immediate as */
503 if (is_ia32_CondJmp(irn) && (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) && op_tp == ia32_AddrModeS) {
504 long pnc = get_negated_pnc(get_ia32_pncode(irn), get_ia32_res_mode(irn));
505 set_ia32_op_type(irn, ia32_AddrModeD);
506 set_ia32_pncode(irn, pnc);
509 /* check if there is a sub which need to be transformed */
510 ia32_transform_sub_to_neg_add(irn, cg);
512 /* transform a LEA into an Add if possible */
513 ia32_transform_lea_to_add(irn, cg);
515 /* check for peephole optimization */
516 ia32_peephole_optimization(irn, cg);
520 * Add Copy nodes for not fulfilled should_be_equal constraints
522 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
523 irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
529 * Dummy functions for hooks we don't need but which must be filled.
531 static void ia32_before_sched(void *self) {
535 * Called before the register allocator.
536 * Calculate a block schedule here. We need it for the x87
537 * simulator and the emitter.
539 static void ia32_before_ra(void *self) {
540 ia32_code_gen_t *cg = self;
542 cg->blk_sched = sched_create_block_schedule(cg->irg);
547 * Transforms a be node into a Load.
549 static void transform_to_Load(ia32_transform_env_t *env) {
550 ir_node *irn = env->irn;
551 entity *ent = be_get_frame_entity(irn);
552 ir_mode *mode = env->mode;
553 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
554 ir_node *nomem = new_rd_NoMem(env->irg);
555 ir_node *sched_point = NULL;
556 ir_node *ptr = get_irn_n(irn, 0);
557 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
558 ir_node *new_op, *proj;
559 const arch_register_t *reg;
561 if (sched_is_scheduled(irn)) {
562 sched_point = sched_prev(irn);
565 if (mode_is_float(mode)) {
566 if (USE_SSE2(env->cg))
567 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
569 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
572 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
575 set_ia32_am_support(new_op, ia32_am_Source);
576 set_ia32_op_type(new_op, ia32_AddrModeS);
577 set_ia32_am_flavour(new_op, ia32_B);
578 set_ia32_ls_mode(new_op, mode);
579 set_ia32_frame_ent(new_op, ent);
580 set_ia32_use_frame(new_op);
582 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
585 sched_add_after(sched_point, new_op);
586 sched_add_after(new_op, proj);
591 /* copy the register from the old node to the new Load */
592 reg = arch_get_irn_register(env->cg->arch_env, irn);
593 arch_set_irn_register(env->cg->arch_env, new_op, reg);
595 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
601 * Transforms a be node into a Store.
603 static void transform_to_Store(ia32_transform_env_t *env) {
604 ir_node *irn = env->irn;
605 entity *ent = be_get_frame_entity(irn);
606 ir_mode *mode = env->mode;
607 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
608 ir_node *nomem = new_rd_NoMem(env->irg);
609 ir_node *ptr = get_irn_n(irn, 0);
610 ir_node *val = get_irn_n(irn, 1);
611 ir_node *new_op, *proj;
612 ir_node *sched_point = NULL;
614 if (sched_is_scheduled(irn)) {
615 sched_point = sched_prev(irn);
618 if (mode_is_float(mode)) {
619 if (USE_SSE2(env->cg))
620 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
622 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
624 else if (get_mode_size_bits(mode) == 8) {
625 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
628 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
631 set_ia32_am_support(new_op, ia32_am_Dest);
632 set_ia32_op_type(new_op, ia32_AddrModeD);
633 set_ia32_am_flavour(new_op, ia32_B);
634 set_ia32_ls_mode(new_op, mode);
635 set_ia32_frame_ent(new_op, ent);
636 set_ia32_use_frame(new_op);
638 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, 0);
641 sched_add_after(sched_point, new_op);
642 sched_add_after(new_op, proj);
647 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
653 * Calls the transform functions for StackParam, Spill and Reload.
655 static void ia32_after_ra_walker(ir_node *node, void *env) {
656 ia32_code_gen_t *cg = env;
657 ia32_transform_env_t tenv;
662 tenv.block = get_nodes_block(node);
663 tenv.dbg = get_irn_dbg_info(node);
664 tenv.irg = current_ir_graph;
666 DEBUG_ONLY(tenv.mod = cg->mod;)
667 tenv.mode = get_irn_mode(node);
670 /* be_is_StackParam(node) || */
671 if (be_is_Reload(node)) {
672 transform_to_Load(&tenv);
674 else if (be_is_Spill(node)) {
675 /* we always spill the whole register */
676 tenv.mode = mode_is_float(get_irn_mode(be_get_Spill_context(node))) ? mode_D : mode_Is;
677 transform_to_Store(&tenv);
682 * We transform StackParam, Spill and Reload here. This needs to be done before
683 * stack biasing otherwise we would miss the corrected offset for these nodes.
685 static void ia32_after_ra(void *self) {
686 ia32_code_gen_t *cg = self;
687 irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
689 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
691 x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
692 be_dump(cg->irg, "-x87", dump_ir_extblock_graph_sched);
698 * Emits the code, closes the output file and frees
699 * the code generator interface.
701 static void ia32_codegen(void *self) {
702 ia32_code_gen_t *cg = self;
703 ir_graph *irg = cg->irg;
706 if (cg->emit_decls) {
707 ia32_gen_decls(cg->out);
711 ia32_finish_irg(irg, cg);
712 be_dump(irg, "-finished", dump_ir_block_graph_sched);
713 ia32_gen_routine(out, irg, cg);
717 pmap_destroy(cg->tv_ent);
718 pmap_destroy(cg->types);
720 /* de-allocate code generator */
721 del_set(cg->reg_set);
725 static void *ia32_cg_init(FILE *F, const be_irg_t *birg);
727 static const arch_code_generator_if_t ia32_code_gen_if = {
729 NULL, /* before abi introduce hook */
731 ia32_before_sched, /* before scheduling hook */
732 ia32_before_ra, /* before register allocation hook */
733 ia32_after_ra, /* after register allocation hook */
734 ia32_codegen /* emit && done */
738 * Initializes the code generator.
740 static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
741 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
742 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
744 cg->impl = &ia32_code_gen_if;
746 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
748 cg->arch_env = birg->main_env->arch_env;
749 cg->types = pmap_create();
750 cg->tv_ent = pmap_create();
752 cg->blk_sched = NULL;
753 cg->fp_kind = isa->fp_kind;
756 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
758 /* set optimizations */
761 cg->opt.placecnst = 1;
766 if (isa->name_obst_size) {
767 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
768 isa->name_obst_size = 0;
769 obstack_free(isa->name_obst, NULL);
770 obstack_init(isa->name_obst);
776 if (isa->num_codegens > 1)
781 cur_reg_set = cg->reg_set;
783 ia32_irn_ops.cg = cg;
785 return (arch_code_generator_t *)cg;
790 /*****************************************************************
791 * ____ _ _ _____ _____
792 * | _ \ | | | | |_ _|/ ____| /\
793 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
794 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
795 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
796 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
798 *****************************************************************/
800 static ia32_isa_t ia32_isa_template = {
801 &ia32_isa_if, /* isa interface implementation */
802 &ia32_gp_regs[REG_ESP], /* stack pointer register */
803 &ia32_gp_regs[REG_EBP], /* base pointer register */
804 -1, /* stack direction */
805 0, /* number of code generator objects so far */
806 NULL, /* 16bit register names */
807 NULL, /* 8bit register names */
808 fp_sse2, /* use SSE2 unit for fp operations */
810 NULL, /* name obstack */
811 0 /* name obst size */
816 * Initializes the backend ISA.
818 static void *ia32_init(void) {
819 static int inited = 0;
825 isa = xcalloc(1, sizeof(*isa));
826 memcpy(isa, &ia32_isa_template, sizeof(*isa));
828 ia32_register_init(isa);
829 ia32_create_opcodes();
830 ia32_register_copy_attr_func();
832 isa->regs_16bit = pmap_create();
833 isa->regs_8bit = pmap_create();
834 // isa->fp_kind = fp_x87;
836 ia32_build_16bit_reg_map(isa->regs_16bit);
837 ia32_build_8bit_reg_map(isa->regs_8bit);
840 isa->name_obst = xcalloc(1, sizeof(*(isa->name_obst)));
841 obstack_init(isa->name_obst);
842 isa->name_obst_size = 0;
853 * Closes the output file and frees the ISA structure.
855 static void ia32_done(void *self) {
856 ia32_isa_t *isa = self;
858 pmap_destroy(isa->regs_16bit);
859 pmap_destroy(isa->regs_8bit);
862 //printf("name obst size = %d bytes\n", isa->name_obst_size);
863 obstack_free(isa->name_obst, NULL);
871 * Return the number of register classes for this architecture.
872 * We report always these:
873 * - the general purpose registers
874 * - the floating point register set (depending on the unit used for FP)
875 * - MMX/SE registers (currently not supported)
877 static int ia32_get_n_reg_class(const void *self) {
882 * Return the register class for index i.
884 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
885 const ia32_isa_t *isa = self;
886 assert(i >= 0 && i < 2 && "Invalid ia32 register class requested.");
888 return &ia32_reg_classes[CLASS_ia32_gp];
889 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
893 * Get the register class which shall be used to store a value of a given mode.
894 * @param self The this pointer.
895 * @param mode The mode in question.
896 * @return A register class which can hold values of the given mode.
898 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
899 const ia32_isa_t *isa = self;
900 if (mode_is_float(mode)) {
901 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
904 return &ia32_reg_classes[CLASS_ia32_gp];
908 * Get the ABI restrictions for procedure calls.
909 * @param self The this pointer.
910 * @param method_type The type of the method (procedure) in question.
911 * @param abi The abi object to be modified
913 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
914 const ia32_isa_t *isa = self;
917 unsigned cc = get_method_calling_convention(method_type);
918 int n = get_method_n_params(method_type);
921 int i, ignore_1, ignore_2;
923 const arch_register_t *reg;
924 be_abi_call_flags_t call_flags;
926 /* set abi flags for calls */
927 call_flags.bits.left_to_right = 0;
928 call_flags.bits.store_args_sequential = 0;
929 call_flags.bits.try_omit_fp = 1;
930 call_flags.bits.fp_free = 0;
931 call_flags.bits.call_has_imm = 1;
933 /* set stack parameter passing style */
934 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
936 /* collect the mode for each type */
937 modes = alloca(n * sizeof(modes[0]));
939 for (i = 0; i < n; i++) {
940 tp = get_method_param_type(method_type, i);
941 modes[i] = get_type_mode(tp);
944 /* set register parameters */
945 if (cc & cc_reg_param) {
946 /* determine the number of parameters passed via registers */
947 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
949 /* loop over all parameters and set the register requirements */
950 for (i = 0; i <= biggest_n; i++) {
951 reg = ia32_get_RegParam_reg(n, modes, i, cc);
952 assert(reg && "kaputt");
953 be_abi_call_param_reg(abi, i, reg);
960 /* set stack parameters */
961 for (i = stack_idx; i < n; i++) {
962 be_abi_call_param_stack(abi, i, 1, 0, 0);
966 /* set return registers */
967 n = get_method_n_ress(method_type);
969 assert(n <= 2 && "more than two results not supported");
971 /* In case of 64bit returns, we will have two 32bit values */
973 tp = get_method_res_type(method_type, 0);
974 mode = get_type_mode(tp);
976 assert(!mode_is_float(mode) && "two FP results not supported");
978 tp = get_method_res_type(method_type, 1);
979 mode = get_type_mode(tp);
981 assert(!mode_is_float(mode) && "two FP results not supported");
983 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
984 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
987 const arch_register_t *reg;
989 tp = get_method_res_type(method_type, 0);
990 assert(is_atomic_type(tp));
991 mode = get_type_mode(tp);
993 reg = mode_is_float(mode) ?
994 (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
995 &ia32_gp_regs[REG_EAX];
997 be_abi_call_res_reg(abi, 0, reg);
1002 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1003 return &ia32_irn_ops;
1006 const arch_irn_handler_t ia32_irn_handler = {
1010 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1011 return &ia32_irn_handler;
1014 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1015 return is_ia32_irn(irn);
1019 * Initializes the code generator interface.
1021 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1022 return &ia32_code_gen_if;
1025 list_sched_selector_t ia32_sched_selector;
1028 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1030 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
1031 // memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1032 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
1033 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1034 return &ia32_sched_selector;
1038 static void ia32_register_options(lc_opt_entry_t *ent)
1041 #endif /* WITH_LIBCORE */
1043 const arch_isa_if_t ia32_isa_if = {
1045 ia32_register_options,
1049 ia32_get_n_reg_class,
1051 ia32_get_reg_class_for_mode,
1053 ia32_get_irn_handler,
1054 ia32_get_code_generator_if,
1055 ia32_get_list_sched_selector