2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
28 #include "lc_opts_enum.h"
36 #include "iredges_t.h"
49 #include "iroptimize.h"
50 #include "instrument.h"
53 #include "lower_calls.h"
54 #include "lower_mode_b.h"
55 #include "lower_softfloat.h"
65 #include "beblocksched.h"
66 #include "bespillutil.h"
67 #include "bespillslots.h"
72 #include "betranshlp.h"
73 #include "belistsched.h"
74 #include "beabihelper.h"
77 #include "bearch_ia32_t.h"
79 #include "ia32_new_nodes.h"
80 #include "gen_ia32_regalloc_if.h"
81 #include "ia32_common_transform.h"
82 #include "ia32_transform.h"
83 #include "ia32_emitter.h"
84 #include "ia32_optimize.h"
86 #include "ia32_dbg_stat.h"
87 #include "ia32_finish.h"
89 #include "ia32_architecture.h"
92 #include "ia32_pbqp_transform.h"
94 transformer_t be_transformer = TRANSFORMER_DEFAULT;
97 ir_mode *ia32_mode_fpcw;
101 /** The current omit-fp state */
102 static ir_type *omit_fp_between_type = NULL;
103 static ir_type *between_type = NULL;
104 static ir_entity *old_bp_ent = NULL;
105 static ir_entity *ret_addr_ent = NULL;
106 static ir_entity *omit_fp_ret_addr_ent = NULL;
109 * The environment for the intrinsic mapping.
111 static ia32_intrinsic_env_t intrinsic_env = {
113 NULL, /* the irg, these entities belong to */
114 NULL, /* entity for __divdi3 library call */
115 NULL, /* entity for __moddi3 library call */
116 NULL, /* entity for __udivdi3 library call */
117 NULL, /* entity for __umoddi3 library call */
121 typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
124 * Used to create per-graph unique pseudo nodes.
126 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
127 create_const_node_func func,
128 const arch_register_t* reg)
130 ir_node *block, *res;
135 block = get_irg_start_block(irg);
136 res = func(NULL, block);
137 arch_set_irn_register(res, reg);
143 /* Creates the unique per irg GP NoReg node. */
144 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
146 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
147 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
148 &ia32_registers[REG_GP_NOREG]);
151 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
153 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
154 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
155 &ia32_registers[REG_VFP_NOREG]);
158 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
160 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
161 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
162 &ia32_registers[REG_XMM_NOREG]);
165 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
167 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
168 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
169 &ia32_registers[REG_FPCW]);
174 * Returns the admissible noreg register node for input register pos of node irn.
176 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
178 ir_graph *irg = get_irn_irg(irn);
179 const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
181 assert(req != NULL && "Missing register requirements");
182 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
183 return ia32_new_NoReg_gp(irg);
185 if (ia32_cg_config.use_sse2) {
186 return ia32_new_NoReg_xmm(irg);
188 return ia32_new_NoReg_vfp(irg);
192 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
194 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
197 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
199 if (is_be_node(node))
200 be_node_set_frame_entity(node, entity);
202 set_ia32_frame_ent(node, entity);
205 static void ia32_set_frame_offset(ir_node *irn, int bias)
207 if (get_ia32_frame_ent(irn) == NULL)
210 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
211 ir_graph *irg = get_irn_irg(irn);
212 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
213 if (layout->sp_relative) {
214 /* Pop nodes modify the stack pointer before calculating the
215 * destination address, so fix this here
220 add_ia32_am_offs_int(irn, bias);
223 static int ia32_get_sp_bias(const ir_node *node)
225 if (is_ia32_Call(node))
226 return -(int)get_ia32_call_attr_const(node)->pop;
228 if (is_ia32_Push(node))
231 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
234 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
235 return SP_BIAS_RESET;
242 * Build the between type and entities if not already build.
244 static void ia32_build_between_type(void)
246 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
247 if (between_type == NULL) {
248 ir_type *old_bp_type = new_type_primitive(mode_Iu);
249 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
251 between_type = new_type_struct(IDENT("ia32_between_type"));
252 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
253 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
255 set_entity_offset(old_bp_ent, 0);
256 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
257 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
258 set_type_state(between_type, layout_fixed);
260 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
261 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
263 set_entity_offset(omit_fp_ret_addr_ent, 0);
264 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
265 set_type_state(omit_fp_between_type, layout_fixed);
271 * Produces the type which sits between the stack args and the locals on the stack.
272 * it will contain the return address and space to store the old base pointer.
273 * @return The Firm type modeling the ABI between type.
275 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
277 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
278 ia32_build_between_type();
279 return layout->sp_relative ? omit_fp_between_type : between_type;
283 * Return the stack entity that contains the return address.
285 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
287 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
288 ia32_build_between_type();
289 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
293 * Return the stack entity that contains the frame address.
295 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
297 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
298 ia32_build_between_type();
299 return layout->sp_relative ? NULL : old_bp_ent;
303 * Get the estimated cycle count for @p irn.
305 * @param self The this pointer.
306 * @param irn The node.
308 * @return The estimated cycle count for this operation
310 static int ia32_get_op_estimated_cost(const ir_node *irn)
313 ia32_op_type_t op_tp;
317 if (!is_ia32_irn(irn))
320 assert(is_ia32_irn(irn));
322 cost = get_ia32_latency(irn);
323 op_tp = get_ia32_op_type(irn);
325 if (is_ia32_CopyB(irn)) {
328 else if (is_ia32_CopyB_i(irn)) {
329 int size = get_ia32_copyb_size(irn);
330 cost = 20 + (int)ceil((4/3) * size);
332 /* in case of address mode operations add additional cycles */
333 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
335 In case of stack access and access to fixed addresses add 5 cycles
336 (we assume they are in cache), other memory operations cost 20
339 if (is_ia32_use_frame(irn) || (
340 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
341 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
353 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
355 * @param irn The original operation
356 * @param i Index of the argument we want the inverse operation to yield
357 * @param inverse struct to be filled with the resulting inverse op
358 * @param obstack The obstack to use for allocation of the returned nodes array
359 * @return The inverse operation or NULL if operation invertible
361 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
372 ir_node *block, *noreg, *nomem;
375 /* we cannot invert non-ia32 irns */
376 if (! is_ia32_irn(irn))
379 /* operand must always be a real operand (not base, index or mem) */
380 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
383 /* we don't invert address mode operations */
384 if (get_ia32_op_type(irn) != ia32_Normal)
387 /* TODO: adjust for new immediates... */
388 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
392 block = get_nodes_block(irn);
393 mode = get_irn_mode(irn);
394 irn_mode = get_irn_mode(irn);
395 noreg = get_irn_n(irn, 0);
396 nomem = get_irg_no_mem(irg);
397 dbgi = get_irn_dbg_info(irn);
399 /* initialize structure */
400 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
404 switch (get_ia32_irn_opcode(irn)) {
406 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
407 /* we have an add with a const here */
408 /* invers == add with negated const */
409 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
411 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
412 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
413 set_ia32_commutative(inverse->nodes[0]);
415 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
416 /* we have an add with a symconst here */
417 /* invers == sub with const */
418 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
420 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
423 /* normal add: inverse == sub */
424 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
429 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
430 /* we have a sub with a const/symconst here */
431 /* invers == add with this const */
432 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
433 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
434 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
438 if (i == n_ia32_binary_left) {
439 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
442 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
448 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
449 /* xor with const: inverse = xor */
450 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
451 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
452 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
456 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
461 inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
466 inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
471 /* inverse operation not supported */
479 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
481 if (mode_is_float(mode))
488 * Get the mode that should be used for spilling value node
490 static ir_mode *get_spill_mode(const ir_node *node)
492 ir_mode *mode = get_irn_mode(node);
493 return get_spill_mode_mode(mode);
497 * Checks whether an addressmode reload for a node with mode mode is compatible
498 * with a spillslot of mode spill_mode
500 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
502 return !mode_is_float(mode) || mode == spillmode;
506 * Check if irn can load its operand at position i from memory (source addressmode).
507 * @param irn The irn to be checked
508 * @param i The operands position
509 * @return Non-Zero if operand can be loaded
511 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
513 ir_node *op = get_irn_n(irn, i);
514 const ir_mode *mode = get_irn_mode(op);
515 const ir_mode *spillmode = get_spill_mode(op);
517 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
518 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
519 !ia32_is_spillmode_compatible(mode, spillmode) ||
520 is_ia32_use_frame(irn)) /* must not already use frame */
523 switch (get_ia32_am_support(irn)) {
528 if (i != n_ia32_unary_op)
534 case n_ia32_binary_left: {
535 const arch_register_req_t *req;
536 if (!is_ia32_commutative(irn))
539 /* we can't swap left/right for limited registers
540 * (As this (currently) breaks constraint handling copies)
542 req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
543 if (req->type & arch_register_req_type_limited)
548 case n_ia32_binary_right:
557 panic("Unknown AM type");
560 /* HACK: must not already use "real" memory.
561 * This can happen for Call and Div */
562 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
568 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
572 ir_mode *dest_op_mode;
574 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
576 set_ia32_op_type(irn, ia32_AddrModeS);
578 load_mode = get_irn_mode(get_irn_n(irn, i));
579 dest_op_mode = get_ia32_ls_mode(irn);
580 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
581 set_ia32_ls_mode(irn, load_mode);
583 set_ia32_use_frame(irn);
584 set_ia32_need_stackent(irn);
586 if (i == n_ia32_binary_left &&
587 get_ia32_am_support(irn) == ia32_am_binary &&
588 /* immediates are only allowed on the right side */
589 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
590 ia32_swap_left_right(irn);
591 i = n_ia32_binary_right;
594 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
596 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
597 set_irn_n(irn, n_ia32_mem, spill);
598 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
599 set_ia32_is_reload(irn);
602 static const be_abi_callbacks_t ia32_abi_callbacks = {
603 ia32_abi_get_between_type,
606 /* register allocator interface */
607 static const arch_irn_ops_t ia32_irn_ops = {
608 ia32_get_frame_entity,
609 ia32_set_frame_offset,
612 ia32_get_op_estimated_cost,
613 ia32_possible_memory_operand,
614 ia32_perform_memory_operand,
617 static ir_entity *mcount = NULL;
618 static int gprof = 0;
620 static void ia32_before_abi(ir_graph *irg)
623 if (mcount == NULL) {
624 ir_type *tp = new_type_method(0, 0);
625 ident *id = new_id_from_str("mcount");
626 mcount = new_entity(get_glob_type(), id, tp);
627 /* FIXME: enter the right ld_ident here */
628 set_entity_ld_ident(mcount, get_entity_ident(mcount));
629 set_entity_visibility(mcount, ir_visibility_external);
631 instrument_initcall(irg, mcount);
636 * Transforms the standard firm graph into
639 static void ia32_prepare_graph(ir_graph *irg)
641 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
644 switch (be_transformer) {
645 case TRANSFORMER_DEFAULT:
646 /* transform remaining nodes into assembler instructions */
647 ia32_transform_graph(irg);
650 case TRANSFORMER_PBQP:
651 case TRANSFORMER_RAND:
652 /* transform nodes into assembler instructions by PBQP magic */
653 ia32_transform_graph_by_pbqp(irg);
657 panic("invalid transformer");
660 ia32_transform_graph(irg);
663 /* do local optimizations (mainly CSE) */
664 optimize_graph_df(irg);
665 /* backend code expects that outedges are always enabled */
669 dump_ir_graph(irg, "transformed");
671 /* optimize address mode */
672 ia32_optimize_graph(irg);
674 /* do code placement, to optimize the position of constants */
676 /* backend code expects that outedges are always enabled */
680 dump_ir_graph(irg, "place");
683 ir_node *ia32_turn_back_am(ir_node *node)
685 dbg_info *dbgi = get_irn_dbg_info(node);
686 ir_graph *irg = get_irn_irg(node);
687 ir_node *block = get_nodes_block(node);
688 ir_node *base = get_irn_n(node, n_ia32_base);
689 ir_node *idx = get_irn_n(node, n_ia32_index);
690 ir_node *mem = get_irn_n(node, n_ia32_mem);
693 ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
694 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
696 ia32_copy_am_attrs(load, node);
697 if (is_ia32_is_reload(node))
698 set_ia32_is_reload(load);
699 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
701 switch (get_ia32_am_support(node)) {
703 set_irn_n(node, n_ia32_unary_op, load_res);
707 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
708 set_irn_n(node, n_ia32_binary_left, load_res);
710 set_irn_n(node, n_ia32_binary_right, load_res);
715 panic("Unknown AM type");
717 noreg = ia32_new_NoReg_gp(current_ir_graph);
718 set_irn_n(node, n_ia32_base, noreg);
719 set_irn_n(node, n_ia32_index, noreg);
720 set_ia32_am_offs_int(node, 0);
721 set_ia32_am_sc(node, NULL);
722 set_ia32_am_scale(node, 0);
723 clear_ia32_am_sc_sign(node);
725 /* rewire mem-proj */
726 if (get_irn_mode(node) == mode_T) {
727 const ir_edge_t *edge;
728 foreach_out_edge(node, edge) {
729 ir_node *out = get_edge_src_irn(edge);
730 if (get_irn_mode(out) == mode_M) {
731 set_Proj_pred(out, load);
732 set_Proj_proj(out, pn_ia32_Load_M);
738 set_ia32_op_type(node, ia32_Normal);
739 if (sched_is_scheduled(node))
740 sched_add_before(node, load);
745 static ir_node *flags_remat(ir_node *node, ir_node *after)
747 /* we should turn back source address mode when rematerializing nodes */
752 if (is_Block(after)) {
755 block = get_nodes_block(after);
758 type = get_ia32_op_type(node);
761 ia32_turn_back_am(node);
765 /* TODO implement this later... */
766 panic("found DestAM with flag user %+F this should not happen", node);
768 default: assert(type == ia32_Normal); break;
771 copy = exact_copy(node);
772 set_nodes_block(copy, block);
773 sched_add_after(after, copy);
779 * Called before the register allocator.
781 static void ia32_before_ra(ir_graph *irg)
783 /* setup fpu rounding modes */
784 ia32_setup_fpu_mode(irg);
787 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
790 be_add_missing_keeps(irg);
795 * Transforms a be_Reload into a ia32 Load.
797 static void transform_to_Load(ir_node *node)
799 ir_graph *irg = get_irn_irg(node);
800 dbg_info *dbgi = get_irn_dbg_info(node);
801 ir_node *block = get_nodes_block(node);
802 ir_entity *ent = be_get_frame_entity(node);
803 ir_mode *mode = get_irn_mode(node);
804 ir_mode *spillmode = get_spill_mode(node);
805 ir_node *noreg = ia32_new_NoReg_gp(irg);
806 ir_node *sched_point = NULL;
807 ir_node *ptr = get_irg_frame(irg);
808 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
809 ir_node *new_op, *proj;
810 const arch_register_t *reg;
812 if (sched_is_scheduled(node)) {
813 sched_point = sched_prev(node);
816 if (mode_is_float(spillmode)) {
817 if (ia32_cg_config.use_sse2)
818 new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
820 new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
822 else if (get_mode_size_bits(spillmode) == 128) {
823 /* Reload 128 bit SSE registers */
824 new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
827 new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
829 set_ia32_op_type(new_op, ia32_AddrModeS);
830 set_ia32_ls_mode(new_op, spillmode);
831 set_ia32_frame_ent(new_op, ent);
832 set_ia32_use_frame(new_op);
833 set_ia32_is_reload(new_op);
835 DBG_OPT_RELOAD2LD(node, new_op);
837 proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
840 sched_add_after(sched_point, new_op);
844 /* copy the register from the old node to the new Load */
845 reg = arch_get_irn_register(node);
846 arch_set_irn_register(proj, reg);
848 SET_IA32_ORIG_NODE(new_op, node);
850 exchange(node, proj);
854 * Transforms a be_Spill node into a ia32 Store.
856 static void transform_to_Store(ir_node *node)
858 ir_graph *irg = get_irn_irg(node);
859 dbg_info *dbgi = get_irn_dbg_info(node);
860 ir_node *block = get_nodes_block(node);
861 ir_entity *ent = be_get_frame_entity(node);
862 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
863 ir_mode *mode = get_spill_mode(spillval);
864 ir_node *noreg = ia32_new_NoReg_gp(irg);
865 ir_node *nomem = get_irg_no_mem(irg);
866 ir_node *ptr = get_irg_frame(irg);
867 ir_node *val = get_irn_n(node, n_be_Spill_val);
870 ir_node *sched_point = NULL;
872 if (sched_is_scheduled(node)) {
873 sched_point = sched_prev(node);
876 if (mode_is_float(mode)) {
877 if (ia32_cg_config.use_sse2) {
878 store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
879 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
881 store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
882 res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
884 } else if (get_mode_size_bits(mode) == 128) {
885 /* Spill 128 bit SSE registers */
886 store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
887 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
888 } else if (get_mode_size_bits(mode) == 8) {
889 store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
890 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
892 store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
893 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
896 set_ia32_op_type(store, ia32_AddrModeD);
897 set_ia32_ls_mode(store, mode);
898 set_ia32_frame_ent(store, ent);
899 set_ia32_use_frame(store);
900 set_ia32_is_spill(store);
901 SET_IA32_ORIG_NODE(store, node);
902 DBG_OPT_SPILL2ST(node, store);
905 sched_add_after(sched_point, store);
912 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
914 dbg_info *dbgi = get_irn_dbg_info(node);
915 ir_node *block = get_nodes_block(node);
916 ir_graph *irg = get_irn_irg(node);
917 ir_node *noreg = ia32_new_NoReg_gp(irg);
918 ir_node *frame = get_irg_frame(irg);
920 ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
922 set_ia32_frame_ent(push, ent);
923 set_ia32_use_frame(push);
924 set_ia32_op_type(push, ia32_AddrModeS);
925 set_ia32_ls_mode(push, mode_Is);
926 set_ia32_is_spill(push);
928 sched_add_before(schedpoint, push);
932 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
934 dbg_info *dbgi = get_irn_dbg_info(node);
935 ir_node *block = get_nodes_block(node);
936 ir_graph *irg = get_irn_irg(node);
937 ir_node *noreg = ia32_new_NoReg_gp(irg);
938 ir_node *frame = get_irg_frame(irg);
940 ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
941 get_irg_no_mem(irg), sp);
943 set_ia32_frame_ent(pop, ent);
944 set_ia32_use_frame(pop);
945 set_ia32_op_type(pop, ia32_AddrModeD);
946 set_ia32_ls_mode(pop, mode_Is);
947 set_ia32_is_reload(pop);
949 sched_add_before(schedpoint, pop);
954 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
956 dbg_info *dbgi = get_irn_dbg_info(node);
957 ir_mode *spmode = mode_Iu;
958 const arch_register_t *spreg = &ia32_registers[REG_ESP];
961 sp = new_rd_Proj(dbgi, pred, spmode, pos);
962 arch_set_irn_register(sp, spreg);
968 * Transform MemPerm, currently we do this the ugly way and produce
969 * push/pop into/from memory cascades. This is possible without using
972 static void transform_MemPerm(ir_node *node)
974 ir_node *block = get_nodes_block(node);
975 ir_graph *irg = get_irn_irg(node);
976 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
977 int arity = be_get_MemPerm_entity_arity(node);
978 ir_node **pops = ALLOCAN(ir_node*, arity);
982 const ir_edge_t *edge;
983 const ir_edge_t *next;
986 for (i = 0; i < arity; ++i) {
987 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
988 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
989 ir_type *enttype = get_entity_type(inent);
990 unsigned entsize = get_type_size_bytes(enttype);
991 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
992 ir_node *mem = get_irn_n(node, i + 1);
995 /* work around cases where entities have different sizes */
996 if (entsize2 < entsize)
998 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1000 push = create_push(node, node, sp, mem, inent);
1001 sp = create_spproj(node, push, pn_ia32_Push_stack);
1003 /* add another push after the first one */
1004 push = create_push(node, node, sp, mem, inent);
1005 add_ia32_am_offs_int(push, 4);
1006 sp = create_spproj(node, push, pn_ia32_Push_stack);
1009 set_irn_n(node, i, new_r_Bad(irg, mode_X));
1013 for (i = arity - 1; i >= 0; --i) {
1014 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1015 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1016 ir_type *enttype = get_entity_type(outent);
1017 unsigned entsize = get_type_size_bytes(enttype);
1018 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1021 /* work around cases where entities have different sizes */
1022 if (entsize2 < entsize)
1024 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1026 pop = create_pop(node, node, sp, outent);
1027 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1029 add_ia32_am_offs_int(pop, 4);
1031 /* add another pop after the first one */
1032 pop = create_pop(node, node, sp, outent);
1033 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1040 keep = be_new_Keep(block, 1, in);
1041 sched_add_before(node, keep);
1043 /* exchange memprojs */
1044 foreach_out_edge_safe(node, edge, next) {
1045 ir_node *proj = get_edge_src_irn(edge);
1046 int p = get_Proj_proj(proj);
1050 set_Proj_pred(proj, pops[p]);
1051 set_Proj_proj(proj, pn_ia32_Pop_M);
1054 /* remove memperm */
1060 * Block-Walker: Calls the transform functions Spill and Reload.
1062 static void ia32_after_ra_walker(ir_node *block, void *env)
1064 ir_node *node, *prev;
1067 /* beware: the schedule is changed here */
1068 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1069 prev = sched_prev(node);
1071 if (be_is_Reload(node)) {
1072 transform_to_Load(node);
1073 } else if (be_is_Spill(node)) {
1074 transform_to_Store(node);
1075 } else if (be_is_MemPerm(node)) {
1076 transform_MemPerm(node);
1082 * Collects nodes that need frame entities assigned.
1084 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1086 be_fec_env_t *env = (be_fec_env_t*)data;
1087 const ir_mode *mode;
1090 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1091 mode = get_spill_mode_mode(get_irn_mode(node));
1092 align = get_mode_size_bytes(mode);
1093 } else if (is_ia32_irn(node) &&
1094 get_ia32_frame_ent(node) == NULL &&
1095 is_ia32_use_frame(node)) {
1096 if (is_ia32_need_stackent(node))
1099 switch (get_ia32_irn_opcode(node)) {
1101 case iro_ia32_Load: {
1102 const ia32_attr_t *attr = get_ia32_attr_const(node);
1104 if (attr->data.need_32bit_stackent) {
1106 } else if (attr->data.need_64bit_stackent) {
1109 mode = get_ia32_ls_mode(node);
1110 if (is_ia32_is_reload(node))
1111 mode = get_spill_mode_mode(mode);
1113 align = get_mode_size_bytes(mode);
1117 case iro_ia32_vfild:
1119 case iro_ia32_xLoad: {
1120 mode = get_ia32_ls_mode(node);
1125 case iro_ia32_FldCW: {
1126 /* although 2 byte would be enough 4 byte performs best */
1134 panic("unexpected frame user while collection frame entity nodes");
1136 case iro_ia32_FnstCW:
1137 case iro_ia32_Store8Bit:
1138 case iro_ia32_Store:
1141 case iro_ia32_vfist:
1142 case iro_ia32_vfisttp:
1144 case iro_ia32_xStore:
1145 case iro_ia32_xStoreSimple:
1152 be_node_needs_frame_entity(env, node, mode, align);
1155 static int determine_ebp_input(ir_node *ret)
1157 const arch_register_t *bp = &ia32_registers[REG_EBP];
1158 int arity = get_irn_arity(ret);
1161 for (i = 0; i < arity; ++i) {
1162 ir_node *input = get_irn_n(ret, i);
1163 if (arch_get_irn_register(input) == bp)
1166 panic("no ebp input found at %+F", ret);
1169 static void introduce_epilog(ir_node *ret)
1171 const arch_register_t *sp = &ia32_registers[REG_ESP];
1172 const arch_register_t *bp = &ia32_registers[REG_EBP];
1173 ir_graph *irg = get_irn_irg(ret);
1174 ir_type *frame_type = get_irg_frame_type(irg);
1175 unsigned frame_size = get_type_size_bytes(frame_type);
1176 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1177 ir_node *block = get_nodes_block(ret);
1178 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1179 ir_node *curr_sp = first_sp;
1180 ir_mode *mode_gp = mode_Iu;
1182 if (!layout->sp_relative) {
1183 int n_ebp = determine_ebp_input(ret);
1184 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1185 if (ia32_cg_config.use_leave) {
1186 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1187 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1188 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1189 arch_set_irn_register(curr_bp, bp);
1190 arch_set_irn_register(curr_sp, sp);
1191 sched_add_before(ret, leave);
1194 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1195 /* copy ebp to esp */
1196 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1197 arch_set_irn_register(curr_sp, sp);
1198 sched_add_before(ret, curr_sp);
1201 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1202 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1203 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1204 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1205 arch_set_irn_register(curr_bp, bp);
1206 arch_set_irn_register(curr_sp, sp);
1207 sched_add_before(ret, pop);
1209 set_irn_n(ret, n_be_Return_mem, curr_mem);
1211 set_irn_n(ret, n_ebp, curr_bp);
1213 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1214 sched_add_before(ret, incsp);
1217 set_irn_n(ret, n_be_Return_sp, curr_sp);
1219 /* keep verifier happy... */
1220 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1221 kill_node(first_sp);
1226 * put the Prolog code at the beginning, epilog code before each return
1228 static void introduce_prolog_epilog(ir_graph *irg)
1230 const arch_register_t *sp = &ia32_registers[REG_ESP];
1231 const arch_register_t *bp = &ia32_registers[REG_EBP];
1232 ir_node *start = get_irg_start(irg);
1233 ir_node *block = get_nodes_block(start);
1234 ir_type *frame_type = get_irg_frame_type(irg);
1235 unsigned frame_size = get_type_size_bytes(frame_type);
1236 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1237 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1238 ir_node *curr_sp = initial_sp;
1239 ir_mode *mode_gp = mode_Iu;
1241 if (!layout->sp_relative) {
1243 ir_node *mem = get_irg_initial_mem(irg);
1244 ir_node *noreg = ia32_new_NoReg_gp(irg);
1245 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1246 ir_node *curr_bp = initial_bp;
1247 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
1250 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1251 mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
1252 arch_set_irn_register(curr_sp, sp);
1253 sched_add_after(start, push);
1255 /* move esp to ebp */
1256 curr_bp = be_new_Copy(block, curr_sp);
1257 sched_add_after(push, curr_bp);
1258 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1259 curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
1260 sched_add_after(curr_bp, curr_sp);
1261 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1262 edges_reroute(initial_bp, curr_bp);
1263 set_irn_n(push, n_ia32_Push_val, initial_bp);
1265 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1266 edges_reroute(initial_sp, incsp);
1267 set_irn_n(push, n_ia32_Push_stack, initial_sp);
1268 sched_add_after(curr_sp, incsp);
1270 /* make sure the initial IncSP is really used by someone */
1271 if (get_irn_n_edges(incsp) <= 1) {
1272 ir_node *in[] = { incsp };
1273 ir_node *keep = be_new_Keep(block, 1, in);
1274 sched_add_after(incsp, keep);
1277 layout->initial_bias = -4;
1279 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1280 edges_reroute(initial_sp, incsp);
1281 be_set_IncSP_pred(incsp, curr_sp);
1282 sched_add_after(start, incsp);
1285 /* introduce epilog for every return node */
1287 ir_node *end_block = get_irg_end_block(irg);
1288 int arity = get_irn_arity(end_block);
1291 for (i = 0; i < arity; ++i) {
1292 ir_node *ret = get_irn_n(end_block, i);
1293 assert(be_is_Return(ret));
1294 introduce_epilog(ret);
1300 * Last touchups for the graph before emit: x87 simulation to replace the
1301 * virtual with real x87 instructions, creating a block schedule and peephole
1304 static void ia32_finish_graph(ir_graph *irg)
1306 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1307 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1308 bool at_begin = stack_layout->sp_relative ? true : false;
1309 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1311 /* create and coalesce frame entities */
1312 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1313 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1314 be_free_frame_entity_coalescer(fec_env);
1316 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1318 introduce_prolog_epilog(irg);
1320 /* fix stack entity offsets */
1321 be_abi_fix_stack_nodes(irg);
1322 be_abi_fix_stack_bias(irg);
1324 /* fix 2-address code constraints */
1325 ia32_finish_irg(irg);
1327 /* we might have to rewrite x87 virtual registers */
1328 if (irg_data->do_x87_sim) {
1329 ia32_x87_simulate_graph(irg);
1332 /* do peephole optimisations */
1333 ia32_peephole_optimization(irg);
1335 be_remove_dead_nodes_from_schedule(irg);
1337 /* create block schedule, this also removes empty blocks which might
1338 * produce critical edges */
1339 irg_data->blk_sched = be_create_block_schedule(irg);
1343 * Emits the code, closes the output file and frees
1344 * the code generator interface.
1346 static void ia32_emit(ir_graph *irg)
1348 if (ia32_cg_config.emit_machcode) {
1349 ia32_gen_binary_routine(irg);
1351 ia32_gen_routine(irg);
1356 * Returns the node representing the PIC base.
1358 static ir_node *ia32_get_pic_base(ir_graph *irg)
1360 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1362 ir_node *get_eip = irg_data->get_eip;
1363 if (get_eip != NULL)
1366 block = get_irg_start_block(irg);
1367 get_eip = new_bd_ia32_GetEIP(NULL, block);
1368 irg_data->get_eip = get_eip;
1374 * Initializes a IA32 code generator.
1376 static void ia32_init_graph(ir_graph *irg)
1378 struct obstack *obst = be_get_be_obst(irg);
1379 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1381 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1384 /* Linux gprof implementation needs base pointer */
1385 be_get_irg_options(irg)->omit_fp = 0;
1388 be_birg_from_irg(irg)->isa_link = irg_data;
1391 static const tarval_mode_info mo_integer = {
1398 * set the tarval output mode of all integer modes to decimal
1400 static void set_tarval_output_modes(void)
1404 for (i = ir_get_n_modes(); i > 0;) {
1405 ir_mode *mode = ir_get_mode(--i);
1407 if (mode_is_int(mode))
1408 set_tarval_mode_output_option(mode, &mo_integer);
1412 extern const arch_isa_if_t ia32_isa_if;
1414 static void init_asm_constraints(void)
1416 be_init_default_asm_constraint_flags();
1418 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1419 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1420 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1421 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1422 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1423 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1424 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1425 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1426 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1427 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1428 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1429 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1430 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1431 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1432 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1433 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1434 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1435 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1436 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1437 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1439 /* no support for autodecrement/autoincrement */
1440 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1441 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1442 /* no float consts */
1443 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1444 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1445 /* makes no sense on x86 */
1446 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1447 /* no support for sse consts yet */
1448 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1449 /* no support for x87 consts yet */
1450 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1451 /* no support for mmx registers yet */
1452 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1453 /* not available in 32bit mode */
1454 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1455 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1457 /* no code yet to determine register class needed... */
1458 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1462 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1464 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1469 ir_relation relation;
1474 cmp_l = get_Cmp_left(sel);
1475 cmp_r = get_Cmp_right(sel);
1476 if (!mode_is_float(get_irn_mode(cmp_l)))
1479 /* check for min/max. They're defined as (C-Semantik):
1480 * min(a, b) = a < b ? a : b
1481 * or min(a, b) = a <= b ? a : b
1482 * max(a, b) = a > b ? a : b
1483 * or max(a, b) = a >= b ? a : b
1484 * (Note we only handle float min/max here)
1486 relation = get_Cmp_relation(sel);
1488 case ir_relation_greater_equal:
1489 case ir_relation_greater:
1491 if (cmp_l == mux_true && cmp_r == mux_false)
1494 case ir_relation_less_equal:
1495 case ir_relation_less:
1497 if (cmp_l == mux_true && cmp_r == mux_false)
1500 case ir_relation_unordered_greater_equal:
1501 case ir_relation_unordered_greater:
1503 if (cmp_l == mux_false && cmp_r == mux_true)
1506 case ir_relation_unordered_less_equal:
1507 case ir_relation_unordered_less:
1509 if (cmp_l == mux_false && cmp_r == mux_true)
1520 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1522 ir_mode *mode = get_irn_mode(mux_true);
1525 if (!mode_is_int(mode) && !mode_is_reference(mode)
1529 if (is_Const(mux_true) && is_Const(mux_false)) {
1530 /* we can create a set plus up two 3 instructions for any combination
1538 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1543 if (!mode_is_float(get_irn_mode(mux_true)))
1546 return is_Const(mux_true) && is_Const(mux_false);
1549 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1556 ir_relation relation;
1561 mode = get_irn_mode(mux_true);
1562 if (mode_is_signed(mode) || mode_is_float(mode))
1565 relation = get_Cmp_relation(sel);
1566 cmp_left = get_Cmp_left(sel);
1567 cmp_right = get_Cmp_right(sel);
1569 /* "move" zero constant to false input */
1570 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1571 ir_node *tmp = mux_false;
1572 mux_false = mux_true;
1574 relation = get_negated_relation(relation);
1576 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1578 if (!is_Sub(mux_true))
1580 sub_left = get_Sub_left(mux_true);
1581 sub_right = get_Sub_right(mux_true);
1583 /* Mux(a >=u b, 0, a-b) */
1584 if ((relation & ir_relation_greater)
1585 && sub_left == cmp_left && sub_right == cmp_right)
1587 /* Mux(a <=u b, 0, b-a) */
1588 if ((relation & ir_relation_less)
1589 && sub_left == cmp_right && sub_right == cmp_left)
1595 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1600 /* middleend can handle some things */
1601 if (ir_is_optimizable_mux(sel, mux_false, mux_true))
1603 /* we can handle Set for all modes and compares */
1604 if (mux_is_set(sel, mux_true, mux_false))
1606 /* SSE has own min/max operations */
1607 if (ia32_cg_config.use_sse2
1608 && mux_is_float_min_max(sel, mux_true, mux_false))
1610 /* we can handle Mux(?, Const[f], Const[f]) */
1611 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1612 #ifdef FIRM_GRGEN_BE
1613 /* well, some code selectors can't handle it */
1614 if (be_transformer != TRANSFORMER_PBQP
1615 || be_transformer != TRANSFORMER_RAND)
1622 /* no support for 64bit inputs to cmov */
1623 mode = get_irn_mode(mux_true);
1624 if (get_mode_size_bits(mode) > 32)
1626 /* we can handle Abs for all modes and compares (except 64bit) */
1627 if (ir_mux_is_abs(sel, mux_false, mux_true) != 0)
1629 /* we can't handle MuxF yet */
1630 if (mode_is_float(mode))
1633 if (mux_is_doz(sel, mux_true, mux_false))
1636 /* Check Cmp before the node */
1638 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1640 /* we can't handle 64bit compares */
1641 if (get_mode_size_bits(cmp_mode) > 32)
1644 /* we can't handle float compares */
1645 if (mode_is_float(cmp_mode))
1649 /* did we disable cmov generation? */
1650 if (!ia32_cg_config.use_cmov)
1653 /* we can use a cmov */
1658 * Create the trampoline code.
1660 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
1662 ir_graph *const irg = get_irn_irg(block);
1663 ir_node * p = trampoline;
1664 ir_mode *const mode = get_irn_mode(p);
1665 ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
1666 ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
1670 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
1671 mem = new_r_Proj(st, mode_M, pn_Store_M);
1672 p = new_r_Add(block, p, one, mode);
1673 st = new_r_Store(block, mem, p, env, cons_none);
1674 mem = new_r_Proj(st, mode_M, pn_Store_M);
1675 p = new_r_Add(block, p, four, mode);
1677 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
1678 mem = new_r_Proj(st, mode_M, pn_Store_M);
1679 p = new_r_Add(block, p, one, mode);
1680 st = new_r_Store(block, mem, p, callee, cons_none);
1681 mem = new_r_Proj(st, mode_M, pn_Store_M);
1682 p = new_r_Add(block, p, four, mode);
1687 static const ir_settings_arch_dep_t ia32_arch_dep = {
1688 1, /* also use subs */
1689 4, /* maximum shifts */
1690 63, /* maximum shift amount */
1691 ia32_evaluate_insn, /* evaluate the instruction sequence */
1693 1, /* allow Mulhs */
1694 1, /* allow Mulus */
1695 32, /* Mulh allowed up to 32 bit */
1697 static backend_params ia32_backend_params = {
1698 1, /* support inline assembly */
1699 1, /* support Rotl nodes */
1700 0, /* little endian */
1701 1, /* modulo shift efficient */
1702 0, /* non-modulo shift not efficient */
1703 &ia32_arch_dep, /* will be set later */
1704 ia32_is_mux_allowed,
1705 32, /* machine_size */
1706 NULL, /* float arithmetic mode, will be set below */
1707 NULL, /* long long type */
1708 NULL, /* unsigned long long type */
1709 NULL, /* long double type */
1710 12, /* size of trampoline code */
1711 4, /* alignment of trampoline code */
1712 ia32_create_trampoline_fkt,
1713 4 /* alignment of stack parameter */
1717 * Initializes the backend ISA.
1719 static void ia32_init(void)
1721 ir_mode *mode_long_long;
1722 ir_mode *mode_unsigned_long_long;
1723 ir_type *type_long_long;
1724 ir_type *type_unsigned_long_long;
1726 ia32_setup_cg_config();
1728 init_asm_constraints();
1730 ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0);
1732 /* note mantissa is 64bit but with explicitely encoded 1 so the really
1733 * usable part as counted by firm is only 63 bits */
1734 ia32_mode_E = new_float_mode("E", irma_x86_extended_float, 15, 63);
1735 ia32_type_E = new_type_primitive(ia32_mode_E);
1736 set_type_size_bytes(ia32_type_E, 12);
1737 set_type_alignment_bytes(ia32_type_E, 16);
1739 mode_long_long = new_int_mode("long long", irma_twos_complement, 64, 1, 64);
1740 type_long_long = new_type_primitive(mode_long_long);
1741 mode_unsigned_long_long
1742 = new_int_mode("unsigned long long", irma_twos_complement, 64, 0, 64);
1743 type_unsigned_long_long = new_type_primitive(mode_unsigned_long_long);
1745 ia32_backend_params.type_long_long = type_long_long;
1746 ia32_backend_params.type_unsigned_long_long = type_unsigned_long_long;
1748 if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
1749 ia32_backend_params.mode_float_arithmetic = NULL;
1750 ia32_backend_params.type_long_double = NULL;
1752 ia32_backend_params.mode_float_arithmetic = ia32_mode_E;
1753 ia32_backend_params.type_long_double = ia32_type_E;
1756 ia32_register_init();
1757 obstack_init(&opcodes_obst);
1758 ia32_create_opcodes(&ia32_irn_ops);
1761 static void ia32_finish(void)
1763 if (between_type != NULL) {
1764 free_type(between_type);
1765 between_type = NULL;
1767 ia32_free_opcodes();
1768 obstack_free(&opcodes_obst, NULL);
1772 * The template that generates a new ISA object.
1773 * Note that this template can be changed by command line
1776 static ia32_isa_t ia32_isa_template = {
1778 &ia32_isa_if, /* isa interface implementation */
1783 &ia32_registers[REG_ESP], /* stack pointer register */
1784 &ia32_registers[REG_EBP], /* base pointer register */
1785 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1786 2, /* power of two stack alignment, 2^2 == 4 */
1787 NULL, /* main environment */
1788 7, /* costs for a spill instruction */
1789 5, /* costs for a reload instruction */
1790 false, /* no custom abi handling */
1793 IA32_FPU_ARCH_X87, /* FPU architecture */
1796 static arch_env_t *ia32_begin_codegeneration(const be_main_env_t *env)
1798 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1800 set_tarval_output_modes();
1802 *isa = ia32_isa_template;
1803 isa->tv_ent = pmap_create();
1805 /* enter the ISA object into the intrinsic environment */
1806 intrinsic_env.isa = isa;
1808 be_emit_init(env->file_handle);
1809 be_gas_begin_compilation_unit(env);
1815 * Closes the output file and frees the ISA structure.
1817 static void ia32_end_codegeneration(void *self)
1819 ia32_isa_t *isa = (ia32_isa_t*)self;
1821 /* emit now all global declarations */
1822 be_gas_end_compilation_unit(isa->base.main_env);
1826 pmap_destroy(isa->tv_ent);
1831 * Returns the register for parameter nr.
1833 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1834 const ir_mode *mode)
1836 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1837 &ia32_registers[REG_ECX],
1838 &ia32_registers[REG_EDX],
1841 static const unsigned MAXNUM_GPREG_ARGS = 3;
1843 static const arch_register_t *gpreg_param_reg_regparam[] = {
1844 &ia32_registers[REG_EAX],
1845 &ia32_registers[REG_EDX],
1846 &ia32_registers[REG_ECX]
1849 static const arch_register_t *gpreg_param_reg_this[] = {
1850 &ia32_registers[REG_ECX],
1855 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1856 &ia32_registers[REG_XMM0],
1857 &ia32_registers[REG_XMM1],
1858 &ia32_registers[REG_XMM2],
1859 &ia32_registers[REG_XMM3],
1860 &ia32_registers[REG_XMM4],
1861 &ia32_registers[REG_XMM5],
1862 &ia32_registers[REG_XMM6],
1863 &ia32_registers[REG_XMM7]
1866 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1867 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1869 static const unsigned MAXNUM_SSE_ARGS = 8;
1871 if ((cc & cc_this_call) && nr == 0)
1872 return gpreg_param_reg_this[0];
1874 if (! (cc & cc_reg_param))
1877 if (mode_is_float(mode)) {
1878 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1880 if (nr >= MAXNUM_SSE_ARGS)
1883 if (cc & cc_this_call) {
1884 return fpreg_sse_param_reg_this[nr];
1886 return fpreg_sse_param_reg_std[nr];
1887 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1888 unsigned num_regparam;
1890 if (get_mode_size_bits(mode) > 32)
1893 if (nr >= MAXNUM_GPREG_ARGS)
1896 if (cc & cc_this_call) {
1897 return gpreg_param_reg_this[nr];
1899 num_regparam = cc & ~cc_bits;
1900 if (num_regparam == 0) {
1901 /* default fastcall */
1902 return gpreg_param_reg_fastcall[nr];
1904 if (nr < num_regparam)
1905 return gpreg_param_reg_regparam[nr];
1909 panic("unknown argument mode");
1913 * Get the ABI restrictions for procedure calls.
1915 static void ia32_get_call_abi(ir_type *method_type, be_abi_call_t *abi)
1920 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1922 /* set abi flags for calls */
1923 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1924 call_flags.bits.call_has_imm = false; /* No call immediate, we handle this by ourselves */
1926 /* set parameter passing style */
1927 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1929 cc = get_method_calling_convention(method_type);
1930 if (get_method_variadicity(method_type) == variadicity_variadic) {
1931 /* pass all parameters of a variadic function on the stack */
1932 cc = cc_cdecl_set | (cc & cc_this_call);
1934 if (get_method_additional_properties(method_type) & mtp_property_private &&
1935 ia32_cg_config.optimize_cc) {
1936 /* set the fast calling conventions (allowing up to 3) */
1937 cc = SET_FASTCALL(cc) | 3;
1941 /* we have to pop the shadow parameter ourself for compound calls */
1942 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1943 && !(cc & cc_reg_param)) {
1944 pop_amount += get_mode_size_bytes(mode_P_data);
1947 n = get_method_n_params(method_type);
1948 for (i = regnum = 0; i < n; i++) {
1949 const arch_register_t *reg = NULL;
1950 ir_type *tp = get_method_param_type(method_type, i);
1951 ir_mode *mode = get_type_mode(tp);
1954 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1957 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1960 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1961 * movl has a shorter opcode than mov[sz][bw]l */
1962 ir_mode *load_mode = mode;
1965 unsigned size = get_mode_size_bytes(mode);
1967 if (cc & cc_callee_clear_stk) {
1968 pop_amount += (size + 3U) & ~3U;
1971 if (size < 4) load_mode = mode_Iu;
1974 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1978 be_abi_call_set_pop(abi, pop_amount);
1980 /* set return registers */
1981 n = get_method_n_ress(method_type);
1983 assert(n <= 2 && "more than two results not supported");
1985 /* In case of 64bit returns, we will have two 32bit values */
1987 ir_type *tp = get_method_res_type(method_type, 0);
1988 ir_mode *mode = get_type_mode(tp);
1990 assert(!mode_is_float(mode) && "two FP results not supported");
1992 tp = get_method_res_type(method_type, 1);
1993 mode = get_type_mode(tp);
1995 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1997 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1998 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
2001 ir_type *tp = get_method_res_type(method_type, 0);
2002 ir_mode *mode = get_type_mode(tp);
2003 const arch_register_t *reg;
2004 assert(is_atomic_type(tp));
2006 reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
2008 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
2012 static void ia32_mark_remat(ir_node *node)
2014 if (is_ia32_irn(node)) {
2015 set_ia32_is_remat(node);
2019 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2023 /* we already added all our simple flags to the flags modifier list in
2024 * init, so this flag we don't know. */
2025 return ASM_CONSTRAINT_FLAG_INVALID;
2028 static int ia32_is_valid_clobber(const char *clobber)
2030 return ia32_get_clobber_register(clobber) != NULL;
2033 static void ia32_lower_for_target(void)
2035 size_t i, n_irgs = get_irp_n_irgs();
2037 /* perform doubleword lowering */
2038 lwrdw_param_t lower_dw_params = {
2039 1, /* little endian */
2040 64, /* doubleword size */
2041 ia32_create_intrinsic_fkt,
2045 /* lower compound param handling
2046 * Note: we lower compound arguments ourself, since on ia32 we don't
2047 * have hidden parameters but know where to find the structs on the stack.
2048 * (This also forces us to always allocate space for the compound arguments
2049 * on the callframe and we can't just use an arbitrary position on the
2052 lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS);
2054 /* replace floating point operations by function calls */
2055 if (ia32_cg_config.use_softfloat) {
2056 lower_floating_point();
2059 ir_prepare_dw_lowering(&lower_dw_params);
2062 for (i = 0; i < n_irgs; ++i) {
2063 ir_graph *irg = get_irp_irg(i);
2064 /* lower for mode_b stuff */
2065 ir_lower_mode_b(irg, mode_Iu);
2066 /* break up switches with wide ranges */
2067 lower_switch(irg, 4, 256, false);
2070 for (i = 0; i < n_irgs; ++i) {
2071 ir_graph *irg = get_irp_irg(i);
2072 /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
2073 * so we can generate rep movs later, and turn all big CopyBs into
2075 lower_CopyB(irg, 64, 8193, true);
2080 * Returns the libFirm configuration parameter for this backend.
2082 static const backend_params *ia32_get_libfirm_params(void)
2084 return &ia32_backend_params;
2088 * Check if the given register is callee or caller save.
2090 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
2093 /* check for callee saved */
2094 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2095 switch (reg->index) {
2106 /* check for caller saved */
2107 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2108 switch (reg->index) {
2116 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
2117 /* all XMM registers are caller save */
2118 return reg->index != REG_XMM_NOREG;
2119 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
2120 /* all VFP registers are caller save */
2121 return reg->index != REG_VFP_NOREG;
2127 static const lc_opt_enum_int_items_t gas_items[] = {
2128 { "elf", OBJECT_FILE_FORMAT_ELF },
2129 { "mingw", OBJECT_FILE_FORMAT_COFF },
2130 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2134 static lc_opt_enum_int_var_t gas_var = {
2135 (int*) &be_gas_object_file_format, gas_items
2138 #ifdef FIRM_GRGEN_BE
2139 static const lc_opt_enum_int_items_t transformer_items[] = {
2140 { "default", TRANSFORMER_DEFAULT },
2141 { "pbqp", TRANSFORMER_PBQP },
2142 { "random", TRANSFORMER_RAND },
2146 static lc_opt_enum_int_var_t transformer_var = {
2147 (int*)&be_transformer, transformer_items
2151 static const lc_opt_table_entry_t ia32_options[] = {
2152 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2153 #ifdef FIRM_GRGEN_BE
2154 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2156 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2157 &ia32_isa_template.base.stack_alignment),
2158 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2162 const arch_isa_if_t ia32_isa_if = {
2165 ia32_get_libfirm_params,
2166 ia32_lower_for_target,
2167 ia32_parse_asm_constraint,
2168 ia32_is_valid_clobber,
2170 ia32_begin_codegeneration,
2171 ia32_end_codegeneration,
2175 ia32_get_pic_base, /* return node used as base in pic code addresses */
2178 ia32_register_saved_by,
2180 ia32_handle_intrinsics,
2181 ia32_before_abi, /* before abi introduce hook */
2183 ia32_before_ra, /* before register allocation hook */
2184 ia32_finish_graph, /* called before codegen */
2185 ia32_emit, /* emit && done */
2188 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2189 void be_init_arch_ia32(void)
2191 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2192 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2194 lc_opt_add_table(ia32_grp, ia32_options);
2195 be_register_isa_if("ia32", &ia32_isa_if);
2197 ia32_init_emitter();
2199 ia32_init_optimize();
2200 ia32_init_transform();
2202 ia32_init_architecture();