2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
57 #include "../benode.h"
58 #include "../belower.h"
59 #include "../besched.h"
62 #include "../beirgmod.h"
63 #include "../be_dbgout.h"
64 #include "../beblocksched.h"
65 #include "../bemachine.h"
66 #include "../beilpsched.h"
67 #include "../bespillslots.h"
68 #include "../bemodule.h"
69 #include "../begnuas.h"
70 #include "../bestate.h"
71 #include "../beflags.h"
72 #include "../betranshlp.h"
73 #include "../belistsched.h"
74 #include "../beabihelper.h"
76 #include "bearch_ia32_t.h"
78 #include "ia32_new_nodes.h"
79 #include "gen_ia32_regalloc_if.h"
80 #include "gen_ia32_machine.h"
81 #include "ia32_common_transform.h"
82 #include "ia32_transform.h"
83 #include "ia32_emitter.h"
84 #include "ia32_map_regs.h"
85 #include "ia32_optimize.h"
87 #include "ia32_dbg_stat.h"
88 #include "ia32_finish.h"
89 #include "ia32_util.h"
91 #include "ia32_architecture.h"
94 #include "ia32_pbqp_transform.h"
96 transformer_t be_transformer = TRANSFORMER_DEFAULT;
99 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
101 ir_mode *mode_fpcw = NULL;
103 /** The current omit-fp state */
104 static unsigned ia32_curr_fp_ommitted = 0;
105 static ir_type *omit_fp_between_type = NULL;
106 static ir_type *between_type = NULL;
107 static ir_entity *old_bp_ent = NULL;
108 static ir_entity *ret_addr_ent = NULL;
109 static ir_entity *omit_fp_ret_addr_ent = NULL;
112 * The environment for the intrinsic mapping.
114 static ia32_intrinsic_env_t intrinsic_env = {
116 NULL, /* the irg, these entities belong to */
117 NULL, /* entity for __divdi3 library call */
118 NULL, /* entity for __moddi3 library call */
119 NULL, /* entity for __udivdi3 library call */
120 NULL, /* entity for __umoddi3 library call */
124 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
127 * Used to create per-graph unique pseudo nodes.
129 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
130 create_const_node_func func,
131 const arch_register_t* reg)
133 ir_node *block, *res;
138 block = get_irg_start_block(irg);
139 res = func(NULL, block);
140 arch_set_irn_register(res, reg);
146 /* Creates the unique per irg GP NoReg node. */
147 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
149 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
150 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
151 &ia32_gp_regs[REG_GP_NOREG]);
154 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
156 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
157 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
158 &ia32_vfp_regs[REG_VFP_NOREG]);
161 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
163 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
164 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
165 &ia32_xmm_regs[REG_XMM_NOREG]);
168 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
170 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
171 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
172 &ia32_fp_cw_regs[REG_FPCW]);
177 * Returns the admissible noreg register node for input register pos of node irn.
179 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
181 ir_graph *irg = get_irn_irg(irn);
182 const arch_register_req_t *req = arch_get_register_req(irn, pos);
184 assert(req != NULL && "Missing register requirements");
185 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
186 return ia32_new_NoReg_gp(irg);
188 if (ia32_cg_config.use_sse2) {
189 return ia32_new_NoReg_xmm(irg);
191 return ia32_new_NoReg_vfp(irg);
195 static arch_irn_class_t ia32_classify(const ir_node *irn)
197 arch_irn_class_t classification = 0;
199 assert(is_ia32_irn(irn));
201 if (is_ia32_is_reload(irn))
202 classification |= arch_irn_class_reload;
204 if (is_ia32_is_spill(irn))
205 classification |= arch_irn_class_spill;
207 if (is_ia32_is_remat(irn))
208 classification |= arch_irn_class_remat;
210 return classification;
214 * The IA32 ABI callback object.
217 be_abi_call_flags_bits_t flags; /**< The call flags. */
218 ir_graph *irg; /**< The associated graph. */
221 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
223 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
226 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
228 if (is_be_node(node))
229 be_node_set_frame_entity(node, entity);
231 set_ia32_frame_ent(node, entity);
234 static void ia32_set_frame_offset(ir_node *irn, int bias)
236 if (get_ia32_frame_ent(irn) == NULL)
239 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
240 ir_graph *irg = get_irn_irg(irn);
241 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
242 if (layout->sp_relative) {
243 /* Pop nodes modify the stack pointer before calculating the
244 * destination address, so fix this here
249 add_ia32_am_offs_int(irn, bias);
252 static int ia32_get_sp_bias(const ir_node *node)
254 if (is_ia32_Call(node))
255 return -(int)get_ia32_call_attr_const(node)->pop;
257 if (is_ia32_Push(node))
260 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
267 * Generate the routine prologue.
269 * @param self The callback object.
270 * @param mem A pointer to the mem node. Update this if you define new memory.
271 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
272 * @param stack_bias Points to the current stack bias, can be modified if needed.
274 * @return The register which shall be used as a stack frame base.
276 * All nodes which define registers in @p reg_map must keep @p reg_map current.
278 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
280 ia32_abi_env_t *env = self;
281 ir_graph *irg = env->irg;
282 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
284 ia32_curr_fp_ommitted = env->flags.try_omit_fp;
285 if (! env->flags.try_omit_fp) {
286 ir_node *bl = get_irg_start_block(env->irg);
287 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
288 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
289 ir_node *noreg = ia32_new_NoReg_gp(irg);
292 /* mark bp register as ignore */
293 be_set_constr_single_reg_out(get_Proj_pred(curr_bp),
294 get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
297 push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
298 curr_sp = new_r_Proj(push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
299 *mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
301 /* the push must have SP out register */
302 arch_set_irn_register(curr_sp, arch_env->sp);
304 /* this modifies the stack bias, because we pushed 32bit */
307 /* move esp to ebp */
308 curr_bp = be_new_Copy(arch_env->bp->reg_class, bl, curr_sp);
309 be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
310 arch_register_req_type_ignore);
312 /* beware: the copy must be done before any other sp use */
313 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
314 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
315 arch_register_req_type_produces_sp);
317 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
318 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
327 * Generate the routine epilogue.
328 * @param self The callback object.
329 * @param bl The block for the epilog
330 * @param mem A pointer to the mem node. Update this if you define new memory.
331 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
332 * @return The register which shall be used as a stack frame base.
334 * All nodes which define registers in @p reg_map must keep @p reg_map current.
336 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
338 ia32_abi_env_t *env = self;
339 const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
340 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
341 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
343 if (env->flags.try_omit_fp) {
344 /* simply remove the stack frame here */
345 curr_sp = be_new_IncSP(arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
347 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
349 if (ia32_cg_config.use_leave) {
353 leave = new_bd_ia32_Leave(NULL, bl, curr_bp);
354 curr_bp = new_r_Proj(leave, mode_bp, pn_ia32_Leave_frame);
355 curr_sp = new_r_Proj(leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
359 /* the old SP is not needed anymore (kill the proj) */
360 assert(is_Proj(curr_sp));
363 /* copy ebp to esp */
364 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], bl, curr_bp);
365 arch_set_irn_register(curr_sp, arch_env->sp);
366 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
367 arch_register_req_type_ignore);
370 pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
371 curr_bp = new_r_Proj(pop, mode_bp, pn_ia32_Pop_res);
372 curr_sp = new_r_Proj(pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
374 *mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
376 arch_set_irn_register(curr_sp, arch_env->sp);
377 arch_set_irn_register(curr_bp, arch_env->bp);
380 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
381 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
385 * Initialize the callback object.
386 * @param call The call object.
387 * @param irg The graph with the method.
388 * @return Some pointer. This pointer is passed to all other callback functions as self object.
390 static void *ia32_abi_init(const be_abi_call_t *call, ir_graph *irg)
392 ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
393 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
394 env->flags = fl.bits;
400 * Destroy the callback object.
401 * @param self The callback object.
403 static void ia32_abi_done(void *self)
409 * Build the between type and entities if not already build.
411 static void ia32_build_between_type(void)
413 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
414 if (! between_type) {
415 ir_type *old_bp_type = new_type_primitive(mode_Iu);
416 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
418 between_type = new_type_struct(IDENT("ia32_between_type"));
419 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
420 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
422 set_entity_offset(old_bp_ent, 0);
423 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
424 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
425 set_type_state(between_type, layout_fixed);
427 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
428 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
430 set_entity_offset(omit_fp_ret_addr_ent, 0);
431 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
432 set_type_state(omit_fp_between_type, layout_fixed);
438 * Produces the type which sits between the stack args and the locals on the stack.
439 * it will contain the return address and space to store the old base pointer.
440 * @return The Firm type modeling the ABI between type.
442 static ir_type *ia32_abi_get_between_type(void *self)
444 ia32_abi_env_t *env = self;
446 ia32_build_between_type();
447 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
451 * Return the stack entity that contains the return address.
453 ir_entity *ia32_get_return_address_entity(void)
455 ia32_build_between_type();
456 return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent;
460 * Return the stack entity that contains the frame address.
462 ir_entity *ia32_get_frame_address_entity(void)
464 ia32_build_between_type();
465 return ia32_curr_fp_ommitted ? NULL : old_bp_ent;
469 * Get the estimated cycle count for @p irn.
471 * @param self The this pointer.
472 * @param irn The node.
474 * @return The estimated cycle count for this operation
476 static int ia32_get_op_estimated_cost(const ir_node *irn)
479 ia32_op_type_t op_tp;
483 if (!is_ia32_irn(irn))
486 assert(is_ia32_irn(irn));
488 cost = get_ia32_latency(irn);
489 op_tp = get_ia32_op_type(irn);
491 if (is_ia32_CopyB(irn)) {
494 else if (is_ia32_CopyB_i(irn)) {
495 int size = get_ia32_copyb_size(irn);
496 cost = 20 + (int)ceil((4/3) * size);
498 /* in case of address mode operations add additional cycles */
499 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
501 In case of stack access and access to fixed addresses add 5 cycles
502 (we assume they are in cache), other memory operations cost 20
505 if (is_ia32_use_frame(irn) || (
506 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
507 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
519 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
521 * @param irn The original operation
522 * @param i Index of the argument we want the inverse operation to yield
523 * @param inverse struct to be filled with the resulting inverse op
524 * @param obstack The obstack to use for allocation of the returned nodes array
525 * @return The inverse operation or NULL if operation invertible
527 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
538 ir_node *block, *noreg, *nomem;
541 /* we cannot invert non-ia32 irns */
542 if (! is_ia32_irn(irn))
545 /* operand must always be a real operand (not base, index or mem) */
546 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
549 /* we don't invert address mode operations */
550 if (get_ia32_op_type(irn) != ia32_Normal)
553 /* TODO: adjust for new immediates... */
554 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
558 block = get_nodes_block(irn);
559 mode = get_irn_mode(irn);
560 irn_mode = get_irn_mode(irn);
561 noreg = get_irn_n(irn, 0);
563 dbg = get_irn_dbg_info(irn);
565 /* initialize structure */
566 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
570 switch (get_ia32_irn_opcode(irn)) {
573 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
574 /* we have an add with a const here */
575 /* invers == add with negated const */
576 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
578 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
579 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
580 set_ia32_commutative(inverse->nodes[0]);
582 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
583 /* we have an add with a symconst here */
584 /* invers == sub with const */
585 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
587 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
590 /* normal add: inverse == sub */
591 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
598 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
599 /* we have a sub with a const/symconst here */
600 /* invers == add with this const */
601 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
602 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
603 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
607 if (i == n_ia32_binary_left) {
608 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
611 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
619 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
620 /* xor with const: inverse = xor */
621 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
622 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
623 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
627 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
633 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
638 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
643 /* inverse operation not supported */
651 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
653 if (mode_is_float(mode))
660 * Get the mode that should be used for spilling value node
662 static ir_mode *get_spill_mode(const ir_node *node)
664 ir_mode *mode = get_irn_mode(node);
665 return get_spill_mode_mode(mode);
669 * Checks whether an addressmode reload for a node with mode mode is compatible
670 * with a spillslot of mode spill_mode
672 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
674 return !mode_is_float(mode) || mode == spillmode;
678 * Check if irn can load its operand at position i from memory (source addressmode).
679 * @param irn The irn to be checked
680 * @param i The operands position
681 * @return Non-Zero if operand can be loaded
683 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
685 ir_node *op = get_irn_n(irn, i);
686 const ir_mode *mode = get_irn_mode(op);
687 const ir_mode *spillmode = get_spill_mode(op);
689 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
690 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
691 !ia32_is_spillmode_compatible(mode, spillmode) ||
692 is_ia32_use_frame(irn)) /* must not already use frame */
695 switch (get_ia32_am_support(irn)) {
700 if (i != n_ia32_unary_op)
706 case n_ia32_binary_left: {
707 const arch_register_req_t *req;
708 if (!is_ia32_commutative(irn))
711 /* we can't swap left/right for limited registers
712 * (As this (currently) breaks constraint handling copies)
714 req = arch_get_in_register_req(irn, n_ia32_binary_left);
715 if (req->type & arch_register_req_type_limited)
720 case n_ia32_binary_right:
729 panic("Unknown AM type");
732 /* HACK: must not already use "real" memory.
733 * This can happen for Call and Div */
734 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
740 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
744 ir_mode *dest_op_mode;
746 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
748 set_ia32_op_type(irn, ia32_AddrModeS);
750 load_mode = get_irn_mode(get_irn_n(irn, i));
751 dest_op_mode = get_ia32_ls_mode(irn);
752 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
753 set_ia32_ls_mode(irn, load_mode);
755 set_ia32_use_frame(irn);
756 set_ia32_need_stackent(irn);
758 if (i == n_ia32_binary_left &&
759 get_ia32_am_support(irn) == ia32_am_binary &&
760 /* immediates are only allowed on the right side */
761 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
762 ia32_swap_left_right(irn);
763 i = n_ia32_binary_right;
766 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
768 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
769 set_irn_n(irn, n_ia32_mem, spill);
770 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
771 set_ia32_is_reload(irn);
774 static const be_abi_callbacks_t ia32_abi_callbacks = {
777 ia32_abi_get_between_type,
782 /* register allocator interface */
783 static const arch_irn_ops_t ia32_irn_ops = {
785 ia32_get_frame_entity,
786 ia32_set_frame_offset,
789 ia32_get_op_estimated_cost,
790 ia32_possible_memory_operand,
791 ia32_perform_memory_operand,
794 static ir_entity *mcount = NULL;
796 static void ia32_before_abi(ir_graph *irg)
798 if (be_get_irg_options(irg)->gprof) {
799 if (mcount == NULL) {
800 ir_type *tp = new_type_method(0, 0);
801 ident *id = new_id_from_str("mcount");
802 mcount = new_entity(get_glob_type(), id, tp);
803 /* FIXME: enter the right ld_ident here */
804 set_entity_ld_ident(mcount, get_entity_ident(mcount));
805 set_entity_visibility(mcount, ir_visibility_external);
807 instrument_initcall(irg, mcount);
812 * Transforms the standard firm graph into
815 static void ia32_prepare_graph(ir_graph *irg)
817 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
820 switch (be_transformer) {
821 case TRANSFORMER_DEFAULT:
822 /* transform remaining nodes into assembler instructions */
823 ia32_transform_graph(irg);
826 case TRANSFORMER_PBQP:
827 case TRANSFORMER_RAND:
828 /* transform nodes into assembler instructions by PBQP magic */
829 ia32_transform_graph_by_pbqp(irg);
833 panic("invalid transformer");
836 ia32_transform_graph(irg);
839 /* do local optimizations (mainly CSE) */
840 optimize_graph_df(irg);
843 dump_ir_graph(irg, "transformed");
845 /* optimize address mode */
846 ia32_optimize_graph(irg);
848 /* do code placement, to optimize the position of constants */
852 dump_ir_graph(irg, "place");
855 ir_node *turn_back_am(ir_node *node)
857 dbg_info *dbgi = get_irn_dbg_info(node);
858 ir_node *block = get_nodes_block(node);
859 ir_node *base = get_irn_n(node, n_ia32_base);
860 ir_node *index = get_irn_n(node, n_ia32_index);
861 ir_node *mem = get_irn_n(node, n_ia32_mem);
864 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
865 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
867 ia32_copy_am_attrs(load, node);
868 if (is_ia32_is_reload(node))
869 set_ia32_is_reload(load);
870 set_irn_n(node, n_ia32_mem, new_NoMem());
872 switch (get_ia32_am_support(node)) {
874 set_irn_n(node, n_ia32_unary_op, load_res);
878 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
879 set_irn_n(node, n_ia32_binary_left, load_res);
881 set_irn_n(node, n_ia32_binary_right, load_res);
886 panic("Unknown AM type");
888 noreg = ia32_new_NoReg_gp(current_ir_graph);
889 set_irn_n(node, n_ia32_base, noreg);
890 set_irn_n(node, n_ia32_index, noreg);
891 set_ia32_am_offs_int(node, 0);
892 set_ia32_am_sc(node, NULL);
893 set_ia32_am_scale(node, 0);
894 clear_ia32_am_sc_sign(node);
896 /* rewire mem-proj */
897 if (get_irn_mode(node) == mode_T) {
898 const ir_edge_t *edge;
899 foreach_out_edge(node, edge) {
900 ir_node *out = get_edge_src_irn(edge);
901 if (get_irn_mode(out) == mode_M) {
902 set_Proj_pred(out, load);
903 set_Proj_proj(out, pn_ia32_Load_M);
909 set_ia32_op_type(node, ia32_Normal);
910 if (sched_is_scheduled(node))
911 sched_add_before(node, load);
916 static ir_node *flags_remat(ir_node *node, ir_node *after)
918 /* we should turn back source address mode when rematerializing nodes */
923 if (is_Block(after)) {
926 block = get_nodes_block(after);
929 type = get_ia32_op_type(node);
936 /* TODO implement this later... */
937 panic("found DestAM with flag user %+F this should not happen", node);
940 default: assert(type == ia32_Normal); break;
943 copy = exact_copy(node);
944 set_nodes_block(copy, block);
945 sched_add_after(after, copy);
951 * Called before the register allocator.
953 static void ia32_before_ra(ir_graph *irg)
955 /* setup fpu rounding modes */
956 ia32_setup_fpu_mode(irg);
959 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
962 be_add_missing_keeps(irg);
967 * Transforms a be_Reload into a ia32 Load.
969 static void transform_to_Load(ir_node *node)
971 ir_graph *irg = get_irn_irg(node);
972 dbg_info *dbg = get_irn_dbg_info(node);
973 ir_node *block = get_nodes_block(node);
974 ir_entity *ent = be_get_frame_entity(node);
975 ir_mode *mode = get_irn_mode(node);
976 ir_mode *spillmode = get_spill_mode(node);
977 ir_node *noreg = ia32_new_NoReg_gp(irg);
978 ir_node *sched_point = NULL;
979 ir_node *ptr = get_irg_frame(irg);
980 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
981 ir_node *new_op, *proj;
982 const arch_register_t *reg;
984 if (sched_is_scheduled(node)) {
985 sched_point = sched_prev(node);
988 if (mode_is_float(spillmode)) {
989 if (ia32_cg_config.use_sse2)
990 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
992 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
994 else if (get_mode_size_bits(spillmode) == 128) {
995 /* Reload 128 bit SSE registers */
996 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
999 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
1001 set_ia32_op_type(new_op, ia32_AddrModeS);
1002 set_ia32_ls_mode(new_op, spillmode);
1003 set_ia32_frame_ent(new_op, ent);
1004 set_ia32_use_frame(new_op);
1005 set_ia32_is_reload(new_op);
1007 DBG_OPT_RELOAD2LD(node, new_op);
1009 proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
1012 sched_add_after(sched_point, new_op);
1016 /* copy the register from the old node to the new Load */
1017 reg = arch_get_irn_register(node);
1018 arch_set_irn_register(proj, reg);
1020 SET_IA32_ORIG_NODE(new_op, node);
1022 exchange(node, proj);
1026 * Transforms a be_Spill node into a ia32 Store.
1028 static void transform_to_Store(ir_node *node)
1030 ir_graph *irg = get_irn_irg(node);
1031 dbg_info *dbg = get_irn_dbg_info(node);
1032 ir_node *block = get_nodes_block(node);
1033 ir_entity *ent = be_get_frame_entity(node);
1034 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1035 ir_mode *mode = get_spill_mode(spillval);
1036 ir_node *noreg = ia32_new_NoReg_gp(irg);
1037 ir_node *nomem = new_NoMem();
1038 ir_node *ptr = get_irg_frame(irg);
1039 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1041 ir_node *sched_point = NULL;
1043 if (sched_is_scheduled(node)) {
1044 sched_point = sched_prev(node);
1047 if (mode_is_float(mode)) {
1048 if (ia32_cg_config.use_sse2)
1049 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
1051 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
1052 } else if (get_mode_size_bits(mode) == 128) {
1053 /* Spill 128 bit SSE registers */
1054 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
1055 } else if (get_mode_size_bits(mode) == 8) {
1056 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
1058 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
1061 set_ia32_op_type(store, ia32_AddrModeD);
1062 set_ia32_ls_mode(store, mode);
1063 set_ia32_frame_ent(store, ent);
1064 set_ia32_use_frame(store);
1065 set_ia32_is_spill(store);
1066 SET_IA32_ORIG_NODE(store, node);
1067 DBG_OPT_SPILL2ST(node, store);
1070 sched_add_after(sched_point, store);
1074 exchange(node, store);
1077 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
1079 dbg_info *dbg = get_irn_dbg_info(node);
1080 ir_node *block = get_nodes_block(node);
1081 ir_graph *irg = get_irn_irg(node);
1082 ir_node *noreg = ia32_new_NoReg_gp(irg);
1083 ir_node *frame = get_irg_frame(irg);
1085 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
1087 set_ia32_frame_ent(push, ent);
1088 set_ia32_use_frame(push);
1089 set_ia32_op_type(push, ia32_AddrModeS);
1090 set_ia32_ls_mode(push, mode_Is);
1091 set_ia32_is_spill(push);
1093 sched_add_before(schedpoint, push);
1097 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
1099 dbg_info *dbg = get_irn_dbg_info(node);
1100 ir_node *block = get_nodes_block(node);
1101 ir_graph *irg = get_irn_irg(node);
1102 ir_node *noreg = ia32_new_NoReg_gp(irg);
1103 ir_node *frame = get_irg_frame(irg);
1105 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
1107 set_ia32_frame_ent(pop, ent);
1108 set_ia32_use_frame(pop);
1109 set_ia32_op_type(pop, ia32_AddrModeD);
1110 set_ia32_ls_mode(pop, mode_Is);
1111 set_ia32_is_reload(pop);
1113 sched_add_before(schedpoint, pop);
1118 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1120 dbg_info *dbg = get_irn_dbg_info(node);
1121 ir_mode *spmode = mode_Iu;
1122 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1125 sp = new_rd_Proj(dbg, pred, spmode, pos);
1126 arch_set_irn_register(sp, spreg);
1132 * Transform MemPerm, currently we do this the ugly way and produce
1133 * push/pop into/from memory cascades. This is possible without using
1136 static void transform_MemPerm(ir_node *node)
1138 ir_node *block = get_nodes_block(node);
1139 ir_graph *irg = get_irn_irg(node);
1140 ir_node *sp = be_abi_get_ignore_irn(be_get_irg_abi(irg), &ia32_gp_regs[REG_ESP]);
1141 int arity = be_get_MemPerm_entity_arity(node);
1142 ir_node **pops = ALLOCAN(ir_node*, arity);
1146 const ir_edge_t *edge;
1147 const ir_edge_t *next;
1150 for (i = 0; i < arity; ++i) {
1151 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1152 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1153 ir_type *enttype = get_entity_type(inent);
1154 unsigned entsize = get_type_size_bytes(enttype);
1155 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1156 ir_node *mem = get_irn_n(node, i + 1);
1159 /* work around cases where entities have different sizes */
1160 if (entsize2 < entsize)
1162 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1164 push = create_push(node, node, sp, mem, inent);
1165 sp = create_spproj(node, push, pn_ia32_Push_stack);
1167 /* add another push after the first one */
1168 push = create_push(node, node, sp, mem, inent);
1169 add_ia32_am_offs_int(push, 4);
1170 sp = create_spproj(node, push, pn_ia32_Push_stack);
1173 set_irn_n(node, i, new_Bad());
1177 for (i = arity - 1; i >= 0; --i) {
1178 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1179 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1180 ir_type *enttype = get_entity_type(outent);
1181 unsigned entsize = get_type_size_bytes(enttype);
1182 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1185 /* work around cases where entities have different sizes */
1186 if (entsize2 < entsize)
1188 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1190 pop = create_pop(node, node, sp, outent);
1191 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1193 add_ia32_am_offs_int(pop, 4);
1195 /* add another pop after the first one */
1196 pop = create_pop(node, node, sp, outent);
1197 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1204 keep = be_new_Keep(block, 1, in);
1205 sched_add_before(node, keep);
1207 /* exchange memprojs */
1208 foreach_out_edge_safe(node, edge, next) {
1209 ir_node *proj = get_edge_src_irn(edge);
1210 int p = get_Proj_proj(proj);
1214 set_Proj_pred(proj, pops[p]);
1215 set_Proj_proj(proj, pn_ia32_Pop_M);
1218 /* remove memperm */
1219 arity = get_irn_arity(node);
1220 for (i = 0; i < arity; ++i) {
1221 set_irn_n(node, i, new_Bad());
1227 * Block-Walker: Calls the transform functions Spill and Reload.
1229 static void ia32_after_ra_walker(ir_node *block, void *env)
1231 ir_node *node, *prev;
1234 /* beware: the schedule is changed here */
1235 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1236 prev = sched_prev(node);
1238 if (be_is_Reload(node)) {
1239 transform_to_Load(node);
1240 } else if (be_is_Spill(node)) {
1241 transform_to_Store(node);
1242 } else if (be_is_MemPerm(node)) {
1243 transform_MemPerm(node);
1249 * Collects nodes that need frame entities assigned.
1251 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1253 be_fec_env_t *env = data;
1254 const ir_mode *mode;
1257 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1258 mode = get_spill_mode_mode(get_irn_mode(node));
1259 align = get_mode_size_bytes(mode);
1260 } else if (is_ia32_irn(node) &&
1261 get_ia32_frame_ent(node) == NULL &&
1262 is_ia32_use_frame(node)) {
1263 if (is_ia32_need_stackent(node))
1266 switch (get_ia32_irn_opcode(node)) {
1268 case iro_ia32_Load: {
1269 const ia32_attr_t *attr = get_ia32_attr_const(node);
1271 if (attr->data.need_32bit_stackent) {
1273 } else if (attr->data.need_64bit_stackent) {
1276 mode = get_ia32_ls_mode(node);
1277 if (is_ia32_is_reload(node))
1278 mode = get_spill_mode_mode(mode);
1280 align = get_mode_size_bytes(mode);
1284 case iro_ia32_vfild:
1286 case iro_ia32_xLoad: {
1287 mode = get_ia32_ls_mode(node);
1292 case iro_ia32_FldCW: {
1293 /* although 2 byte would be enough 4 byte performs best */
1301 panic("unexpected frame user while collection frame entity nodes");
1303 case iro_ia32_FnstCW:
1304 case iro_ia32_Store8Bit:
1305 case iro_ia32_Store:
1308 case iro_ia32_vfist:
1309 case iro_ia32_vfisttp:
1311 case iro_ia32_xStore:
1312 case iro_ia32_xStoreSimple:
1319 be_node_needs_frame_entity(env, node, mode, align);
1323 * We transform Spill and Reload here. This needs to be done before
1324 * stack biasing otherwise we would miss the corrected offset for these nodes.
1326 static void ia32_after_ra(ir_graph *irg)
1328 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1330 /* create and coalesce frame entities */
1331 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1332 be_assign_entities(fec_env, ia32_set_frame_entity);
1333 be_free_frame_entity_coalescer(fec_env);
1335 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1339 * Last touchups for the graph before emit: x87 simulation to replace the
1340 * virtual with real x87 instructions, creating a block schedule and peephole
1343 static void ia32_finish(ir_graph *irg)
1345 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1347 ia32_finish_irg(irg);
1349 /* we might have to rewrite x87 virtual registers */
1350 if (irg_data->do_x87_sim) {
1351 x87_simulate_graph(irg);
1354 /* do peephole optimisations */
1355 ia32_peephole_optimization(irg);
1357 /* create block schedule, this also removes empty blocks which might
1358 * produce critical edges */
1359 irg_data->blk_sched = be_create_block_schedule(irg);
1363 * Emits the code, closes the output file and frees
1364 * the code generator interface.
1366 static void ia32_emit(ir_graph *irg)
1368 if (ia32_cg_config.emit_machcode) {
1369 ia32_gen_binary_routine(irg);
1371 ia32_gen_routine(irg);
1376 * Returns the node representing the PIC base.
1378 static ir_node *ia32_get_pic_base(ir_graph *irg)
1380 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1382 ir_node *get_eip = irg_data->get_eip;
1383 if (get_eip != NULL)
1386 block = get_irg_start_block(irg);
1387 get_eip = new_bd_ia32_GetEIP(NULL, block);
1388 irg_data->get_eip = get_eip;
1390 be_dep_on_frame(get_eip);
1395 * Initializes a IA32 code generator.
1397 static void ia32_init_graph(ir_graph *irg)
1399 struct obstack *obst = be_get_be_obst(irg);
1400 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1402 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1404 if (be_get_irg_options(irg)->gprof) {
1405 /* Linux gprof implementation needs base pointer */
1406 be_get_irg_options(irg)->omit_fp = 0;
1409 be_birg_from_irg(irg)->isa_link = irg_data;
1414 * Set output modes for GCC
1416 static const tarval_mode_info mo_integer = {
1423 * set the tarval output mode of all integer modes to decimal
1425 static void set_tarval_output_modes(void)
1429 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1430 ir_mode *mode = get_irp_mode(i);
1432 if (mode_is_int(mode))
1433 set_tarval_mode_output_option(mode, &mo_integer);
1437 const arch_isa_if_t ia32_isa_if;
1440 * The template that generates a new ISA object.
1441 * Note that this template can be changed by command line
1444 static ia32_isa_t ia32_isa_template = {
1446 &ia32_isa_if, /* isa interface implementation */
1447 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1448 &ia32_gp_regs[REG_EBP], /* base pointer register */
1449 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1450 -1, /* stack direction */
1451 2, /* power of two stack alignment, 2^2 == 4 */
1452 NULL, /* main environment */
1453 7, /* costs for a spill instruction */
1454 5, /* costs for a reload instruction */
1455 false, /* no custom abi handling */
1457 NULL, /* 16bit register names */
1458 NULL, /* 8bit register names */
1459 NULL, /* 8bit register names high */
1462 NULL, /* abstract machine */
1465 static void init_asm_constraints(void)
1467 be_init_default_asm_constraint_flags();
1469 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1470 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1471 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1472 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1473 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1474 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1475 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1476 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1477 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1478 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1479 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1480 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1481 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1482 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1483 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1484 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1485 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1486 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1487 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1488 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1490 /* no support for autodecrement/autoincrement */
1491 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1492 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1493 /* no float consts */
1494 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1495 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1496 /* makes no sense on x86 */
1497 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1498 /* no support for sse consts yet */
1499 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1500 /* no support for x87 consts yet */
1501 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1502 /* no support for mmx registers yet */
1503 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1504 /* not available in 32bit mode */
1505 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1506 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1508 /* no code yet to determine register class needed... */
1509 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1513 * Initializes the backend ISA.
1515 static arch_env_t *ia32_init(FILE *file_handle)
1517 static int inited = 0;
1525 set_tarval_output_modes();
1527 isa = XMALLOC(ia32_isa_t);
1528 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1530 if (mode_fpcw == NULL) {
1531 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1534 ia32_register_init();
1535 ia32_create_opcodes(&ia32_irn_ops);
1537 be_emit_init(file_handle);
1538 isa->regs_16bit = pmap_create();
1539 isa->regs_8bit = pmap_create();
1540 isa->regs_8bit_high = pmap_create();
1541 isa->types = pmap_create();
1542 isa->tv_ent = pmap_create();
1543 isa->cpu = ia32_init_machine_description();
1545 ia32_build_16bit_reg_map(isa->regs_16bit);
1546 ia32_build_8bit_reg_map(isa->regs_8bit);
1547 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1549 /* enter the ISA object into the intrinsic environment */
1550 intrinsic_env.isa = isa;
1552 /* emit asm includes */
1553 n = get_irp_n_asms();
1554 for (i = 0; i < n; ++i) {
1555 be_emit_cstring("#APP\n");
1556 be_emit_ident(get_irp_asm(i));
1557 be_emit_cstring("\n#NO_APP\n");
1560 /* needed for the debug support */
1561 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1562 be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
1563 be_emit_write_line();
1571 * Closes the output file and frees the ISA structure.
1573 static void ia32_done(void *self)
1575 ia32_isa_t *isa = self;
1577 /* emit now all global declarations */
1578 be_gas_emit_decls(isa->base.main_env);
1580 pmap_destroy(isa->regs_16bit);
1581 pmap_destroy(isa->regs_8bit);
1582 pmap_destroy(isa->regs_8bit_high);
1583 pmap_destroy(isa->tv_ent);
1584 pmap_destroy(isa->types);
1593 * Return the number of register classes for this architecture.
1594 * We report always these:
1595 * - the general purpose registers
1596 * - the SSE floating point register set
1597 * - the virtual floating point registers
1598 * - the SSE vector register set
1600 static unsigned ia32_get_n_reg_class(void)
1606 * Return the register class for index i.
1608 static const arch_register_class_t *ia32_get_reg_class(unsigned i)
1610 assert(i < N_CLASSES);
1611 return &ia32_reg_classes[i];
1615 * Get the register class which shall be used to store a value of a given mode.
1616 * @param self The this pointer.
1617 * @param mode The mode in question.
1618 * @return A register class which can hold values of the given mode.
1620 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1622 if (mode_is_float(mode)) {
1623 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1626 return &ia32_reg_classes[CLASS_ia32_gp];
1630 * Returns the register for parameter nr.
1632 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1633 const ir_mode *mode)
1635 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1636 &ia32_gp_regs[REG_ECX],
1637 &ia32_gp_regs[REG_EDX],
1640 static const unsigned MAXNUM_GPREG_ARGS = 3;
1642 static const arch_register_t *gpreg_param_reg_regparam[] = {
1643 &ia32_gp_regs[REG_EAX],
1644 &ia32_gp_regs[REG_EDX],
1645 &ia32_gp_regs[REG_ECX]
1648 static const arch_register_t *gpreg_param_reg_this[] = {
1649 &ia32_gp_regs[REG_ECX],
1654 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1655 &ia32_xmm_regs[REG_XMM0],
1656 &ia32_xmm_regs[REG_XMM1],
1657 &ia32_xmm_regs[REG_XMM2],
1658 &ia32_xmm_regs[REG_XMM3],
1659 &ia32_xmm_regs[REG_XMM4],
1660 &ia32_xmm_regs[REG_XMM5],
1661 &ia32_xmm_regs[REG_XMM6],
1662 &ia32_xmm_regs[REG_XMM7]
1665 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1666 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1668 static const unsigned MAXNUM_SSE_ARGS = 8;
1670 if ((cc & cc_this_call) && nr == 0)
1671 return gpreg_param_reg_this[0];
1673 if (! (cc & cc_reg_param))
1676 if (mode_is_float(mode)) {
1677 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1679 if (nr >= MAXNUM_SSE_ARGS)
1682 if (cc & cc_this_call) {
1683 return fpreg_sse_param_reg_this[nr];
1685 return fpreg_sse_param_reg_std[nr];
1686 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1687 unsigned num_regparam;
1689 if (get_mode_size_bits(mode) > 32)
1692 if (nr >= MAXNUM_GPREG_ARGS)
1695 if (cc & cc_this_call) {
1696 return gpreg_param_reg_this[nr];
1698 num_regparam = cc & ~cc_bits;
1699 if (num_regparam == 0) {
1700 /* default fastcall */
1701 return gpreg_param_reg_fastcall[nr];
1703 if (nr < num_regparam)
1704 return gpreg_param_reg_regparam[nr];
1708 panic("unknown argument mode");
1712 * Get the ABI restrictions for procedure calls.
1713 * @param self The this pointer.
1714 * @param method_type The type of the method (procedure) in question.
1715 * @param abi The abi object to be modified
1717 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1725 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1729 /* set abi flags for calls */
1730 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1731 call_flags.bits.store_args_sequential = 0;
1732 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1733 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1734 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1736 /* set parameter passing style */
1737 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1739 cc = get_method_calling_convention(method_type);
1740 if (get_method_variadicity(method_type) == variadicity_variadic) {
1741 /* pass all parameters of a variadic function on the stack */
1742 cc = cc_cdecl_set | (cc & cc_this_call);
1744 if (get_method_additional_properties(method_type) & mtp_property_private &&
1745 ia32_cg_config.optimize_cc) {
1746 /* set the fast calling conventions (allowing up to 3) */
1747 cc = SET_FASTCALL(cc) | 3;
1751 /* we have to pop the shadow parameter ourself for compound calls */
1752 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1753 && !(cc & cc_reg_param)) {
1754 pop_amount += get_mode_size_bytes(mode_P_data);
1757 n = get_method_n_params(method_type);
1758 for (i = regnum = 0; i < n; i++) {
1760 const arch_register_t *reg = NULL;
1762 tp = get_method_param_type(method_type, i);
1763 mode = get_type_mode(tp);
1765 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1768 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1771 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1772 * movl has a shorter opcode than mov[sz][bw]l */
1773 ir_mode *load_mode = mode;
1776 unsigned size = get_mode_size_bytes(mode);
1778 if (cc & cc_callee_clear_stk) {
1779 pop_amount += (size + 3U) & ~3U;
1782 if (size < 4) load_mode = mode_Iu;
1785 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1789 be_abi_call_set_pop(abi, pop_amount);
1791 /* set return registers */
1792 n = get_method_n_ress(method_type);
1794 assert(n <= 2 && "more than two results not supported");
1796 /* In case of 64bit returns, we will have two 32bit values */
1798 tp = get_method_res_type(method_type, 0);
1799 mode = get_type_mode(tp);
1801 assert(!mode_is_float(mode) && "two FP results not supported");
1803 tp = get_method_res_type(method_type, 1);
1804 mode = get_type_mode(tp);
1806 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1808 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX], ABI_CONTEXT_BOTH);
1809 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX], ABI_CONTEXT_BOTH);
1812 const arch_register_t *reg;
1814 tp = get_method_res_type(method_type, 0);
1815 assert(is_atomic_type(tp));
1816 mode = get_type_mode(tp);
1818 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1820 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1824 static int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1828 if (!is_ia32_irn(irn)) {
1832 if (is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1833 || is_ia32_ChangeCW(irn) || is_ia32_Immediate(irn))
1840 * Returns the estimated execution time of an ia32 irn.
1842 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn)
1845 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
1848 list_sched_selector_t ia32_sched_selector;
1851 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1853 static const list_sched_selector_t *ia32_get_list_sched_selector(
1854 const void *self, list_sched_selector_t *selector)
1857 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1858 ia32_sched_selector.exectime = ia32_sched_exectime;
1859 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1860 return &ia32_sched_selector;
1863 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1870 * Returns the necessary byte alignment for storing a register of given class.
1872 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1874 ir_mode *mode = arch_register_class_mode(cls);
1875 int bytes = get_mode_size_bytes(mode);
1877 if (mode_is_float(mode) && bytes > 8)
1882 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1885 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1886 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1887 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1890 static const be_execution_unit_t *_allowed_units_GP[] = {
1891 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1892 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1893 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1894 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1895 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1896 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1897 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1900 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1901 &be_machine_execution_units_DUMMY[0],
1904 static const be_execution_unit_t **_units_callret[] = {
1905 _allowed_units_BRANCH,
1908 static const be_execution_unit_t **_units_other[] = {
1912 static const be_execution_unit_t **_units_dummy[] = {
1913 _allowed_units_DUMMY,
1916 const be_execution_unit_t ***ret;
1918 if (is_ia32_irn(irn)) {
1919 ret = get_ia32_exec_units(irn);
1920 } else if (is_be_node(irn)) {
1921 if (be_is_Return(irn)) {
1922 ret = _units_callret;
1923 } else if (be_is_Barrier(irn)) {
1937 * Return the abstract ia32 machine.
1939 static const be_machine_t *ia32_get_machine(const void *self)
1941 const ia32_isa_t *isa = self;
1946 * Return irp irgs in the desired order.
1948 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1955 static void ia32_mark_remat(ir_node *node)
1957 if (is_ia32_irn(node)) {
1958 set_ia32_is_remat(node);
1963 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1965 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1975 cmp = get_Proj_pred(sel);
1979 cmp_l = get_Cmp_left(cmp);
1980 cmp_r = get_Cmp_right(cmp);
1981 if (!mode_is_float(get_irn_mode(cmp_l)))
1984 /* check for min/max. They're defined as (C-Semantik):
1985 * min(a, b) = a < b ? a : b
1986 * or min(a, b) = a <= b ? a : b
1987 * max(a, b) = a > b ? a : b
1988 * or max(a, b) = a >= b ? a : b
1989 * (Note we only handle float min/max here)
1991 pnc = get_Proj_proj(sel);
1996 if (cmp_l == mux_true && cmp_r == mux_false)
2002 if (cmp_l == mux_true && cmp_r == mux_false)
2008 if (cmp_l == mux_false && cmp_r == mux_true)
2014 if (cmp_l == mux_false && cmp_r == mux_true)
2025 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
2027 ir_mode *mode = get_irn_mode(mux_true);
2030 if (!mode_is_int(mode) && !mode_is_reference(mode)
2034 if (is_Const(mux_true) && is_Const(mux_false)) {
2035 /* we can create a set plus up two 3 instructions for any combination of constants */
2042 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
2047 if (!mode_is_float(get_irn_mode(mux_true)))
2050 return is_Const(mux_true) && is_Const(mux_false);
2053 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
2066 cmp = get_Proj_pred(sel);
2070 mode = get_irn_mode(mux_true);
2071 if (mode_is_signed(mode) || mode_is_float(mode))
2074 pn = get_Proj_proj(sel);
2075 cmp_left = get_Cmp_left(cmp);
2076 cmp_right = get_Cmp_right(cmp);
2078 /* "move" zero constant to false input */
2079 if (is_Const(mux_true) && is_Const_null(mux_true)) {
2080 ir_node *tmp = mux_false;
2081 mux_false = mux_true;
2083 pn = get_negated_pnc(pn, mode);
2085 if (!is_Const(mux_false) || !is_Const_null(mux_false))
2087 if (!is_Sub(mux_true))
2089 sub_left = get_Sub_left(mux_true);
2090 sub_right = get_Sub_right(mux_true);
2092 /* Mux(a >=u b, 0, a-b) */
2093 if ((pn == pn_Cmp_Gt || pn == pn_Cmp_Ge)
2094 && sub_left == cmp_left && sub_right == cmp_right)
2096 /* Mux(a <=u b, 0, b-a) */
2097 if ((pn == pn_Cmp_Lt || pn == pn_Cmp_Le)
2098 && sub_left == cmp_right && sub_right == cmp_left)
2104 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
2109 /* we can handle Set for all modes and compares */
2110 if (mux_is_set(sel, mux_true, mux_false))
2112 /* SSE has own min/max operations */
2113 if (ia32_cg_config.use_sse2
2114 && mux_is_float_min_max(sel, mux_true, mux_false))
2116 /* we can handle Mux(?, Const[f], Const[f]) */
2117 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
2118 #ifdef FIRM_GRGEN_BE
2119 /* well, some code selectors can't handle it */
2120 if (be_transformer != TRANSFORMER_PBQP
2121 || be_transformer != TRANSFORMER_RAND)
2128 /* no support for 64bit inputs to cmov */
2129 mode = get_irn_mode(mux_true);
2130 if (get_mode_size_bits(mode) > 32)
2132 /* we can handle Abs for all modes and compares (except 64bit) */
2133 if (be_mux_is_abs(sel, mux_true, mux_false) != 0)
2135 /* we can't handle MuxF yet */
2136 if (mode_is_float(mode))
2139 if (mux_is_doz(sel, mux_true, mux_false))
2142 /* Check Cmp before the node */
2144 ir_node *cmp = get_Proj_pred(sel);
2146 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(cmp));
2148 /* we can't handle 64bit compares */
2149 if (get_mode_size_bits(cmp_mode) > 32)
2152 /* we can't handle float compares */
2153 if (mode_is_float(cmp_mode))
2158 /* did we disable cmov generation? */
2159 if (!ia32_cg_config.use_cmov)
2162 /* we can use a cmov */
2166 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2170 /* we already added all our simple flags to the flags modifier list in
2171 * init, so this flag we don't know. */
2172 return ASM_CONSTRAINT_FLAG_INVALID;
2175 static int ia32_is_valid_clobber(const char *clobber)
2177 return ia32_get_clobber_register(clobber) != NULL;
2180 static void ia32_lower_for_target(void)
2182 int n_irgs = get_irp_n_irgs();
2184 lower_mode_b_config_t lower_mode_b_config = {
2185 mode_Iu, /* lowered mode */
2186 mode_Bu, /* preferred mode for set */
2187 0, /* don't lower direct compares */
2190 /* perform doubleword lowering */
2191 lwrdw_param_t lower_dw_params = {
2192 1, /* little endian */
2193 64, /* doubleword size */
2194 ia32_create_intrinsic_fkt,
2197 lower_dw_ops(&lower_dw_params);
2199 for (i = 0; i < n_irgs; ++i) {
2200 ir_graph *irg = get_irp_irg(i);
2201 /* lower for mode_b stuff */
2202 ir_lower_mode_b(irg, &lower_mode_b_config);
2203 /* break up switches with wide ranges */
2204 lower_switch(irg, 256, true);
2209 * Create the trampoline code.
2211 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2213 ir_node *st, *p = trampoline;
2214 ir_mode *mode = get_irn_mode(p);
2217 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xb9), 0);
2218 mem = new_r_Proj(st, mode_M, pn_Store_M);
2219 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2220 st = new_r_Store(block, mem, p, env, 0);
2221 mem = new_r_Proj(st, mode_M, pn_Store_M);
2222 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2224 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xe9), 0);
2225 mem = new_r_Proj(st, mode_M, pn_Store_M);
2226 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2227 st = new_r_Store(block, mem, p, callee, 0);
2228 mem = new_r_Proj(st, mode_M, pn_Store_M);
2229 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2235 * Returns the libFirm configuration parameter for this backend.
2237 static const backend_params *ia32_get_libfirm_params(void)
2239 static const ir_settings_arch_dep_t ad = {
2240 1, /* also use subs */
2241 4, /* maximum shifts */
2242 31, /* maximum shift amount */
2243 ia32_evaluate_insn, /* evaluate the instruction sequence */
2245 1, /* allow Mulhs */
2246 1, /* allow Mulus */
2247 32, /* Mulh allowed up to 32 bit */
2249 static backend_params p = {
2250 1, /* support inline assembly */
2251 1, /* support Rotl nodes */
2252 0, /* little endian */
2253 ia32_lower_for_target,
2254 NULL, /* will be set later */
2255 ia32_is_mux_allowed,
2256 NULL, /* float arithmetic mode, will be set below */
2257 12, /* size of trampoline code */
2258 4, /* alignment of trampoline code */
2259 ia32_create_trampoline_fkt,
2260 4 /* alignment of stack parameter */
2263 ia32_setup_cg_config();
2265 /* doesn't really belong here, but this is the earliest place the backend
2267 init_asm_constraints();
2270 if (! ia32_cg_config.use_sse2)
2271 p.mode_float_arithmetic = mode_E;
2275 static const lc_opt_enum_int_items_t gas_items[] = {
2276 { "elf", OBJECT_FILE_FORMAT_ELF },
2277 { "mingw", OBJECT_FILE_FORMAT_COFF },
2278 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2282 static lc_opt_enum_int_var_t gas_var = {
2283 (int*) &be_gas_object_file_format, gas_items
2286 #ifdef FIRM_GRGEN_BE
2287 static const lc_opt_enum_int_items_t transformer_items[] = {
2288 { "default", TRANSFORMER_DEFAULT },
2289 { "pbqp", TRANSFORMER_PBQP },
2290 { "random", TRANSFORMER_RAND },
2294 static lc_opt_enum_int_var_t transformer_var = {
2295 (int*)&be_transformer, transformer_items
2299 static const lc_opt_table_entry_t ia32_options[] = {
2300 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2301 #ifdef FIRM_GRGEN_BE
2302 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2304 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2305 &ia32_isa_template.base.stack_alignment),
2309 const arch_isa_if_t ia32_isa_if = {
2312 ia32_handle_intrinsics,
2313 ia32_get_n_reg_class,
2315 ia32_get_reg_class_for_mode,
2317 ia32_get_list_sched_selector,
2318 ia32_get_ilp_sched_selector,
2319 ia32_get_reg_class_alignment,
2320 ia32_get_libfirm_params,
2321 ia32_get_allowed_execution_units,
2325 ia32_parse_asm_constraint,
2326 ia32_is_valid_clobber,
2329 ia32_get_pic_base, /* return node used as base in pic code addresses */
2330 ia32_before_abi, /* before abi introduce hook */
2332 ia32_before_ra, /* before register allocation hook */
2333 ia32_after_ra, /* after register allocation hook */
2334 ia32_finish, /* called before codegen */
2335 ia32_emit, /* emit && done */
2338 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
2339 void be_init_arch_ia32(void)
2341 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2342 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2344 lc_opt_add_table(ia32_grp, ia32_options);
2345 be_register_isa_if("ia32", &ia32_isa_if);
2347 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2349 ia32_init_emitter();
2351 ia32_init_optimize();
2352 ia32_init_transform();
2354 ia32_init_architecture();