2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
28 #include "lc_opts_enum.h"
36 #include "iredges_t.h"
49 #include "iroptimize.h"
50 #include "instrument.h"
53 #include "lower_calls.h"
54 #include "lower_mode_b.h"
55 #include "lower_softfloat.h"
56 #include "firmstat_t.h"
65 #include "beblocksched.h"
66 #include "bespillutil.h"
67 #include "bespillslots.h"
72 #include "betranshlp.h"
73 #include "belistsched.h"
74 #include "beabihelper.h"
77 #include "bearch_ia32_t.h"
79 #include "ia32_new_nodes.h"
80 #include "gen_ia32_regalloc_if.h"
81 #include "ia32_common_transform.h"
82 #include "ia32_transform.h"
83 #include "ia32_emitter.h"
84 #include "ia32_optimize.h"
86 #include "ia32_dbg_stat.h"
87 #include "ia32_finish.h"
89 #include "ia32_architecture.h"
92 #include "ia32_pbqp_transform.h"
94 transformer_t be_transformer = TRANSFORMER_DEFAULT;
97 ir_mode *ia32_mode_fpcw;
101 /** The current omit-fp state */
102 static ir_type *omit_fp_between_type = NULL;
103 static ir_type *between_type = NULL;
104 static ir_entity *old_bp_ent = NULL;
105 static ir_entity *ret_addr_ent = NULL;
106 static ir_entity *omit_fp_ret_addr_ent = NULL;
109 * The environment for the intrinsic mapping.
111 static ia32_intrinsic_env_t intrinsic_env = {
112 NULL, /* entity for __divdi3 library call */
113 NULL, /* entity for __moddi3 library call */
114 NULL, /* entity for __udivdi3 library call */
115 NULL, /* entity for __umoddi3 library call */
119 typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
122 * Used to create per-graph unique pseudo nodes.
124 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
125 create_const_node_func func,
126 const arch_register_t* reg)
128 ir_node *block, *res;
133 block = get_irg_start_block(irg);
134 res = func(NULL, block);
135 arch_set_irn_register(res, reg);
141 /* Creates the unique per irg GP NoReg node. */
142 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
144 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
145 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
146 &ia32_registers[REG_GP_NOREG]);
149 ir_node *ia32_new_NoReg_fp(ir_graph *irg)
151 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
152 return create_const(irg, &irg_data->noreg_fp, new_bd_ia32_NoReg_FP,
153 &ia32_registers[REG_FP_NOREG]);
156 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
158 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
159 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
160 &ia32_registers[REG_XMM_NOREG]);
163 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
165 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
166 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
167 &ia32_registers[REG_FPCW]);
172 * Returns the admissible noreg register node for input register pos of node irn.
174 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
176 ir_graph *irg = get_irn_irg(irn);
177 const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
179 assert(req != NULL && "Missing register requirements");
180 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
181 return ia32_new_NoReg_gp(irg);
183 if (ia32_cg_config.use_sse2) {
184 return ia32_new_NoReg_xmm(irg);
186 return ia32_new_NoReg_fp(irg);
190 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
192 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
195 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
197 if (is_be_node(node))
198 be_node_set_frame_entity(node, entity);
200 set_ia32_frame_ent(node, entity);
203 static void ia32_set_frame_offset(ir_node *irn, int bias)
205 if (get_ia32_frame_ent(irn) == NULL)
208 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
209 ir_graph *irg = get_irn_irg(irn);
210 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
211 if (layout->sp_relative) {
212 /* Pop nodes modify the stack pointer before calculating the
213 * destination address, so fix this here
218 add_ia32_am_offs_int(irn, bias);
221 static int ia32_get_sp_bias(const ir_node *node)
223 if (is_ia32_Call(node))
224 return -(int)get_ia32_call_attr_const(node)->pop;
226 if (is_ia32_Push(node))
229 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
232 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
233 return SP_BIAS_RESET;
240 * Build the between type and entities if not already build.
242 static void ia32_build_between_type(void)
244 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
245 if (between_type == NULL) {
246 ir_type *old_bp_type = new_type_primitive(mode_Iu);
247 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
249 between_type = new_type_struct(IDENT("ia32_between_type"));
250 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
251 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
253 set_entity_offset(old_bp_ent, 0);
254 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
255 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
256 set_type_state(between_type, layout_fixed);
258 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
259 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
261 set_entity_offset(omit_fp_ret_addr_ent, 0);
262 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
263 set_type_state(omit_fp_between_type, layout_fixed);
269 * Produces the type which sits between the stack args and the locals on the stack.
270 * it will contain the return address and space to store the old base pointer.
271 * @return The Firm type modeling the ABI between type.
273 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
275 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
276 ia32_build_between_type();
277 return layout->sp_relative ? omit_fp_between_type : between_type;
281 * Return the stack entity that contains the return address.
283 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
285 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
286 ia32_build_between_type();
287 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
291 * Return the stack entity that contains the frame address.
293 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
295 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
296 ia32_build_between_type();
297 return layout->sp_relative ? NULL : old_bp_ent;
301 * Get the estimated cycle count for @p irn.
303 * @param self The this pointer.
304 * @param irn The node.
306 * @return The estimated cycle count for this operation
308 static int ia32_get_op_estimated_cost(const ir_node *irn)
311 ia32_op_type_t op_tp;
315 if (!is_ia32_irn(irn))
318 assert(is_ia32_irn(irn));
320 cost = get_ia32_latency(irn);
321 op_tp = get_ia32_op_type(irn);
323 if (is_ia32_CopyB(irn)) {
326 else if (is_ia32_CopyB_i(irn)) {
327 int size = get_ia32_copyb_size(irn);
328 cost = 20 + (int)ceil((4/3) * size);
330 /* in case of address mode operations add additional cycles */
331 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
333 In case of stack access and access to fixed addresses add 5 cycles
334 (we assume they are in cache), other memory operations cost 20
337 if (is_ia32_use_frame(irn) || (
338 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
339 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
350 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
352 if (mode_is_float(mode))
359 * Get the mode that should be used for spilling value node
361 static ir_mode *get_spill_mode(const ir_node *node)
363 ir_mode *mode = get_irn_mode(node);
364 return get_spill_mode_mode(mode);
368 * Checks whether an addressmode reload for a node with mode mode is compatible
369 * with a spillslot of mode spill_mode
371 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
373 return !mode_is_float(mode) || mode == spillmode;
377 * Check if irn can load its operand at position i from memory (source addressmode).
378 * @param irn The irn to be checked
379 * @param i The operands position
380 * @return Non-Zero if operand can be loaded
382 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
384 ir_node *op = get_irn_n(irn, i);
385 const ir_mode *mode = get_irn_mode(op);
386 const ir_mode *spillmode = get_spill_mode(op);
388 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
389 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
390 !ia32_is_spillmode_compatible(mode, spillmode) ||
391 is_ia32_use_frame(irn)) /* must not already use frame */
394 switch (get_ia32_am_support(irn)) {
399 if (i != n_ia32_unary_op)
405 case n_ia32_binary_left: {
406 if (!is_ia32_commutative(irn))
409 /* we can't swap left/right for limited registers
410 * (As this (currently) breaks constraint handling copies) */
411 arch_register_req_t const *const req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
412 if (arch_register_req_is(req, limited))
417 case n_ia32_binary_right:
426 panic("Unknown AM type");
429 /* HACK: must not already use "real" memory.
430 * This can happen for Call and Div */
431 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
437 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
441 ir_mode *dest_op_mode;
443 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
445 set_ia32_op_type(irn, ia32_AddrModeS);
447 load_mode = get_irn_mode(get_irn_n(irn, i));
448 dest_op_mode = get_ia32_ls_mode(irn);
449 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
450 set_ia32_ls_mode(irn, load_mode);
452 set_ia32_use_frame(irn);
453 set_ia32_need_stackent(irn);
455 if (i == n_ia32_binary_left &&
456 get_ia32_am_support(irn) == ia32_am_binary &&
457 /* immediates are only allowed on the right side */
458 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
459 ia32_swap_left_right(irn);
460 i = n_ia32_binary_right;
463 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
465 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
466 set_irn_n(irn, n_ia32_mem, spill);
467 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
468 set_ia32_is_reload(irn);
471 static const be_abi_callbacks_t ia32_abi_callbacks = {
472 ia32_abi_get_between_type,
475 /* register allocator interface */
476 static const arch_irn_ops_t ia32_irn_ops = {
477 ia32_get_frame_entity,
478 ia32_set_frame_offset,
480 ia32_get_op_estimated_cost,
481 ia32_possible_memory_operand,
482 ia32_perform_memory_operand,
485 static int gprof = 0;
487 static void ia32_before_abi(ir_graph *irg)
490 static ir_entity *mcount = NULL;
491 if (mcount == NULL) {
492 ir_type *tp = new_type_method(0, 0);
493 ident *id = new_id_from_str("mcount");
494 mcount = new_entity(get_glob_type(), id, tp);
495 /* FIXME: enter the right ld_ident here */
496 set_entity_ld_ident(mcount, get_entity_ident(mcount));
497 set_entity_visibility(mcount, ir_visibility_external);
499 instrument_initcall(irg, mcount);
504 * Transforms the standard firm graph into
507 static void ia32_prepare_graph(ir_graph *irg)
509 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
512 switch (be_transformer) {
513 case TRANSFORMER_DEFAULT:
514 /* transform remaining nodes into assembler instructions */
515 ia32_transform_graph(irg);
518 case TRANSFORMER_PBQP:
519 case TRANSFORMER_RAND:
520 /* transform nodes into assembler instructions by PBQP magic */
521 ia32_transform_graph_by_pbqp(irg);
525 panic("invalid transformer");
528 ia32_transform_graph(irg);
531 /* do local optimizations (mainly CSE) */
532 optimize_graph_df(irg);
533 /* backend code expects that outedges are always enabled */
537 dump_ir_graph(irg, "transformed");
539 /* optimize address mode */
540 ia32_optimize_graph(irg);
542 /* do code placement, to optimize the position of constants */
544 /* backend code expects that outedges are always enabled */
548 dump_ir_graph(irg, "place");
551 ir_node *ia32_turn_back_am(ir_node *node)
553 dbg_info *dbgi = get_irn_dbg_info(node);
554 ir_graph *irg = get_irn_irg(node);
555 ir_node *block = get_nodes_block(node);
556 ir_node *base = get_irn_n(node, n_ia32_base);
557 ir_node *idx = get_irn_n(node, n_ia32_index);
558 ir_node *mem = get_irn_n(node, n_ia32_mem);
561 ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
562 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
564 ia32_copy_am_attrs(load, node);
565 if (is_ia32_is_reload(node))
566 set_ia32_is_reload(load);
567 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
569 switch (get_ia32_am_support(node)) {
571 set_irn_n(node, n_ia32_unary_op, load_res);
575 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
576 set_irn_n(node, n_ia32_binary_left, load_res);
578 set_irn_n(node, n_ia32_binary_right, load_res);
583 panic("Unknown AM type");
585 noreg = ia32_new_NoReg_gp(irg);
586 set_irn_n(node, n_ia32_base, noreg);
587 set_irn_n(node, n_ia32_index, noreg);
588 set_ia32_am_offs_int(node, 0);
589 set_ia32_am_sc(node, NULL);
590 set_ia32_am_scale(node, 0);
591 clear_ia32_am_sc_sign(node);
593 /* rewire mem-proj */
594 if (get_irn_mode(node) == mode_T) {
595 foreach_out_edge(node, edge) {
596 ir_node *out = get_edge_src_irn(edge);
597 if (get_irn_mode(out) == mode_M) {
598 set_Proj_pred(out, load);
599 set_Proj_proj(out, pn_ia32_Load_M);
605 set_ia32_op_type(node, ia32_Normal);
606 if (sched_is_scheduled(node))
607 sched_add_before(node, load);
612 static ir_node *flags_remat(ir_node *node, ir_node *after)
614 /* we should turn back source address mode when rematerializing nodes */
619 if (is_Block(after)) {
622 block = get_nodes_block(after);
625 type = get_ia32_op_type(node);
628 ia32_turn_back_am(node);
632 /* TODO implement this later... */
633 panic("found DestAM with flag user %+F this should not happen", node);
635 default: assert(type == ia32_Normal); break;
638 copy = exact_copy(node);
639 set_nodes_block(copy, block);
640 sched_add_after(after, copy);
646 * Called before the register allocator.
648 static void ia32_before_ra(ir_graph *irg)
650 /* setup fpu rounding modes */
651 ia32_setup_fpu_mode(irg);
654 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
657 be_add_missing_keeps(irg);
662 * Transforms a be_Reload into a ia32 Load.
664 static void transform_to_Load(ir_node *node)
666 ir_graph *irg = get_irn_irg(node);
667 dbg_info *dbgi = get_irn_dbg_info(node);
668 ir_node *block = get_nodes_block(node);
669 ir_entity *ent = be_get_frame_entity(node);
670 ir_mode *mode = get_irn_mode(node);
671 ir_mode *spillmode = get_spill_mode(node);
672 ir_node *noreg = ia32_new_NoReg_gp(irg);
673 ir_node *sched_point = NULL;
674 ir_node *ptr = get_irg_frame(irg);
675 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
676 ir_node *new_op, *proj;
677 const arch_register_t *reg;
679 if (sched_is_scheduled(node)) {
680 sched_point = sched_prev(node);
683 if (mode_is_float(spillmode)) {
684 if (ia32_cg_config.use_sse2)
685 new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
687 new_op = new_bd_ia32_fld(dbgi, block, ptr, noreg, mem, spillmode);
689 else if (get_mode_size_bits(spillmode) == 128) {
690 /* Reload 128 bit SSE registers */
691 new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
694 new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
696 set_ia32_op_type(new_op, ia32_AddrModeS);
697 set_ia32_ls_mode(new_op, spillmode);
698 set_ia32_frame_ent(new_op, ent);
699 set_ia32_use_frame(new_op);
700 set_ia32_is_reload(new_op);
702 DBG_OPT_RELOAD2LD(node, new_op);
704 proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
707 sched_add_after(sched_point, new_op);
711 /* copy the register from the old node to the new Load */
712 reg = arch_get_irn_register(node);
713 arch_set_irn_register(proj, reg);
715 SET_IA32_ORIG_NODE(new_op, node);
717 exchange(node, proj);
721 * Transforms a be_Spill node into a ia32 Store.
723 static void transform_to_Store(ir_node *node)
725 ir_graph *irg = get_irn_irg(node);
726 dbg_info *dbgi = get_irn_dbg_info(node);
727 ir_node *block = get_nodes_block(node);
728 ir_entity *ent = be_get_frame_entity(node);
729 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
730 ir_mode *mode = get_spill_mode(spillval);
731 ir_node *noreg = ia32_new_NoReg_gp(irg);
732 ir_node *nomem = get_irg_no_mem(irg);
733 ir_node *ptr = get_irg_frame(irg);
734 ir_node *val = get_irn_n(node, n_be_Spill_val);
737 ir_node *sched_point = NULL;
739 if (sched_is_scheduled(node)) {
740 sched_point = sched_prev(node);
743 if (mode_is_float(mode)) {
744 if (ia32_cg_config.use_sse2) {
745 store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
746 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
748 store = new_bd_ia32_fst(dbgi, block, ptr, noreg, nomem, val, mode);
749 res = new_r_Proj(store, mode_M, pn_ia32_fst_M);
751 } else if (get_mode_size_bits(mode) == 128) {
752 /* Spill 128 bit SSE registers */
753 store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
754 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
755 } else if (get_mode_size_bits(mode) == 8) {
756 store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
757 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
759 store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
760 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
763 set_ia32_op_type(store, ia32_AddrModeD);
764 set_ia32_ls_mode(store, mode);
765 set_ia32_frame_ent(store, ent);
766 set_ia32_use_frame(store);
767 set_ia32_is_spill(store);
768 SET_IA32_ORIG_NODE(store, node);
769 DBG_OPT_SPILL2ST(node, store);
772 sched_add_after(sched_point, store);
779 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
781 dbg_info *dbgi = get_irn_dbg_info(node);
782 ir_node *block = get_nodes_block(node);
783 ir_graph *irg = get_irn_irg(node);
784 ir_node *noreg = ia32_new_NoReg_gp(irg);
785 ir_node *frame = get_irg_frame(irg);
787 ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
789 set_ia32_frame_ent(push, ent);
790 set_ia32_use_frame(push);
791 set_ia32_op_type(push, ia32_AddrModeS);
792 set_ia32_ls_mode(push, mode_Is);
793 set_ia32_is_spill(push);
795 sched_add_before(schedpoint, push);
799 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
801 dbg_info *dbgi = get_irn_dbg_info(node);
802 ir_node *block = get_nodes_block(node);
803 ir_graph *irg = get_irn_irg(node);
804 ir_node *noreg = ia32_new_NoReg_gp(irg);
805 ir_node *frame = get_irg_frame(irg);
807 ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
808 get_irg_no_mem(irg), sp);
810 set_ia32_frame_ent(pop, ent);
811 set_ia32_use_frame(pop);
812 set_ia32_op_type(pop, ia32_AddrModeD);
813 set_ia32_ls_mode(pop, mode_Is);
814 set_ia32_is_reload(pop);
816 sched_add_before(schedpoint, pop);
821 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
823 dbg_info *dbgi = get_irn_dbg_info(node);
824 ir_mode *spmode = mode_Iu;
825 const arch_register_t *spreg = &ia32_registers[REG_ESP];
828 sp = new_rd_Proj(dbgi, pred, spmode, pos);
829 arch_set_irn_register(sp, spreg);
835 * Transform MemPerm, currently we do this the ugly way and produce
836 * push/pop into/from memory cascades. This is possible without using
839 static void transform_MemPerm(ir_node *node)
841 ir_node *block = get_nodes_block(node);
842 ir_graph *irg = get_irn_irg(node);
843 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
844 int arity = be_get_MemPerm_entity_arity(node);
845 ir_node **pops = ALLOCAN(ir_node*, arity);
851 for (i = 0; i < arity; ++i) {
852 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
853 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
854 ir_type *enttype = get_entity_type(inent);
855 unsigned entsize = get_type_size_bytes(enttype);
856 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
857 ir_node *mem = get_irn_n(node, i + 1);
860 /* work around cases where entities have different sizes */
861 if (entsize2 < entsize)
863 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
865 push = create_push(node, node, sp, mem, inent);
866 sp = create_spproj(node, push, pn_ia32_Push_stack);
868 /* add another push after the first one */
869 push = create_push(node, node, sp, mem, inent);
870 add_ia32_am_offs_int(push, 4);
871 sp = create_spproj(node, push, pn_ia32_Push_stack);
874 set_irn_n(node, i, new_r_Bad(irg, mode_X));
878 for (i = arity - 1; i >= 0; --i) {
879 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
880 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
881 ir_type *enttype = get_entity_type(outent);
882 unsigned entsize = get_type_size_bytes(enttype);
883 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
886 /* work around cases where entities have different sizes */
887 if (entsize2 < entsize)
889 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
891 pop = create_pop(node, node, sp, outent);
892 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
894 add_ia32_am_offs_int(pop, 4);
896 /* add another pop after the first one */
897 pop = create_pop(node, node, sp, outent);
898 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
905 keep = be_new_Keep(block, 1, in);
906 sched_add_before(node, keep);
908 /* exchange memprojs */
909 foreach_out_edge_safe(node, edge) {
910 ir_node *proj = get_edge_src_irn(edge);
911 int p = get_Proj_proj(proj);
915 set_Proj_pred(proj, pops[p]);
916 set_Proj_proj(proj, pn_ia32_Pop_M);
925 * Block-Walker: Calls the transform functions Spill and Reload.
927 static void ia32_after_ra_walker(ir_node *block, void *env)
929 ir_node *node, *prev;
932 /* beware: the schedule is changed here */
933 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
934 prev = sched_prev(node);
936 if (be_is_Reload(node)) {
937 transform_to_Load(node);
938 } else if (be_is_Spill(node)) {
939 transform_to_Store(node);
940 } else if (be_is_MemPerm(node)) {
941 transform_MemPerm(node);
947 * Collects nodes that need frame entities assigned.
949 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
951 be_fec_env_t *env = (be_fec_env_t*)data;
955 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
956 mode = get_spill_mode_mode(get_irn_mode(node));
957 align = get_mode_size_bytes(mode);
958 } else if (is_ia32_irn(node) &&
959 get_ia32_frame_ent(node) == NULL &&
960 is_ia32_use_frame(node)) {
961 if (is_ia32_need_stackent(node))
964 switch (get_ia32_irn_opcode(node)) {
966 case iro_ia32_Load: {
967 const ia32_attr_t *attr = get_ia32_attr_const(node);
969 if (attr->data.need_32bit_stackent) {
971 } else if (attr->data.need_64bit_stackent) {
974 mode = get_ia32_ls_mode(node);
975 if (is_ia32_is_reload(node))
976 mode = get_spill_mode_mode(mode);
978 align = get_mode_size_bytes(mode);
984 case iro_ia32_xLoad: {
985 mode = get_ia32_ls_mode(node);
990 case iro_ia32_FldCW: {
991 /* although 2 byte would be enough 4 byte performs best */
999 panic("unexpected frame user while collection frame entity nodes");
1001 case iro_ia32_FnstCW:
1002 case iro_ia32_Store8Bit:
1003 case iro_ia32_Store:
1006 case iro_ia32_fisttp:
1007 case iro_ia32_xStore:
1008 case iro_ia32_xStoreSimple:
1015 be_node_needs_frame_entity(env, node, mode, align);
1018 static int determine_ebp_input(ir_node *ret)
1020 const arch_register_t *bp = &ia32_registers[REG_EBP];
1021 int arity = get_irn_arity(ret);
1024 for (i = 0; i < arity; ++i) {
1025 ir_node *input = get_irn_n(ret, i);
1026 if (arch_get_irn_register(input) == bp)
1029 panic("no ebp input found at %+F", ret);
1032 static void introduce_epilog(ir_node *ret)
1034 const arch_register_t *sp = &ia32_registers[REG_ESP];
1035 const arch_register_t *bp = &ia32_registers[REG_EBP];
1036 ir_graph *irg = get_irn_irg(ret);
1037 ir_type *frame_type = get_irg_frame_type(irg);
1038 unsigned frame_size = get_type_size_bytes(frame_type);
1039 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1040 ir_node *block = get_nodes_block(ret);
1041 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1042 ir_node *curr_sp = first_sp;
1043 ir_mode *mode_gp = ia32_reg_classes[CLASS_ia32_gp].mode;
1045 if (!layout->sp_relative) {
1046 int n_ebp = determine_ebp_input(ret);
1047 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1048 if (ia32_cg_config.use_leave) {
1049 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1050 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1051 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1052 arch_set_irn_register(curr_bp, bp);
1053 arch_set_irn_register(curr_sp, sp);
1054 sched_add_before(ret, leave);
1057 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1058 /* copy ebp to esp */
1059 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1060 arch_set_irn_register(curr_sp, sp);
1061 sched_add_before(ret, curr_sp);
1064 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1065 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1066 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1067 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1068 arch_set_irn_register(curr_bp, bp);
1069 arch_set_irn_register(curr_sp, sp);
1070 sched_add_before(ret, pop);
1072 set_irn_n(ret, n_be_Return_mem, curr_mem);
1074 set_irn_n(ret, n_ebp, curr_bp);
1076 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1077 sched_add_before(ret, incsp);
1080 set_irn_n(ret, n_be_Return_sp, curr_sp);
1082 /* keep verifier happy... */
1083 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1084 kill_node(first_sp);
1089 * put the Prolog code at the beginning, epilog code before each return
1091 static void introduce_prolog_epilog(ir_graph *irg)
1093 const arch_register_t *sp = &ia32_registers[REG_ESP];
1094 const arch_register_t *bp = &ia32_registers[REG_EBP];
1095 ir_node *start = get_irg_start(irg);
1096 ir_node *block = get_nodes_block(start);
1097 ir_type *frame_type = get_irg_frame_type(irg);
1098 unsigned frame_size = get_type_size_bytes(frame_type);
1099 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1100 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1101 ir_node *curr_sp = initial_sp;
1102 ir_mode *mode_gp = mode_Iu;
1104 if (!layout->sp_relative) {
1106 ir_node *mem = get_irg_initial_mem(irg);
1107 ir_node *noreg = ia32_new_NoReg_gp(irg);
1108 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1109 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, initial_bp, initial_sp);
1112 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1113 arch_set_irn_register(curr_sp, sp);
1114 sched_add_after(start, push);
1116 /* move esp to ebp */
1117 ir_node *const curr_bp = be_new_Copy(block, curr_sp);
1118 sched_add_after(push, curr_bp);
1119 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1120 curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
1121 sched_add_after(curr_bp, curr_sp);
1122 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1123 edges_reroute_except(initial_bp, curr_bp, push);
1125 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1126 edges_reroute_except(initial_sp, incsp, push);
1127 sched_add_after(curr_sp, incsp);
1129 /* make sure the initial IncSP is really used by someone */
1130 if (get_irn_n_edges(incsp) <= 1) {
1131 ir_node *in[] = { incsp };
1132 ir_node *keep = be_new_Keep(block, 1, in);
1133 sched_add_after(incsp, keep);
1136 layout->initial_bias = -4;
1138 ir_node *const incsp = be_new_IncSP(sp, block, initial_sp, frame_size, 0);
1139 edges_reroute_except(initial_sp, incsp, incsp);
1140 sched_add_after(start, incsp);
1143 /* introduce epilog for every return node */
1145 ir_node *end_block = get_irg_end_block(irg);
1146 int arity = get_irn_arity(end_block);
1149 for (i = 0; i < arity; ++i) {
1150 ir_node *ret = get_irn_n(end_block, i);
1151 assert(be_is_Return(ret));
1152 introduce_epilog(ret);
1158 * Last touchups for the graph before emit: x87 simulation to replace the
1159 * virtual with real x87 instructions, creating a block schedule and peephole
1162 static void ia32_finish_graph(ir_graph *irg)
1164 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1165 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1166 bool at_begin = stack_layout->sp_relative ? true : false;
1167 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1169 /* create and coalesce frame entities */
1170 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1171 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1172 be_free_frame_entity_coalescer(fec_env);
1174 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1176 introduce_prolog_epilog(irg);
1178 /* fix stack entity offsets */
1179 be_abi_fix_stack_nodes(irg);
1180 be_abi_fix_stack_bias(irg);
1182 /* fix 2-address code constraints */
1183 ia32_finish_irg(irg);
1185 /* we might have to rewrite x87 virtual registers */
1186 if (irg_data->do_x87_sim) {
1187 ia32_x87_simulate_graph(irg);
1190 /* do peephole optimisations */
1191 ia32_peephole_optimization(irg);
1193 be_remove_dead_nodes_from_schedule(irg);
1195 /* create block schedule, this also removes empty blocks which might
1196 * produce critical edges */
1197 irg_data->blk_sched = be_create_block_schedule(irg);
1201 * Emits the code, closes the output file and frees
1202 * the code generator interface.
1204 static void ia32_emit(ir_graph *irg)
1206 if (ia32_cg_config.emit_machcode) {
1207 ia32_gen_binary_routine(irg);
1209 ia32_gen_routine(irg);
1214 * Returns the node representing the PIC base.
1216 static ir_node *ia32_get_pic_base(ir_graph *irg)
1218 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1220 ir_node *get_eip = irg_data->get_eip;
1221 if (get_eip != NULL)
1224 block = get_irg_start_block(irg);
1225 get_eip = new_bd_ia32_GetEIP(NULL, block);
1226 irg_data->get_eip = get_eip;
1232 * Initializes a IA32 code generator.
1234 static void ia32_init_graph(ir_graph *irg)
1236 struct obstack *obst = be_get_be_obst(irg);
1237 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1239 irg_data->dump = (be_options.dump_flags & DUMP_BE) ? 1 : 0;
1242 /* Linux gprof implementation needs base pointer */
1243 be_options.omit_fp = 0;
1246 be_birg_from_irg(irg)->isa_link = irg_data;
1249 static const tarval_mode_info mo_integer = {
1256 * set the tarval output mode of all integer modes to decimal
1258 static void set_tarval_output_modes(void)
1262 for (i = ir_get_n_modes(); i > 0;) {
1263 ir_mode *mode = ir_get_mode(--i);
1265 if (mode_is_int(mode))
1266 set_tarval_mode_output_option(mode, &mo_integer);
1270 extern const arch_isa_if_t ia32_isa_if;
1272 static void init_asm_constraints(void)
1274 be_init_default_asm_constraint_flags();
1276 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1277 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1278 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1279 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1280 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1281 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1282 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1283 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1284 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1285 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1286 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1287 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1288 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1289 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1290 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1291 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1292 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1293 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1294 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1295 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1297 /* no support for autodecrement/autoincrement */
1298 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1299 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1300 /* no float consts */
1301 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1302 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1303 /* makes no sense on x86 */
1304 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1305 /* no support for sse consts yet */
1306 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1307 /* no support for x87 consts yet */
1308 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1309 /* no support for mmx registers yet */
1310 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1311 /* not available in 32bit mode */
1312 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1313 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1315 /* no code yet to determine register class needed... */
1316 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1320 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1322 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1327 ir_relation relation;
1332 cmp_l = get_Cmp_left(sel);
1333 cmp_r = get_Cmp_right(sel);
1334 if (!mode_is_float(get_irn_mode(cmp_l)))
1337 /* check for min/max. They're defined as (C-Semantik):
1338 * min(a, b) = a < b ? a : b
1339 * or min(a, b) = a <= b ? a : b
1340 * max(a, b) = a > b ? a : b
1341 * or max(a, b) = a >= b ? a : b
1342 * (Note we only handle float min/max here)
1344 relation = get_Cmp_relation(sel);
1346 case ir_relation_greater_equal:
1347 case ir_relation_greater:
1349 if (cmp_l == mux_true && cmp_r == mux_false)
1352 case ir_relation_less_equal:
1353 case ir_relation_less:
1355 if (cmp_l == mux_true && cmp_r == mux_false)
1358 case ir_relation_unordered_greater_equal:
1359 case ir_relation_unordered_greater:
1361 if (cmp_l == mux_false && cmp_r == mux_true)
1364 case ir_relation_unordered_less_equal:
1365 case ir_relation_unordered_less:
1367 if (cmp_l == mux_false && cmp_r == mux_true)
1378 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1380 ir_mode *mode = get_irn_mode(mux_true);
1383 if (!mode_is_int(mode) && !mode_is_reference(mode)
1387 if (is_Const(mux_true) && is_Const(mux_false)) {
1388 /* we can create a set plus up two 3 instructions for any combination
1396 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1401 if (!mode_is_float(get_irn_mode(mux_true)))
1404 return is_Const(mux_true) && is_Const(mux_false);
1407 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1414 ir_relation relation;
1419 mode = get_irn_mode(mux_true);
1420 if (mode_is_signed(mode) || mode_is_float(mode))
1423 relation = get_Cmp_relation(sel);
1424 cmp_left = get_Cmp_left(sel);
1425 cmp_right = get_Cmp_right(sel);
1427 /* "move" zero constant to false input */
1428 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1429 ir_node *tmp = mux_false;
1430 mux_false = mux_true;
1432 relation = get_negated_relation(relation);
1434 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1436 if (!is_Sub(mux_true))
1438 sub_left = get_Sub_left(mux_true);
1439 sub_right = get_Sub_right(mux_true);
1441 /* Mux(a >=u b, 0, a-b) */
1442 if ((relation & ir_relation_greater)
1443 && sub_left == cmp_left && sub_right == cmp_right)
1445 /* Mux(a <=u b, 0, b-a) */
1446 if ((relation & ir_relation_less)
1447 && sub_left == cmp_right && sub_right == cmp_left)
1453 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1458 /* middleend can handle some things */
1459 if (ir_is_optimizable_mux(sel, mux_false, mux_true))
1461 /* we can handle Set for all modes and compares */
1462 if (mux_is_set(sel, mux_true, mux_false))
1464 /* SSE has own min/max operations */
1465 if (ia32_cg_config.use_sse2
1466 && mux_is_float_min_max(sel, mux_true, mux_false))
1468 /* we can handle Mux(?, Const[f], Const[f]) */
1469 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1470 #ifdef FIRM_GRGEN_BE
1471 /* well, some code selectors can't handle it */
1472 if (be_transformer != TRANSFORMER_PBQP
1473 || be_transformer != TRANSFORMER_RAND)
1480 /* no support for 64bit inputs to cmov */
1481 mode = get_irn_mode(mux_true);
1482 if (get_mode_size_bits(mode) > 32)
1484 /* we can handle Abs for all modes and compares (except 64bit) */
1485 if (ir_mux_is_abs(sel, mux_false, mux_true) != 0)
1487 /* we can't handle MuxF yet */
1488 if (mode_is_float(mode))
1491 if (mux_is_doz(sel, mux_true, mux_false))
1494 /* Check Cmp before the node */
1496 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1498 /* we can't handle 64bit compares */
1499 if (get_mode_size_bits(cmp_mode) > 32)
1502 /* we can't handle float compares */
1503 if (mode_is_float(cmp_mode))
1507 /* did we disable cmov generation? */
1508 if (!ia32_cg_config.use_cmov)
1511 /* we can use a cmov */
1516 * Create the trampoline code.
1518 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
1520 ir_graph *const irg = get_irn_irg(block);
1521 ir_node * p = trampoline;
1522 ir_mode *const mode = get_irn_mode(p);
1523 ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
1524 ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
1528 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
1529 mem = new_r_Proj(st, mode_M, pn_Store_M);
1530 p = new_r_Add(block, p, one, mode);
1531 st = new_r_Store(block, mem, p, env, cons_none);
1532 mem = new_r_Proj(st, mode_M, pn_Store_M);
1533 p = new_r_Add(block, p, four, mode);
1535 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
1536 mem = new_r_Proj(st, mode_M, pn_Store_M);
1537 p = new_r_Add(block, p, one, mode);
1538 st = new_r_Store(block, mem, p, callee, cons_none);
1539 mem = new_r_Proj(st, mode_M, pn_Store_M);
1544 static const ir_settings_arch_dep_t ia32_arch_dep = {
1545 1, /* also use subs */
1546 4, /* maximum shifts */
1547 63, /* maximum shift amount */
1548 ia32_evaluate_insn, /* evaluate the instruction sequence */
1550 1, /* allow Mulhs */
1551 1, /* allow Mulus */
1552 32, /* Mulh allowed up to 32 bit */
1554 static backend_params ia32_backend_params = {
1555 1, /* support inline assembly */
1556 1, /* support Rotl nodes */
1557 0, /* little endian */
1558 1, /* modulo shift efficient */
1559 0, /* non-modulo shift not efficient */
1560 &ia32_arch_dep, /* will be set later */
1561 ia32_is_mux_allowed,
1562 32, /* machine_size */
1563 NULL, /* float arithmetic mode, will be set below */
1564 NULL, /* long long type */
1565 NULL, /* unsigned long long type */
1566 NULL, /* long double type */
1567 12, /* size of trampoline code */
1568 4, /* alignment of trampoline code */
1569 ia32_create_trampoline_fkt,
1570 4 /* alignment of stack parameter */
1574 * Initializes the backend ISA.
1576 static void ia32_init(void)
1578 ir_mode *mode_long_long;
1579 ir_mode *mode_unsigned_long_long;
1580 ir_type *type_long_long;
1581 ir_type *type_unsigned_long_long;
1583 ia32_setup_cg_config();
1585 init_asm_constraints();
1587 ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0);
1589 /* note mantissa is 64bit but with explicitely encoded 1 so the really
1590 * usable part as counted by firm is only 63 bits */
1591 ia32_mode_E = new_float_mode("E", irma_x86_extended_float, 15, 63);
1592 ia32_type_E = new_type_primitive(ia32_mode_E);
1593 set_type_size_bytes(ia32_type_E, 12);
1594 set_type_alignment_bytes(ia32_type_E, 4);
1596 mode_long_long = new_int_mode("long long", irma_twos_complement, 64, 1, 64);
1597 type_long_long = new_type_primitive(mode_long_long);
1598 mode_unsigned_long_long
1599 = new_int_mode("unsigned long long", irma_twos_complement, 64, 0, 64);
1600 type_unsigned_long_long = new_type_primitive(mode_unsigned_long_long);
1602 ia32_backend_params.type_long_long = type_long_long;
1603 ia32_backend_params.type_unsigned_long_long = type_unsigned_long_long;
1605 if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
1606 ia32_backend_params.mode_float_arithmetic = NULL;
1607 ia32_backend_params.type_long_double = NULL;
1609 ia32_backend_params.mode_float_arithmetic = ia32_mode_E;
1610 ia32_backend_params.type_long_double = ia32_type_E;
1613 ia32_register_init();
1614 obstack_init(&opcodes_obst);
1615 ia32_create_opcodes(&ia32_irn_ops);
1618 static void ia32_finish(void)
1620 if (between_type != NULL) {
1621 free_type(between_type);
1622 between_type = NULL;
1624 ia32_free_opcodes();
1625 obstack_free(&opcodes_obst, NULL);
1629 * The template that generates a new ISA object.
1630 * Note that this template can be changed by command line
1633 static ia32_isa_t ia32_isa_template = {
1635 &ia32_isa_if, /* isa interface implementation */
1640 &ia32_registers[REG_ESP], /* stack pointer register */
1641 &ia32_registers[REG_EBP], /* base pointer register */
1642 2, /* power of two stack alignment, 2^2 == 4 */
1643 7, /* costs for a spill instruction */
1644 5, /* costs for a reload instruction */
1645 false, /* no custom abi handling */
1648 IA32_FPU_ARCH_X87, /* FPU architecture */
1651 static arch_env_t *ia32_begin_codegeneration(void)
1653 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1655 set_tarval_output_modes();
1657 *isa = ia32_isa_template;
1658 isa->tv_ent = pmap_create();
1664 * Closes the output file and frees the ISA structure.
1666 static void ia32_end_codegeneration(void *self)
1668 ia32_isa_t *isa = (ia32_isa_t*)self;
1669 pmap_destroy(isa->tv_ent);
1674 * Returns the register for parameter nr.
1676 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1677 const ir_mode *mode)
1679 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1680 &ia32_registers[REG_ECX],
1681 &ia32_registers[REG_EDX],
1684 static const unsigned MAXNUM_GPREG_ARGS = 3;
1686 static const arch_register_t *gpreg_param_reg_regparam[] = {
1687 &ia32_registers[REG_EAX],
1688 &ia32_registers[REG_EDX],
1689 &ia32_registers[REG_ECX]
1692 static const arch_register_t *gpreg_param_reg_this[] = {
1693 &ia32_registers[REG_ECX],
1698 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1699 &ia32_registers[REG_XMM0],
1700 &ia32_registers[REG_XMM1],
1701 &ia32_registers[REG_XMM2],
1702 &ia32_registers[REG_XMM3],
1703 &ia32_registers[REG_XMM4],
1704 &ia32_registers[REG_XMM5],
1705 &ia32_registers[REG_XMM6],
1706 &ia32_registers[REG_XMM7]
1709 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1710 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1712 static const unsigned MAXNUM_SSE_ARGS = 8;
1714 if ((cc & cc_this_call) && nr == 0)
1715 return gpreg_param_reg_this[0];
1717 if (! (cc & cc_reg_param))
1720 if (mode_is_float(mode)) {
1721 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1723 if (nr >= MAXNUM_SSE_ARGS)
1726 if (cc & cc_this_call) {
1727 return fpreg_sse_param_reg_this[nr];
1729 return fpreg_sse_param_reg_std[nr];
1730 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1731 unsigned num_regparam;
1733 if (get_mode_size_bits(mode) > 32)
1736 if (nr >= MAXNUM_GPREG_ARGS)
1739 if (cc & cc_this_call) {
1740 return gpreg_param_reg_this[nr];
1742 num_regparam = cc & ~cc_bits;
1743 if (num_regparam == 0) {
1744 /* default fastcall */
1745 return gpreg_param_reg_fastcall[nr];
1747 if (nr < num_regparam)
1748 return gpreg_param_reg_regparam[nr];
1752 panic("unknown argument mode");
1756 * Get the ABI restrictions for procedure calls.
1758 static void ia32_get_call_abi(ir_type *method_type, be_abi_call_t *abi)
1763 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1765 /* set abi flags for calls */
1766 /* call_flags.try_omit_fp not changed: can handle both settings */
1767 call_flags.call_has_imm = false; /* No call immediate, we handle this by ourselves */
1769 /* set parameter passing style */
1770 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1772 cc = get_method_calling_convention(method_type);
1773 if (get_method_variadicity(method_type) == variadicity_variadic) {
1774 /* pass all parameters of a variadic function on the stack */
1775 cc = cc_cdecl_set | (cc & cc_this_call);
1777 if (get_method_additional_properties(method_type) & mtp_property_private &&
1778 ia32_cg_config.optimize_cc) {
1779 /* set the fast calling conventions (allowing up to 3) */
1780 cc = SET_FASTCALL(cc) | 3;
1784 /* we have to pop the shadow parameter ourself for compound calls */
1785 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1786 && !(cc & cc_reg_param)) {
1787 pop_amount += get_mode_size_bytes(mode_P_data);
1790 n = get_method_n_params(method_type);
1791 for (i = regnum = 0; i < n; i++) {
1792 const arch_register_t *reg = NULL;
1793 ir_type *tp = get_method_param_type(method_type, i);
1794 ir_mode *mode = get_type_mode(tp);
1797 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1800 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1803 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1804 * movl has a shorter opcode than mov[sz][bw]l */
1805 ir_mode *load_mode = mode;
1808 unsigned size = get_mode_size_bytes(mode);
1810 if (cc & cc_callee_clear_stk) {
1811 pop_amount += (size + 3U) & ~3U;
1814 if (size < 4) load_mode = mode_Iu;
1817 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1821 be_abi_call_set_pop(abi, pop_amount);
1823 /* set return registers */
1824 n = get_method_n_ress(method_type);
1826 assert(n <= 2 && "more than two results not supported");
1828 /* In case of 64bit returns, we will have two 32bit values */
1830 ir_type *tp = get_method_res_type(method_type, 0);
1831 ir_mode *mode = get_type_mode(tp);
1833 assert(!mode_is_float(mode) && "two FP results not supported");
1835 tp = get_method_res_type(method_type, 1);
1836 mode = get_type_mode(tp);
1838 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1840 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1841 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1844 ir_type *tp = get_method_res_type(method_type, 0);
1845 ir_mode *mode = get_type_mode(tp);
1846 const arch_register_t *reg;
1847 assert(is_atomic_type(tp));
1849 reg = mode_is_float(mode) ? &ia32_registers[REG_ST0] : &ia32_registers[REG_EAX];
1851 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1855 static void ia32_mark_remat(ir_node *node)
1857 if (is_ia32_irn(node)) {
1858 set_ia32_is_remat(node);
1862 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
1866 /* we already added all our simple flags to the flags modifier list in
1867 * init, so this flag we don't know. */
1868 return ASM_CONSTRAINT_FLAG_INVALID;
1871 static int ia32_is_valid_clobber(const char *clobber)
1873 return ia32_get_clobber_register(clobber) != NULL;
1876 static void ia32_lower_for_target(void)
1878 ir_mode *mode_gp = ia32_reg_classes[CLASS_ia32_gp].mode;
1879 size_t i, n_irgs = get_irp_n_irgs();
1881 /* perform doubleword lowering */
1882 lwrdw_param_t lower_dw_params = {
1883 1, /* little endian */
1884 64, /* doubleword size */
1885 ia32_create_intrinsic_fkt,
1889 /* lower compound param handling
1890 * Note: we lower compound arguments ourself, since on ia32 we don't
1891 * have hidden parameters but know where to find the structs on the stack.
1892 * (This also forces us to always allocate space for the compound arguments
1893 * on the callframe and we can't just use an arbitrary position on the
1896 lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS);
1898 /* replace floating point operations by function calls */
1899 if (ia32_cg_config.use_softfloat) {
1900 lower_floating_point();
1903 for (i = 0; i < n_irgs; ++i) {
1904 ir_graph *irg = get_irp_irg(i);
1905 /* break up switches with wide ranges */
1906 lower_switch(irg, 4, 256, mode_gp);
1909 ir_prepare_dw_lowering(&lower_dw_params);
1912 for (i = 0; i < n_irgs; ++i) {
1913 ir_graph *irg = get_irp_irg(i);
1914 /* lower for mode_b stuff */
1915 ir_lower_mode_b(irg, mode_Iu);
1918 for (i = 0; i < n_irgs; ++i) {
1919 ir_graph *irg = get_irp_irg(i);
1920 /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
1921 * so we can generate rep movs later, and turn all big CopyBs into
1923 lower_CopyB(irg, 64, 8193, true);
1928 * Returns the libFirm configuration parameter for this backend.
1930 static const backend_params *ia32_get_libfirm_params(void)
1932 return &ia32_backend_params;
1936 * Check if the given register is callee or caller save.
1938 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
1940 switch (reg->global_index) {
1974 static const lc_opt_enum_int_items_t gas_items[] = {
1975 { "elf", OBJECT_FILE_FORMAT_ELF },
1976 { "mingw", OBJECT_FILE_FORMAT_COFF },
1977 { "macho", OBJECT_FILE_FORMAT_MACH_O },
1981 static lc_opt_enum_int_var_t gas_var = {
1982 (int*) &be_gas_object_file_format, gas_items
1985 #ifdef FIRM_GRGEN_BE
1986 static const lc_opt_enum_int_items_t transformer_items[] = {
1987 { "default", TRANSFORMER_DEFAULT },
1988 { "pbqp", TRANSFORMER_PBQP },
1989 { "random", TRANSFORMER_RAND },
1993 static lc_opt_enum_int_var_t transformer_var = {
1994 (int*)&be_transformer, transformer_items
1998 static const lc_opt_table_entry_t ia32_options[] = {
1999 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2000 #ifdef FIRM_GRGEN_BE
2001 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2003 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2004 &ia32_isa_template.base.stack_alignment),
2005 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2009 const arch_isa_if_t ia32_isa_if = {
2012 ia32_get_libfirm_params,
2013 ia32_lower_for_target,
2014 ia32_parse_asm_constraint,
2015 ia32_is_valid_clobber,
2017 ia32_begin_codegeneration,
2018 ia32_end_codegeneration,
2022 ia32_get_pic_base, /* return node used as base in pic code addresses */
2025 ia32_register_saved_by,
2027 ia32_handle_intrinsics,
2028 ia32_before_abi, /* before abi introduce hook */
2030 ia32_before_ra, /* before register allocation hook */
2031 ia32_finish_graph, /* called before codegen */
2032 ia32_emit, /* emit && done */
2035 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2036 void be_init_arch_ia32(void)
2038 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2039 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2041 lc_opt_add_table(ia32_grp, ia32_options);
2042 be_register_isa_if("ia32", &ia32_isa_if);
2044 ia32_init_emitter();
2046 ia32_init_optimize();
2047 ia32_init_transform();
2049 ia32_init_architecture();