2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
55 #include "lower_calls.h"
56 #include "lower_softfloat.h"
60 #include "../benode.h"
61 #include "../belower.h"
62 #include "../besched.h"
65 #include "../beirgmod.h"
66 #include "../be_dbgout.h"
67 #include "../beblocksched.h"
68 #include "../bemachine.h"
69 #include "../bespillslots.h"
70 #include "../bemodule.h"
71 #include "../begnuas.h"
72 #include "../bestate.h"
73 #include "../beflags.h"
74 #include "../betranshlp.h"
75 #include "../belistsched.h"
76 #include "../beabihelper.h"
77 #include "../bestack.h"
79 #include "bearch_ia32_t.h"
81 #include "ia32_new_nodes.h"
82 #include "gen_ia32_regalloc_if.h"
83 #include "gen_ia32_machine.h"
84 #include "ia32_common_transform.h"
85 #include "ia32_transform.h"
86 #include "ia32_emitter.h"
87 #include "ia32_optimize.h"
89 #include "ia32_dbg_stat.h"
90 #include "ia32_finish.h"
92 #include "ia32_architecture.h"
95 #include "ia32_pbqp_transform.h"
97 transformer_t be_transformer = TRANSFORMER_DEFAULT;
100 ir_mode *ia32_mode_fpcw = NULL;
102 /** The current omit-fp state */
103 static ir_type *omit_fp_between_type = NULL;
104 static ir_type *between_type = NULL;
105 static ir_entity *old_bp_ent = NULL;
106 static ir_entity *ret_addr_ent = NULL;
107 static ir_entity *omit_fp_ret_addr_ent = NULL;
110 * The environment for the intrinsic mapping.
112 static ia32_intrinsic_env_t intrinsic_env = {
114 NULL, /* the irg, these entities belong to */
115 NULL, /* entity for __divdi3 library call */
116 NULL, /* entity for __moddi3 library call */
117 NULL, /* entity for __udivdi3 library call */
118 NULL, /* entity for __umoddi3 library call */
122 typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
125 * Used to create per-graph unique pseudo nodes.
127 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
128 create_const_node_func func,
129 const arch_register_t* reg)
131 ir_node *block, *res;
136 block = get_irg_start_block(irg);
137 res = func(NULL, block);
138 arch_set_irn_register(res, reg);
144 /* Creates the unique per irg GP NoReg node. */
145 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
147 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
148 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
149 &ia32_registers[REG_GP_NOREG]);
152 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
154 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
155 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
156 &ia32_registers[REG_VFP_NOREG]);
159 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
161 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
162 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
163 &ia32_registers[REG_XMM_NOREG]);
166 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
168 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
169 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
170 &ia32_registers[REG_FPCW]);
175 * Returns the admissible noreg register node for input register pos of node irn.
177 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
179 ir_graph *irg = get_irn_irg(irn);
180 const arch_register_req_t *req = arch_get_register_req(irn, pos);
182 assert(req != NULL && "Missing register requirements");
183 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
184 return ia32_new_NoReg_gp(irg);
186 if (ia32_cg_config.use_sse2) {
187 return ia32_new_NoReg_xmm(irg);
189 return ia32_new_NoReg_vfp(irg);
193 static arch_irn_class_t ia32_classify(const ir_node *irn)
195 arch_irn_class_t classification = arch_irn_class_none;
197 assert(is_ia32_irn(irn));
199 if (is_ia32_is_reload(irn))
200 classification |= arch_irn_class_reload;
202 if (is_ia32_is_spill(irn))
203 classification |= arch_irn_class_spill;
205 if (is_ia32_is_remat(irn))
206 classification |= arch_irn_class_remat;
208 return classification;
212 * The IA32 ABI callback object.
215 be_abi_call_flags_bits_t flags; /**< The call flags. */
216 ir_graph *irg; /**< The associated graph. */
219 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
221 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
224 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
226 if (is_be_node(node))
227 be_node_set_frame_entity(node, entity);
229 set_ia32_frame_ent(node, entity);
232 static void ia32_set_frame_offset(ir_node *irn, int bias)
234 if (get_ia32_frame_ent(irn) == NULL)
237 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
238 ir_graph *irg = get_irn_irg(irn);
239 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
240 if (layout->sp_relative) {
241 /* Pop nodes modify the stack pointer before calculating the
242 * destination address, so fix this here
247 add_ia32_am_offs_int(irn, bias);
250 static int ia32_get_sp_bias(const ir_node *node)
252 if (is_ia32_Call(node))
253 return -(int)get_ia32_call_attr_const(node)->pop;
255 if (is_ia32_Push(node))
258 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
261 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
262 return SP_BIAS_RESET;
269 * Build the between type and entities if not already build.
271 static void ia32_build_between_type(void)
273 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
274 if (! between_type) {
275 ir_type *old_bp_type = new_type_primitive(mode_Iu);
276 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
278 between_type = new_type_struct(IDENT("ia32_between_type"));
279 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
280 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
282 set_entity_offset(old_bp_ent, 0);
283 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
284 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
285 set_type_state(between_type, layout_fixed);
287 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
288 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
290 set_entity_offset(omit_fp_ret_addr_ent, 0);
291 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
292 set_type_state(omit_fp_between_type, layout_fixed);
298 * Produces the type which sits between the stack args and the locals on the stack.
299 * it will contain the return address and space to store the old base pointer.
300 * @return The Firm type modeling the ABI between type.
302 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
304 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
305 ia32_build_between_type();
306 return layout->sp_relative ? omit_fp_between_type : between_type;
310 * Return the stack entity that contains the return address.
312 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
314 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
315 ia32_build_between_type();
316 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
320 * Return the stack entity that contains the frame address.
322 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
324 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
325 ia32_build_between_type();
326 return layout->sp_relative ? NULL : old_bp_ent;
330 * Get the estimated cycle count for @p irn.
332 * @param self The this pointer.
333 * @param irn The node.
335 * @return The estimated cycle count for this operation
337 static int ia32_get_op_estimated_cost(const ir_node *irn)
340 ia32_op_type_t op_tp;
344 if (!is_ia32_irn(irn))
347 assert(is_ia32_irn(irn));
349 cost = get_ia32_latency(irn);
350 op_tp = get_ia32_op_type(irn);
352 if (is_ia32_CopyB(irn)) {
355 else if (is_ia32_CopyB_i(irn)) {
356 int size = get_ia32_copyb_size(irn);
357 cost = 20 + (int)ceil((4/3) * size);
359 /* in case of address mode operations add additional cycles */
360 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
362 In case of stack access and access to fixed addresses add 5 cycles
363 (we assume they are in cache), other memory operations cost 20
366 if (is_ia32_use_frame(irn) || (
367 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
368 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
380 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
382 * @param irn The original operation
383 * @param i Index of the argument we want the inverse operation to yield
384 * @param inverse struct to be filled with the resulting inverse op
385 * @param obstack The obstack to use for allocation of the returned nodes array
386 * @return The inverse operation or NULL if operation invertible
388 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
399 ir_node *block, *noreg, *nomem;
402 /* we cannot invert non-ia32 irns */
403 if (! is_ia32_irn(irn))
406 /* operand must always be a real operand (not base, index or mem) */
407 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
410 /* we don't invert address mode operations */
411 if (get_ia32_op_type(irn) != ia32_Normal)
414 /* TODO: adjust for new immediates... */
415 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
419 block = get_nodes_block(irn);
420 mode = get_irn_mode(irn);
421 irn_mode = get_irn_mode(irn);
422 noreg = get_irn_n(irn, 0);
423 nomem = get_irg_no_mem(irg);
424 dbgi = get_irn_dbg_info(irn);
426 /* initialize structure */
427 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
431 switch (get_ia32_irn_opcode(irn)) {
433 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
434 /* we have an add with a const here */
435 /* invers == add with negated const */
436 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
438 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
439 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
440 set_ia32_commutative(inverse->nodes[0]);
442 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
443 /* we have an add with a symconst here */
444 /* invers == sub with const */
445 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
447 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
450 /* normal add: inverse == sub */
451 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
456 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
457 /* we have a sub with a const/symconst here */
458 /* invers == add with this const */
459 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
460 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
461 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
465 if (i == n_ia32_binary_left) {
466 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
469 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
475 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
476 /* xor with const: inverse = xor */
477 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
478 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
479 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
483 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
488 inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
493 inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
498 /* inverse operation not supported */
506 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
508 if (mode_is_float(mode))
515 * Get the mode that should be used for spilling value node
517 static ir_mode *get_spill_mode(const ir_node *node)
519 ir_mode *mode = get_irn_mode(node);
520 return get_spill_mode_mode(mode);
524 * Checks whether an addressmode reload for a node with mode mode is compatible
525 * with a spillslot of mode spill_mode
527 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
529 return !mode_is_float(mode) || mode == spillmode;
533 * Check if irn can load its operand at position i from memory (source addressmode).
534 * @param irn The irn to be checked
535 * @param i The operands position
536 * @return Non-Zero if operand can be loaded
538 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
540 ir_node *op = get_irn_n(irn, i);
541 const ir_mode *mode = get_irn_mode(op);
542 const ir_mode *spillmode = get_spill_mode(op);
544 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
545 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
546 !ia32_is_spillmode_compatible(mode, spillmode) ||
547 is_ia32_use_frame(irn)) /* must not already use frame */
550 switch (get_ia32_am_support(irn)) {
555 if (i != n_ia32_unary_op)
561 case n_ia32_binary_left: {
562 const arch_register_req_t *req;
563 if (!is_ia32_commutative(irn))
566 /* we can't swap left/right for limited registers
567 * (As this (currently) breaks constraint handling copies)
569 req = arch_get_in_register_req(irn, n_ia32_binary_left);
570 if (req->type & arch_register_req_type_limited)
575 case n_ia32_binary_right:
584 panic("Unknown AM type");
587 /* HACK: must not already use "real" memory.
588 * This can happen for Call and Div */
589 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
595 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
599 ir_mode *dest_op_mode;
601 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
603 set_ia32_op_type(irn, ia32_AddrModeS);
605 load_mode = get_irn_mode(get_irn_n(irn, i));
606 dest_op_mode = get_ia32_ls_mode(irn);
607 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
608 set_ia32_ls_mode(irn, load_mode);
610 set_ia32_use_frame(irn);
611 set_ia32_need_stackent(irn);
613 if (i == n_ia32_binary_left &&
614 get_ia32_am_support(irn) == ia32_am_binary &&
615 /* immediates are only allowed on the right side */
616 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
617 ia32_swap_left_right(irn);
618 i = n_ia32_binary_right;
621 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
623 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
624 set_irn_n(irn, n_ia32_mem, spill);
625 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
626 set_ia32_is_reload(irn);
629 static const be_abi_callbacks_t ia32_abi_callbacks = {
630 ia32_abi_get_between_type,
633 /* register allocator interface */
634 static const arch_irn_ops_t ia32_irn_ops = {
636 ia32_get_frame_entity,
637 ia32_set_frame_offset,
640 ia32_get_op_estimated_cost,
641 ia32_possible_memory_operand,
642 ia32_perform_memory_operand,
645 static ir_entity *mcount = NULL;
646 static int gprof = 0;
648 static void ia32_before_abi(ir_graph *irg)
651 if (mcount == NULL) {
652 ir_type *tp = new_type_method(0, 0);
653 ident *id = new_id_from_str("mcount");
654 mcount = new_entity(get_glob_type(), id, tp);
655 /* FIXME: enter the right ld_ident here */
656 set_entity_ld_ident(mcount, get_entity_ident(mcount));
657 set_entity_visibility(mcount, ir_visibility_external);
659 instrument_initcall(irg, mcount);
664 * Transforms the standard firm graph into
667 static void ia32_prepare_graph(ir_graph *irg)
669 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
672 switch (be_transformer) {
673 case TRANSFORMER_DEFAULT:
674 /* transform remaining nodes into assembler instructions */
675 ia32_transform_graph(irg);
678 case TRANSFORMER_PBQP:
679 case TRANSFORMER_RAND:
680 /* transform nodes into assembler instructions by PBQP magic */
681 ia32_transform_graph_by_pbqp(irg);
685 panic("invalid transformer");
688 ia32_transform_graph(irg);
691 /* do local optimizations (mainly CSE) */
692 optimize_graph_df(irg);
695 dump_ir_graph(irg, "transformed");
697 /* optimize address mode */
698 ia32_optimize_graph(irg);
700 /* do code placement, to optimize the position of constants */
704 dump_ir_graph(irg, "place");
707 ir_node *ia32_turn_back_am(ir_node *node)
709 dbg_info *dbgi = get_irn_dbg_info(node);
710 ir_graph *irg = get_irn_irg(node);
711 ir_node *block = get_nodes_block(node);
712 ir_node *base = get_irn_n(node, n_ia32_base);
713 ir_node *idx = get_irn_n(node, n_ia32_index);
714 ir_node *mem = get_irn_n(node, n_ia32_mem);
717 ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
718 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
720 ia32_copy_am_attrs(load, node);
721 if (is_ia32_is_reload(node))
722 set_ia32_is_reload(load);
723 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
725 switch (get_ia32_am_support(node)) {
727 set_irn_n(node, n_ia32_unary_op, load_res);
731 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
732 set_irn_n(node, n_ia32_binary_left, load_res);
734 set_irn_n(node, n_ia32_binary_right, load_res);
739 panic("Unknown AM type");
741 noreg = ia32_new_NoReg_gp(current_ir_graph);
742 set_irn_n(node, n_ia32_base, noreg);
743 set_irn_n(node, n_ia32_index, noreg);
744 set_ia32_am_offs_int(node, 0);
745 set_ia32_am_sc(node, NULL);
746 set_ia32_am_scale(node, 0);
747 clear_ia32_am_sc_sign(node);
749 /* rewire mem-proj */
750 if (get_irn_mode(node) == mode_T) {
751 const ir_edge_t *edge;
752 foreach_out_edge(node, edge) {
753 ir_node *out = get_edge_src_irn(edge);
754 if (get_irn_mode(out) == mode_M) {
755 set_Proj_pred(out, load);
756 set_Proj_proj(out, pn_ia32_Load_M);
762 set_ia32_op_type(node, ia32_Normal);
763 if (sched_is_scheduled(node))
764 sched_add_before(node, load);
769 static ir_node *flags_remat(ir_node *node, ir_node *after)
771 /* we should turn back source address mode when rematerializing nodes */
776 if (is_Block(after)) {
779 block = get_nodes_block(after);
782 type = get_ia32_op_type(node);
785 ia32_turn_back_am(node);
789 /* TODO implement this later... */
790 panic("found DestAM with flag user %+F this should not happen", node);
792 default: assert(type == ia32_Normal); break;
795 copy = exact_copy(node);
796 set_nodes_block(copy, block);
797 sched_add_after(after, copy);
803 * Called before the register allocator.
805 static void ia32_before_ra(ir_graph *irg)
807 /* setup fpu rounding modes */
808 ia32_setup_fpu_mode(irg);
811 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
814 be_add_missing_keeps(irg);
819 * Transforms a be_Reload into a ia32 Load.
821 static void transform_to_Load(ir_node *node)
823 ir_graph *irg = get_irn_irg(node);
824 dbg_info *dbgi = get_irn_dbg_info(node);
825 ir_node *block = get_nodes_block(node);
826 ir_entity *ent = be_get_frame_entity(node);
827 ir_mode *mode = get_irn_mode(node);
828 ir_mode *spillmode = get_spill_mode(node);
829 ir_node *noreg = ia32_new_NoReg_gp(irg);
830 ir_node *sched_point = NULL;
831 ir_node *ptr = get_irg_frame(irg);
832 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
833 ir_node *new_op, *proj;
834 const arch_register_t *reg;
836 if (sched_is_scheduled(node)) {
837 sched_point = sched_prev(node);
840 if (mode_is_float(spillmode)) {
841 if (ia32_cg_config.use_sse2)
842 new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
844 new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
846 else if (get_mode_size_bits(spillmode) == 128) {
847 /* Reload 128 bit SSE registers */
848 new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
851 new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
853 set_ia32_op_type(new_op, ia32_AddrModeS);
854 set_ia32_ls_mode(new_op, spillmode);
855 set_ia32_frame_ent(new_op, ent);
856 set_ia32_use_frame(new_op);
857 set_ia32_is_reload(new_op);
859 DBG_OPT_RELOAD2LD(node, new_op);
861 proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
864 sched_add_after(sched_point, new_op);
868 /* copy the register from the old node to the new Load */
869 reg = arch_get_irn_register(node);
870 arch_set_irn_register(proj, reg);
872 SET_IA32_ORIG_NODE(new_op, node);
874 exchange(node, proj);
878 * Transforms a be_Spill node into a ia32 Store.
880 static void transform_to_Store(ir_node *node)
882 ir_graph *irg = get_irn_irg(node);
883 dbg_info *dbgi = get_irn_dbg_info(node);
884 ir_node *block = get_nodes_block(node);
885 ir_entity *ent = be_get_frame_entity(node);
886 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
887 ir_mode *mode = get_spill_mode(spillval);
888 ir_node *noreg = ia32_new_NoReg_gp(irg);
889 ir_node *nomem = get_irg_no_mem(irg);
890 ir_node *ptr = get_irg_frame(irg);
891 ir_node *val = get_irn_n(node, n_be_Spill_val);
894 ir_node *sched_point = NULL;
896 if (sched_is_scheduled(node)) {
897 sched_point = sched_prev(node);
900 if (mode_is_float(mode)) {
901 if (ia32_cg_config.use_sse2) {
902 store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
903 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
905 store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
906 res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
908 } else if (get_mode_size_bits(mode) == 128) {
909 /* Spill 128 bit SSE registers */
910 store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
911 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
912 } else if (get_mode_size_bits(mode) == 8) {
913 store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
914 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
916 store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
917 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
920 set_ia32_op_type(store, ia32_AddrModeD);
921 set_ia32_ls_mode(store, mode);
922 set_ia32_frame_ent(store, ent);
923 set_ia32_use_frame(store);
924 set_ia32_is_spill(store);
925 SET_IA32_ORIG_NODE(store, node);
926 DBG_OPT_SPILL2ST(node, store);
929 sched_add_after(sched_point, store);
936 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
938 dbg_info *dbgi = get_irn_dbg_info(node);
939 ir_node *block = get_nodes_block(node);
940 ir_graph *irg = get_irn_irg(node);
941 ir_node *noreg = ia32_new_NoReg_gp(irg);
942 ir_node *frame = get_irg_frame(irg);
944 ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
946 set_ia32_frame_ent(push, ent);
947 set_ia32_use_frame(push);
948 set_ia32_op_type(push, ia32_AddrModeS);
949 set_ia32_ls_mode(push, mode_Is);
950 set_ia32_is_spill(push);
952 sched_add_before(schedpoint, push);
956 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
958 dbg_info *dbgi = get_irn_dbg_info(node);
959 ir_node *block = get_nodes_block(node);
960 ir_graph *irg = get_irn_irg(node);
961 ir_node *noreg = ia32_new_NoReg_gp(irg);
962 ir_node *frame = get_irg_frame(irg);
964 ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
965 get_irg_no_mem(irg), sp);
967 set_ia32_frame_ent(pop, ent);
968 set_ia32_use_frame(pop);
969 set_ia32_op_type(pop, ia32_AddrModeD);
970 set_ia32_ls_mode(pop, mode_Is);
971 set_ia32_is_reload(pop);
973 sched_add_before(schedpoint, pop);
978 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
980 dbg_info *dbgi = get_irn_dbg_info(node);
981 ir_mode *spmode = mode_Iu;
982 const arch_register_t *spreg = &ia32_registers[REG_ESP];
985 sp = new_rd_Proj(dbgi, pred, spmode, pos);
986 arch_set_irn_register(sp, spreg);
992 * Transform MemPerm, currently we do this the ugly way and produce
993 * push/pop into/from memory cascades. This is possible without using
996 static void transform_MemPerm(ir_node *node)
998 ir_node *block = get_nodes_block(node);
999 ir_graph *irg = get_irn_irg(node);
1000 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
1001 int arity = be_get_MemPerm_entity_arity(node);
1002 ir_node **pops = ALLOCAN(ir_node*, arity);
1006 const ir_edge_t *edge;
1007 const ir_edge_t *next;
1010 for (i = 0; i < arity; ++i) {
1011 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1012 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1013 ir_type *enttype = get_entity_type(inent);
1014 unsigned entsize = get_type_size_bytes(enttype);
1015 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1016 ir_node *mem = get_irn_n(node, i + 1);
1019 /* work around cases where entities have different sizes */
1020 if (entsize2 < entsize)
1022 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1024 push = create_push(node, node, sp, mem, inent);
1025 sp = create_spproj(node, push, pn_ia32_Push_stack);
1027 /* add another push after the first one */
1028 push = create_push(node, node, sp, mem, inent);
1029 add_ia32_am_offs_int(push, 4);
1030 sp = create_spproj(node, push, pn_ia32_Push_stack);
1033 set_irn_n(node, i, new_r_Bad(irg, mode_X));
1037 for (i = arity - 1; i >= 0; --i) {
1038 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1039 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1040 ir_type *enttype = get_entity_type(outent);
1041 unsigned entsize = get_type_size_bytes(enttype);
1042 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1045 /* work around cases where entities have different sizes */
1046 if (entsize2 < entsize)
1048 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1050 pop = create_pop(node, node, sp, outent);
1051 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1053 add_ia32_am_offs_int(pop, 4);
1055 /* add another pop after the first one */
1056 pop = create_pop(node, node, sp, outent);
1057 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1064 keep = be_new_Keep(block, 1, in);
1065 sched_add_before(node, keep);
1067 /* exchange memprojs */
1068 foreach_out_edge_safe(node, edge, next) {
1069 ir_node *proj = get_edge_src_irn(edge);
1070 int p = get_Proj_proj(proj);
1074 set_Proj_pred(proj, pops[p]);
1075 set_Proj_proj(proj, pn_ia32_Pop_M);
1078 /* remove memperm */
1084 * Block-Walker: Calls the transform functions Spill and Reload.
1086 static void ia32_after_ra_walker(ir_node *block, void *env)
1088 ir_node *node, *prev;
1091 /* beware: the schedule is changed here */
1092 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1093 prev = sched_prev(node);
1095 if (be_is_Reload(node)) {
1096 transform_to_Load(node);
1097 } else if (be_is_Spill(node)) {
1098 transform_to_Store(node);
1099 } else if (be_is_MemPerm(node)) {
1100 transform_MemPerm(node);
1106 * Collects nodes that need frame entities assigned.
1108 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1110 be_fec_env_t *env = (be_fec_env_t*)data;
1111 const ir_mode *mode;
1114 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1115 mode = get_spill_mode_mode(get_irn_mode(node));
1116 align = get_mode_size_bytes(mode);
1117 } else if (is_ia32_irn(node) &&
1118 get_ia32_frame_ent(node) == NULL &&
1119 is_ia32_use_frame(node)) {
1120 if (is_ia32_need_stackent(node))
1123 switch (get_ia32_irn_opcode(node)) {
1125 case iro_ia32_Load: {
1126 const ia32_attr_t *attr = get_ia32_attr_const(node);
1128 if (attr->data.need_32bit_stackent) {
1130 } else if (attr->data.need_64bit_stackent) {
1133 mode = get_ia32_ls_mode(node);
1134 if (is_ia32_is_reload(node))
1135 mode = get_spill_mode_mode(mode);
1137 align = get_mode_size_bytes(mode);
1141 case iro_ia32_vfild:
1143 case iro_ia32_xLoad: {
1144 mode = get_ia32_ls_mode(node);
1149 case iro_ia32_FldCW: {
1150 /* although 2 byte would be enough 4 byte performs best */
1158 panic("unexpected frame user while collection frame entity nodes");
1160 case iro_ia32_FnstCW:
1161 case iro_ia32_Store8Bit:
1162 case iro_ia32_Store:
1165 case iro_ia32_vfist:
1166 case iro_ia32_vfisttp:
1168 case iro_ia32_xStore:
1169 case iro_ia32_xStoreSimple:
1176 be_node_needs_frame_entity(env, node, mode, align);
1179 static int determine_ebp_input(ir_node *ret)
1181 const arch_register_t *bp = &ia32_registers[REG_EBP];
1182 int arity = get_irn_arity(ret);
1185 for (i = 0; i < arity; ++i) {
1186 ir_node *input = get_irn_n(ret, i);
1187 if (arch_get_irn_register(input) == bp)
1190 panic("no ebp input found at %+F", ret);
1193 static void introduce_epilog(ir_node *ret)
1195 const arch_register_t *sp = &ia32_registers[REG_ESP];
1196 const arch_register_t *bp = &ia32_registers[REG_EBP];
1197 ir_graph *irg = get_irn_irg(ret);
1198 ir_type *frame_type = get_irg_frame_type(irg);
1199 unsigned frame_size = get_type_size_bytes(frame_type);
1200 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1201 ir_node *block = get_nodes_block(ret);
1202 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1203 ir_node *curr_sp = first_sp;
1204 ir_mode *mode_gp = mode_Iu;
1206 if (!layout->sp_relative) {
1207 int n_ebp = determine_ebp_input(ret);
1208 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1209 if (ia32_cg_config.use_leave) {
1210 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1211 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1212 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1213 arch_set_irn_register(curr_bp, bp);
1214 arch_set_irn_register(curr_sp, sp);
1215 sched_add_before(ret, leave);
1218 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1219 /* copy ebp to esp */
1220 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1221 arch_set_irn_register(curr_sp, sp);
1222 sched_add_before(ret, curr_sp);
1225 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1226 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1227 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1228 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1229 arch_set_irn_register(curr_bp, bp);
1230 arch_set_irn_register(curr_sp, sp);
1231 sched_add_before(ret, pop);
1233 set_irn_n(ret, n_be_Return_mem, curr_mem);
1235 set_irn_n(ret, n_ebp, curr_bp);
1237 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1238 sched_add_before(ret, incsp);
1241 set_irn_n(ret, n_be_Return_sp, curr_sp);
1243 /* keep verifier happy... */
1244 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1245 kill_node(first_sp);
1250 * put the Prolog code at the beginning, epilog code before each return
1252 static void introduce_prolog_epilog(ir_graph *irg)
1254 const arch_register_t *sp = &ia32_registers[REG_ESP];
1255 const arch_register_t *bp = &ia32_registers[REG_EBP];
1256 ir_node *start = get_irg_start(irg);
1257 ir_node *block = get_nodes_block(start);
1258 ir_type *frame_type = get_irg_frame_type(irg);
1259 unsigned frame_size = get_type_size_bytes(frame_type);
1260 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1261 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1262 ir_node *curr_sp = initial_sp;
1263 ir_mode *mode_gp = mode_Iu;
1265 if (!layout->sp_relative) {
1267 ir_node *mem = get_irg_initial_mem(irg);
1268 ir_node *noreg = ia32_new_NoReg_gp(irg);
1269 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1270 ir_node *curr_bp = initial_bp;
1271 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
1274 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1275 mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
1276 arch_set_irn_register(curr_sp, sp);
1277 sched_add_after(start, push);
1279 /* move esp to ebp */
1280 curr_bp = be_new_Copy(bp->reg_class, block, curr_sp);
1281 sched_add_after(push, curr_bp);
1282 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1283 curr_sp = be_new_CopyKeep_single(sp->reg_class, block, curr_sp, curr_bp, mode_gp);
1284 sched_add_after(curr_bp, curr_sp);
1285 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1286 edges_reroute(initial_bp, curr_bp);
1287 set_irn_n(push, n_ia32_Push_val, initial_bp);
1289 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1290 edges_reroute(initial_sp, incsp);
1291 set_irn_n(push, n_ia32_Push_stack, initial_sp);
1292 sched_add_after(curr_sp, incsp);
1294 layout->initial_bias = -4;
1296 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1297 edges_reroute(initial_sp, incsp);
1298 be_set_IncSP_pred(incsp, curr_sp);
1299 sched_add_after(start, incsp);
1302 /* introduce epilog for every return node */
1304 ir_node *end_block = get_irg_end_block(irg);
1305 int arity = get_irn_arity(end_block);
1308 for (i = 0; i < arity; ++i) {
1309 ir_node *ret = get_irn_n(end_block, i);
1310 assert(be_is_Return(ret));
1311 introduce_epilog(ret);
1317 * Last touchups for the graph before emit: x87 simulation to replace the
1318 * virtual with real x87 instructions, creating a block schedule and peephole
1321 static void ia32_finish(ir_graph *irg)
1323 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1324 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1325 bool at_begin = stack_layout->sp_relative ? true : false;
1326 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1328 /* create and coalesce frame entities */
1329 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1330 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1331 be_free_frame_entity_coalescer(fec_env);
1333 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1335 introduce_prolog_epilog(irg);
1337 /* fix stack entity offsets */
1338 be_abi_fix_stack_nodes(irg);
1339 be_abi_fix_stack_bias(irg);
1341 /* fix 2-address code constraints */
1342 ia32_finish_irg(irg);
1344 /* we might have to rewrite x87 virtual registers */
1345 if (irg_data->do_x87_sim) {
1346 ia32_x87_simulate_graph(irg);
1349 /* do peephole optimisations */
1350 ia32_peephole_optimization(irg);
1352 be_remove_dead_nodes_from_schedule(irg);
1354 /* create block schedule, this also removes empty blocks which might
1355 * produce critical edges */
1356 irg_data->blk_sched = be_create_block_schedule(irg);
1360 * Emits the code, closes the output file and frees
1361 * the code generator interface.
1363 static void ia32_emit(ir_graph *irg)
1365 if (ia32_cg_config.emit_machcode) {
1366 ia32_gen_binary_routine(irg);
1368 ia32_gen_routine(irg);
1373 * Returns the node representing the PIC base.
1375 static ir_node *ia32_get_pic_base(ir_graph *irg)
1377 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1379 ir_node *get_eip = irg_data->get_eip;
1380 if (get_eip != NULL)
1383 block = get_irg_start_block(irg);
1384 get_eip = new_bd_ia32_GetEIP(NULL, block);
1385 irg_data->get_eip = get_eip;
1391 * Initializes a IA32 code generator.
1393 static void ia32_init_graph(ir_graph *irg)
1395 struct obstack *obst = be_get_be_obst(irg);
1396 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1398 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1401 /* Linux gprof implementation needs base pointer */
1402 be_get_irg_options(irg)->omit_fp = 0;
1405 be_birg_from_irg(irg)->isa_link = irg_data;
1410 * Set output modes for GCC
1412 static const tarval_mode_info mo_integer = {
1419 * set the tarval output mode of all integer modes to decimal
1421 static void set_tarval_output_modes(void)
1425 for (i = get_irp_n_modes(); i > 0;) {
1426 ir_mode *mode = get_irp_mode(--i);
1428 if (mode_is_int(mode))
1429 set_tarval_mode_output_option(mode, &mo_integer);
1433 extern const arch_isa_if_t ia32_isa_if;
1436 * The template that generates a new ISA object.
1437 * Note that this template can be changed by command line
1440 static ia32_isa_t ia32_isa_template = {
1442 &ia32_isa_if, /* isa interface implementation */
1447 &ia32_registers[REG_ESP], /* stack pointer register */
1448 &ia32_registers[REG_EBP], /* base pointer register */
1449 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1450 2, /* power of two stack alignment, 2^2 == 4 */
1451 NULL, /* main environment */
1452 7, /* costs for a spill instruction */
1453 5, /* costs for a reload instruction */
1454 false, /* no custom abi handling */
1458 NULL, /* abstract machine */
1459 IA32_FPU_ARCH_X87, /* FPU architecture */
1462 static void init_asm_constraints(void)
1464 be_init_default_asm_constraint_flags();
1466 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1467 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1468 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1469 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1470 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1471 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1472 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1473 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1474 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1475 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1476 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1477 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1478 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1479 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1480 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1481 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1482 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1483 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1484 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1485 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1487 /* no support for autodecrement/autoincrement */
1488 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1489 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1490 /* no float consts */
1491 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1492 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1493 /* makes no sense on x86 */
1494 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1495 /* no support for sse consts yet */
1496 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1497 /* no support for x87 consts yet */
1498 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1499 /* no support for mmx registers yet */
1500 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1501 /* not available in 32bit mode */
1502 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1503 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1505 /* no code yet to determine register class needed... */
1506 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1510 * Initializes the backend ISA.
1512 static arch_env_t *ia32_init(FILE *file_handle)
1514 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1516 set_tarval_output_modes();
1518 *isa = ia32_isa_template;
1520 if (ia32_mode_fpcw == NULL) {
1521 ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1524 ia32_register_init();
1525 ia32_create_opcodes(&ia32_irn_ops);
1527 be_emit_init(file_handle);
1528 isa->types = pmap_create();
1529 isa->tv_ent = pmap_create();
1530 isa->cpu = ia32_init_machine_description();
1532 /* enter the ISA object into the intrinsic environment */
1533 intrinsic_env.isa = isa;
1541 * Closes the output file and frees the ISA structure.
1543 static void ia32_done(void *self)
1545 ia32_isa_t *isa = (ia32_isa_t*)self;
1547 /* emit now all global declarations */
1548 be_gas_emit_decls(isa->base.main_env);
1550 pmap_destroy(isa->tv_ent);
1551 pmap_destroy(isa->types);
1560 * Get the register class which shall be used to store a value of a given mode.
1561 * @param self The this pointer.
1562 * @param mode The mode in question.
1563 * @return A register class which can hold values of the given mode.
1565 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1567 if (mode_is_float(mode)) {
1568 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1571 return &ia32_reg_classes[CLASS_ia32_gp];
1575 * Returns the register for parameter nr.
1577 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1578 const ir_mode *mode)
1580 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1581 &ia32_registers[REG_ECX],
1582 &ia32_registers[REG_EDX],
1585 static const unsigned MAXNUM_GPREG_ARGS = 3;
1587 static const arch_register_t *gpreg_param_reg_regparam[] = {
1588 &ia32_registers[REG_EAX],
1589 &ia32_registers[REG_EDX],
1590 &ia32_registers[REG_ECX]
1593 static const arch_register_t *gpreg_param_reg_this[] = {
1594 &ia32_registers[REG_ECX],
1599 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1600 &ia32_registers[REG_XMM0],
1601 &ia32_registers[REG_XMM1],
1602 &ia32_registers[REG_XMM2],
1603 &ia32_registers[REG_XMM3],
1604 &ia32_registers[REG_XMM4],
1605 &ia32_registers[REG_XMM5],
1606 &ia32_registers[REG_XMM6],
1607 &ia32_registers[REG_XMM7]
1610 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1611 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1613 static const unsigned MAXNUM_SSE_ARGS = 8;
1615 if ((cc & cc_this_call) && nr == 0)
1616 return gpreg_param_reg_this[0];
1618 if (! (cc & cc_reg_param))
1621 if (mode_is_float(mode)) {
1622 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1624 if (nr >= MAXNUM_SSE_ARGS)
1627 if (cc & cc_this_call) {
1628 return fpreg_sse_param_reg_this[nr];
1630 return fpreg_sse_param_reg_std[nr];
1631 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1632 unsigned num_regparam;
1634 if (get_mode_size_bits(mode) > 32)
1637 if (nr >= MAXNUM_GPREG_ARGS)
1640 if (cc & cc_this_call) {
1641 return gpreg_param_reg_this[nr];
1643 num_regparam = cc & ~cc_bits;
1644 if (num_regparam == 0) {
1645 /* default fastcall */
1646 return gpreg_param_reg_fastcall[nr];
1648 if (nr < num_regparam)
1649 return gpreg_param_reg_regparam[nr];
1653 panic("unknown argument mode");
1657 * Get the ABI restrictions for procedure calls.
1658 * @param self The this pointer.
1659 * @param method_type The type of the method (procedure) in question.
1660 * @param abi The abi object to be modified
1662 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1668 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1672 /* set abi flags for calls */
1673 call_flags.bits.store_args_sequential = 0;
1674 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1675 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1676 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1678 /* set parameter passing style */
1679 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1681 cc = get_method_calling_convention(method_type);
1682 if (get_method_variadicity(method_type) == variadicity_variadic) {
1683 /* pass all parameters of a variadic function on the stack */
1684 cc = cc_cdecl_set | (cc & cc_this_call);
1686 if (get_method_additional_properties(method_type) & mtp_property_private &&
1687 ia32_cg_config.optimize_cc) {
1688 /* set the fast calling conventions (allowing up to 3) */
1689 cc = SET_FASTCALL(cc) | 3;
1693 /* we have to pop the shadow parameter ourself for compound calls */
1694 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1695 && !(cc & cc_reg_param)) {
1696 pop_amount += get_mode_size_bytes(mode_P_data);
1699 n = get_method_n_params(method_type);
1700 for (i = regnum = 0; i < n; i++) {
1701 const arch_register_t *reg = NULL;
1702 ir_type *tp = get_method_param_type(method_type, i);
1703 ir_mode *mode = get_type_mode(tp);
1706 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1709 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1712 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1713 * movl has a shorter opcode than mov[sz][bw]l */
1714 ir_mode *load_mode = mode;
1717 unsigned size = get_mode_size_bytes(mode);
1719 if (cc & cc_callee_clear_stk) {
1720 pop_amount += (size + 3U) & ~3U;
1723 if (size < 4) load_mode = mode_Iu;
1726 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1730 be_abi_call_set_pop(abi, pop_amount);
1732 /* set return registers */
1733 n = get_method_n_ress(method_type);
1735 assert(n <= 2 && "more than two results not supported");
1737 /* In case of 64bit returns, we will have two 32bit values */
1739 ir_type *tp = get_method_res_type(method_type, 0);
1740 ir_mode *mode = get_type_mode(tp);
1742 assert(!mode_is_float(mode) && "two FP results not supported");
1744 tp = get_method_res_type(method_type, 1);
1745 mode = get_type_mode(tp);
1747 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1749 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1750 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1753 ir_type *tp = get_method_res_type(method_type, 0);
1754 ir_mode *mode = get_type_mode(tp);
1755 const arch_register_t *reg;
1756 assert(is_atomic_type(tp));
1758 reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
1760 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1765 * Returns the necessary byte alignment for storing a register of given class.
1767 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1769 ir_mode *mode = arch_register_class_mode(cls);
1770 int bytes = get_mode_size_bytes(mode);
1772 if (mode_is_float(mode) && bytes > 8)
1778 * Return irp irgs in the desired order.
1780 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1787 static void ia32_mark_remat(ir_node *node)
1789 if (is_ia32_irn(node)) {
1790 set_ia32_is_remat(node);
1795 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1797 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1802 ir_relation relation;
1807 cmp_l = get_Cmp_left(sel);
1808 cmp_r = get_Cmp_right(sel);
1809 if (!mode_is_float(get_irn_mode(cmp_l)))
1812 /* check for min/max. They're defined as (C-Semantik):
1813 * min(a, b) = a < b ? a : b
1814 * or min(a, b) = a <= b ? a : b
1815 * max(a, b) = a > b ? a : b
1816 * or max(a, b) = a >= b ? a : b
1817 * (Note we only handle float min/max here)
1819 relation = get_Cmp_relation(sel);
1821 case ir_relation_greater_equal:
1822 case ir_relation_greater:
1824 if (cmp_l == mux_true && cmp_r == mux_false)
1827 case ir_relation_less_equal:
1828 case ir_relation_less:
1830 if (cmp_l == mux_true && cmp_r == mux_false)
1833 case ir_relation_unordered_greater_equal:
1834 case ir_relation_unordered_greater:
1836 if (cmp_l == mux_false && cmp_r == mux_true)
1839 case ir_relation_unordered_less_equal:
1840 case ir_relation_unordered_less:
1842 if (cmp_l == mux_false && cmp_r == mux_true)
1853 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1855 ir_mode *mode = get_irn_mode(mux_true);
1858 if (!mode_is_int(mode) && !mode_is_reference(mode)
1862 if (is_Const(mux_true) && is_Const(mux_false)) {
1863 /* we can create a set plus up two 3 instructions for any combination
1871 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1876 if (!mode_is_float(get_irn_mode(mux_true)))
1879 return is_Const(mux_true) && is_Const(mux_false);
1882 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1889 ir_relation relation;
1894 mode = get_irn_mode(mux_true);
1895 if (mode_is_signed(mode) || mode_is_float(mode))
1898 relation = get_Cmp_relation(sel);
1899 cmp_left = get_Cmp_left(sel);
1900 cmp_right = get_Cmp_right(sel);
1902 /* "move" zero constant to false input */
1903 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1904 ir_node *tmp = mux_false;
1905 mux_false = mux_true;
1907 relation = get_negated_relation(relation);
1909 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1911 if (!is_Sub(mux_true))
1913 sub_left = get_Sub_left(mux_true);
1914 sub_right = get_Sub_right(mux_true);
1916 /* Mux(a >=u b, 0, a-b) */
1917 if ((relation & ir_relation_greater)
1918 && sub_left == cmp_left && sub_right == cmp_right)
1920 /* Mux(a <=u b, 0, b-a) */
1921 if ((relation & ir_relation_less)
1922 && sub_left == cmp_right && sub_right == cmp_left)
1928 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1933 /* we can handle Set for all modes and compares */
1934 if (mux_is_set(sel, mux_true, mux_false))
1936 /* SSE has own min/max operations */
1937 if (ia32_cg_config.use_sse2
1938 && mux_is_float_min_max(sel, mux_true, mux_false))
1940 /* we can handle Mux(?, Const[f], Const[f]) */
1941 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1942 #ifdef FIRM_GRGEN_BE
1943 /* well, some code selectors can't handle it */
1944 if (be_transformer != TRANSFORMER_PBQP
1945 || be_transformer != TRANSFORMER_RAND)
1952 /* no support for 64bit inputs to cmov */
1953 mode = get_irn_mode(mux_true);
1954 if (get_mode_size_bits(mode) > 32)
1956 /* we can handle Abs for all modes and compares (except 64bit) */
1957 if (ir_mux_is_abs(sel, mux_true, mux_false) != 0)
1959 /* we can't handle MuxF yet */
1960 if (mode_is_float(mode))
1963 if (mux_is_doz(sel, mux_true, mux_false))
1966 /* Check Cmp before the node */
1968 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1970 /* we can't handle 64bit compares */
1971 if (get_mode_size_bits(cmp_mode) > 32)
1974 /* we can't handle float compares */
1975 if (mode_is_float(cmp_mode))
1979 /* did we disable cmov generation? */
1980 if (!ia32_cg_config.use_cmov)
1983 /* we can use a cmov */
1987 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
1991 /* we already added all our simple flags to the flags modifier list in
1992 * init, so this flag we don't know. */
1993 return ASM_CONSTRAINT_FLAG_INVALID;
1996 static int ia32_is_valid_clobber(const char *clobber)
1998 return ia32_get_clobber_register(clobber) != NULL;
2001 static ir_node *ia32_create_set(ir_node *cond)
2003 /* ia32-set function produces 8-bit results which have to be converted */
2004 ir_node *set = ir_create_mux_set(cond, mode_Bu);
2005 ir_node *block = get_nodes_block(set);
2006 return new_r_Conv(block, set, mode_Iu);
2009 static void ia32_lower_for_target(void)
2011 size_t i, n_irgs = get_irp_n_irgs();
2012 lower_mode_b_config_t lower_mode_b_config = {
2013 mode_Iu, /* lowered mode */
2015 0, /* don't lower direct compares */
2018 /* perform doubleword lowering */
2019 lwrdw_param_t lower_dw_params = {
2020 1, /* little endian */
2021 64, /* doubleword size */
2022 ia32_create_intrinsic_fkt,
2026 /* lower compound param handling */
2027 lower_calls_with_compounds(LF_RETURN_HIDDEN);
2029 /* replace floating point operations by function calls */
2030 if (ia32_cg_config.use_softfloat) {
2031 lower_floating_point();
2034 ir_prepare_dw_lowering(&lower_dw_params);
2037 for (i = 0; i < n_irgs; ++i) {
2038 ir_graph *irg = get_irp_irg(i);
2039 /* lower for mode_b stuff */
2040 ir_lower_mode_b(irg, &lower_mode_b_config);
2041 /* break up switches with wide ranges */
2042 lower_switch(irg, 4, 256, false);
2047 * Create the trampoline code.
2049 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2051 ir_graph *irg = get_irn_irg(block);
2052 ir_node *p = trampoline;
2053 ir_mode *mode = get_irn_mode(p);
2057 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
2058 mem = new_r_Proj(st, mode_M, pn_Store_M);
2059 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2060 st = new_r_Store(block, mem, p, env, cons_none);
2061 mem = new_r_Proj(st, mode_M, pn_Store_M);
2062 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2064 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
2065 mem = new_r_Proj(st, mode_M, pn_Store_M);
2066 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2067 st = new_r_Store(block, mem, p, callee, cons_none);
2068 mem = new_r_Proj(st, mode_M, pn_Store_M);
2069 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2075 * Returns the libFirm configuration parameter for this backend.
2077 static const backend_params *ia32_get_libfirm_params(void)
2079 static const ir_settings_arch_dep_t ad = {
2080 1, /* also use subs */
2081 4, /* maximum shifts */
2082 63, /* maximum shift amount */
2083 ia32_evaluate_insn, /* evaluate the instruction sequence */
2085 1, /* allow Mulhs */
2086 1, /* allow Mulus */
2087 32, /* Mulh allowed up to 32 bit */
2089 static backend_params p = {
2090 1, /* support inline assembly */
2091 1, /* support Rotl nodes */
2092 0, /* little endian */
2093 1, /* modulo shift efficient */
2094 0, /* non-modulo shift not efficient */
2095 &ad, /* will be set later */
2096 ia32_is_mux_allowed,
2097 32, /* machine_size */
2098 NULL, /* float arithmetic mode, will be set below */
2099 NULL, /* long long type */
2100 NULL, /* unsigned long long type */
2101 NULL, /* long double type */
2102 12, /* size of trampoline code */
2103 4, /* alignment of trampoline code */
2104 ia32_create_trampoline_fkt,
2105 4 /* alignment of stack parameter */
2107 ir_mode *mode_long_long
2108 = new_ir_mode("long long", irms_int_number, 64, 1, irma_twos_complement,
2110 ir_type *type_long_long = new_type_primitive(mode_long_long);
2111 ir_mode *mode_unsigned_long_long
2112 = new_ir_mode("unsigned long long", irms_int_number, 64, 0,
2113 irma_twos_complement, 64);
2114 ir_type *type_unsigned_long_long
2115 = new_type_primitive(mode_unsigned_long_long);
2117 ia32_setup_cg_config();
2119 /* doesn't really belong here, but this is the earliest place the backend
2121 init_asm_constraints();
2123 p.type_long_long = type_long_long;
2124 p.type_unsigned_long_long = type_unsigned_long_long;
2126 if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
2127 p.mode_float_arithmetic = NULL;
2128 p.type_long_double = NULL;
2130 p.mode_float_arithmetic = mode_E;
2131 ir_mode *mode = new_ir_mode("long double", irms_float_number, 80, 1,
2133 ir_type *type = new_type_primitive(mode);
2134 set_type_size_bytes(type, 12);
2135 set_type_alignment_bytes(type, 4);
2136 p.type_long_double = type;
2142 * Check if the given register is callee or caller save.
2144 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
2147 /* check for callee saved */
2148 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2149 switch (reg->index) {
2160 /* check for caller saved */
2161 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2162 switch (reg->index) {
2170 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
2171 /* all XMM registers are caller save */
2172 return reg->index != REG_XMM_NOREG;
2173 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
2174 /* all VFP registers are caller save */
2175 return reg->index != REG_VFP_NOREG;
2181 static const lc_opt_enum_int_items_t gas_items[] = {
2182 { "elf", OBJECT_FILE_FORMAT_ELF },
2183 { "mingw", OBJECT_FILE_FORMAT_COFF },
2184 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2188 static lc_opt_enum_int_var_t gas_var = {
2189 (int*) &be_gas_object_file_format, gas_items
2192 #ifdef FIRM_GRGEN_BE
2193 static const lc_opt_enum_int_items_t transformer_items[] = {
2194 { "default", TRANSFORMER_DEFAULT },
2195 { "pbqp", TRANSFORMER_PBQP },
2196 { "random", TRANSFORMER_RAND },
2200 static lc_opt_enum_int_var_t transformer_var = {
2201 (int*)&be_transformer, transformer_items
2205 static const lc_opt_table_entry_t ia32_options[] = {
2206 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2207 #ifdef FIRM_GRGEN_BE
2208 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2210 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2211 &ia32_isa_template.base.stack_alignment),
2212 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2216 const arch_isa_if_t ia32_isa_if = {
2218 ia32_lower_for_target,
2220 ia32_handle_intrinsics,
2221 ia32_get_reg_class_for_mode,
2223 ia32_get_reg_class_alignment,
2224 ia32_get_libfirm_params,
2227 ia32_parse_asm_constraint,
2228 ia32_is_valid_clobber,
2231 ia32_get_pic_base, /* return node used as base in pic code addresses */
2232 ia32_before_abi, /* before abi introduce hook */
2234 ia32_before_ra, /* before register allocation hook */
2235 ia32_finish, /* called before codegen */
2236 ia32_emit, /* emit && done */
2237 ia32_register_saved_by,
2240 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2241 void be_init_arch_ia32(void)
2243 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2244 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2246 lc_opt_add_table(ia32_grp, ia32_options);
2247 be_register_isa_if("ia32", &ia32_isa_if);
2249 ia32_init_emitter();
2251 ia32_init_optimize();
2252 ia32_init_transform();
2254 ia32_init_architecture();