2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
28 #include "lc_opts_enum.h"
36 #include "iredges_t.h"
49 #include "iroptimize.h"
50 #include "instrument.h"
53 #include "lower_calls.h"
54 #include "lower_mode_b.h"
55 #include "lower_softfloat.h"
65 #include "be_dbgout.h"
66 #include "beblocksched.h"
67 #include "bespillutil.h"
68 #include "bespillslots.h"
73 #include "betranshlp.h"
74 #include "belistsched.h"
75 #include "beabihelper.h"
78 #include "bearch_ia32_t.h"
80 #include "ia32_new_nodes.h"
81 #include "gen_ia32_regalloc_if.h"
82 #include "ia32_common_transform.h"
83 #include "ia32_transform.h"
84 #include "ia32_emitter.h"
85 #include "ia32_optimize.h"
87 #include "ia32_dbg_stat.h"
88 #include "ia32_finish.h"
90 #include "ia32_architecture.h"
93 #include "ia32_pbqp_transform.h"
95 transformer_t be_transformer = TRANSFORMER_DEFAULT;
98 ir_mode *ia32_mode_fpcw;
100 ir_type *ia32_type_E;
102 /** The current omit-fp state */
103 static ir_type *omit_fp_between_type = NULL;
104 static ir_type *between_type = NULL;
105 static ir_entity *old_bp_ent = NULL;
106 static ir_entity *ret_addr_ent = NULL;
107 static ir_entity *omit_fp_ret_addr_ent = NULL;
110 * The environment for the intrinsic mapping.
112 static ia32_intrinsic_env_t intrinsic_env = {
114 NULL, /* the irg, these entities belong to */
115 NULL, /* entity for __divdi3 library call */
116 NULL, /* entity for __moddi3 library call */
117 NULL, /* entity for __udivdi3 library call */
118 NULL, /* entity for __umoddi3 library call */
122 typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
125 * Used to create per-graph unique pseudo nodes.
127 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
128 create_const_node_func func,
129 const arch_register_t* reg)
131 ir_node *block, *res;
136 block = get_irg_start_block(irg);
137 res = func(NULL, block);
138 arch_set_irn_register(res, reg);
144 /* Creates the unique per irg GP NoReg node. */
145 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
147 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
148 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
149 &ia32_registers[REG_GP_NOREG]);
152 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
154 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
155 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
156 &ia32_registers[REG_VFP_NOREG]);
159 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
161 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
162 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
163 &ia32_registers[REG_XMM_NOREG]);
166 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
168 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
169 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
170 &ia32_registers[REG_FPCW]);
175 * Returns the admissible noreg register node for input register pos of node irn.
177 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
179 ir_graph *irg = get_irn_irg(irn);
180 const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
182 assert(req != NULL && "Missing register requirements");
183 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
184 return ia32_new_NoReg_gp(irg);
186 if (ia32_cg_config.use_sse2) {
187 return ia32_new_NoReg_xmm(irg);
189 return ia32_new_NoReg_vfp(irg);
194 * The IA32 ABI callback object.
197 be_abi_call_flags_bits_t flags; /**< The call flags. */
198 ir_graph *irg; /**< The associated graph. */
201 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
203 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
206 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
208 if (is_be_node(node))
209 be_node_set_frame_entity(node, entity);
211 set_ia32_frame_ent(node, entity);
214 static void ia32_set_frame_offset(ir_node *irn, int bias)
216 if (get_ia32_frame_ent(irn) == NULL)
219 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
220 ir_graph *irg = get_irn_irg(irn);
221 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
222 if (layout->sp_relative) {
223 /* Pop nodes modify the stack pointer before calculating the
224 * destination address, so fix this here
229 add_ia32_am_offs_int(irn, bias);
232 static int ia32_get_sp_bias(const ir_node *node)
234 if (is_ia32_Call(node))
235 return -(int)get_ia32_call_attr_const(node)->pop;
237 if (is_ia32_Push(node))
240 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
243 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
244 return SP_BIAS_RESET;
251 * Build the between type and entities if not already build.
253 static void ia32_build_between_type(void)
255 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
256 if (between_type == NULL) {
257 ir_type *old_bp_type = new_type_primitive(mode_Iu);
258 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
260 between_type = new_type_struct(IDENT("ia32_between_type"));
261 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
262 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
264 set_entity_offset(old_bp_ent, 0);
265 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
266 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
267 set_type_state(between_type, layout_fixed);
269 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
270 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
272 set_entity_offset(omit_fp_ret_addr_ent, 0);
273 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
274 set_type_state(omit_fp_between_type, layout_fixed);
280 * Produces the type which sits between the stack args and the locals on the stack.
281 * it will contain the return address and space to store the old base pointer.
282 * @return The Firm type modeling the ABI between type.
284 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
286 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
287 ia32_build_between_type();
288 return layout->sp_relative ? omit_fp_between_type : between_type;
292 * Return the stack entity that contains the return address.
294 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
296 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
297 ia32_build_between_type();
298 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
302 * Return the stack entity that contains the frame address.
304 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
306 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
307 ia32_build_between_type();
308 return layout->sp_relative ? NULL : old_bp_ent;
312 * Get the estimated cycle count for @p irn.
314 * @param self The this pointer.
315 * @param irn The node.
317 * @return The estimated cycle count for this operation
319 static int ia32_get_op_estimated_cost(const ir_node *irn)
322 ia32_op_type_t op_tp;
326 if (!is_ia32_irn(irn))
329 assert(is_ia32_irn(irn));
331 cost = get_ia32_latency(irn);
332 op_tp = get_ia32_op_type(irn);
334 if (is_ia32_CopyB(irn)) {
337 else if (is_ia32_CopyB_i(irn)) {
338 int size = get_ia32_copyb_size(irn);
339 cost = 20 + (int)ceil((4/3) * size);
341 /* in case of address mode operations add additional cycles */
342 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
344 In case of stack access and access to fixed addresses add 5 cycles
345 (we assume they are in cache), other memory operations cost 20
348 if (is_ia32_use_frame(irn) || (
349 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
350 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
362 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
364 * @param irn The original operation
365 * @param i Index of the argument we want the inverse operation to yield
366 * @param inverse struct to be filled with the resulting inverse op
367 * @param obstack The obstack to use for allocation of the returned nodes array
368 * @return The inverse operation or NULL if operation invertible
370 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
381 ir_node *block, *noreg, *nomem;
384 /* we cannot invert non-ia32 irns */
385 if (! is_ia32_irn(irn))
388 /* operand must always be a real operand (not base, index or mem) */
389 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
392 /* we don't invert address mode operations */
393 if (get_ia32_op_type(irn) != ia32_Normal)
396 /* TODO: adjust for new immediates... */
397 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
401 block = get_nodes_block(irn);
402 mode = get_irn_mode(irn);
403 irn_mode = get_irn_mode(irn);
404 noreg = get_irn_n(irn, 0);
405 nomem = get_irg_no_mem(irg);
406 dbgi = get_irn_dbg_info(irn);
408 /* initialize structure */
409 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
413 switch (get_ia32_irn_opcode(irn)) {
415 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
416 /* we have an add with a const here */
417 /* invers == add with negated const */
418 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
420 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
421 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
422 set_ia32_commutative(inverse->nodes[0]);
424 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
425 /* we have an add with a symconst here */
426 /* invers == sub with const */
427 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
429 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
432 /* normal add: inverse == sub */
433 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
438 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
439 /* we have a sub with a const/symconst here */
440 /* invers == add with this const */
441 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
442 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
443 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
447 if (i == n_ia32_binary_left) {
448 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
451 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
457 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
458 /* xor with const: inverse = xor */
459 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
460 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
461 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
465 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
470 inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
475 inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
480 /* inverse operation not supported */
488 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
490 if (mode_is_float(mode))
497 * Get the mode that should be used for spilling value node
499 static ir_mode *get_spill_mode(const ir_node *node)
501 ir_mode *mode = get_irn_mode(node);
502 return get_spill_mode_mode(mode);
506 * Checks whether an addressmode reload for a node with mode mode is compatible
507 * with a spillslot of mode spill_mode
509 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
511 return !mode_is_float(mode) || mode == spillmode;
515 * Check if irn can load its operand at position i from memory (source addressmode).
516 * @param irn The irn to be checked
517 * @param i The operands position
518 * @return Non-Zero if operand can be loaded
520 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
522 ir_node *op = get_irn_n(irn, i);
523 const ir_mode *mode = get_irn_mode(op);
524 const ir_mode *spillmode = get_spill_mode(op);
526 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
527 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
528 !ia32_is_spillmode_compatible(mode, spillmode) ||
529 is_ia32_use_frame(irn)) /* must not already use frame */
532 switch (get_ia32_am_support(irn)) {
537 if (i != n_ia32_unary_op)
543 case n_ia32_binary_left: {
544 const arch_register_req_t *req;
545 if (!is_ia32_commutative(irn))
548 /* we can't swap left/right for limited registers
549 * (As this (currently) breaks constraint handling copies)
551 req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
552 if (req->type & arch_register_req_type_limited)
557 case n_ia32_binary_right:
566 panic("Unknown AM type");
569 /* HACK: must not already use "real" memory.
570 * This can happen for Call and Div */
571 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
577 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
581 ir_mode *dest_op_mode;
583 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
585 set_ia32_op_type(irn, ia32_AddrModeS);
587 load_mode = get_irn_mode(get_irn_n(irn, i));
588 dest_op_mode = get_ia32_ls_mode(irn);
589 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
590 set_ia32_ls_mode(irn, load_mode);
592 set_ia32_use_frame(irn);
593 set_ia32_need_stackent(irn);
595 if (i == n_ia32_binary_left &&
596 get_ia32_am_support(irn) == ia32_am_binary &&
597 /* immediates are only allowed on the right side */
598 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
599 ia32_swap_left_right(irn);
600 i = n_ia32_binary_right;
603 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
605 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
606 set_irn_n(irn, n_ia32_mem, spill);
607 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
608 set_ia32_is_reload(irn);
611 static const be_abi_callbacks_t ia32_abi_callbacks = {
612 ia32_abi_get_between_type,
615 /* register allocator interface */
616 static const arch_irn_ops_t ia32_irn_ops = {
617 ia32_get_frame_entity,
618 ia32_set_frame_offset,
621 ia32_get_op_estimated_cost,
622 ia32_possible_memory_operand,
623 ia32_perform_memory_operand,
626 static ir_entity *mcount = NULL;
627 static int gprof = 0;
629 static void ia32_before_abi(ir_graph *irg)
632 if (mcount == NULL) {
633 ir_type *tp = new_type_method(0, 0);
634 ident *id = new_id_from_str("mcount");
635 mcount = new_entity(get_glob_type(), id, tp);
636 /* FIXME: enter the right ld_ident here */
637 set_entity_ld_ident(mcount, get_entity_ident(mcount));
638 set_entity_visibility(mcount, ir_visibility_external);
640 instrument_initcall(irg, mcount);
645 * Transforms the standard firm graph into
648 static void ia32_prepare_graph(ir_graph *irg)
650 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
653 switch (be_transformer) {
654 case TRANSFORMER_DEFAULT:
655 /* transform remaining nodes into assembler instructions */
656 ia32_transform_graph(irg);
659 case TRANSFORMER_PBQP:
660 case TRANSFORMER_RAND:
661 /* transform nodes into assembler instructions by PBQP magic */
662 ia32_transform_graph_by_pbqp(irg);
666 panic("invalid transformer");
669 ia32_transform_graph(irg);
672 /* do local optimizations (mainly CSE) */
673 optimize_graph_df(irg);
674 /* backend code expects that outedges are always enabled */
678 dump_ir_graph(irg, "transformed");
680 /* optimize address mode */
681 ia32_optimize_graph(irg);
683 /* do code placement, to optimize the position of constants */
685 /* backend code expects that outedges are always enabled */
689 dump_ir_graph(irg, "place");
692 ir_node *ia32_turn_back_am(ir_node *node)
694 dbg_info *dbgi = get_irn_dbg_info(node);
695 ir_graph *irg = get_irn_irg(node);
696 ir_node *block = get_nodes_block(node);
697 ir_node *base = get_irn_n(node, n_ia32_base);
698 ir_node *idx = get_irn_n(node, n_ia32_index);
699 ir_node *mem = get_irn_n(node, n_ia32_mem);
702 ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
703 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
705 ia32_copy_am_attrs(load, node);
706 if (is_ia32_is_reload(node))
707 set_ia32_is_reload(load);
708 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
710 switch (get_ia32_am_support(node)) {
712 set_irn_n(node, n_ia32_unary_op, load_res);
716 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
717 set_irn_n(node, n_ia32_binary_left, load_res);
719 set_irn_n(node, n_ia32_binary_right, load_res);
724 panic("Unknown AM type");
726 noreg = ia32_new_NoReg_gp(current_ir_graph);
727 set_irn_n(node, n_ia32_base, noreg);
728 set_irn_n(node, n_ia32_index, noreg);
729 set_ia32_am_offs_int(node, 0);
730 set_ia32_am_sc(node, NULL);
731 set_ia32_am_scale(node, 0);
732 clear_ia32_am_sc_sign(node);
734 /* rewire mem-proj */
735 if (get_irn_mode(node) == mode_T) {
736 const ir_edge_t *edge;
737 foreach_out_edge(node, edge) {
738 ir_node *out = get_edge_src_irn(edge);
739 if (get_irn_mode(out) == mode_M) {
740 set_Proj_pred(out, load);
741 set_Proj_proj(out, pn_ia32_Load_M);
747 set_ia32_op_type(node, ia32_Normal);
748 if (sched_is_scheduled(node))
749 sched_add_before(node, load);
754 static ir_node *flags_remat(ir_node *node, ir_node *after)
756 /* we should turn back source address mode when rematerializing nodes */
761 if (is_Block(after)) {
764 block = get_nodes_block(after);
767 type = get_ia32_op_type(node);
770 ia32_turn_back_am(node);
774 /* TODO implement this later... */
775 panic("found DestAM with flag user %+F this should not happen", node);
777 default: assert(type == ia32_Normal); break;
780 copy = exact_copy(node);
781 set_nodes_block(copy, block);
782 sched_add_after(after, copy);
788 * Called before the register allocator.
790 static void ia32_before_ra(ir_graph *irg)
792 /* setup fpu rounding modes */
793 ia32_setup_fpu_mode(irg);
796 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
799 be_add_missing_keeps(irg);
804 * Transforms a be_Reload into a ia32 Load.
806 static void transform_to_Load(ir_node *node)
808 ir_graph *irg = get_irn_irg(node);
809 dbg_info *dbgi = get_irn_dbg_info(node);
810 ir_node *block = get_nodes_block(node);
811 ir_entity *ent = be_get_frame_entity(node);
812 ir_mode *mode = get_irn_mode(node);
813 ir_mode *spillmode = get_spill_mode(node);
814 ir_node *noreg = ia32_new_NoReg_gp(irg);
815 ir_node *sched_point = NULL;
816 ir_node *ptr = get_irg_frame(irg);
817 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
818 ir_node *new_op, *proj;
819 const arch_register_t *reg;
821 if (sched_is_scheduled(node)) {
822 sched_point = sched_prev(node);
825 if (mode_is_float(spillmode)) {
826 if (ia32_cg_config.use_sse2)
827 new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
829 new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
831 else if (get_mode_size_bits(spillmode) == 128) {
832 /* Reload 128 bit SSE registers */
833 new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
836 new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
838 set_ia32_op_type(new_op, ia32_AddrModeS);
839 set_ia32_ls_mode(new_op, spillmode);
840 set_ia32_frame_ent(new_op, ent);
841 set_ia32_use_frame(new_op);
842 set_ia32_is_reload(new_op);
844 DBG_OPT_RELOAD2LD(node, new_op);
846 proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
849 sched_add_after(sched_point, new_op);
853 /* copy the register from the old node to the new Load */
854 reg = arch_get_irn_register(node);
855 arch_set_irn_register(proj, reg);
857 SET_IA32_ORIG_NODE(new_op, node);
859 exchange(node, proj);
863 * Transforms a be_Spill node into a ia32 Store.
865 static void transform_to_Store(ir_node *node)
867 ir_graph *irg = get_irn_irg(node);
868 dbg_info *dbgi = get_irn_dbg_info(node);
869 ir_node *block = get_nodes_block(node);
870 ir_entity *ent = be_get_frame_entity(node);
871 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
872 ir_mode *mode = get_spill_mode(spillval);
873 ir_node *noreg = ia32_new_NoReg_gp(irg);
874 ir_node *nomem = get_irg_no_mem(irg);
875 ir_node *ptr = get_irg_frame(irg);
876 ir_node *val = get_irn_n(node, n_be_Spill_val);
879 ir_node *sched_point = NULL;
881 if (sched_is_scheduled(node)) {
882 sched_point = sched_prev(node);
885 if (mode_is_float(mode)) {
886 if (ia32_cg_config.use_sse2) {
887 store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
888 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
890 store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
891 res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
893 } else if (get_mode_size_bits(mode) == 128) {
894 /* Spill 128 bit SSE registers */
895 store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
896 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
897 } else if (get_mode_size_bits(mode) == 8) {
898 store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
899 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
901 store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
902 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
905 set_ia32_op_type(store, ia32_AddrModeD);
906 set_ia32_ls_mode(store, mode);
907 set_ia32_frame_ent(store, ent);
908 set_ia32_use_frame(store);
909 set_ia32_is_spill(store);
910 SET_IA32_ORIG_NODE(store, node);
911 DBG_OPT_SPILL2ST(node, store);
914 sched_add_after(sched_point, store);
921 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
923 dbg_info *dbgi = get_irn_dbg_info(node);
924 ir_node *block = get_nodes_block(node);
925 ir_graph *irg = get_irn_irg(node);
926 ir_node *noreg = ia32_new_NoReg_gp(irg);
927 ir_node *frame = get_irg_frame(irg);
929 ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
931 set_ia32_frame_ent(push, ent);
932 set_ia32_use_frame(push);
933 set_ia32_op_type(push, ia32_AddrModeS);
934 set_ia32_ls_mode(push, mode_Is);
935 set_ia32_is_spill(push);
937 sched_add_before(schedpoint, push);
941 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
943 dbg_info *dbgi = get_irn_dbg_info(node);
944 ir_node *block = get_nodes_block(node);
945 ir_graph *irg = get_irn_irg(node);
946 ir_node *noreg = ia32_new_NoReg_gp(irg);
947 ir_node *frame = get_irg_frame(irg);
949 ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
950 get_irg_no_mem(irg), sp);
952 set_ia32_frame_ent(pop, ent);
953 set_ia32_use_frame(pop);
954 set_ia32_op_type(pop, ia32_AddrModeD);
955 set_ia32_ls_mode(pop, mode_Is);
956 set_ia32_is_reload(pop);
958 sched_add_before(schedpoint, pop);
963 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
965 dbg_info *dbgi = get_irn_dbg_info(node);
966 ir_mode *spmode = mode_Iu;
967 const arch_register_t *spreg = &ia32_registers[REG_ESP];
970 sp = new_rd_Proj(dbgi, pred, spmode, pos);
971 arch_set_irn_register(sp, spreg);
977 * Transform MemPerm, currently we do this the ugly way and produce
978 * push/pop into/from memory cascades. This is possible without using
981 static void transform_MemPerm(ir_node *node)
983 ir_node *block = get_nodes_block(node);
984 ir_graph *irg = get_irn_irg(node);
985 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
986 int arity = be_get_MemPerm_entity_arity(node);
987 ir_node **pops = ALLOCAN(ir_node*, arity);
991 const ir_edge_t *edge;
992 const ir_edge_t *next;
995 for (i = 0; i < arity; ++i) {
996 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
997 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
998 ir_type *enttype = get_entity_type(inent);
999 unsigned entsize = get_type_size_bytes(enttype);
1000 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1001 ir_node *mem = get_irn_n(node, i + 1);
1004 /* work around cases where entities have different sizes */
1005 if (entsize2 < entsize)
1007 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1009 push = create_push(node, node, sp, mem, inent);
1010 sp = create_spproj(node, push, pn_ia32_Push_stack);
1012 /* add another push after the first one */
1013 push = create_push(node, node, sp, mem, inent);
1014 add_ia32_am_offs_int(push, 4);
1015 sp = create_spproj(node, push, pn_ia32_Push_stack);
1018 set_irn_n(node, i, new_r_Bad(irg, mode_X));
1022 for (i = arity - 1; i >= 0; --i) {
1023 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1024 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1025 ir_type *enttype = get_entity_type(outent);
1026 unsigned entsize = get_type_size_bytes(enttype);
1027 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1030 /* work around cases where entities have different sizes */
1031 if (entsize2 < entsize)
1033 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1035 pop = create_pop(node, node, sp, outent);
1036 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1038 add_ia32_am_offs_int(pop, 4);
1040 /* add another pop after the first one */
1041 pop = create_pop(node, node, sp, outent);
1042 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1049 keep = be_new_Keep(block, 1, in);
1050 sched_add_before(node, keep);
1052 /* exchange memprojs */
1053 foreach_out_edge_safe(node, edge, next) {
1054 ir_node *proj = get_edge_src_irn(edge);
1055 int p = get_Proj_proj(proj);
1059 set_Proj_pred(proj, pops[p]);
1060 set_Proj_proj(proj, pn_ia32_Pop_M);
1063 /* remove memperm */
1069 * Block-Walker: Calls the transform functions Spill and Reload.
1071 static void ia32_after_ra_walker(ir_node *block, void *env)
1073 ir_node *node, *prev;
1076 /* beware: the schedule is changed here */
1077 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1078 prev = sched_prev(node);
1080 if (be_is_Reload(node)) {
1081 transform_to_Load(node);
1082 } else if (be_is_Spill(node)) {
1083 transform_to_Store(node);
1084 } else if (be_is_MemPerm(node)) {
1085 transform_MemPerm(node);
1091 * Collects nodes that need frame entities assigned.
1093 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1095 be_fec_env_t *env = (be_fec_env_t*)data;
1096 const ir_mode *mode;
1099 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1100 mode = get_spill_mode_mode(get_irn_mode(node));
1101 align = get_mode_size_bytes(mode);
1102 } else if (is_ia32_irn(node) &&
1103 get_ia32_frame_ent(node) == NULL &&
1104 is_ia32_use_frame(node)) {
1105 if (is_ia32_need_stackent(node))
1108 switch (get_ia32_irn_opcode(node)) {
1110 case iro_ia32_Load: {
1111 const ia32_attr_t *attr = get_ia32_attr_const(node);
1113 if (attr->data.need_32bit_stackent) {
1115 } else if (attr->data.need_64bit_stackent) {
1118 mode = get_ia32_ls_mode(node);
1119 if (is_ia32_is_reload(node))
1120 mode = get_spill_mode_mode(mode);
1122 align = get_mode_size_bytes(mode);
1126 case iro_ia32_vfild:
1128 case iro_ia32_xLoad: {
1129 mode = get_ia32_ls_mode(node);
1134 case iro_ia32_FldCW: {
1135 /* although 2 byte would be enough 4 byte performs best */
1143 panic("unexpected frame user while collection frame entity nodes");
1145 case iro_ia32_FnstCW:
1146 case iro_ia32_Store8Bit:
1147 case iro_ia32_Store:
1150 case iro_ia32_vfist:
1151 case iro_ia32_vfisttp:
1153 case iro_ia32_xStore:
1154 case iro_ia32_xStoreSimple:
1161 be_node_needs_frame_entity(env, node, mode, align);
1164 static int determine_ebp_input(ir_node *ret)
1166 const arch_register_t *bp = &ia32_registers[REG_EBP];
1167 int arity = get_irn_arity(ret);
1170 for (i = 0; i < arity; ++i) {
1171 ir_node *input = get_irn_n(ret, i);
1172 if (arch_get_irn_register(input) == bp)
1175 panic("no ebp input found at %+F", ret);
1178 static void introduce_epilog(ir_node *ret)
1180 const arch_register_t *sp = &ia32_registers[REG_ESP];
1181 const arch_register_t *bp = &ia32_registers[REG_EBP];
1182 ir_graph *irg = get_irn_irg(ret);
1183 ir_type *frame_type = get_irg_frame_type(irg);
1184 unsigned frame_size = get_type_size_bytes(frame_type);
1185 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1186 ir_node *block = get_nodes_block(ret);
1187 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1188 ir_node *curr_sp = first_sp;
1189 ir_mode *mode_gp = mode_Iu;
1191 if (!layout->sp_relative) {
1192 int n_ebp = determine_ebp_input(ret);
1193 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1194 if (ia32_cg_config.use_leave) {
1195 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1196 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1197 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1198 arch_set_irn_register(curr_bp, bp);
1199 arch_set_irn_register(curr_sp, sp);
1200 sched_add_before(ret, leave);
1203 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1204 /* copy ebp to esp */
1205 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1206 arch_set_irn_register(curr_sp, sp);
1207 sched_add_before(ret, curr_sp);
1210 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1211 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1212 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1213 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1214 arch_set_irn_register(curr_bp, bp);
1215 arch_set_irn_register(curr_sp, sp);
1216 sched_add_before(ret, pop);
1218 set_irn_n(ret, n_be_Return_mem, curr_mem);
1220 set_irn_n(ret, n_ebp, curr_bp);
1222 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1223 sched_add_before(ret, incsp);
1226 set_irn_n(ret, n_be_Return_sp, curr_sp);
1228 /* keep verifier happy... */
1229 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1230 kill_node(first_sp);
1235 * put the Prolog code at the beginning, epilog code before each return
1237 static void introduce_prolog_epilog(ir_graph *irg)
1239 const arch_register_t *sp = &ia32_registers[REG_ESP];
1240 const arch_register_t *bp = &ia32_registers[REG_EBP];
1241 ir_node *start = get_irg_start(irg);
1242 ir_node *block = get_nodes_block(start);
1243 ir_type *frame_type = get_irg_frame_type(irg);
1244 unsigned frame_size = get_type_size_bytes(frame_type);
1245 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1246 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1247 ir_node *curr_sp = initial_sp;
1248 ir_mode *mode_gp = mode_Iu;
1250 if (!layout->sp_relative) {
1252 ir_node *mem = get_irg_initial_mem(irg);
1253 ir_node *noreg = ia32_new_NoReg_gp(irg);
1254 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1255 ir_node *curr_bp = initial_bp;
1256 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
1259 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1260 mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
1261 arch_set_irn_register(curr_sp, sp);
1262 sched_add_after(start, push);
1264 /* move esp to ebp */
1265 curr_bp = be_new_Copy(block, curr_sp);
1266 sched_add_after(push, curr_bp);
1267 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1268 curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
1269 sched_add_after(curr_bp, curr_sp);
1270 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1271 edges_reroute(initial_bp, curr_bp);
1272 set_irn_n(push, n_ia32_Push_val, initial_bp);
1274 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1275 edges_reroute(initial_sp, incsp);
1276 set_irn_n(push, n_ia32_Push_stack, initial_sp);
1277 sched_add_after(curr_sp, incsp);
1279 /* make sure the initial IncSP is really used by someone */
1280 if (get_irn_n_edges(incsp) <= 1) {
1281 ir_node *in[] = { incsp };
1282 ir_node *keep = be_new_Keep(block, 1, in);
1283 sched_add_after(incsp, keep);
1286 layout->initial_bias = -4;
1288 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1289 edges_reroute(initial_sp, incsp);
1290 be_set_IncSP_pred(incsp, curr_sp);
1291 sched_add_after(start, incsp);
1294 /* introduce epilog for every return node */
1296 ir_node *end_block = get_irg_end_block(irg);
1297 int arity = get_irn_arity(end_block);
1300 for (i = 0; i < arity; ++i) {
1301 ir_node *ret = get_irn_n(end_block, i);
1302 assert(be_is_Return(ret));
1303 introduce_epilog(ret);
1309 * Last touchups for the graph before emit: x87 simulation to replace the
1310 * virtual with real x87 instructions, creating a block schedule and peephole
1313 static void ia32_finish_graph(ir_graph *irg)
1315 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1316 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1317 bool at_begin = stack_layout->sp_relative ? true : false;
1318 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1320 /* create and coalesce frame entities */
1321 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1322 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1323 be_free_frame_entity_coalescer(fec_env);
1325 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1327 introduce_prolog_epilog(irg);
1329 /* fix stack entity offsets */
1330 be_abi_fix_stack_nodes(irg);
1331 be_abi_fix_stack_bias(irg);
1333 /* fix 2-address code constraints */
1334 ia32_finish_irg(irg);
1336 /* we might have to rewrite x87 virtual registers */
1337 if (irg_data->do_x87_sim) {
1338 ia32_x87_simulate_graph(irg);
1341 /* do peephole optimisations */
1342 ia32_peephole_optimization(irg);
1344 be_remove_dead_nodes_from_schedule(irg);
1346 /* create block schedule, this also removes empty blocks which might
1347 * produce critical edges */
1348 irg_data->blk_sched = be_create_block_schedule(irg);
1352 * Emits the code, closes the output file and frees
1353 * the code generator interface.
1355 static void ia32_emit(ir_graph *irg)
1357 if (ia32_cg_config.emit_machcode) {
1358 ia32_gen_binary_routine(irg);
1360 ia32_gen_routine(irg);
1365 * Returns the node representing the PIC base.
1367 static ir_node *ia32_get_pic_base(ir_graph *irg)
1369 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1371 ir_node *get_eip = irg_data->get_eip;
1372 if (get_eip != NULL)
1375 block = get_irg_start_block(irg);
1376 get_eip = new_bd_ia32_GetEIP(NULL, block);
1377 irg_data->get_eip = get_eip;
1383 * Initializes a IA32 code generator.
1385 static void ia32_init_graph(ir_graph *irg)
1387 struct obstack *obst = be_get_be_obst(irg);
1388 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1390 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1393 /* Linux gprof implementation needs base pointer */
1394 be_get_irg_options(irg)->omit_fp = 0;
1397 be_birg_from_irg(irg)->isa_link = irg_data;
1400 static const tarval_mode_info mo_integer = {
1407 * set the tarval output mode of all integer modes to decimal
1409 static void set_tarval_output_modes(void)
1413 for (i = ir_get_n_modes(); i > 0;) {
1414 ir_mode *mode = ir_get_mode(--i);
1416 if (mode_is_int(mode))
1417 set_tarval_mode_output_option(mode, &mo_integer);
1421 extern const arch_isa_if_t ia32_isa_if;
1423 static void init_asm_constraints(void)
1425 be_init_default_asm_constraint_flags();
1427 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1428 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1429 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1430 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1431 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1432 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1433 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1434 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1435 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1436 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1437 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1438 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1439 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1440 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1441 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1442 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1443 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1444 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1445 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1446 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1448 /* no support for autodecrement/autoincrement */
1449 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1450 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1451 /* no float consts */
1452 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1453 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1454 /* makes no sense on x86 */
1455 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1456 /* no support for sse consts yet */
1457 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1458 /* no support for x87 consts yet */
1459 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1460 /* no support for mmx registers yet */
1461 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1462 /* not available in 32bit mode */
1463 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1464 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1466 /* no code yet to determine register class needed... */
1467 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1471 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1473 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1478 ir_relation relation;
1483 cmp_l = get_Cmp_left(sel);
1484 cmp_r = get_Cmp_right(sel);
1485 if (!mode_is_float(get_irn_mode(cmp_l)))
1488 /* check for min/max. They're defined as (C-Semantik):
1489 * min(a, b) = a < b ? a : b
1490 * or min(a, b) = a <= b ? a : b
1491 * max(a, b) = a > b ? a : b
1492 * or max(a, b) = a >= b ? a : b
1493 * (Note we only handle float min/max here)
1495 relation = get_Cmp_relation(sel);
1497 case ir_relation_greater_equal:
1498 case ir_relation_greater:
1500 if (cmp_l == mux_true && cmp_r == mux_false)
1503 case ir_relation_less_equal:
1504 case ir_relation_less:
1506 if (cmp_l == mux_true && cmp_r == mux_false)
1509 case ir_relation_unordered_greater_equal:
1510 case ir_relation_unordered_greater:
1512 if (cmp_l == mux_false && cmp_r == mux_true)
1515 case ir_relation_unordered_less_equal:
1516 case ir_relation_unordered_less:
1518 if (cmp_l == mux_false && cmp_r == mux_true)
1529 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1531 ir_mode *mode = get_irn_mode(mux_true);
1534 if (!mode_is_int(mode) && !mode_is_reference(mode)
1538 if (is_Const(mux_true) && is_Const(mux_false)) {
1539 /* we can create a set plus up two 3 instructions for any combination
1547 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1552 if (!mode_is_float(get_irn_mode(mux_true)))
1555 return is_Const(mux_true) && is_Const(mux_false);
1558 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1565 ir_relation relation;
1570 mode = get_irn_mode(mux_true);
1571 if (mode_is_signed(mode) || mode_is_float(mode))
1574 relation = get_Cmp_relation(sel);
1575 cmp_left = get_Cmp_left(sel);
1576 cmp_right = get_Cmp_right(sel);
1578 /* "move" zero constant to false input */
1579 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1580 ir_node *tmp = mux_false;
1581 mux_false = mux_true;
1583 relation = get_negated_relation(relation);
1585 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1587 if (!is_Sub(mux_true))
1589 sub_left = get_Sub_left(mux_true);
1590 sub_right = get_Sub_right(mux_true);
1592 /* Mux(a >=u b, 0, a-b) */
1593 if ((relation & ir_relation_greater)
1594 && sub_left == cmp_left && sub_right == cmp_right)
1596 /* Mux(a <=u b, 0, b-a) */
1597 if ((relation & ir_relation_less)
1598 && sub_left == cmp_right && sub_right == cmp_left)
1604 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1609 /* middleend can handle some things */
1610 if (ir_is_optimizable_mux(sel, mux_false, mux_true))
1612 /* we can handle Set for all modes and compares */
1613 if (mux_is_set(sel, mux_true, mux_false))
1615 /* SSE has own min/max operations */
1616 if (ia32_cg_config.use_sse2
1617 && mux_is_float_min_max(sel, mux_true, mux_false))
1619 /* we can handle Mux(?, Const[f], Const[f]) */
1620 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1621 #ifdef FIRM_GRGEN_BE
1622 /* well, some code selectors can't handle it */
1623 if (be_transformer != TRANSFORMER_PBQP
1624 || be_transformer != TRANSFORMER_RAND)
1631 /* no support for 64bit inputs to cmov */
1632 mode = get_irn_mode(mux_true);
1633 if (get_mode_size_bits(mode) > 32)
1635 /* we can handle Abs for all modes and compares (except 64bit) */
1636 if (ir_mux_is_abs(sel, mux_false, mux_true) != 0)
1638 /* we can't handle MuxF yet */
1639 if (mode_is_float(mode))
1642 if (mux_is_doz(sel, mux_true, mux_false))
1645 /* Check Cmp before the node */
1647 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1649 /* we can't handle 64bit compares */
1650 if (get_mode_size_bits(cmp_mode) > 32)
1653 /* we can't handle float compares */
1654 if (mode_is_float(cmp_mode))
1658 /* did we disable cmov generation? */
1659 if (!ia32_cg_config.use_cmov)
1662 /* we can use a cmov */
1667 * Create the trampoline code.
1669 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
1671 ir_graph *const irg = get_irn_irg(block);
1672 ir_node * p = trampoline;
1673 ir_mode *const mode = get_irn_mode(p);
1674 ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
1675 ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
1679 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
1680 mem = new_r_Proj(st, mode_M, pn_Store_M);
1681 p = new_r_Add(block, p, one, mode);
1682 st = new_r_Store(block, mem, p, env, cons_none);
1683 mem = new_r_Proj(st, mode_M, pn_Store_M);
1684 p = new_r_Add(block, p, four, mode);
1686 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
1687 mem = new_r_Proj(st, mode_M, pn_Store_M);
1688 p = new_r_Add(block, p, one, mode);
1689 st = new_r_Store(block, mem, p, callee, cons_none);
1690 mem = new_r_Proj(st, mode_M, pn_Store_M);
1691 p = new_r_Add(block, p, four, mode);
1696 static const ir_settings_arch_dep_t ia32_arch_dep = {
1697 1, /* also use subs */
1698 4, /* maximum shifts */
1699 63, /* maximum shift amount */
1700 ia32_evaluate_insn, /* evaluate the instruction sequence */
1702 1, /* allow Mulhs */
1703 1, /* allow Mulus */
1704 32, /* Mulh allowed up to 32 bit */
1706 static backend_params ia32_backend_params = {
1707 1, /* support inline assembly */
1708 1, /* support Rotl nodes */
1709 0, /* little endian */
1710 1, /* modulo shift efficient */
1711 0, /* non-modulo shift not efficient */
1712 &ia32_arch_dep, /* will be set later */
1713 ia32_is_mux_allowed,
1714 32, /* machine_size */
1715 NULL, /* float arithmetic mode, will be set below */
1716 NULL, /* long long type */
1717 NULL, /* unsigned long long type */
1718 NULL, /* long double type */
1719 12, /* size of trampoline code */
1720 4, /* alignment of trampoline code */
1721 ia32_create_trampoline_fkt,
1722 4 /* alignment of stack parameter */
1726 * Initializes the backend ISA.
1728 static void ia32_init(void)
1730 ir_mode *mode_long_long;
1731 ir_mode *mode_unsigned_long_long;
1732 ir_type *type_long_long;
1733 ir_type *type_unsigned_long_long;
1735 ia32_setup_cg_config();
1737 init_asm_constraints();
1739 ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0);
1741 /* note mantissa is 64bit but with explicitely encoded 1 so the really
1742 * usable part as counted by firm is only 63 bits */
1743 ia32_mode_E = new_float_mode("E", irma_x86_extended_float, 15, 63);
1744 ia32_type_E = new_type_primitive(ia32_mode_E);
1745 set_type_size_bytes(ia32_type_E, 12);
1746 set_type_alignment_bytes(ia32_type_E, 16);
1748 mode_long_long = new_int_mode("long long", irma_twos_complement, 64, 1, 64);
1749 type_long_long = new_type_primitive(mode_long_long);
1750 mode_unsigned_long_long
1751 = new_int_mode("unsigned long long", irma_twos_complement, 64, 0, 64);
1752 type_unsigned_long_long = new_type_primitive(mode_unsigned_long_long);
1754 ia32_backend_params.type_long_long = type_long_long;
1755 ia32_backend_params.type_unsigned_long_long = type_unsigned_long_long;
1757 if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
1758 ia32_backend_params.mode_float_arithmetic = NULL;
1759 ia32_backend_params.type_long_double = NULL;
1761 ia32_backend_params.mode_float_arithmetic = ia32_mode_E;
1762 ia32_backend_params.type_long_double = ia32_type_E;
1765 ia32_register_init();
1766 obstack_init(&opcodes_obst);
1767 ia32_create_opcodes(&ia32_irn_ops);
1770 static void ia32_finish(void)
1772 if (between_type != NULL) {
1773 free_type(between_type);
1774 between_type = NULL;
1776 ia32_free_opcodes();
1777 obstack_free(&opcodes_obst, NULL);
1781 * The template that generates a new ISA object.
1782 * Note that this template can be changed by command line
1785 static ia32_isa_t ia32_isa_template = {
1787 &ia32_isa_if, /* isa interface implementation */
1792 &ia32_registers[REG_ESP], /* stack pointer register */
1793 &ia32_registers[REG_EBP], /* base pointer register */
1794 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1795 2, /* power of two stack alignment, 2^2 == 4 */
1796 NULL, /* main environment */
1797 7, /* costs for a spill instruction */
1798 5, /* costs for a reload instruction */
1799 false, /* no custom abi handling */
1802 IA32_FPU_ARCH_X87, /* FPU architecture */
1805 static arch_env_t *ia32_begin_codegeneration(const be_main_env_t *env)
1807 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1809 set_tarval_output_modes();
1811 *isa = ia32_isa_template;
1812 isa->tv_ent = pmap_create();
1814 /* enter the ISA object into the intrinsic environment */
1815 intrinsic_env.isa = isa;
1817 be_emit_init(env->file_handle);
1818 be_gas_begin_compilation_unit(env);
1824 * Closes the output file and frees the ISA structure.
1826 static void ia32_end_codegeneration(void *self)
1828 ia32_isa_t *isa = (ia32_isa_t*)self;
1830 /* emit now all global declarations */
1831 be_gas_end_compilation_unit(isa->base.main_env);
1835 pmap_destroy(isa->tv_ent);
1840 * Returns the register for parameter nr.
1842 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1843 const ir_mode *mode)
1845 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1846 &ia32_registers[REG_ECX],
1847 &ia32_registers[REG_EDX],
1850 static const unsigned MAXNUM_GPREG_ARGS = 3;
1852 static const arch_register_t *gpreg_param_reg_regparam[] = {
1853 &ia32_registers[REG_EAX],
1854 &ia32_registers[REG_EDX],
1855 &ia32_registers[REG_ECX]
1858 static const arch_register_t *gpreg_param_reg_this[] = {
1859 &ia32_registers[REG_ECX],
1864 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1865 &ia32_registers[REG_XMM0],
1866 &ia32_registers[REG_XMM1],
1867 &ia32_registers[REG_XMM2],
1868 &ia32_registers[REG_XMM3],
1869 &ia32_registers[REG_XMM4],
1870 &ia32_registers[REG_XMM5],
1871 &ia32_registers[REG_XMM6],
1872 &ia32_registers[REG_XMM7]
1875 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1876 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1878 static const unsigned MAXNUM_SSE_ARGS = 8;
1880 if ((cc & cc_this_call) && nr == 0)
1881 return gpreg_param_reg_this[0];
1883 if (! (cc & cc_reg_param))
1886 if (mode_is_float(mode)) {
1887 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1889 if (nr >= MAXNUM_SSE_ARGS)
1892 if (cc & cc_this_call) {
1893 return fpreg_sse_param_reg_this[nr];
1895 return fpreg_sse_param_reg_std[nr];
1896 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1897 unsigned num_regparam;
1899 if (get_mode_size_bits(mode) > 32)
1902 if (nr >= MAXNUM_GPREG_ARGS)
1905 if (cc & cc_this_call) {
1906 return gpreg_param_reg_this[nr];
1908 num_regparam = cc & ~cc_bits;
1909 if (num_regparam == 0) {
1910 /* default fastcall */
1911 return gpreg_param_reg_fastcall[nr];
1913 if (nr < num_regparam)
1914 return gpreg_param_reg_regparam[nr];
1918 panic("unknown argument mode");
1922 * Get the ABI restrictions for procedure calls.
1924 static void ia32_get_call_abi(ir_type *method_type, be_abi_call_t *abi)
1929 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1931 /* set abi flags for calls */
1932 call_flags.bits.store_args_sequential = 0;
1933 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1934 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1935 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1937 /* set parameter passing style */
1938 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1940 cc = get_method_calling_convention(method_type);
1941 if (get_method_variadicity(method_type) == variadicity_variadic) {
1942 /* pass all parameters of a variadic function on the stack */
1943 cc = cc_cdecl_set | (cc & cc_this_call);
1945 if (get_method_additional_properties(method_type) & mtp_property_private &&
1946 ia32_cg_config.optimize_cc) {
1947 /* set the fast calling conventions (allowing up to 3) */
1948 cc = SET_FASTCALL(cc) | 3;
1952 /* we have to pop the shadow parameter ourself for compound calls */
1953 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1954 && !(cc & cc_reg_param)) {
1955 pop_amount += get_mode_size_bytes(mode_P_data);
1958 n = get_method_n_params(method_type);
1959 for (i = regnum = 0; i < n; i++) {
1960 const arch_register_t *reg = NULL;
1961 ir_type *tp = get_method_param_type(method_type, i);
1962 ir_mode *mode = get_type_mode(tp);
1965 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1968 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1971 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1972 * movl has a shorter opcode than mov[sz][bw]l */
1973 ir_mode *load_mode = mode;
1976 unsigned size = get_mode_size_bytes(mode);
1978 if (cc & cc_callee_clear_stk) {
1979 pop_amount += (size + 3U) & ~3U;
1982 if (size < 4) load_mode = mode_Iu;
1985 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1989 be_abi_call_set_pop(abi, pop_amount);
1991 /* set return registers */
1992 n = get_method_n_ress(method_type);
1994 assert(n <= 2 && "more than two results not supported");
1996 /* In case of 64bit returns, we will have two 32bit values */
1998 ir_type *tp = get_method_res_type(method_type, 0);
1999 ir_mode *mode = get_type_mode(tp);
2001 assert(!mode_is_float(mode) && "two FP results not supported");
2003 tp = get_method_res_type(method_type, 1);
2004 mode = get_type_mode(tp);
2006 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
2008 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
2009 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
2012 ir_type *tp = get_method_res_type(method_type, 0);
2013 ir_mode *mode = get_type_mode(tp);
2014 const arch_register_t *reg;
2015 assert(is_atomic_type(tp));
2017 reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
2019 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
2023 static void ia32_mark_remat(ir_node *node)
2025 if (is_ia32_irn(node)) {
2026 set_ia32_is_remat(node);
2030 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2034 /* we already added all our simple flags to the flags modifier list in
2035 * init, so this flag we don't know. */
2036 return ASM_CONSTRAINT_FLAG_INVALID;
2039 static int ia32_is_valid_clobber(const char *clobber)
2041 return ia32_get_clobber_register(clobber) != NULL;
2044 static void ia32_lower_for_target(void)
2046 size_t i, n_irgs = get_irp_n_irgs();
2048 /* perform doubleword lowering */
2049 lwrdw_param_t lower_dw_params = {
2050 1, /* little endian */
2051 64, /* doubleword size */
2052 ia32_create_intrinsic_fkt,
2056 /* lower compound param handling
2057 * Note: we lower compound arguments ourself, since on ia32 we don't
2058 * have hidden parameters but know where to find the structs on the stack.
2059 * (This also forces us to always allocate space for the compound arguments
2060 * on the callframe and we can't just use an arbitrary position on the
2063 lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS);
2065 /* replace floating point operations by function calls */
2066 if (ia32_cg_config.use_softfloat) {
2067 lower_floating_point();
2070 ir_prepare_dw_lowering(&lower_dw_params);
2073 for (i = 0; i < n_irgs; ++i) {
2074 ir_graph *irg = get_irp_irg(i);
2075 /* lower for mode_b stuff */
2076 ir_lower_mode_b(irg, mode_Iu);
2077 /* break up switches with wide ranges */
2078 lower_switch(irg, 4, 256, false);
2081 for (i = 0; i < n_irgs; ++i) {
2082 ir_graph *irg = get_irp_irg(i);
2083 /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
2084 * so we can generate rep movs later, and turn all big CopyBs into
2086 lower_CopyB(irg, 64, 8193, true);
2091 * Returns the libFirm configuration parameter for this backend.
2093 static const backend_params *ia32_get_libfirm_params(void)
2095 return &ia32_backend_params;
2099 * Check if the given register is callee or caller save.
2101 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
2104 /* check for callee saved */
2105 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2106 switch (reg->index) {
2117 /* check for caller saved */
2118 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2119 switch (reg->index) {
2127 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
2128 /* all XMM registers are caller save */
2129 return reg->index != REG_XMM_NOREG;
2130 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
2131 /* all VFP registers are caller save */
2132 return reg->index != REG_VFP_NOREG;
2138 static const lc_opt_enum_int_items_t gas_items[] = {
2139 { "elf", OBJECT_FILE_FORMAT_ELF },
2140 { "mingw", OBJECT_FILE_FORMAT_COFF },
2141 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2145 static lc_opt_enum_int_var_t gas_var = {
2146 (int*) &be_gas_object_file_format, gas_items
2149 #ifdef FIRM_GRGEN_BE
2150 static const lc_opt_enum_int_items_t transformer_items[] = {
2151 { "default", TRANSFORMER_DEFAULT },
2152 { "pbqp", TRANSFORMER_PBQP },
2153 { "random", TRANSFORMER_RAND },
2157 static lc_opt_enum_int_var_t transformer_var = {
2158 (int*)&be_transformer, transformer_items
2162 static const lc_opt_table_entry_t ia32_options[] = {
2163 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2164 #ifdef FIRM_GRGEN_BE
2165 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2167 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2168 &ia32_isa_template.base.stack_alignment),
2169 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2173 const arch_isa_if_t ia32_isa_if = {
2176 ia32_get_libfirm_params,
2177 ia32_lower_for_target,
2178 ia32_parse_asm_constraint,
2179 ia32_is_valid_clobber,
2181 ia32_begin_codegeneration,
2182 ia32_end_codegeneration,
2186 ia32_get_pic_base, /* return node used as base in pic code addresses */
2189 ia32_register_saved_by,
2191 ia32_handle_intrinsics,
2192 ia32_before_abi, /* before abi introduce hook */
2194 ia32_before_ra, /* before register allocation hook */
2195 ia32_finish_graph, /* called before codegen */
2196 ia32_emit, /* emit && done */
2199 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2200 void be_init_arch_ia32(void)
2202 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2203 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2205 lc_opt_add_table(ia32_grp, ia32_options);
2206 be_register_isa_if("ia32", &ia32_isa_if);
2208 ia32_init_emitter();
2210 ia32_init_optimize();
2211 ia32_init_transform();
2213 ia32_init_architecture();