2 * This is the main ia32 firm backend driver.
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
24 #include "pseudo_irg.h"
28 #include "iredges_t.h"
36 #include "../beabi.h" /* the general register allocator interface */
37 #include "../benode_t.h"
38 #include "../belower.h"
39 #include "../besched_t.h"
41 #include "bearch_ia32_t.h"
43 #include "ia32_new_nodes.h" /* ia32 nodes interface */
44 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
45 #include "ia32_gen_decls.h" /* interface declaration emitter */
46 #include "ia32_transform.h"
47 #include "ia32_emitter.h"
48 #include "ia32_map_regs.h"
49 #include "ia32_optimize.h"
52 #define DEBUG_MODULE "firm.be.ia32.isa"
55 static set *cur_reg_set = NULL;
58 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
60 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
61 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
64 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
65 return be_abi_get_callee_save_irn(cg->birg->abi,
66 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
69 /**************************************************
72 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
73 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
74 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
75 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
78 **************************************************/
80 static ir_node *my_skip_proj(const ir_node *n) {
88 * Return register requirements for an ia32 node.
89 * If the node returns a tuple (mode_T) then the proj's
90 * will be asked for this information.
92 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
93 const ia32_irn_ops_t *ops = self;
94 const ia32_register_req_t *irn_req;
95 long node_pos = pos == -1 ? 0 : pos;
96 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
97 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
99 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
100 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
104 if (mode == mode_T && pos < 0) {
105 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
109 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
113 node_pos = ia32_translate_proj_pos(irn);
119 irn = my_skip_proj(irn);
121 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
124 if (is_ia32_irn(irn)) {
126 irn_req = get_ia32_in_req(irn, pos);
129 irn_req = get_ia32_out_req(irn, node_pos);
132 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
134 memcpy(req, &(irn_req->req), sizeof(*req));
136 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
137 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
138 req->other_same = get_irn_n(irn, irn_req->same_pos);
141 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
142 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
143 req->other_different = get_irn_n(irn, irn_req->different_pos);
147 /* treat Phi like Const with default requirements */
149 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
150 if (mode_is_float(mode)) {
151 if (USE_SSE2(ops->cg))
152 memcpy(req, &(ia32_default_req_ia32_xmm.req), sizeof(*req));
154 memcpy(req, &(ia32_default_req_ia32_vfp.req), sizeof(*req));
156 else if (mode_is_int(mode) || mode_is_reference(mode))
157 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
158 else if (mode == mode_T || mode == mode_M) {
159 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
163 assert(0 && "unsupported Phi-Mode");
166 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
174 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
176 const ia32_irn_ops_t *ops = self;
178 if (get_irn_mode(irn) == mode_X) {
182 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
185 pos = ia32_translate_proj_pos(irn);
186 irn = my_skip_proj(irn);
189 if (is_ia32_irn(irn)) {
190 const arch_register_t **slots;
192 slots = get_ia32_slots(irn);
196 ia32_set_firm_reg(irn, reg, cur_reg_set);
200 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
202 const arch_register_t *reg = NULL;
206 if (get_irn_mode(irn) == mode_X) {
210 pos = ia32_translate_proj_pos(irn);
211 irn = my_skip_proj(irn);
214 if (is_ia32_irn(irn)) {
215 const arch_register_t **slots;
216 slots = get_ia32_slots(irn);
220 reg = ia32_get_firm_reg(irn, cur_reg_set);
226 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
227 irn = my_skip_proj(irn);
229 return arch_irn_class_branch;
230 else if (is_ia32_irn(irn))
231 return arch_irn_class_normal;
236 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
237 irn = my_skip_proj(irn);
238 if (is_ia32_irn(irn))
239 return get_ia32_flags(irn);
245 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
246 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
249 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
251 const ia32_irn_ops_t *ops = self;
253 if (get_ia32_frame_ent(irn)) {
254 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
256 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
257 snprintf(buf, sizeof(buf), "%d", bias);
259 if (get_ia32_op_type(irn) == ia32_Normal) {
260 set_ia32_cnst(irn, buf);
263 add_ia32_am_offs(irn, buf);
265 set_ia32_am_flavour(irn, am_flav);
271 be_abi_call_flags_bits_t flags;
272 const arch_isa_t *isa;
276 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
278 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
279 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
280 env->flags = fl.bits;
282 env->isa = aenv->isa;
286 static void ia32_abi_dont_save_regs(void *self, pset *s)
288 ia32_abi_env_t *env = self;
289 if(env->flags.try_omit_fp)
290 pset_insert_ptr(s, env->isa->bp);
293 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
295 ia32_abi_env_t *env = self;
296 const arch_register_t *frame_reg = env->isa->sp;
298 if(!env->flags.try_omit_fp) {
299 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
300 ir_node *bl = get_irg_start_block(env->irg);
301 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
302 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
303 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
306 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_expand);
307 store_bp = new_rd_ia32_Store(NULL, env->irg, bl, curr_sp, curr_no_reg, curr_bp, *mem, mode_T);
308 set_ia32_am_support(store_bp, ia32_am_Dest);
309 set_ia32_am_flavour(store_bp, ia32_B);
310 set_ia32_op_type(store_bp, ia32_AddrModeD);
311 *mem = new_r_Proj(env->irg, bl, store_bp, mode_M, 0);
312 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
313 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
314 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
316 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
317 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
323 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
325 ia32_abi_env_t *env = self;
326 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
327 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
328 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
330 if(env->flags.try_omit_fp) {
331 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
336 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
338 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
339 load_bp = new_rd_ia32_Load(NULL, env->irg, bl, curr_sp, curr_no_reg, *mem, mode_T);
340 set_ia32_am_support(load_bp, ia32_am_Source);
341 set_ia32_am_flavour(load_bp, ia32_B);
342 set_ia32_op_type(load_bp, ia32_AddrModeS);
343 set_ia32_ls_mode(load_bp, mode_bp);
344 curr_bp = new_r_Proj(env->irg, bl, load_bp, mode_bp, 0);
345 *mem = new_r_Proj(env->irg, bl, load_bp, mode_M, 1);
348 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
349 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
353 * Produces the type which sits between the stack args and the locals on the stack.
354 * it will contain the return address and space to store the old base pointer.
355 * @return The Firm type modeling the ABI between type.
357 static ir_type *ia32_abi_get_between_type(void *self)
359 static ir_type *omit_fp_between_type = NULL;
360 static ir_type *between_type = NULL;
362 ia32_abi_env_t *env = self;
366 entity *ret_addr_ent;
367 entity *omit_fp_ret_addr_ent;
369 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
370 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
372 between_type = new_type_class(new_id_from_str("ia32_between_type"));
373 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
374 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
376 set_entity_offset_bytes(old_bp_ent, 0);
377 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
378 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
380 omit_fp_between_type = new_type_class(new_id_from_str("ia32_between_type_omit_fp"));
381 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, new_id_from_str("ret_addr"), ret_addr_type);
383 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
384 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
387 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
390 static const be_abi_callbacks_t ia32_abi_callbacks = {
393 ia32_abi_get_between_type,
394 ia32_abi_dont_save_regs,
399 /* fill register allocator interface */
401 static const arch_irn_ops_if_t ia32_irn_ops_if = {
402 ia32_get_irn_reg_req,
407 ia32_get_frame_entity,
411 ia32_irn_ops_t ia32_irn_ops = {
418 /**************************************************
421 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
422 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
423 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
424 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
427 **************************************************/
430 * Transforms the standard firm graph into
433 static void ia32_prepare_graph(void *self) {
434 ia32_code_gen_t *cg = self;
435 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
437 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
438 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
439 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
441 DEBUG_ONLY(cg->mod = old_mod;)
444 edges_deactivate(cg->irg);
445 //dead_node_elimination(cg->irg);
446 edges_activate(cg->irg);
448 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
449 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
455 * Insert copies for all ia32 nodes where the should_be_same requirement
457 * Transform Sub into Neg -- Add if IN2 == OUT
459 static void ia32_finish_irg_walker(ir_node *irn, void *env) {
460 ia32_code_gen_t *cg = env;
461 const ia32_register_req_t **reqs;
462 const arch_register_t *out_reg, *in_reg, *in2_reg;
464 ir_node *copy, *in_node, *block, *in2_node;
465 ia32_op_type_t op_tp;
467 if (is_ia32_irn(irn)) {
468 /* AM Dest nodes don't produce any values */
469 op_tp = get_ia32_op_type(irn);
470 if (op_tp == ia32_AddrModeD)
473 reqs = get_ia32_out_req_all(irn);
474 n_res = get_ia32_n_res(irn);
475 block = get_nodes_block(irn);
477 /* check all OUT requirements, if there is a should_be_same */
478 if (op_tp == ia32_Normal) {
479 for (i = 0; i < n_res; i++) {
480 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
481 /* get in and out register */
482 out_reg = get_ia32_out_reg(irn, i);
483 in_node = get_irn_n(irn, reqs[i]->same_pos);
484 in_reg = arch_get_irn_register(cg->arch_env, in_node);
485 in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
486 in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
488 /* don't copy ignore nodes */
489 if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
492 /* check if in and out register are equal */
493 if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
494 /* in case of a commutative op: just exchange the in's */
495 if (is_ia32_commutative(irn) && REGS_ARE_EQUAL(out_reg, in2_reg)) {
496 set_irn_n(irn, reqs[i]->same_pos, in2_node);
497 set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
500 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
501 /* create copy from in register */
502 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
504 /* destination is the out register */
505 arch_set_irn_register(cg->arch_env, copy, out_reg);
507 /* insert copy before the node into the schedule */
508 sched_add_before(irn, copy);
511 set_irn_n(irn, reqs[i]->same_pos, copy);
518 /* If we have a CondJmp with immediate, we need to */
519 /* check if it's the right operand, otherwise we have */
520 /* to change it, as CMP doesn't support immediate as */
522 if (is_ia32_CondJmp(irn) && (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) && op_tp == ia32_AddrModeS) {
523 long pnc = get_negated_pnc(get_ia32_pncode(irn), get_ia32_res_mode(irn));
524 set_ia32_op_type(irn, ia32_AddrModeD);
525 set_ia32_pncode(irn, pnc);
528 /* check if there is a sub which need to be transformed */
529 ia32_transform_sub_to_neg_add(irn, cg);
531 /* transform a LEA into an Add if possible */
532 ia32_transform_lea_to_add(irn, cg);
535 /* check for peephole optimization */
536 ia32_peephole_optimization(irn, cg);
540 * Add Copy nodes for not fulfilled should_be_equal constraints
542 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
543 irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
549 * Dummy functions for hooks we don't need but which must be filled.
551 static void ia32_before_sched(void *self) {
555 * Called before the register allocator.
556 * Calculate a block schedule here. We need it for the x87
557 * simulator and the emitter.
559 static void ia32_before_ra(void *self) {
560 ia32_code_gen_t *cg = self;
562 cg->blk_sched = sched_create_block_schedule(cg->irg);
567 * Transforms a be node into a Load.
569 static void transform_to_Load(ia32_transform_env_t *env) {
570 ir_node *irn = env->irn;
571 entity *ent = be_get_frame_entity(irn);
572 ir_mode *mode = env->mode;
573 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
574 ir_node *nomem = new_rd_NoMem(env->irg);
575 ir_node *sched_point = NULL;
576 ir_node *ptr = get_irn_n(irn, 0);
577 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
578 ir_node *new_op, *proj;
579 const arch_register_t *reg;
581 if (sched_is_scheduled(irn)) {
582 sched_point = sched_prev(irn);
585 if (mode_is_float(mode)) {
586 if (USE_SSE2(env->cg))
587 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
589 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
592 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
595 set_ia32_am_support(new_op, ia32_am_Source);
596 set_ia32_op_type(new_op, ia32_AddrModeS);
597 set_ia32_am_flavour(new_op, ia32_B);
598 set_ia32_ls_mode(new_op, mode);
599 set_ia32_frame_ent(new_op, ent);
600 set_ia32_use_frame(new_op);
602 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
605 sched_add_after(sched_point, new_op);
606 sched_add_after(new_op, proj);
611 /* copy the register from the old node to the new Load */
612 reg = arch_get_irn_register(env->cg->arch_env, irn);
613 arch_set_irn_register(env->cg->arch_env, new_op, reg);
615 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
621 * Transforms a be node into a Store.
623 static void transform_to_Store(ia32_transform_env_t *env) {
624 ir_node *irn = env->irn;
625 entity *ent = be_get_frame_entity(irn);
626 ir_mode *mode = env->mode;
627 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
628 ir_node *nomem = new_rd_NoMem(env->irg);
629 ir_node *ptr = get_irn_n(irn, 0);
630 ir_node *val = get_irn_n(irn, 1);
631 ir_node *new_op, *proj;
632 ir_node *sched_point = NULL;
634 if (sched_is_scheduled(irn)) {
635 sched_point = sched_prev(irn);
638 if (mode_is_float(mode)) {
639 if (USE_SSE2(env->cg))
640 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
642 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
644 else if (get_mode_size_bits(mode) == 8) {
645 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
648 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
651 set_ia32_am_support(new_op, ia32_am_Dest);
652 set_ia32_op_type(new_op, ia32_AddrModeD);
653 set_ia32_am_flavour(new_op, ia32_B);
654 set_ia32_ls_mode(new_op, mode);
655 set_ia32_frame_ent(new_op, ent);
656 set_ia32_use_frame(new_op);
658 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, 0);
661 sched_add_after(sched_point, new_op);
662 sched_add_after(new_op, proj);
667 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
673 * Fix the mode of Spill/Reload
675 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
677 if (mode_is_float(mode)) {
689 * Block-Walker: Calls the transform functions Spill and Reload.
691 static void ia32_after_ra_walker(ir_node *block, void *env) {
692 ir_node *node, *prev;
693 ia32_code_gen_t *cg = env;
694 ia32_transform_env_t tenv;
697 tenv.irg = current_ir_graph;
699 DEBUG_ONLY(tenv.mod = cg->mod;)
701 /* beware: the schedule is changed here */
702 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
703 prev = sched_prev(node);
704 if (be_is_Reload(node)) {
705 /* we always reload the whole register */
706 tenv.dbg = get_irn_dbg_info(node);
708 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
709 transform_to_Load(&tenv);
711 else if (be_is_Spill(node)) {
712 /* we always spill the whole register */
713 tenv.dbg = get_irn_dbg_info(node);
715 tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node)));
716 transform_to_Store(&tenv);
722 * We transform Spill and Reload here. This needs to be done before
723 * stack biasing otherwise we would miss the corrected offset for these nodes.
725 * If x87 instruction should be emitted, run the x87 simulator and patch
726 * the virtual instructions. This must obviously be done after register allocation.
728 static void ia32_after_ra(void *self) {
729 ia32_code_gen_t *cg = self;
730 irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self);
732 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
734 x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
740 * Emits the code, closes the output file and frees
741 * the code generator interface.
743 static void ia32_codegen(void *self) {
744 ia32_code_gen_t *cg = self;
745 ir_graph *irg = cg->irg;
748 if (cg->emit_decls) {
749 ia32_gen_decls(cg->out);
753 ia32_finish_irg(irg, cg);
754 be_dump(irg, "-finished", dump_ir_block_graph_sched);
755 ia32_gen_routine(out, irg, cg);
759 pmap_destroy(cg->tv_ent);
760 pmap_destroy(cg->types);
762 /* de-allocate code generator */
763 del_set(cg->reg_set);
767 static void *ia32_cg_init(FILE *F, const be_irg_t *birg);
769 static const arch_code_generator_if_t ia32_code_gen_if = {
771 NULL, /* before abi introduce hook */
773 ia32_before_sched, /* before scheduling hook */
774 ia32_before_ra, /* before register allocation hook */
775 ia32_after_ra, /* after register allocation hook */
776 ia32_codegen /* emit && done */
780 * Initializes the code generator.
782 static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
783 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
784 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
786 cg->impl = &ia32_code_gen_if;
788 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
790 cg->arch_env = birg->main_env->arch_env;
791 cg->types = pmap_create();
792 cg->tv_ent = pmap_create();
794 cg->blk_sched = NULL;
795 cg->fp_kind = isa->fp_kind;
798 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
800 /* set optimizations */
803 cg->opt.placecnst = 1;
808 if (isa->name_obst_size) {
809 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
810 isa->name_obst_size = 0;
811 obstack_free(isa->name_obst, NULL);
812 obstack_init(isa->name_obst);
818 if (isa->num_codegens > 1)
823 cur_reg_set = cg->reg_set;
825 ia32_irn_ops.cg = cg;
827 return (arch_code_generator_t *)cg;
832 /*****************************************************************
833 * ____ _ _ _____ _____
834 * | _ \ | | | | |_ _|/ ____| /\
835 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
836 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
837 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
838 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
840 *****************************************************************/
842 static ia32_isa_t ia32_isa_template = {
843 &ia32_isa_if, /* isa interface implementation */
844 &ia32_gp_regs[REG_ESP], /* stack pointer register */
845 &ia32_gp_regs[REG_EBP], /* base pointer register */
846 -1, /* stack direction */
847 0, /* number of code generator objects so far */
848 NULL, /* 16bit register names */
849 NULL, /* 8bit register names */
850 arch_pentium_4, /* instruction architecture */
851 arch_pentium_4, /* optimize for architecture */
852 fp_sse2, /* use sse2 unit */
854 NULL, /* name obstack */
855 0 /* name obst size */
860 * Initializes the backend ISA.
862 static void *ia32_init(void) {
863 static int inited = 0;
869 isa = xcalloc(1, sizeof(*isa));
870 memcpy(isa, &ia32_isa_template, sizeof(*isa));
872 ia32_register_init(isa);
873 ia32_create_opcodes();
874 ia32_register_copy_attr_func();
876 isa->regs_16bit = pmap_create();
877 isa->regs_8bit = pmap_create();
879 ia32_build_16bit_reg_map(isa->regs_16bit);
880 ia32_build_8bit_reg_map(isa->regs_8bit);
883 isa->name_obst = xcalloc(1, sizeof(*(isa->name_obst)));
884 obstack_init(isa->name_obst);
885 isa->name_obst_size = 0;
896 * Closes the output file and frees the ISA structure.
898 static void ia32_done(void *self) {
899 ia32_isa_t *isa = self;
901 pmap_destroy(isa->regs_16bit);
902 pmap_destroy(isa->regs_8bit);
905 //printf("name obst size = %d bytes\n", isa->name_obst_size);
906 obstack_free(isa->name_obst, NULL);
914 * Return the number of register classes for this architecture.
915 * We report always these:
916 * - the general purpose registers
917 * - the floating point register set (depending on the unit used for FP)
918 * - MMX/SE registers (currently not supported)
920 static int ia32_get_n_reg_class(const void *self) {
925 * Return the register class for index i.
927 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
928 const ia32_isa_t *isa = self;
929 assert(i >= 0 && i < 2 && "Invalid ia32 register class requested.");
931 return &ia32_reg_classes[CLASS_ia32_gp];
932 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
936 * Get the register class which shall be used to store a value of a given mode.
937 * @param self The this pointer.
938 * @param mode The mode in question.
939 * @return A register class which can hold values of the given mode.
941 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
942 const ia32_isa_t *isa = self;
943 if (mode_is_float(mode)) {
944 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
947 return &ia32_reg_classes[CLASS_ia32_gp];
951 * Get the ABI restrictions for procedure calls.
952 * @param self The this pointer.
953 * @param method_type The type of the method (procedure) in question.
954 * @param abi The abi object to be modified
956 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
957 const ia32_isa_t *isa = self;
960 unsigned cc = get_method_calling_convention(method_type);
961 int n = get_method_n_params(method_type);
964 int i, ignore_1, ignore_2;
966 const arch_register_t *reg;
967 be_abi_call_flags_t call_flags;
969 /* set abi flags for calls */
970 call_flags.bits.left_to_right = 0;
971 call_flags.bits.store_args_sequential = 0;
972 call_flags.bits.try_omit_fp = 1;
973 call_flags.bits.fp_free = 0;
974 call_flags.bits.call_has_imm = 1;
976 /* set stack parameter passing style */
977 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
979 /* collect the mode for each type */
980 modes = alloca(n * sizeof(modes[0]));
982 for (i = 0; i < n; i++) {
983 tp = get_method_param_type(method_type, i);
984 modes[i] = get_type_mode(tp);
987 /* set register parameters */
988 if (cc & cc_reg_param) {
989 /* determine the number of parameters passed via registers */
990 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
992 /* loop over all parameters and set the register requirements */
993 for (i = 0; i <= biggest_n; i++) {
994 reg = ia32_get_RegParam_reg(n, modes, i, cc);
995 assert(reg && "kaputt");
996 be_abi_call_param_reg(abi, i, reg);
1003 /* set stack parameters */
1004 for (i = stack_idx; i < n; i++) {
1005 be_abi_call_param_stack(abi, i, 1, 0, 0);
1009 /* set return registers */
1010 n = get_method_n_ress(method_type);
1012 assert(n <= 2 && "more than two results not supported");
1014 /* In case of 64bit returns, we will have two 32bit values */
1016 tp = get_method_res_type(method_type, 0);
1017 mode = get_type_mode(tp);
1019 assert(!mode_is_float(mode) && "two FP results not supported");
1021 tp = get_method_res_type(method_type, 1);
1022 mode = get_type_mode(tp);
1024 assert(!mode_is_float(mode) && "two FP results not supported");
1026 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1027 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1030 const arch_register_t *reg;
1032 tp = get_method_res_type(method_type, 0);
1033 assert(is_atomic_type(tp));
1034 mode = get_type_mode(tp);
1036 reg = mode_is_float(mode) ?
1037 (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
1038 &ia32_gp_regs[REG_EAX];
1040 be_abi_call_res_reg(abi, 0, reg);
1045 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1046 return &ia32_irn_ops;
1049 const arch_irn_handler_t ia32_irn_handler = {
1053 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1054 return &ia32_irn_handler;
1057 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1058 return is_ia32_irn(irn);
1062 * Initializes the code generator interface.
1064 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1065 return &ia32_code_gen_if;
1068 list_sched_selector_t ia32_sched_selector;
1071 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1073 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
1074 // memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1075 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
1076 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1077 return &ia32_sched_selector;
1081 * Returns the necessary byte alignment for storing a register of given class.
1083 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1084 ir_mode *mode = arch_register_class_mode(cls);
1085 int bytes = get_mode_size_bytes(mode);
1087 if (mode_is_float(mode) && bytes > 8)
1094 /* instruction set architectures. */
1095 static const lc_opt_enum_int_items_t arch_items[] = {
1096 { "386", arch_i386, },
1097 { "486", arch_i486, },
1098 { "pentium", arch_pentium, },
1099 { "586", arch_pentium, },
1100 { "pentiumpro", arch_pentium_pro, },
1101 { "686", arch_pentium_pro, },
1102 { "pentiummmx", arch_pentium_mmx, },
1103 { "pentiummmx", arch_pentium_mmx, },
1104 { "pentium2", arch_pentium_2, },
1105 { "p2", arch_pentium_2, },
1106 { "pentium3", arch_pentium_3, },
1107 { "p3", arch_pentium_3, },
1108 { "pentium4", arch_pentium_4, },
1109 { "p4", arch_pentium_4, },
1110 { "pentiumm", arch_pentium_m, },
1111 { "pm", arch_pentium_m, },
1112 { "core", arch_core, },
1114 { "athlon", arch_athlon, },
1115 { "athlon64", arch_athlon_64, },
1116 { "opteron", arch_opteron, },
1120 static lc_opt_enum_int_var_t arch_var = {
1121 &ia32_isa_template.arch, arch_items
1124 static lc_opt_enum_int_var_t opt_arch_var = {
1125 &ia32_isa_template.opt_arch, arch_items
1128 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1130 { "sse2", fp_sse2 },
1134 static lc_opt_enum_int_var_t fp_unit_var = {
1135 &ia32_isa_template.fp_kind, fp_unit_items
1138 static const lc_opt_table_entry_t ia32_options[] = {
1139 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1140 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1141 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1146 * Register command line options for the ia32 backend.
1150 * ia32-arch=arch create instruction for arch
1151 * ia32-opt=arch optimize for run on arch
1152 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1154 static void ia32_register_options(lc_opt_entry_t *ent)
1156 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1157 lc_opt_add_table(be_grp_ia32, ia32_options);
1159 #endif /* WITH_LIBCORE */
1161 const arch_isa_if_t ia32_isa_if = {
1164 ia32_get_n_reg_class,
1166 ia32_get_reg_class_for_mode,
1168 ia32_get_irn_handler,
1169 ia32_get_code_generator_if,
1170 ia32_get_list_sched_selector,
1171 ia32_get_reg_class_alignment,
1173 ia32_register_options