2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
58 #include "../benode.h"
59 #include "../belower.h"
60 #include "../besched.h"
63 #include "../beirgmod.h"
64 #include "../be_dbgout.h"
65 #include "../beblocksched.h"
66 #include "../bemachine.h"
67 #include "../bespillslots.h"
68 #include "../bemodule.h"
69 #include "../begnuas.h"
70 #include "../bestate.h"
71 #include "../beflags.h"
72 #include "../betranshlp.h"
73 #include "../belistsched.h"
74 #include "../beabihelper.h"
76 #include "bearch_ia32_t.h"
78 #include "ia32_new_nodes.h"
79 #include "gen_ia32_regalloc_if.h"
80 #include "gen_ia32_machine.h"
81 #include "ia32_common_transform.h"
82 #include "ia32_transform.h"
83 #include "ia32_emitter.h"
84 #include "ia32_optimize.h"
86 #include "ia32_dbg_stat.h"
87 #include "ia32_finish.h"
89 #include "ia32_architecture.h"
92 #include "ia32_pbqp_transform.h"
94 transformer_t be_transformer = TRANSFORMER_DEFAULT;
97 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
99 ir_mode *ia32_mode_fpcw = NULL;
101 /** The current omit-fp state */
102 static ir_type *omit_fp_between_type = NULL;
103 static ir_type *between_type = NULL;
104 static ir_entity *old_bp_ent = NULL;
105 static ir_entity *ret_addr_ent = NULL;
106 static ir_entity *omit_fp_ret_addr_ent = NULL;
109 * The environment for the intrinsic mapping.
111 static ia32_intrinsic_env_t intrinsic_env = {
113 NULL, /* the irg, these entities belong to */
114 NULL, /* entity for __divdi3 library call */
115 NULL, /* entity for __moddi3 library call */
116 NULL, /* entity for __udivdi3 library call */
117 NULL, /* entity for __umoddi3 library call */
121 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
124 * Used to create per-graph unique pseudo nodes.
126 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
127 create_const_node_func func,
128 const arch_register_t* reg)
130 ir_node *block, *res;
135 block = get_irg_start_block(irg);
136 res = func(NULL, block);
137 arch_set_irn_register(res, reg);
143 /* Creates the unique per irg GP NoReg node. */
144 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
146 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
147 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
148 &ia32_registers[REG_GP_NOREG]);
151 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
153 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
154 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
155 &ia32_registers[REG_VFP_NOREG]);
158 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
160 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
161 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
162 &ia32_registers[REG_XMM_NOREG]);
165 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
167 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
168 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
169 &ia32_registers[REG_FPCW]);
174 * Returns the admissible noreg register node for input register pos of node irn.
176 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
178 ir_graph *irg = get_irn_irg(irn);
179 const arch_register_req_t *req = arch_get_register_req(irn, pos);
181 assert(req != NULL && "Missing register requirements");
182 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
183 return ia32_new_NoReg_gp(irg);
185 if (ia32_cg_config.use_sse2) {
186 return ia32_new_NoReg_xmm(irg);
188 return ia32_new_NoReg_vfp(irg);
192 static arch_irn_class_t ia32_classify(const ir_node *irn)
194 arch_irn_class_t classification = arch_irn_class_none;
196 assert(is_ia32_irn(irn));
198 if (is_ia32_is_reload(irn))
199 classification |= arch_irn_class_reload;
201 if (is_ia32_is_spill(irn))
202 classification |= arch_irn_class_spill;
204 if (is_ia32_is_remat(irn))
205 classification |= arch_irn_class_remat;
207 return classification;
211 * The IA32 ABI callback object.
214 be_abi_call_flags_bits_t flags; /**< The call flags. */
215 ir_graph *irg; /**< The associated graph. */
218 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
220 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
223 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
225 if (is_be_node(node))
226 be_node_set_frame_entity(node, entity);
228 set_ia32_frame_ent(node, entity);
231 static void ia32_set_frame_offset(ir_node *irn, int bias)
233 if (get_ia32_frame_ent(irn) == NULL)
236 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
237 ir_graph *irg = get_irn_irg(irn);
238 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
239 if (layout->sp_relative) {
240 /* Pop nodes modify the stack pointer before calculating the
241 * destination address, so fix this here
246 add_ia32_am_offs_int(irn, bias);
249 static int ia32_get_sp_bias(const ir_node *node)
251 if (is_ia32_Call(node))
252 return -(int)get_ia32_call_attr_const(node)->pop;
254 if (is_ia32_Push(node))
257 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
260 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
261 return SP_BIAS_RESET;
268 * Build the between type and entities if not already build.
270 static void ia32_build_between_type(void)
272 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
273 if (! between_type) {
274 ir_type *old_bp_type = new_type_primitive(mode_Iu);
275 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
277 between_type = new_type_struct(IDENT("ia32_between_type"));
278 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
279 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
281 set_entity_offset(old_bp_ent, 0);
282 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
283 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
284 set_type_state(between_type, layout_fixed);
286 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
287 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
289 set_entity_offset(omit_fp_ret_addr_ent, 0);
290 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
291 set_type_state(omit_fp_between_type, layout_fixed);
297 * Produces the type which sits between the stack args and the locals on the stack.
298 * it will contain the return address and space to store the old base pointer.
299 * @return The Firm type modeling the ABI between type.
301 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
303 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
304 ia32_build_between_type();
305 return layout->sp_relative ? omit_fp_between_type : between_type;
309 * Return the stack entity that contains the return address.
311 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
313 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
314 ia32_build_between_type();
315 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
319 * Return the stack entity that contains the frame address.
321 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
323 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
324 ia32_build_between_type();
325 return layout->sp_relative ? NULL : old_bp_ent;
329 * Get the estimated cycle count for @p irn.
331 * @param self The this pointer.
332 * @param irn The node.
334 * @return The estimated cycle count for this operation
336 static int ia32_get_op_estimated_cost(const ir_node *irn)
339 ia32_op_type_t op_tp;
343 if (!is_ia32_irn(irn))
346 assert(is_ia32_irn(irn));
348 cost = get_ia32_latency(irn);
349 op_tp = get_ia32_op_type(irn);
351 if (is_ia32_CopyB(irn)) {
354 else if (is_ia32_CopyB_i(irn)) {
355 int size = get_ia32_copyb_size(irn);
356 cost = 20 + (int)ceil((4/3) * size);
358 /* in case of address mode operations add additional cycles */
359 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
361 In case of stack access and access to fixed addresses add 5 cycles
362 (we assume they are in cache), other memory operations cost 20
365 if (is_ia32_use_frame(irn) || (
366 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
367 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
379 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
381 * @param irn The original operation
382 * @param i Index of the argument we want the inverse operation to yield
383 * @param inverse struct to be filled with the resulting inverse op
384 * @param obstack The obstack to use for allocation of the returned nodes array
385 * @return The inverse operation or NULL if operation invertible
387 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
398 ir_node *block, *noreg, *nomem;
401 /* we cannot invert non-ia32 irns */
402 if (! is_ia32_irn(irn))
405 /* operand must always be a real operand (not base, index or mem) */
406 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
409 /* we don't invert address mode operations */
410 if (get_ia32_op_type(irn) != ia32_Normal)
413 /* TODO: adjust for new immediates... */
414 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
418 block = get_nodes_block(irn);
419 mode = get_irn_mode(irn);
420 irn_mode = get_irn_mode(irn);
421 noreg = get_irn_n(irn, 0);
422 nomem = get_irg_no_mem(irg);
423 dbg = get_irn_dbg_info(irn);
425 /* initialize structure */
426 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
430 switch (get_ia32_irn_opcode(irn)) {
432 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
433 /* we have an add with a const here */
434 /* invers == add with negated const */
435 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
437 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
438 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
439 set_ia32_commutative(inverse->nodes[0]);
441 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
442 /* we have an add with a symconst here */
443 /* invers == sub with const */
444 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
446 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
449 /* normal add: inverse == sub */
450 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
455 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
456 /* we have a sub with a const/symconst here */
457 /* invers == add with this const */
458 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
459 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
460 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
464 if (i == n_ia32_binary_left) {
465 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
468 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
474 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
475 /* xor with const: inverse = xor */
476 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
477 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
478 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
482 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
487 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
492 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
497 /* inverse operation not supported */
505 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
507 if (mode_is_float(mode))
514 * Get the mode that should be used for spilling value node
516 static ir_mode *get_spill_mode(const ir_node *node)
518 ir_mode *mode = get_irn_mode(node);
519 return get_spill_mode_mode(mode);
523 * Checks whether an addressmode reload for a node with mode mode is compatible
524 * with a spillslot of mode spill_mode
526 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
528 return !mode_is_float(mode) || mode == spillmode;
532 * Check if irn can load its operand at position i from memory (source addressmode).
533 * @param irn The irn to be checked
534 * @param i The operands position
535 * @return Non-Zero if operand can be loaded
537 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
539 ir_node *op = get_irn_n(irn, i);
540 const ir_mode *mode = get_irn_mode(op);
541 const ir_mode *spillmode = get_spill_mode(op);
543 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
544 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
545 !ia32_is_spillmode_compatible(mode, spillmode) ||
546 is_ia32_use_frame(irn)) /* must not already use frame */
549 switch (get_ia32_am_support(irn)) {
554 if (i != n_ia32_unary_op)
560 case n_ia32_binary_left: {
561 const arch_register_req_t *req;
562 if (!is_ia32_commutative(irn))
565 /* we can't swap left/right for limited registers
566 * (As this (currently) breaks constraint handling copies)
568 req = arch_get_in_register_req(irn, n_ia32_binary_left);
569 if (req->type & arch_register_req_type_limited)
574 case n_ia32_binary_right:
583 panic("Unknown AM type");
586 /* HACK: must not already use "real" memory.
587 * This can happen for Call and Div */
588 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
594 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
598 ir_mode *dest_op_mode;
600 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
602 set_ia32_op_type(irn, ia32_AddrModeS);
604 load_mode = get_irn_mode(get_irn_n(irn, i));
605 dest_op_mode = get_ia32_ls_mode(irn);
606 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
607 set_ia32_ls_mode(irn, load_mode);
609 set_ia32_use_frame(irn);
610 set_ia32_need_stackent(irn);
612 if (i == n_ia32_binary_left &&
613 get_ia32_am_support(irn) == ia32_am_binary &&
614 /* immediates are only allowed on the right side */
615 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
616 ia32_swap_left_right(irn);
617 i = n_ia32_binary_right;
620 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
622 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
623 set_irn_n(irn, n_ia32_mem, spill);
624 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
625 set_ia32_is_reload(irn);
628 static const be_abi_callbacks_t ia32_abi_callbacks = {
629 ia32_abi_get_between_type,
632 /* register allocator interface */
633 static const arch_irn_ops_t ia32_irn_ops = {
635 ia32_get_frame_entity,
636 ia32_set_frame_offset,
639 ia32_get_op_estimated_cost,
640 ia32_possible_memory_operand,
641 ia32_perform_memory_operand,
644 static ir_entity *mcount = NULL;
645 static int gprof = 0;
647 static void ia32_before_abi(ir_graph *irg)
650 if (mcount == NULL) {
651 ir_type *tp = new_type_method(0, 0);
652 ident *id = new_id_from_str("mcount");
653 mcount = new_entity(get_glob_type(), id, tp);
654 /* FIXME: enter the right ld_ident here */
655 set_entity_ld_ident(mcount, get_entity_ident(mcount));
656 set_entity_visibility(mcount, ir_visibility_external);
658 instrument_initcall(irg, mcount);
663 * Transforms the standard firm graph into
666 static void ia32_prepare_graph(ir_graph *irg)
668 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
671 switch (be_transformer) {
672 case TRANSFORMER_DEFAULT:
673 /* transform remaining nodes into assembler instructions */
674 ia32_transform_graph(irg);
677 case TRANSFORMER_PBQP:
678 case TRANSFORMER_RAND:
679 /* transform nodes into assembler instructions by PBQP magic */
680 ia32_transform_graph_by_pbqp(irg);
684 panic("invalid transformer");
687 ia32_transform_graph(irg);
690 /* do local optimizations (mainly CSE) */
691 optimize_graph_df(irg);
694 dump_ir_graph(irg, "transformed");
696 /* optimize address mode */
697 ia32_optimize_graph(irg);
699 /* do code placement, to optimize the position of constants */
703 dump_ir_graph(irg, "place");
706 ir_node *ia32_turn_back_am(ir_node *node)
708 dbg_info *dbgi = get_irn_dbg_info(node);
709 ir_graph *irg = get_irn_irg(node);
710 ir_node *block = get_nodes_block(node);
711 ir_node *base = get_irn_n(node, n_ia32_base);
712 ir_node *index = get_irn_n(node, n_ia32_index);
713 ir_node *mem = get_irn_n(node, n_ia32_mem);
716 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
717 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
719 ia32_copy_am_attrs(load, node);
720 if (is_ia32_is_reload(node))
721 set_ia32_is_reload(load);
722 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
724 switch (get_ia32_am_support(node)) {
726 set_irn_n(node, n_ia32_unary_op, load_res);
730 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
731 set_irn_n(node, n_ia32_binary_left, load_res);
733 set_irn_n(node, n_ia32_binary_right, load_res);
738 panic("Unknown AM type");
740 noreg = ia32_new_NoReg_gp(current_ir_graph);
741 set_irn_n(node, n_ia32_base, noreg);
742 set_irn_n(node, n_ia32_index, noreg);
743 set_ia32_am_offs_int(node, 0);
744 set_ia32_am_sc(node, NULL);
745 set_ia32_am_scale(node, 0);
746 clear_ia32_am_sc_sign(node);
748 /* rewire mem-proj */
749 if (get_irn_mode(node) == mode_T) {
750 const ir_edge_t *edge;
751 foreach_out_edge(node, edge) {
752 ir_node *out = get_edge_src_irn(edge);
753 if (get_irn_mode(out) == mode_M) {
754 set_Proj_pred(out, load);
755 set_Proj_proj(out, pn_ia32_Load_M);
761 set_ia32_op_type(node, ia32_Normal);
762 if (sched_is_scheduled(node))
763 sched_add_before(node, load);
768 static ir_node *flags_remat(ir_node *node, ir_node *after)
770 /* we should turn back source address mode when rematerializing nodes */
775 if (is_Block(after)) {
778 block = get_nodes_block(after);
781 type = get_ia32_op_type(node);
784 ia32_turn_back_am(node);
788 /* TODO implement this later... */
789 panic("found DestAM with flag user %+F this should not happen", node);
792 default: assert(type == ia32_Normal); break;
795 copy = exact_copy(node);
796 set_nodes_block(copy, block);
797 sched_add_after(after, copy);
803 * Called before the register allocator.
805 static void ia32_before_ra(ir_graph *irg)
807 /* setup fpu rounding modes */
808 ia32_setup_fpu_mode(irg);
811 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
814 be_add_missing_keeps(irg);
819 * Transforms a be_Reload into a ia32 Load.
821 static void transform_to_Load(ir_node *node)
823 ir_graph *irg = get_irn_irg(node);
824 dbg_info *dbg = get_irn_dbg_info(node);
825 ir_node *block = get_nodes_block(node);
826 ir_entity *ent = be_get_frame_entity(node);
827 ir_mode *mode = get_irn_mode(node);
828 ir_mode *spillmode = get_spill_mode(node);
829 ir_node *noreg = ia32_new_NoReg_gp(irg);
830 ir_node *sched_point = NULL;
831 ir_node *ptr = get_irg_frame(irg);
832 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
833 ir_node *new_op, *proj;
834 const arch_register_t *reg;
836 if (sched_is_scheduled(node)) {
837 sched_point = sched_prev(node);
840 if (mode_is_float(spillmode)) {
841 if (ia32_cg_config.use_sse2)
842 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
844 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
846 else if (get_mode_size_bits(spillmode) == 128) {
847 /* Reload 128 bit SSE registers */
848 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
851 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
853 set_ia32_op_type(new_op, ia32_AddrModeS);
854 set_ia32_ls_mode(new_op, spillmode);
855 set_ia32_frame_ent(new_op, ent);
856 set_ia32_use_frame(new_op);
857 set_ia32_is_reload(new_op);
859 DBG_OPT_RELOAD2LD(node, new_op);
861 proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
864 sched_add_after(sched_point, new_op);
868 /* copy the register from the old node to the new Load */
869 reg = arch_get_irn_register(node);
870 arch_set_irn_register(proj, reg);
872 SET_IA32_ORIG_NODE(new_op, node);
874 exchange(node, proj);
878 * Transforms a be_Spill node into a ia32 Store.
880 static void transform_to_Store(ir_node *node)
882 ir_graph *irg = get_irn_irg(node);
883 dbg_info *dbg = get_irn_dbg_info(node);
884 ir_node *block = get_nodes_block(node);
885 ir_entity *ent = be_get_frame_entity(node);
886 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
887 ir_mode *mode = get_spill_mode(spillval);
888 ir_node *noreg = ia32_new_NoReg_gp(irg);
889 ir_node *nomem = get_irg_no_mem(irg);
890 ir_node *ptr = get_irg_frame(irg);
891 ir_node *val = get_irn_n(node, n_be_Spill_val);
894 ir_node *sched_point = NULL;
896 if (sched_is_scheduled(node)) {
897 sched_point = sched_prev(node);
900 if (mode_is_float(mode)) {
901 if (ia32_cg_config.use_sse2) {
902 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
903 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
905 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
906 res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
908 } else if (get_mode_size_bits(mode) == 128) {
909 /* Spill 128 bit SSE registers */
910 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
911 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
912 } else if (get_mode_size_bits(mode) == 8) {
913 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
914 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
916 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
917 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
920 set_ia32_op_type(store, ia32_AddrModeD);
921 set_ia32_ls_mode(store, mode);
922 set_ia32_frame_ent(store, ent);
923 set_ia32_use_frame(store);
924 set_ia32_is_spill(store);
925 SET_IA32_ORIG_NODE(store, node);
926 DBG_OPT_SPILL2ST(node, store);
929 sched_add_after(sched_point, store);
936 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
938 dbg_info *dbg = get_irn_dbg_info(node);
939 ir_node *block = get_nodes_block(node);
940 ir_graph *irg = get_irn_irg(node);
941 ir_node *noreg = ia32_new_NoReg_gp(irg);
942 ir_node *frame = get_irg_frame(irg);
944 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
946 set_ia32_frame_ent(push, ent);
947 set_ia32_use_frame(push);
948 set_ia32_op_type(push, ia32_AddrModeS);
949 set_ia32_ls_mode(push, mode_Is);
950 set_ia32_is_spill(push);
952 sched_add_before(schedpoint, push);
956 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
958 dbg_info *dbg = get_irn_dbg_info(node);
959 ir_node *block = get_nodes_block(node);
960 ir_graph *irg = get_irn_irg(node);
961 ir_node *noreg = ia32_new_NoReg_gp(irg);
962 ir_node *frame = get_irg_frame(irg);
964 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg,
965 get_irg_no_mem(irg), sp);
967 set_ia32_frame_ent(pop, ent);
968 set_ia32_use_frame(pop);
969 set_ia32_op_type(pop, ia32_AddrModeD);
970 set_ia32_ls_mode(pop, mode_Is);
971 set_ia32_is_reload(pop);
973 sched_add_before(schedpoint, pop);
978 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
980 dbg_info *dbg = get_irn_dbg_info(node);
981 ir_mode *spmode = mode_Iu;
982 const arch_register_t *spreg = &ia32_registers[REG_ESP];
985 sp = new_rd_Proj(dbg, pred, spmode, pos);
986 arch_set_irn_register(sp, spreg);
992 * Transform MemPerm, currently we do this the ugly way and produce
993 * push/pop into/from memory cascades. This is possible without using
996 static void transform_MemPerm(ir_node *node)
998 ir_node *block = get_nodes_block(node);
999 ir_graph *irg = get_irn_irg(node);
1000 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
1001 int arity = be_get_MemPerm_entity_arity(node);
1002 ir_node **pops = ALLOCAN(ir_node*, arity);
1006 const ir_edge_t *edge;
1007 const ir_edge_t *next;
1010 for (i = 0; i < arity; ++i) {
1011 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1012 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1013 ir_type *enttype = get_entity_type(inent);
1014 unsigned entsize = get_type_size_bytes(enttype);
1015 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1016 ir_node *mem = get_irn_n(node, i + 1);
1019 /* work around cases where entities have different sizes */
1020 if (entsize2 < entsize)
1022 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1024 push = create_push(node, node, sp, mem, inent);
1025 sp = create_spproj(node, push, pn_ia32_Push_stack);
1027 /* add another push after the first one */
1028 push = create_push(node, node, sp, mem, inent);
1029 add_ia32_am_offs_int(push, 4);
1030 sp = create_spproj(node, push, pn_ia32_Push_stack);
1033 set_irn_n(node, i, new_r_Bad(irg, mode_X));
1037 for (i = arity - 1; i >= 0; --i) {
1038 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1039 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1040 ir_type *enttype = get_entity_type(outent);
1041 unsigned entsize = get_type_size_bytes(enttype);
1042 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1045 /* work around cases where entities have different sizes */
1046 if (entsize2 < entsize)
1048 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1050 pop = create_pop(node, node, sp, outent);
1051 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1053 add_ia32_am_offs_int(pop, 4);
1055 /* add another pop after the first one */
1056 pop = create_pop(node, node, sp, outent);
1057 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1064 keep = be_new_Keep(block, 1, in);
1065 sched_add_before(node, keep);
1067 /* exchange memprojs */
1068 foreach_out_edge_safe(node, edge, next) {
1069 ir_node *proj = get_edge_src_irn(edge);
1070 int p = get_Proj_proj(proj);
1074 set_Proj_pred(proj, pops[p]);
1075 set_Proj_proj(proj, pn_ia32_Pop_M);
1078 /* remove memperm */
1084 * Block-Walker: Calls the transform functions Spill and Reload.
1086 static void ia32_after_ra_walker(ir_node *block, void *env)
1088 ir_node *node, *prev;
1091 /* beware: the schedule is changed here */
1092 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1093 prev = sched_prev(node);
1095 if (be_is_Reload(node)) {
1096 transform_to_Load(node);
1097 } else if (be_is_Spill(node)) {
1098 transform_to_Store(node);
1099 } else if (be_is_MemPerm(node)) {
1100 transform_MemPerm(node);
1106 * Collects nodes that need frame entities assigned.
1108 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1110 be_fec_env_t *env = (be_fec_env_t*)data;
1111 const ir_mode *mode;
1114 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1115 mode = get_spill_mode_mode(get_irn_mode(node));
1116 align = get_mode_size_bytes(mode);
1117 } else if (is_ia32_irn(node) &&
1118 get_ia32_frame_ent(node) == NULL &&
1119 is_ia32_use_frame(node)) {
1120 if (is_ia32_need_stackent(node))
1123 switch (get_ia32_irn_opcode(node)) {
1125 case iro_ia32_Load: {
1126 const ia32_attr_t *attr = get_ia32_attr_const(node);
1128 if (attr->data.need_32bit_stackent) {
1130 } else if (attr->data.need_64bit_stackent) {
1133 mode = get_ia32_ls_mode(node);
1134 if (is_ia32_is_reload(node))
1135 mode = get_spill_mode_mode(mode);
1137 align = get_mode_size_bytes(mode);
1141 case iro_ia32_vfild:
1143 case iro_ia32_xLoad: {
1144 mode = get_ia32_ls_mode(node);
1149 case iro_ia32_FldCW: {
1150 /* although 2 byte would be enough 4 byte performs best */
1158 panic("unexpected frame user while collection frame entity nodes");
1160 case iro_ia32_FnstCW:
1161 case iro_ia32_Store8Bit:
1162 case iro_ia32_Store:
1165 case iro_ia32_vfist:
1166 case iro_ia32_vfisttp:
1168 case iro_ia32_xStore:
1169 case iro_ia32_xStoreSimple:
1176 be_node_needs_frame_entity(env, node, mode, align);
1179 static int determine_ebp_input(ir_node *ret)
1181 const arch_register_t *bp = &ia32_registers[REG_EBP];
1182 int arity = get_irn_arity(ret);
1185 for (i = 0; i < arity; ++i) {
1186 ir_node *input = get_irn_n(ret, i);
1187 if (arch_get_irn_register(input) == bp)
1190 panic("no ebp input found at %+F", ret);
1193 static void introduce_epilog(ir_node *ret)
1195 const arch_register_t *sp = &ia32_registers[REG_ESP];
1196 const arch_register_t *bp = &ia32_registers[REG_EBP];
1197 ir_graph *irg = get_irn_irg(ret);
1198 ir_type *frame_type = get_irg_frame_type(irg);
1199 unsigned frame_size = get_type_size_bytes(frame_type);
1200 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1201 ir_node *block = get_nodes_block(ret);
1202 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1203 ir_node *curr_sp = first_sp;
1204 ir_mode *mode_gp = mode_Iu;
1206 if (!layout->sp_relative) {
1207 int n_ebp = determine_ebp_input(ret);
1208 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1209 if (ia32_cg_config.use_leave) {
1210 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1211 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1212 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1213 arch_set_irn_register(curr_bp, bp);
1214 arch_set_irn_register(curr_sp, sp);
1215 sched_add_before(ret, leave);
1218 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1219 /* copy ebp to esp */
1220 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1221 arch_set_irn_register(curr_sp, sp);
1222 sched_add_before(ret, curr_sp);
1225 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1226 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1227 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1228 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1229 arch_set_irn_register(curr_bp, bp);
1230 arch_set_irn_register(curr_sp, sp);
1231 sched_add_before(ret, pop);
1233 set_irn_n(ret, n_be_Return_mem, curr_mem);
1235 set_irn_n(ret, n_ebp, curr_bp);
1237 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1238 sched_add_before(ret, incsp);
1241 set_irn_n(ret, n_be_Return_sp, curr_sp);
1243 /* keep verifier happy... */
1244 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1245 kill_node(first_sp);
1250 * put the Prolog code at the beginning, epilog code before each return
1252 static void introduce_prolog_epilog(ir_graph *irg)
1254 const arch_register_t *sp = &ia32_registers[REG_ESP];
1255 const arch_register_t *bp = &ia32_registers[REG_EBP];
1256 ir_node *start = get_irg_start(irg);
1257 ir_node *block = get_nodes_block(start);
1258 ir_type *frame_type = get_irg_frame_type(irg);
1259 unsigned frame_size = get_type_size_bytes(frame_type);
1260 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1261 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1262 ir_node *curr_sp = initial_sp;
1263 ir_mode *mode_gp = mode_Iu;
1265 if (!layout->sp_relative) {
1267 ir_node *mem = get_irg_initial_mem(irg);
1268 ir_node *noreg = ia32_new_NoReg_gp(irg);
1269 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1270 ir_node *curr_bp = initial_bp;
1271 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
1274 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1275 mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
1276 arch_set_irn_register(curr_sp, sp);
1277 sched_add_after(start, push);
1279 /* move esp to ebp */
1280 curr_bp = be_new_Copy(bp->reg_class, block, curr_sp);
1281 sched_add_after(push, curr_bp);
1282 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1283 curr_sp = be_new_CopyKeep_single(sp->reg_class, block, curr_sp, curr_bp, mode_gp);
1284 sched_add_after(curr_bp, curr_sp);
1285 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1286 edges_reroute(initial_bp, curr_bp);
1287 set_irn_n(push, n_ia32_Push_val, initial_bp);
1289 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1290 edges_reroute(initial_sp, incsp);
1291 set_irn_n(push, n_ia32_Push_stack, initial_sp);
1292 sched_add_after(curr_sp, incsp);
1294 layout->initial_bias = -4;
1296 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1297 edges_reroute(initial_sp, incsp);
1298 be_set_IncSP_pred(incsp, curr_sp);
1299 sched_add_after(start, incsp);
1302 /* introduce epilog for every return node */
1304 ir_node *end_block = get_irg_end_block(irg);
1305 int arity = get_irn_arity(end_block);
1308 for (i = 0; i < arity; ++i) {
1309 ir_node *ret = get_irn_n(end_block, i);
1310 assert(be_is_Return(ret));
1311 introduce_epilog(ret);
1317 * We transform Spill and Reload here. This needs to be done before
1318 * stack biasing otherwise we would miss the corrected offset for these nodes.
1320 static void ia32_after_ra(ir_graph *irg)
1322 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1323 bool at_begin = stack_layout->sp_relative ? true : false;
1324 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1326 /* create and coalesce frame entities */
1327 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1328 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1329 be_free_frame_entity_coalescer(fec_env);
1331 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1333 introduce_prolog_epilog(irg);
1337 * Last touchups for the graph before emit: x87 simulation to replace the
1338 * virtual with real x87 instructions, creating a block schedule and peephole
1341 static void ia32_finish(ir_graph *irg)
1343 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1345 ia32_finish_irg(irg);
1347 /* we might have to rewrite x87 virtual registers */
1348 if (irg_data->do_x87_sim) {
1349 ia32_x87_simulate_graph(irg);
1352 /* do peephole optimisations */
1353 ia32_peephole_optimization(irg);
1355 /* create block schedule, this also removes empty blocks which might
1356 * produce critical edges */
1357 irg_data->blk_sched = be_create_block_schedule(irg);
1361 * Emits the code, closes the output file and frees
1362 * the code generator interface.
1364 static void ia32_emit(ir_graph *irg)
1366 if (ia32_cg_config.emit_machcode) {
1367 ia32_gen_binary_routine(irg);
1369 ia32_gen_routine(irg);
1374 * Returns the node representing the PIC base.
1376 static ir_node *ia32_get_pic_base(ir_graph *irg)
1378 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1380 ir_node *get_eip = irg_data->get_eip;
1381 if (get_eip != NULL)
1384 block = get_irg_start_block(irg);
1385 get_eip = new_bd_ia32_GetEIP(NULL, block);
1386 irg_data->get_eip = get_eip;
1392 * Initializes a IA32 code generator.
1394 static void ia32_init_graph(ir_graph *irg)
1396 struct obstack *obst = be_get_be_obst(irg);
1397 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1399 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1402 /* Linux gprof implementation needs base pointer */
1403 be_get_irg_options(irg)->omit_fp = 0;
1406 be_birg_from_irg(irg)->isa_link = irg_data;
1411 * Set output modes for GCC
1413 static const tarval_mode_info mo_integer = {
1420 * set the tarval output mode of all integer modes to decimal
1422 static void set_tarval_output_modes(void)
1426 for (i = get_irp_n_modes(); i > 0;) {
1427 ir_mode *mode = get_irp_mode(--i);
1429 if (mode_is_int(mode))
1430 set_tarval_mode_output_option(mode, &mo_integer);
1434 extern const arch_isa_if_t ia32_isa_if;
1437 * The template that generates a new ISA object.
1438 * Note that this template can be changed by command line
1441 static ia32_isa_t ia32_isa_template = {
1443 &ia32_isa_if, /* isa interface implementation */
1448 &ia32_registers[REG_ESP], /* stack pointer register */
1449 &ia32_registers[REG_EBP], /* base pointer register */
1450 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1451 2, /* power of two stack alignment, 2^2 == 4 */
1452 NULL, /* main environment */
1453 7, /* costs for a spill instruction */
1454 5, /* costs for a reload instruction */
1455 false, /* no custom abi handling */
1459 NULL, /* abstract machine */
1462 static void init_asm_constraints(void)
1464 be_init_default_asm_constraint_flags();
1466 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1467 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1468 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1469 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1470 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1471 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1472 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1473 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1474 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1475 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1476 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1477 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1478 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1479 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1480 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1481 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1482 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1483 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1484 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1485 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1487 /* no support for autodecrement/autoincrement */
1488 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1489 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1490 /* no float consts */
1491 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1492 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1493 /* makes no sense on x86 */
1494 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1495 /* no support for sse consts yet */
1496 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1497 /* no support for x87 consts yet */
1498 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1499 /* no support for mmx registers yet */
1500 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1501 /* not available in 32bit mode */
1502 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1503 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1505 /* no code yet to determine register class needed... */
1506 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1510 * Initializes the backend ISA.
1512 static arch_env_t *ia32_init(FILE *file_handle)
1514 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1516 set_tarval_output_modes();
1518 *isa = ia32_isa_template;
1520 if (ia32_mode_fpcw == NULL) {
1521 ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1524 ia32_register_init();
1525 ia32_create_opcodes(&ia32_irn_ops);
1527 be_emit_init(file_handle);
1528 isa->types = pmap_create();
1529 isa->tv_ent = pmap_create();
1530 isa->cpu = ia32_init_machine_description();
1532 /* enter the ISA object into the intrinsic environment */
1533 intrinsic_env.isa = isa;
1541 * Closes the output file and frees the ISA structure.
1543 static void ia32_done(void *self)
1545 ia32_isa_t *isa = (ia32_isa_t*)self;
1547 /* emit now all global declarations */
1548 be_gas_emit_decls(isa->base.main_env);
1550 pmap_destroy(isa->tv_ent);
1551 pmap_destroy(isa->types);
1560 * Get the register class which shall be used to store a value of a given mode.
1561 * @param self The this pointer.
1562 * @param mode The mode in question.
1563 * @return A register class which can hold values of the given mode.
1565 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1567 if (mode_is_float(mode)) {
1568 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1571 return &ia32_reg_classes[CLASS_ia32_gp];
1575 * Returns the register for parameter nr.
1577 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1578 const ir_mode *mode)
1580 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1581 &ia32_registers[REG_ECX],
1582 &ia32_registers[REG_EDX],
1585 static const unsigned MAXNUM_GPREG_ARGS = 3;
1587 static const arch_register_t *gpreg_param_reg_regparam[] = {
1588 &ia32_registers[REG_EAX],
1589 &ia32_registers[REG_EDX],
1590 &ia32_registers[REG_ECX]
1593 static const arch_register_t *gpreg_param_reg_this[] = {
1594 &ia32_registers[REG_ECX],
1599 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1600 &ia32_registers[REG_XMM0],
1601 &ia32_registers[REG_XMM1],
1602 &ia32_registers[REG_XMM2],
1603 &ia32_registers[REG_XMM3],
1604 &ia32_registers[REG_XMM4],
1605 &ia32_registers[REG_XMM5],
1606 &ia32_registers[REG_XMM6],
1607 &ia32_registers[REG_XMM7]
1610 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1611 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1613 static const unsigned MAXNUM_SSE_ARGS = 8;
1615 if ((cc & cc_this_call) && nr == 0)
1616 return gpreg_param_reg_this[0];
1618 if (! (cc & cc_reg_param))
1621 if (mode_is_float(mode)) {
1622 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1624 if (nr >= MAXNUM_SSE_ARGS)
1627 if (cc & cc_this_call) {
1628 return fpreg_sse_param_reg_this[nr];
1630 return fpreg_sse_param_reg_std[nr];
1631 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1632 unsigned num_regparam;
1634 if (get_mode_size_bits(mode) > 32)
1637 if (nr >= MAXNUM_GPREG_ARGS)
1640 if (cc & cc_this_call) {
1641 return gpreg_param_reg_this[nr];
1643 num_regparam = cc & ~cc_bits;
1644 if (num_regparam == 0) {
1645 /* default fastcall */
1646 return gpreg_param_reg_fastcall[nr];
1648 if (nr < num_regparam)
1649 return gpreg_param_reg_regparam[nr];
1653 panic("unknown argument mode");
1657 * Get the ABI restrictions for procedure calls.
1658 * @param self The this pointer.
1659 * @param method_type The type of the method (procedure) in question.
1660 * @param abi The abi object to be modified
1662 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1670 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1674 /* set abi flags for calls */
1675 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1676 call_flags.bits.store_args_sequential = 0;
1677 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1678 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1679 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1681 /* set parameter passing style */
1682 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1684 cc = get_method_calling_convention(method_type);
1685 if (get_method_variadicity(method_type) == variadicity_variadic) {
1686 /* pass all parameters of a variadic function on the stack */
1687 cc = cc_cdecl_set | (cc & cc_this_call);
1689 if (get_method_additional_properties(method_type) & mtp_property_private &&
1690 ia32_cg_config.optimize_cc) {
1691 /* set the fast calling conventions (allowing up to 3) */
1692 cc = SET_FASTCALL(cc) | 3;
1696 /* we have to pop the shadow parameter ourself for compound calls */
1697 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1698 && !(cc & cc_reg_param)) {
1699 pop_amount += get_mode_size_bytes(mode_P_data);
1702 n = get_method_n_params(method_type);
1703 for (i = regnum = 0; i < n; i++) {
1705 const arch_register_t *reg = NULL;
1707 tp = get_method_param_type(method_type, i);
1708 mode = get_type_mode(tp);
1710 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1713 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1716 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1717 * movl has a shorter opcode than mov[sz][bw]l */
1718 ir_mode *load_mode = mode;
1721 unsigned size = get_mode_size_bytes(mode);
1723 if (cc & cc_callee_clear_stk) {
1724 pop_amount += (size + 3U) & ~3U;
1727 if (size < 4) load_mode = mode_Iu;
1730 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1734 be_abi_call_set_pop(abi, pop_amount);
1736 /* set return registers */
1737 n = get_method_n_ress(method_type);
1739 assert(n <= 2 && "more than two results not supported");
1741 /* In case of 64bit returns, we will have two 32bit values */
1743 tp = get_method_res_type(method_type, 0);
1744 mode = get_type_mode(tp);
1746 assert(!mode_is_float(mode) && "two FP results not supported");
1748 tp = get_method_res_type(method_type, 1);
1749 mode = get_type_mode(tp);
1751 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1753 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1754 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1757 const arch_register_t *reg;
1759 tp = get_method_res_type(method_type, 0);
1760 assert(is_atomic_type(tp));
1761 mode = get_type_mode(tp);
1763 reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
1765 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1770 * Returns the necessary byte alignment for storing a register of given class.
1772 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1774 ir_mode *mode = arch_register_class_mode(cls);
1775 int bytes = get_mode_size_bytes(mode);
1777 if (mode_is_float(mode) && bytes > 8)
1783 * Return irp irgs in the desired order.
1785 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1792 static void ia32_mark_remat(ir_node *node)
1794 if (is_ia32_irn(node)) {
1795 set_ia32_is_remat(node);
1800 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1802 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1807 ir_relation relation;
1812 cmp_l = get_Cmp_left(sel);
1813 cmp_r = get_Cmp_right(sel);
1814 if (!mode_is_float(get_irn_mode(cmp_l)))
1817 /* check for min/max. They're defined as (C-Semantik):
1818 * min(a, b) = a < b ? a : b
1819 * or min(a, b) = a <= b ? a : b
1820 * max(a, b) = a > b ? a : b
1821 * or max(a, b) = a >= b ? a : b
1822 * (Note we only handle float min/max here)
1824 relation = get_Cmp_relation(sel);
1826 case ir_relation_greater_equal:
1827 case ir_relation_greater:
1829 if (cmp_l == mux_true && cmp_r == mux_false)
1832 case ir_relation_less_equal:
1833 case ir_relation_less:
1835 if (cmp_l == mux_true && cmp_r == mux_false)
1838 case ir_relation_unordered_greater_equal:
1839 case ir_relation_unordered_greater:
1841 if (cmp_l == mux_false && cmp_r == mux_true)
1844 case ir_relation_unordered_less_equal:
1845 case ir_relation_unordered_less:
1847 if (cmp_l == mux_false && cmp_r == mux_true)
1858 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1860 ir_mode *mode = get_irn_mode(mux_true);
1863 if (!mode_is_int(mode) && !mode_is_reference(mode)
1867 if (is_Const(mux_true) && is_Const(mux_false)) {
1868 /* we can create a set plus up two 3 instructions for any combination
1876 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1881 if (!mode_is_float(get_irn_mode(mux_true)))
1884 return is_Const(mux_true) && is_Const(mux_false);
1887 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1894 ir_relation relation;
1899 mode = get_irn_mode(mux_true);
1900 if (mode_is_signed(mode) || mode_is_float(mode))
1903 relation = get_Cmp_relation(sel);
1904 cmp_left = get_Cmp_left(sel);
1905 cmp_right = get_Cmp_right(sel);
1907 /* "move" zero constant to false input */
1908 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1909 ir_node *tmp = mux_false;
1910 mux_false = mux_true;
1912 relation = get_negated_relation(relation);
1914 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1916 if (!is_Sub(mux_true))
1918 sub_left = get_Sub_left(mux_true);
1919 sub_right = get_Sub_right(mux_true);
1921 /* Mux(a >=u b, 0, a-b) */
1922 if ((relation & ir_relation_greater)
1923 && sub_left == cmp_left && sub_right == cmp_right)
1925 /* Mux(a <=u b, 0, b-a) */
1926 if ((relation & ir_relation_less)
1927 && sub_left == cmp_right && sub_right == cmp_left)
1933 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1938 /* we can handle Set for all modes and compares */
1939 if (mux_is_set(sel, mux_true, mux_false))
1941 /* SSE has own min/max operations */
1942 if (ia32_cg_config.use_sse2
1943 && mux_is_float_min_max(sel, mux_true, mux_false))
1945 /* we can handle Mux(?, Const[f], Const[f]) */
1946 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1947 #ifdef FIRM_GRGEN_BE
1948 /* well, some code selectors can't handle it */
1949 if (be_transformer != TRANSFORMER_PBQP
1950 || be_transformer != TRANSFORMER_RAND)
1957 /* no support for 64bit inputs to cmov */
1958 mode = get_irn_mode(mux_true);
1959 if (get_mode_size_bits(mode) > 32)
1961 /* we can handle Abs for all modes and compares (except 64bit) */
1962 if (ir_mux_is_abs(sel, mux_true, mux_false) != 0)
1964 /* we can't handle MuxF yet */
1965 if (mode_is_float(mode))
1968 if (mux_is_doz(sel, mux_true, mux_false))
1971 /* Check Cmp before the node */
1973 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1975 /* we can't handle 64bit compares */
1976 if (get_mode_size_bits(cmp_mode) > 32)
1979 /* we can't handle float compares */
1980 if (mode_is_float(cmp_mode))
1984 /* did we disable cmov generation? */
1985 if (!ia32_cg_config.use_cmov)
1988 /* we can use a cmov */
1992 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
1996 /* we already added all our simple flags to the flags modifier list in
1997 * init, so this flag we don't know. */
1998 return ASM_CONSTRAINT_FLAG_INVALID;
2001 static int ia32_is_valid_clobber(const char *clobber)
2003 return ia32_get_clobber_register(clobber) != NULL;
2006 static ir_node *ia32_create_set(ir_node *cond)
2008 /* ia32-set function produces 8-bit results which have to be converted */
2009 ir_node *set = ir_create_mux_set(cond, mode_Bu);
2010 ir_node *block = get_nodes_block(set);
2011 return new_r_Conv(block, set, mode_Iu);
2014 static void ia32_lower_for_target(void)
2016 size_t i, n_irgs = get_irp_n_irgs();
2017 lower_mode_b_config_t lower_mode_b_config = {
2018 mode_Iu, /* lowered mode */
2020 0, /* don't lower direct compares */
2022 lower_params_t params = {
2023 4, /* def_ptr_alignment */
2024 LF_COMPOUND_RETURN | LF_RETURN_HIDDEN, /* flags */
2025 ADD_HIDDEN_ALWAYS_IN_FRONT, /* hidden_params */
2026 NULL, /* find pointer type */
2027 NULL, /* ret_compound_in_regs */
2030 /* perform doubleword lowering */
2031 lwrdw_param_t lower_dw_params = {
2032 1, /* little endian */
2033 64, /* doubleword size */
2034 ia32_create_intrinsic_fkt,
2038 /* lower compound param handling */
2039 lower_calls_with_compounds(¶ms);
2041 ir_prepare_dw_lowering(&lower_dw_params);
2044 for (i = 0; i < n_irgs; ++i) {
2045 ir_graph *irg = get_irp_irg(i);
2046 /* lower for mode_b stuff */
2047 ir_lower_mode_b(irg, &lower_mode_b_config);
2048 /* break up switches with wide ranges */
2049 lower_switch(irg, 4, 256, false);
2054 * Create the trampoline code.
2056 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2058 ir_graph *irg = get_irn_irg(block);
2059 ir_node *p = trampoline;
2060 ir_mode *mode = get_irn_mode(p);
2064 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
2065 mem = new_r_Proj(st, mode_M, pn_Store_M);
2066 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2067 st = new_r_Store(block, mem, p, env, cons_none);
2068 mem = new_r_Proj(st, mode_M, pn_Store_M);
2069 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2071 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
2072 mem = new_r_Proj(st, mode_M, pn_Store_M);
2073 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2074 st = new_r_Store(block, mem, p, callee, cons_none);
2075 mem = new_r_Proj(st, mode_M, pn_Store_M);
2076 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2082 * Returns the libFirm configuration parameter for this backend.
2084 static const backend_params *ia32_get_libfirm_params(void)
2086 static const ir_settings_arch_dep_t ad = {
2087 1, /* also use subs */
2088 4, /* maximum shifts */
2089 63, /* maximum shift amount */
2090 ia32_evaluate_insn, /* evaluate the instruction sequence */
2092 1, /* allow Mulhs */
2093 1, /* allow Mulus */
2094 32, /* Mulh allowed up to 32 bit */
2096 static backend_params p = {
2097 1, /* support inline assembly */
2098 1, /* support Rotl nodes */
2099 0, /* little endian */
2100 NULL, /* will be set later */
2101 ia32_is_mux_allowed,
2102 NULL, /* float arithmetic mode, will be set below */
2103 12, /* size of trampoline code */
2104 4, /* alignment of trampoline code */
2105 ia32_create_trampoline_fkt,
2106 4 /* alignment of stack parameter */
2109 ia32_setup_cg_config();
2111 /* doesn't really belong here, but this is the earliest place the backend
2113 init_asm_constraints();
2116 if (! ia32_cg_config.use_sse2)
2117 p.mode_float_arithmetic = mode_E;
2122 * Check if the given register is callee or caller save.
2124 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
2127 /* check for callee saved */
2128 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2129 switch (reg->index) {
2140 /* check for caller saved */
2141 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2142 switch (reg->index) {
2150 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
2151 /* all XMM registers are caller save */
2152 return reg->index != REG_XMM_NOREG;
2153 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
2154 /* all VFP registers are caller save */
2155 return reg->index != REG_VFP_NOREG;
2161 static const lc_opt_enum_int_items_t gas_items[] = {
2162 { "elf", OBJECT_FILE_FORMAT_ELF },
2163 { "mingw", OBJECT_FILE_FORMAT_COFF },
2164 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2168 static lc_opt_enum_int_var_t gas_var = {
2169 (int*) &be_gas_object_file_format, gas_items
2172 #ifdef FIRM_GRGEN_BE
2173 static const lc_opt_enum_int_items_t transformer_items[] = {
2174 { "default", TRANSFORMER_DEFAULT },
2175 { "pbqp", TRANSFORMER_PBQP },
2176 { "random", TRANSFORMER_RAND },
2180 static lc_opt_enum_int_var_t transformer_var = {
2181 (int*)&be_transformer, transformer_items
2185 static const lc_opt_table_entry_t ia32_options[] = {
2186 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2187 #ifdef FIRM_GRGEN_BE
2188 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2190 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2191 &ia32_isa_template.base.stack_alignment),
2192 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2196 const arch_isa_if_t ia32_isa_if = {
2198 ia32_lower_for_target,
2200 ia32_handle_intrinsics,
2201 ia32_get_reg_class_for_mode,
2203 ia32_get_reg_class_alignment,
2204 ia32_get_libfirm_params,
2207 ia32_parse_asm_constraint,
2208 ia32_is_valid_clobber,
2211 ia32_get_pic_base, /* return node used as base in pic code addresses */
2212 ia32_before_abi, /* before abi introduce hook */
2214 ia32_before_ra, /* before register allocation hook */
2215 ia32_after_ra, /* after register allocation hook */
2216 ia32_finish, /* called before codegen */
2217 ia32_emit, /* emit && done */
2218 ia32_register_saved_by,
2221 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2222 void be_init_arch_ia32(void)
2224 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2225 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2227 lc_opt_add_table(ia32_grp, ia32_options);
2228 be_register_isa_if("ia32", &ia32_isa_if);
2230 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2232 ia32_init_emitter();
2234 ia32_init_optimize();
2235 ia32_init_transform();
2237 ia32_init_architecture();