2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
33 #include "pseudo_irg.h"
38 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
55 #include "../beirg_t.h"
56 #include "../benode_t.h"
57 #include "../belower.h"
58 #include "../besched_t.h"
61 #include "../beirgmod.h"
62 #include "../be_dbgout.h"
63 #include "../beblocksched.h"
64 #include "../bemachine.h"
65 #include "../beilpsched.h"
66 #include "../bespillslots.h"
67 #include "../bemodule.h"
68 #include "../begnuas.h"
69 #include "../bestate.h"
70 #include "../beflags.h"
71 #include "../betranshlp.h"
73 #include "bearch_ia32_t.h"
75 #include "ia32_new_nodes.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "gen_ia32_machine.h"
78 #include "ia32_common_transform.h"
79 #include "ia32_transform.h"
80 #include "ia32_emitter.h"
81 #include "ia32_map_regs.h"
82 #include "ia32_optimize.h"
84 #include "ia32_dbg_stat.h"
85 #include "ia32_finish.h"
86 #include "ia32_util.h"
88 #include "ia32_architecture.h"
91 #include "ia32_pbqp_transform.h"
93 transformer_t be_transformer = TRANSFORMER_DEFAULT;
96 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
99 static set *cur_reg_set = NULL;
101 ir_mode *mode_fpcw = NULL;
102 ia32_code_gen_t *ia32_current_cg = NULL;
105 * The environment for the intrinsic mapping.
107 static ia32_intrinsic_env_t intrinsic_env = {
109 NULL, /* the irg, these entities belong to */
110 NULL, /* entity for first div operand (move into FPU) */
111 NULL, /* entity for second div operand (move into FPU) */
112 NULL, /* entity for converts ll -> d */
113 NULL, /* entity for converts d -> ll */
114 NULL, /* entity for __divdi3 library call */
115 NULL, /* entity for __moddi3 library call */
116 NULL, /* entity for __udivdi3 library call */
117 NULL, /* entity for __umoddi3 library call */
118 NULL, /* bias value for conversion from float to unsigned 64 */
122 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
124 static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
125 create_const_node_func func,
126 const arch_register_t* reg)
128 ir_node *block, *res;
133 block = get_irg_start_block(cg->irg);
134 res = func(NULL, cg->irg, block);
135 arch_set_irn_register(res, reg);
138 add_irn_dep(get_irg_end(cg->irg), res);
139 /* add_irn_dep(get_irg_start(cg->irg), res); */
144 /* Creates the unique per irg GP NoReg node. */
145 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
146 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
147 &ia32_gp_regs[REG_GP_NOREG]);
150 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
151 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
152 &ia32_vfp_regs[REG_VFP_NOREG]);
155 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
156 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
157 &ia32_xmm_regs[REG_XMM_NOREG]);
160 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
161 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
162 &ia32_gp_regs[REG_GP_UKNWN]);
165 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
166 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
167 &ia32_vfp_regs[REG_VFP_UKNWN]);
170 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
171 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
172 &ia32_xmm_regs[REG_XMM_UKNWN]);
175 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
176 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
177 &ia32_fp_cw_regs[REG_FPCW]);
182 * Returns the admissible noreg register node for input register pos of node irn.
184 static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
186 const arch_register_req_t *req = arch_get_register_req(irn, pos);
188 assert(req != NULL && "Missing register requirements");
189 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
190 return ia32_new_NoReg_gp(cg);
192 if (ia32_cg_config.use_sse2) {
193 return ia32_new_NoReg_xmm(cg);
195 return ia32_new_NoReg_vfp(cg);
199 /**************************************************
202 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
203 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
204 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
205 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
208 **************************************************/
211 * Return register requirements for an ia32 node.
212 * If the node returns a tuple (mode_T) then the proj's
213 * will be asked for this information.
215 static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node,
218 ir_mode *mode = get_irn_mode(node);
221 if (mode == mode_X || is_Block(node)) {
222 return arch_no_register_req;
225 if (mode == mode_T && pos < 0) {
226 return arch_no_register_req;
229 node_pos = pos == -1 ? 0 : pos;
231 if (mode == mode_M || pos >= 0) {
232 return arch_no_register_req;
235 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
236 node = skip_Proj_const(node);
239 if (is_ia32_irn(node)) {
240 const arch_register_req_t *req;
242 req = get_ia32_in_req(node, pos);
244 req = get_ia32_out_req(node, node_pos);
251 /* unknowns should be transformed already */
252 assert(!is_Unknown(node));
253 return arch_no_register_req;
256 static void ia32_set_irn_reg(ir_node *irn, const arch_register_t *reg)
260 if (get_irn_mode(irn) == mode_X) {
265 pos = get_Proj_proj(irn);
266 irn = skip_Proj(irn);
269 if (is_ia32_irn(irn)) {
270 const arch_register_t **slots;
272 slots = get_ia32_slots(irn);
275 ia32_set_firm_reg(irn, reg, cur_reg_set);
279 static const arch_register_t *ia32_get_irn_reg(const ir_node *irn)
284 if (get_irn_mode(irn) == mode_X) {
288 pos = get_Proj_proj(irn);
289 irn = skip_Proj_const(irn);
292 if (is_ia32_irn(irn)) {
293 const arch_register_t **slots = get_ia32_slots(irn);
294 assert(pos < get_ia32_n_res(irn));
297 return ia32_get_firm_reg(irn, cur_reg_set);
301 static arch_irn_class_t ia32_classify(const ir_node *irn) {
302 arch_irn_class_t classification = 0;
304 irn = skip_Proj_const(irn);
307 classification |= arch_irn_class_branch;
309 if (! is_ia32_irn(irn))
310 return classification;
312 if (is_ia32_is_reload(irn))
313 classification |= arch_irn_class_reload;
315 if (is_ia32_is_spill(irn))
316 classification |= arch_irn_class_spill;
318 if (is_ia32_is_remat(irn))
319 classification |= arch_irn_class_remat;
321 return classification;
324 static arch_irn_flags_t ia32_get_flags(const ir_node *irn) {
325 arch_irn_flags_t flags = arch_irn_flags_none;
328 return arch_irn_flags_ignore;
330 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
331 ir_node *pred = get_Proj_pred(irn);
333 if(is_ia32_irn(pred)) {
334 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
340 if (is_ia32_irn(irn)) {
341 flags |= get_ia32_flags(irn);
348 * The IA32 ABI callback object.
351 be_abi_call_flags_bits_t flags; /**< The call flags. */
352 const arch_env_t *aenv; /**< The architecture environment. */
353 ir_graph *irg; /**< The associated graph. */
356 static ir_entity *ia32_get_frame_entity(const ir_node *irn) {
357 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
360 static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) {
361 set_ia32_frame_ent(irn, ent);
364 static void ia32_set_frame_offset(ir_node *irn, int bias)
366 if (get_ia32_frame_ent(irn) == NULL)
369 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
370 ia32_code_gen_t *cg = ia32_current_cg;
371 int omit_fp = be_abi_omit_fp(cg->birg->abi);
373 /* Pop nodes modify the stack pointer before calculating the
374 * destination address, so fix this here
379 add_ia32_am_offs_int(irn, bias);
382 static int ia32_get_sp_bias(const ir_node *node)
384 if (is_ia32_Call(node))
385 return -(int)get_ia32_call_attr_const(node)->pop;
387 if (is_ia32_Push(node))
390 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
397 * Generate the routine prologue.
399 * @param self The callback object.
400 * @param mem A pointer to the mem node. Update this if you define new memory.
401 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
402 * @param stack_bias Points to the current stack bias, can be modified if needed.
404 * @return The register which shall be used as a stack frame base.
406 * All nodes which define registers in @p reg_map must keep @p reg_map current.
408 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
410 ia32_abi_env_t *env = self;
411 ia32_code_gen_t *cg = ia32_current_cg;
412 const arch_env_t *arch_env = env->aenv;
414 if (! env->flags.try_omit_fp) {
415 ir_graph *irg =env->irg;
416 ir_node *bl = get_irg_start_block(irg);
417 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
418 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
419 ir_node *noreg = ia32_new_NoReg_gp(cg);
422 /* ALL nodes representing bp must be set to ignore. */
423 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
426 push = new_rd_ia32_Push(NULL, irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
427 curr_sp = new_r_Proj(irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
428 *mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M);
430 /* the push must have SP out register */
431 arch_set_irn_register(curr_sp, arch_env->sp);
432 set_ia32_flags(push, arch_irn_flags_ignore);
434 /* this modifies the stack bias, because we pushed 32bit */
437 /* move esp to ebp */
438 curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp);
439 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp);
440 arch_set_irn_register(curr_bp, arch_env->bp);
441 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
443 /* beware: the copy must be done before any other sp use */
444 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
445 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), arch_env->sp);
446 arch_set_irn_register(curr_sp, arch_env->sp);
447 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
449 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
450 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
459 * Generate the routine epilogue.
460 * @param self The callback object.
461 * @param bl The block for the epilog
462 * @param mem A pointer to the mem node. Update this if you define new memory.
463 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
464 * @return The register which shall be used as a stack frame base.
466 * All nodes which define registers in @p reg_map must keep @p reg_map current.
468 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
470 ia32_abi_env_t *env = self;
471 const arch_env_t *arch_env = env->aenv;
472 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
473 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
474 ir_graph *irg = env->irg;
476 if (env->flags.try_omit_fp) {
477 /* simply remove the stack frame here */
478 curr_sp = be_new_IncSP(arch_env->sp, irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
480 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
482 if (ia32_cg_config.use_leave) {
486 leave = new_rd_ia32_Leave(NULL, irg, bl, curr_bp);
487 set_ia32_flags(leave, arch_irn_flags_ignore);
488 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
489 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
493 /* the old SP is not needed anymore (kill the proj) */
494 assert(is_Proj(curr_sp));
497 /* copy ebp to esp */
498 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
499 arch_set_irn_register(curr_sp, arch_env->sp);
500 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
503 pop = new_rd_ia32_Pop(NULL, env->irg, bl, *mem, curr_sp);
504 set_ia32_flags(pop, arch_irn_flags_ignore);
505 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
506 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
508 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
510 arch_set_irn_register(curr_sp, arch_env->sp);
511 arch_set_irn_register(curr_bp, arch_env->bp);
514 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
515 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
519 * Initialize the callback object.
520 * @param call The call object.
521 * @param aenv The architecture environment.
522 * @param irg The graph with the method.
523 * @return Some pointer. This pointer is passed to all other callback functions as self object.
525 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
527 ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
528 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
529 env->flags = fl.bits;
536 * Destroy the callback object.
537 * @param self The callback object.
539 static void ia32_abi_done(void *self) {
544 * Produces the type which sits between the stack args and the locals on the stack.
545 * it will contain the return address and space to store the old base pointer.
546 * @return The Firm type modeling the ABI between type.
548 static ir_type *ia32_abi_get_between_type(void *self)
550 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
551 static ir_type *omit_fp_between_type = NULL;
552 static ir_type *between_type = NULL;
554 ia32_abi_env_t *env = self;
556 if (! between_type) {
557 ir_entity *old_bp_ent;
558 ir_entity *ret_addr_ent;
559 ir_entity *omit_fp_ret_addr_ent;
561 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
562 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
564 between_type = new_type_struct(IDENT("ia32_between_type"));
565 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
566 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
568 set_entity_offset(old_bp_ent, 0);
569 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
570 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
571 set_type_state(between_type, layout_fixed);
573 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
574 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
576 set_entity_offset(omit_fp_ret_addr_ent, 0);
577 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
578 set_type_state(omit_fp_between_type, layout_fixed);
581 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
586 * Get the estimated cycle count for @p irn.
588 * @param self The this pointer.
589 * @param irn The node.
591 * @return The estimated cycle count for this operation
593 static int ia32_get_op_estimated_cost(const ir_node *irn)
596 ia32_op_type_t op_tp;
600 if (!is_ia32_irn(irn))
603 assert(is_ia32_irn(irn));
605 cost = get_ia32_latency(irn);
606 op_tp = get_ia32_op_type(irn);
608 if (is_ia32_CopyB(irn)) {
611 else if (is_ia32_CopyB_i(irn)) {
612 int size = get_ia32_copyb_size(irn);
613 cost = 20 + (int)ceil((4/3) * size);
615 /* in case of address mode operations add additional cycles */
616 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
618 In case of stack access and access to fixed addresses add 5 cycles
619 (we assume they are in cache), other memory operations cost 20
622 if (is_ia32_use_frame(irn) || (
623 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
624 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
636 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
638 * @param irn The original operation
639 * @param i Index of the argument we want the inverse operation to yield
640 * @param inverse struct to be filled with the resulting inverse op
641 * @param obstack The obstack to use for allocation of the returned nodes array
642 * @return The inverse operation or NULL if operation invertible
644 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
648 ir_node *block, *noreg, *nomem;
651 /* we cannot invert non-ia32 irns */
652 if (! is_ia32_irn(irn))
655 /* operand must always be a real operand (not base, index or mem) */
656 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
659 /* we don't invert address mode operations */
660 if (get_ia32_op_type(irn) != ia32_Normal)
663 /* TODO: adjust for new immediates... */
664 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
668 irg = get_irn_irg(irn);
669 block = get_nodes_block(irn);
670 mode = get_irn_mode(irn);
671 irn_mode = get_irn_mode(irn);
672 noreg = get_irn_n(irn, 0);
673 nomem = new_r_NoMem(irg);
674 dbg = get_irn_dbg_info(irn);
676 /* initialize structure */
677 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
681 switch (get_ia32_irn_opcode(irn)) {
684 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
685 /* we have an add with a const here */
686 /* invers == add with negated const */
687 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
689 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
690 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
691 set_ia32_commutative(inverse->nodes[0]);
693 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
694 /* we have an add with a symconst here */
695 /* invers == sub with const */
696 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
698 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
701 /* normal add: inverse == sub */
702 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
709 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
710 /* we have a sub with a const/symconst here */
711 /* invers == add with this const */
712 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
713 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
714 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
718 if (i == n_ia32_binary_left) {
719 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
722 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
730 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
731 /* xor with const: inverse = xor */
732 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
733 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
734 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
738 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
744 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
749 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
754 /* inverse operation not supported */
761 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
763 if(mode_is_float(mode))
770 * Get the mode that should be used for spilling value node
772 static ir_mode *get_spill_mode(const ir_node *node)
774 ir_mode *mode = get_irn_mode(node);
775 return get_spill_mode_mode(mode);
779 * Checks whether an addressmode reload for a node with mode mode is compatible
780 * with a spillslot of mode spill_mode
782 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
784 return !mode_is_float(mode) || mode == spillmode;
788 * Check if irn can load its operand at position i from memory (source addressmode).
789 * @param irn The irn to be checked
790 * @param i The operands position
791 * @return Non-Zero if operand can be loaded
793 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
795 ir_node *op = get_irn_n(irn, i);
796 const ir_mode *mode = get_irn_mode(op);
797 const ir_mode *spillmode = get_spill_mode(op);
799 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
800 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
801 !ia32_is_spillmode_compatible(mode, spillmode) ||
802 is_ia32_use_frame(irn)) /* must not already use frame */
805 switch (get_ia32_am_support(irn)) {
810 if (i != n_ia32_unary_op)
816 case n_ia32_binary_left: {
817 const arch_register_req_t *req;
818 if (!is_ia32_commutative(irn))
821 /* we can't swap left/right for limited registers
822 * (As this (currently) breaks constraint handling copies)
824 req = get_ia32_in_req(irn, n_ia32_binary_left);
825 if (req->type & arch_register_req_type_limited)
830 case n_ia32_binary_right:
839 panic("Unknown AM type");
842 /* HACK: must not already use "real" memory.
843 * This can happen for Call and Div */
844 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
850 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
854 ir_mode *dest_op_mode;
856 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
858 set_ia32_op_type(irn, ia32_AddrModeS);
860 load_mode = get_irn_mode(get_irn_n(irn, i));
861 dest_op_mode = get_ia32_ls_mode(irn);
862 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
863 set_ia32_ls_mode(irn, load_mode);
865 set_ia32_use_frame(irn);
866 set_ia32_need_stackent(irn);
868 if (i == n_ia32_binary_left &&
869 get_ia32_am_support(irn) == ia32_am_binary &&
870 /* immediates are only allowed on the right side */
871 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
872 ia32_swap_left_right(irn);
873 i = n_ia32_binary_right;
876 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
878 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
879 set_irn_n(irn, n_ia32_mem, spill);
880 set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i));
881 set_ia32_is_reload(irn);
884 static const be_abi_callbacks_t ia32_abi_callbacks = {
887 ia32_abi_get_between_type,
892 /* fill register allocator interface */
894 static const arch_irn_ops_t ia32_irn_ops = {
895 ia32_get_irn_reg_req,
900 ia32_get_frame_entity,
901 ia32_set_frame_entity,
902 ia32_set_frame_offset,
905 ia32_get_op_estimated_cost,
906 ia32_possible_memory_operand,
907 ia32_perform_memory_operand,
910 /**************************************************
913 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
914 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
915 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
916 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
919 **************************************************/
921 static ir_entity *mcount = NULL;
923 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
925 static void ia32_before_abi(void *self) {
926 lower_mode_b_config_t lower_mode_b_config = {
927 mode_Iu, /* lowered mode */
928 mode_Bu, /* preferred mode for set */
929 0, /* don't lower direct compares */
931 ia32_code_gen_t *cg = self;
933 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
935 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
937 if (mcount == NULL) {
938 ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
939 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
940 /* FIXME: enter the right ld_ident here */
941 set_entity_ld_ident(mcount, get_entity_ident(mcount));
942 set_entity_visibility(mcount, visibility_external_allocated);
944 instrument_initcall(cg->irg, mcount);
949 * Transforms the standard firm graph into
952 static void ia32_prepare_graph(void *self) {
953 ia32_code_gen_t *cg = self;
955 /* do local optimizations */
956 optimize_graph_df(cg->irg);
958 /* TODO: we often have dead code reachable through out-edges here. So for
959 * now we rebuild edges (as we need correct user count for code selection)
962 edges_deactivate(cg->irg);
963 edges_activate(cg->irg);
967 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
969 switch (be_transformer) {
970 case TRANSFORMER_DEFAULT:
971 /* transform remaining nodes into assembler instructions */
972 ia32_transform_graph(cg);
976 case TRANSFORMER_PBQP:
977 case TRANSFORMER_RAND:
978 /* transform nodes into assembler instructions by PBQP magic */
979 ia32_transform_graph_by_pbqp(cg);
984 panic("invalid transformer");
987 /* do local optimizations (mainly CSE) */
988 optimize_graph_df(cg->irg);
991 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
993 /* optimize address mode */
994 ia32_optimize_graph(cg);
996 /* do code placement, to optimize the position of constants */
1000 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
1003 ir_node *turn_back_am(ir_node *node)
1005 ir_graph *irg = current_ir_graph;
1006 dbg_info *dbgi = get_irn_dbg_info(node);
1007 ir_node *block = get_nodes_block(node);
1008 ir_node *base = get_irn_n(node, n_ia32_base);
1009 ir_node *index = get_irn_n(node, n_ia32_index);
1010 ir_node *mem = get_irn_n(node, n_ia32_mem);
1013 ir_node *load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1014 ir_node *load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1016 ia32_copy_am_attrs(load, node);
1017 if (is_ia32_is_reload(node))
1018 set_ia32_is_reload(load);
1019 set_irn_n(node, n_ia32_mem, new_NoMem());
1021 switch (get_ia32_am_support(node)) {
1023 set_irn_n(node, n_ia32_unary_op, load_res);
1026 case ia32_am_binary:
1027 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
1028 set_irn_n(node, n_ia32_binary_left, load_res);
1030 set_irn_n(node, n_ia32_binary_right, load_res);
1035 panic("Unknown AM type");
1037 noreg = ia32_new_NoReg_gp(ia32_current_cg);
1038 set_irn_n(node, n_ia32_base, noreg);
1039 set_irn_n(node, n_ia32_index, noreg);
1040 set_ia32_am_offs_int(node, 0);
1041 set_ia32_am_sc(node, NULL);
1042 set_ia32_am_scale(node, 0);
1043 clear_ia32_am_sc_sign(node);
1045 /* rewire mem-proj */
1046 if (get_irn_mode(node) == mode_T) {
1047 const ir_edge_t *edge;
1048 foreach_out_edge(node, edge) {
1049 ir_node *out = get_edge_src_irn(edge);
1050 if (get_irn_mode(out) == mode_M) {
1051 set_Proj_pred(out, load);
1052 set_Proj_proj(out, pn_ia32_Load_M);
1058 set_ia32_op_type(node, ia32_Normal);
1059 if (sched_is_scheduled(node))
1060 sched_add_before(node, load);
1065 static ir_node *flags_remat(ir_node *node, ir_node *after)
1067 /* we should turn back source address mode when rematerializing nodes */
1068 ia32_op_type_t type;
1072 if (is_Block(after)) {
1075 block = get_nodes_block(after);
1078 type = get_ia32_op_type(node);
1080 case ia32_AddrModeS:
1084 case ia32_AddrModeD:
1085 /* TODO implement this later... */
1086 panic("found DestAM with flag user %+F this should not happen", node);
1089 default: assert(type == ia32_Normal); break;
1092 copy = exact_copy(node);
1093 set_nodes_block(copy, block);
1094 sched_add_after(after, copy);
1100 * Called before the register allocator.
1102 static void ia32_before_ra(void *self) {
1103 ia32_code_gen_t *cg = self;
1105 /* setup fpu rounding modes */
1106 ia32_setup_fpu_mode(cg);
1109 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1112 ia32_add_missing_keeps(cg);
1117 * Transforms a be_Reload into a ia32 Load.
1119 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1120 ir_graph *irg = get_irn_irg(node);
1121 dbg_info *dbg = get_irn_dbg_info(node);
1122 ir_node *block = get_nodes_block(node);
1123 ir_entity *ent = be_get_frame_entity(node);
1124 ir_mode *mode = get_irn_mode(node);
1125 ir_mode *spillmode = get_spill_mode(node);
1126 ir_node *noreg = ia32_new_NoReg_gp(cg);
1127 ir_node *sched_point = NULL;
1128 ir_node *ptr = get_irg_frame(irg);
1129 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1130 ir_node *new_op, *proj;
1131 const arch_register_t *reg;
1133 if (sched_is_scheduled(node)) {
1134 sched_point = sched_prev(node);
1137 if (mode_is_float(spillmode)) {
1138 if (ia32_cg_config.use_sse2)
1139 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
1141 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
1143 else if (get_mode_size_bits(spillmode) == 128) {
1144 /* Reload 128 bit SSE registers */
1145 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1148 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1150 set_ia32_op_type(new_op, ia32_AddrModeS);
1151 set_ia32_ls_mode(new_op, spillmode);
1152 set_ia32_frame_ent(new_op, ent);
1153 set_ia32_use_frame(new_op);
1154 set_ia32_is_reload(new_op);
1156 DBG_OPT_RELOAD2LD(node, new_op);
1158 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1161 sched_add_after(sched_point, new_op);
1165 /* copy the register from the old node to the new Load */
1166 reg = arch_get_irn_register(node);
1167 arch_set_irn_register(new_op, reg);
1169 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1171 exchange(node, proj);
1175 * Transforms a be_Spill node into a ia32 Store.
1177 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1178 ir_graph *irg = get_irn_irg(node);
1179 dbg_info *dbg = get_irn_dbg_info(node);
1180 ir_node *block = get_nodes_block(node);
1181 ir_entity *ent = be_get_frame_entity(node);
1182 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1183 ir_mode *mode = get_spill_mode(spillval);
1184 ir_node *noreg = ia32_new_NoReg_gp(cg);
1185 ir_node *nomem = new_rd_NoMem(irg);
1186 ir_node *ptr = get_irg_frame(irg);
1187 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1189 ir_node *sched_point = NULL;
1191 if (sched_is_scheduled(node)) {
1192 sched_point = sched_prev(node);
1195 /* No need to spill unknown values... */
1196 if(is_ia32_Unknown_GP(val) ||
1197 is_ia32_Unknown_VFP(val) ||
1198 is_ia32_Unknown_XMM(val)) {
1203 exchange(node, store);
1207 if (mode_is_float(mode)) {
1208 if (ia32_cg_config.use_sse2)
1209 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
1211 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
1212 } else if (get_mode_size_bits(mode) == 128) {
1213 /* Spill 128 bit SSE registers */
1214 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
1215 } else if (get_mode_size_bits(mode) == 8) {
1216 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
1218 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
1221 set_ia32_op_type(store, ia32_AddrModeD);
1222 set_ia32_ls_mode(store, mode);
1223 set_ia32_frame_ent(store, ent);
1224 set_ia32_use_frame(store);
1225 set_ia32_is_spill(store);
1226 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1227 DBG_OPT_SPILL2ST(node, store);
1230 sched_add_after(sched_point, store);
1234 exchange(node, store);
1237 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1238 ir_graph *irg = get_irn_irg(node);
1239 dbg_info *dbg = get_irn_dbg_info(node);
1240 ir_node *block = get_nodes_block(node);
1241 ir_node *noreg = ia32_new_NoReg_gp(cg);
1242 ir_node *frame = get_irg_frame(irg);
1244 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
1246 set_ia32_frame_ent(push, ent);
1247 set_ia32_use_frame(push);
1248 set_ia32_op_type(push, ia32_AddrModeS);
1249 set_ia32_ls_mode(push, mode_Is);
1250 set_ia32_is_spill(push);
1252 sched_add_before(schedpoint, push);
1256 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1257 ir_graph *irg = get_irn_irg(node);
1258 dbg_info *dbg = get_irn_dbg_info(node);
1259 ir_node *block = get_nodes_block(node);
1260 ir_node *noreg = ia32_new_NoReg_gp(cg);
1261 ir_node *frame = get_irg_frame(irg);
1263 ir_node *pop = new_rd_ia32_PopMem(dbg, irg, block, frame, noreg, new_NoMem(), sp);
1265 set_ia32_frame_ent(pop, ent);
1266 set_ia32_use_frame(pop);
1267 set_ia32_op_type(pop, ia32_AddrModeD);
1268 set_ia32_ls_mode(pop, mode_Is);
1269 set_ia32_is_reload(pop);
1271 sched_add_before(schedpoint, pop);
1276 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1278 ir_graph *irg = get_irn_irg(node);
1279 dbg_info *dbg = get_irn_dbg_info(node);
1280 ir_node *block = get_nodes_block(node);
1281 ir_mode *spmode = mode_Iu;
1282 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1285 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1286 arch_set_irn_register(sp, spreg);
1292 * Transform MemPerm, currently we do this the ugly way and produce
1293 * push/pop into/from memory cascades. This is possible without using
1296 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
1298 ir_graph *irg = get_irn_irg(node);
1299 ir_node *block = get_nodes_block(node);
1300 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1301 int arity = be_get_MemPerm_entity_arity(node);
1302 ir_node **pops = ALLOCAN(ir_node*, arity);
1306 const ir_edge_t *edge;
1307 const ir_edge_t *next;
1310 for(i = 0; i < arity; ++i) {
1311 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1312 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1313 ir_type *enttype = get_entity_type(inent);
1314 unsigned entsize = get_type_size_bytes(enttype);
1315 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1316 ir_node *mem = get_irn_n(node, i + 1);
1319 /* work around cases where entities have different sizes */
1320 if(entsize2 < entsize)
1322 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1324 push = create_push(cg, node, node, sp, mem, inent);
1325 sp = create_spproj(node, push, pn_ia32_Push_stack);
1327 /* add another push after the first one */
1328 push = create_push(cg, node, node, sp, mem, inent);
1329 add_ia32_am_offs_int(push, 4);
1330 sp = create_spproj(node, push, pn_ia32_Push_stack);
1333 set_irn_n(node, i, new_Bad());
1337 for(i = arity - 1; i >= 0; --i) {
1338 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1339 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1340 ir_type *enttype = get_entity_type(outent);
1341 unsigned entsize = get_type_size_bytes(enttype);
1342 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1345 /* work around cases where entities have different sizes */
1346 if(entsize2 < entsize)
1348 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1350 pop = create_pop(cg, node, node, sp, outent);
1351 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1353 add_ia32_am_offs_int(pop, 4);
1355 /* add another pop after the first one */
1356 pop = create_pop(cg, node, node, sp, outent);
1357 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1364 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1365 sched_add_before(node, keep);
1367 /* exchange memprojs */
1368 foreach_out_edge_safe(node, edge, next) {
1369 ir_node *proj = get_edge_src_irn(edge);
1370 int p = get_Proj_proj(proj);
1374 set_Proj_pred(proj, pops[p]);
1375 set_Proj_proj(proj, pn_ia32_Pop_M);
1378 /* remove memperm */
1379 arity = get_irn_arity(node);
1380 for(i = 0; i < arity; ++i) {
1381 set_irn_n(node, i, new_Bad());
1387 * Block-Walker: Calls the transform functions Spill and Reload.
1389 static void ia32_after_ra_walker(ir_node *block, void *env) {
1390 ir_node *node, *prev;
1391 ia32_code_gen_t *cg = env;
1393 /* beware: the schedule is changed here */
1394 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1395 prev = sched_prev(node);
1397 if (be_is_Reload(node)) {
1398 transform_to_Load(cg, node);
1399 } else if (be_is_Spill(node)) {
1400 transform_to_Store(cg, node);
1401 } else if (be_is_MemPerm(node)) {
1402 transform_MemPerm(cg, node);
1408 * Collects nodes that need frame entities assigned.
1410 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1412 be_fec_env_t *env = data;
1413 const ir_mode *mode;
1416 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1417 mode = get_spill_mode_mode(get_irn_mode(node));
1418 align = get_mode_size_bytes(mode);
1419 } else if (is_ia32_irn(node) &&
1420 get_ia32_frame_ent(node) == NULL &&
1421 is_ia32_use_frame(node)) {
1422 if (is_ia32_need_stackent(node))
1425 switch (get_ia32_irn_opcode(node)) {
1427 case iro_ia32_Load: {
1428 const ia32_attr_t *attr = get_ia32_attr_const(node);
1430 if (attr->data.need_32bit_stackent) {
1432 } else if (attr->data.need_64bit_stackent) {
1435 mode = get_ia32_ls_mode(node);
1436 if (is_ia32_is_reload(node))
1437 mode = get_spill_mode_mode(mode);
1439 align = get_mode_size_bytes(mode);
1443 case iro_ia32_vfild:
1445 case iro_ia32_xLoad: {
1446 mode = get_ia32_ls_mode(node);
1451 case iro_ia32_FldCW: {
1452 /* although 2 byte would be enough 4 byte performs best */
1460 panic("unexpected frame user while collection frame entity nodes");
1462 case iro_ia32_FnstCW:
1463 case iro_ia32_Store8Bit:
1464 case iro_ia32_Store:
1467 case iro_ia32_vfist:
1468 case iro_ia32_vfisttp:
1470 case iro_ia32_xStore:
1471 case iro_ia32_xStoreSimple:
1478 be_node_needs_frame_entity(env, node, mode, align);
1482 * We transform Spill and Reload here. This needs to be done before
1483 * stack biasing otherwise we would miss the corrected offset for these nodes.
1485 static void ia32_after_ra(void *self) {
1486 ia32_code_gen_t *cg = self;
1487 ir_graph *irg = cg->irg;
1488 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1490 /* create and coalesce frame entities */
1491 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1492 be_assign_entities(fec_env);
1493 be_free_frame_entity_coalescer(fec_env);
1495 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1499 * Last touchups for the graph before emit: x87 simulation to replace the
1500 * virtual with real x87 instructions, creating a block schedule and peephole
1503 static void ia32_finish(void *self) {
1504 ia32_code_gen_t *cg = self;
1505 ir_graph *irg = cg->irg;
1507 ia32_finish_irg(irg, cg);
1509 /* we might have to rewrite x87 virtual registers */
1510 if (cg->do_x87_sim) {
1511 x87_simulate_graph(cg->birg);
1514 /* do peephole optimisations */
1515 ia32_peephole_optimization(cg);
1517 /* create block schedule, this also removes empty blocks which might
1518 * produce critical edges */
1519 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1523 * Emits the code, closes the output file and frees
1524 * the code generator interface.
1526 static void ia32_codegen(void *self) {
1527 ia32_code_gen_t *cg = self;
1528 ir_graph *irg = cg->irg;
1530 ia32_gen_routine(cg, irg);
1534 /* remove it from the isa */
1537 assert(ia32_current_cg == cg);
1538 ia32_current_cg = NULL;
1540 /* de-allocate code generator */
1541 del_set(cg->reg_set);
1546 * Returns the node representing the PIC base.
1548 static ir_node *ia32_get_pic_base(void *self) {
1550 ia32_code_gen_t *cg = self;
1551 ir_node *get_eip = cg->get_eip;
1552 if (get_eip != NULL)
1555 block = get_irg_start_block(cg->irg);
1556 get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block);
1557 cg->get_eip = get_eip;
1559 be_dep_on_frame(get_eip);
1563 static void *ia32_cg_init(be_irg_t *birg);
1565 static const arch_code_generator_if_t ia32_code_gen_if = {
1567 ia32_get_pic_base, /* return node used as base in pic code addresses */
1568 ia32_before_abi, /* before abi introduce hook */
1571 ia32_before_ra, /* before register allocation hook */
1572 ia32_after_ra, /* after register allocation hook */
1573 ia32_finish, /* called before codegen */
1574 ia32_codegen /* emit && done */
1578 * Initializes a IA32 code generator.
1580 static void *ia32_cg_init(be_irg_t *birg) {
1581 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
1582 ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t);
1584 cg->impl = &ia32_code_gen_if;
1585 cg->irg = birg->irg;
1586 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1589 cg->blk_sched = NULL;
1590 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1591 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1594 /* Linux gprof implementation needs base pointer */
1595 birg->main_env->options->omit_fp = 0;
1602 if (isa->name_obst) {
1603 obstack_free(isa->name_obst, NULL);
1604 obstack_init(isa->name_obst);
1608 cur_reg_set = cg->reg_set;
1610 assert(ia32_current_cg == NULL);
1611 ia32_current_cg = cg;
1613 return (arch_code_generator_t *)cg;
1618 /*****************************************************************
1619 * ____ _ _ _____ _____
1620 * | _ \ | | | | |_ _|/ ____| /\
1621 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1622 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1623 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1624 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1626 *****************************************************************/
1629 * Set output modes for GCC
1631 static const tarval_mode_info mo_integer = {
1638 * set the tarval output mode of all integer modes to decimal
1640 static void set_tarval_output_modes(void)
1644 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1645 ir_mode *mode = get_irp_mode(i);
1647 if (mode_is_int(mode))
1648 set_tarval_mode_output_option(mode, &mo_integer);
1652 const arch_isa_if_t ia32_isa_if;
1655 * The template that generates a new ISA object.
1656 * Note that this template can be changed by command line
1659 static ia32_isa_t ia32_isa_template = {
1661 &ia32_isa_if, /* isa interface implementation */
1662 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1663 &ia32_gp_regs[REG_EBP], /* base pointer register */
1664 -1, /* stack direction */
1665 2, /* power of two stack alignment, 2^2 == 4 */
1666 NULL, /* main environment */
1667 7, /* costs for a spill instruction */
1668 5, /* costs for a reload instruction */
1670 NULL, /* 16bit register names */
1671 NULL, /* 8bit register names */
1672 NULL, /* 8bit register names high */
1675 NULL, /* current code generator */
1676 NULL, /* abstract machine */
1678 NULL, /* name obstack */
1682 static void init_asm_constraints(void)
1684 be_init_default_asm_constraint_flags();
1686 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1687 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1688 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1689 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1690 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1691 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1692 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1693 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1694 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1695 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1696 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1697 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1698 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1699 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1700 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1701 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1702 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1703 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1704 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1705 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1707 /* no support for autodecrement/autoincrement */
1708 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1709 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1710 /* no float consts */
1711 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1712 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1713 /* makes no sense on x86 */
1714 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1715 /* no support for sse consts yet */
1716 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1717 /* no support for x87 consts yet */
1718 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1719 /* no support for mmx registers yet */
1720 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1721 /* not available in 32bit mode */
1722 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1723 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1725 /* no code yet to determine register class needed... */
1726 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1730 * Initializes the backend ISA.
1732 static arch_env_t *ia32_init(FILE *file_handle) {
1733 static int inited = 0;
1741 set_tarval_output_modes();
1743 isa = XMALLOC(ia32_isa_t);
1744 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1746 if(mode_fpcw == NULL) {
1747 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1750 ia32_register_init();
1751 ia32_create_opcodes(&ia32_irn_ops);
1753 be_emit_init(file_handle);
1754 isa->regs_16bit = pmap_create();
1755 isa->regs_8bit = pmap_create();
1756 isa->regs_8bit_high = pmap_create();
1757 isa->types = pmap_create();
1758 isa->tv_ent = pmap_create();
1759 isa->cpu = ia32_init_machine_description();
1761 ia32_build_16bit_reg_map(isa->regs_16bit);
1762 ia32_build_8bit_reg_map(isa->regs_8bit);
1763 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1766 isa->name_obst = XMALLOC(struct obstack);
1767 obstack_init(isa->name_obst);
1770 /* enter the ISA object into the intrinsic environment */
1771 intrinsic_env.isa = isa;
1772 ia32_handle_intrinsics();
1774 /* emit asm includes */
1775 n = get_irp_n_asms();
1776 for (i = 0; i < n; ++i) {
1777 be_emit_cstring("#APP\n");
1778 be_emit_ident(get_irp_asm(i));
1779 be_emit_cstring("\n#NO_APP\n");
1782 /* needed for the debug support */
1783 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1784 be_emit_cstring(".Ltext0:\n");
1785 be_emit_write_line();
1787 /* we mark referenced global entities, so we can only emit those which
1788 * are actually referenced. (Note: you mustn't use the type visited flag
1789 * elsewhere in the backend)
1791 inc_master_type_visited();
1793 return &isa->arch_env;
1799 * Closes the output file and frees the ISA structure.
1801 static void ia32_done(void *self) {
1802 ia32_isa_t *isa = self;
1804 /* emit now all global declarations */
1805 be_gas_emit_decls(isa->arch_env.main_env, 1);
1807 pmap_destroy(isa->regs_16bit);
1808 pmap_destroy(isa->regs_8bit);
1809 pmap_destroy(isa->regs_8bit_high);
1810 pmap_destroy(isa->tv_ent);
1811 pmap_destroy(isa->types);
1814 obstack_free(isa->name_obst, NULL);
1824 * Return the number of register classes for this architecture.
1825 * We report always these:
1826 * - the general purpose registers
1827 * - the SSE floating point register set
1828 * - the virtual floating point registers
1829 * - the SSE vector register set
1831 static unsigned ia32_get_n_reg_class(const void *self) {
1837 * Return the register class for index i.
1839 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1843 assert(i < N_CLASSES);
1844 return &ia32_reg_classes[i];
1848 * Get the register class which shall be used to store a value of a given mode.
1849 * @param self The this pointer.
1850 * @param mode The mode in question.
1851 * @return A register class which can hold values of the given mode.
1853 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1854 const ir_mode *mode)
1858 if (mode_is_float(mode)) {
1859 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1862 return &ia32_reg_classes[CLASS_ia32_gp];
1866 * Get the ABI restrictions for procedure calls.
1867 * @param self The this pointer.
1868 * @param method_type The type of the method (procedure) in question.
1869 * @param abi The abi object to be modified
1871 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1879 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1883 /* set abi flags for calls */
1884 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1885 call_flags.bits.store_args_sequential = 0;
1886 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1887 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1888 call_flags.bits.call_has_imm = 0; /* No call immediates, we handle this by ourselves */
1890 /* set parameter passing style */
1891 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1893 if (get_method_variadicity(method_type) == variadicity_variadic) {
1894 /* pass all parameters of a variadic function on the stack */
1897 cc = get_method_calling_convention(method_type);
1898 if (get_method_additional_properties(method_type) & mtp_property_private &&
1899 ia32_cg_config.optimize_cc) {
1900 /* set the calling conventions to register parameter */
1901 cc = (cc & ~cc_bits) | cc_reg_param;
1905 /* we have to pop the shadow parameter ourself for compound calls */
1906 if( (get_method_calling_convention(method_type) & cc_compound_ret)
1907 && !(cc & cc_reg_param)) {
1908 pop_amount += get_mode_size_bytes(mode_P_data);
1911 n = get_method_n_params(method_type);
1912 for (i = regnum = 0; i < n; i++) {
1914 const arch_register_t *reg = NULL;
1916 tp = get_method_param_type(method_type, i);
1917 mode = get_type_mode(tp);
1919 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1922 be_abi_call_param_reg(abi, i, reg);
1925 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1926 * movl has a shorter opcode than mov[sz][bw]l */
1927 ir_mode *load_mode = mode;
1930 unsigned size = get_mode_size_bytes(mode);
1932 if (cc & cc_callee_clear_stk) {
1933 pop_amount += (size + 3U) & ~3U;
1936 if (size < 4) load_mode = mode_Iu;
1939 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1943 be_abi_call_set_pop(abi, pop_amount);
1945 /* set return registers */
1946 n = get_method_n_ress(method_type);
1948 assert(n <= 2 && "more than two results not supported");
1950 /* In case of 64bit returns, we will have two 32bit values */
1952 tp = get_method_res_type(method_type, 0);
1953 mode = get_type_mode(tp);
1955 assert(!mode_is_float(mode) && "two FP results not supported");
1957 tp = get_method_res_type(method_type, 1);
1958 mode = get_type_mode(tp);
1960 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1962 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1963 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1966 const arch_register_t *reg;
1968 tp = get_method_res_type(method_type, 0);
1969 assert(is_atomic_type(tp));
1970 mode = get_type_mode(tp);
1972 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1974 be_abi_call_res_reg(abi, 0, reg);
1978 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1982 if(!is_ia32_irn(irn)) {
1986 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1987 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1988 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1989 || is_ia32_Immediate(irn))
1996 * Initializes the code generator interface.
1998 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
2001 return &ia32_code_gen_if;
2005 * Returns the estimated execution time of an ia32 irn.
2007 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
2009 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
2012 list_sched_selector_t ia32_sched_selector;
2015 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
2017 static const list_sched_selector_t *ia32_get_list_sched_selector(
2018 const void *self, list_sched_selector_t *selector)
2021 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
2022 ia32_sched_selector.exectime = ia32_sched_exectime;
2023 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
2024 return &ia32_sched_selector;
2027 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
2034 * Returns the necessary byte alignment for storing a register of given class.
2036 static int ia32_get_reg_class_alignment(const void *self,
2037 const arch_register_class_t *cls)
2039 ir_mode *mode = arch_register_class_mode(cls);
2040 int bytes = get_mode_size_bytes(mode);
2043 if (mode_is_float(mode) && bytes > 8)
2048 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
2049 const void *self, const ir_node *irn)
2051 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
2052 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
2053 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
2056 static const be_execution_unit_t *_allowed_units_GP[] = {
2057 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
2058 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
2059 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
2060 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
2061 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
2062 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
2063 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2066 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2067 &be_machine_execution_units_DUMMY[0],
2070 static const be_execution_unit_t **_units_callret[] = {
2071 _allowed_units_BRANCH,
2074 static const be_execution_unit_t **_units_other[] = {
2078 static const be_execution_unit_t **_units_dummy[] = {
2079 _allowed_units_DUMMY,
2082 const be_execution_unit_t ***ret;
2085 if (is_ia32_irn(irn)) {
2086 ret = get_ia32_exec_units(irn);
2087 } else if (is_be_node(irn)) {
2088 if (be_is_Return(irn)) {
2089 ret = _units_callret;
2090 } else if (be_is_Barrier(irn)) {
2104 * Return the abstract ia32 machine.
2106 static const be_machine_t *ia32_get_machine(const void *self) {
2107 const ia32_isa_t *isa = self;
2112 * Return irp irgs in the desired order.
2114 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2121 static void ia32_mark_remat(const void *self, ir_node *node) {
2123 if (is_ia32_irn(node)) {
2124 set_ia32_is_remat(node);
2129 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2130 * @return 1 if allowed, 0 otherwise
2132 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2135 ir_node *cmp = NULL;
2137 /* we can't handle psis with 64bit compares yet */
2139 cmp = get_Proj_pred(sel);
2141 ir_node *left = get_Cmp_left(cmp);
2142 ir_mode *cmp_mode = get_irn_mode(left);
2143 if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
2150 if (ia32_cg_config.use_cmov) {
2151 if (ia32_cg_config.use_sse2 && cmp != NULL) {
2152 pn_Cmp pn = get_Proj_proj(sel);
2153 ir_node *cl = get_Cmp_left(cmp);
2154 ir_node *cr = get_Cmp_right(cmp);
2156 /* check the Phi nodes: no 64bit and no floating point cmov */
2157 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2158 ir_mode *mode = get_irn_mode(phi);
2160 if (mode_is_float(mode)) {
2161 /* check for Min, Max */
2162 ir_node *t = get_Phi_pred(phi, i);
2163 ir_node *f = get_Phi_pred(phi, j);
2166 /* SSE2 supports Min & Max */
2167 if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2168 if (cl == t && cr == f) {
2169 /* Psi(a <=/>= b, a, b) => MIN, MAX */
2171 } else if (cl == f && cr == t) {
2172 /* Psi(a <=/>= b, b, a) => MAX, MIN */
2179 } else if (get_mode_size_bits(mode) > 32)
2183 /* check the Phi nodes: no 64bit and no floating point cmov */
2184 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2185 ir_mode *mode = get_irn_mode(phi);
2187 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2197 /* No cmov, only some special cases */
2201 /* Now some supported cases here */
2202 pn = get_Proj_proj(sel);
2203 cl = get_Cmp_left(cmp);
2204 cr = get_Cmp_right(cmp);
2206 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2207 ir_mode *mode = get_irn_mode(phi);
2211 t = get_Phi_pred(phi, i);
2212 f = get_Phi_pred(phi, j);
2214 /* no floating point and no 64bit yet */
2215 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2218 if (is_Const(t) && is_Const(f)) {
2219 if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
2220 /* always support Psi(x, C1, C2) */
2223 } else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2226 } else if (cl == t && cr == f) {
2227 /* Psi(a <=/>= b, a, b) => Min, Max */
2229 } else if (cl == f && cr == t) {
2230 /* Psi(a <=/>= b, b, a) => Max, Min */
2233 } else if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
2234 is_Const(f) && is_Const_null(f) && is_Sub(t) &&
2235 get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
2236 /* Psi(a >=u b, a - b, 0) unsigned Doz */
2238 } else if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
2239 is_Const(t) && is_Const_null(t) && is_Sub(f) &&
2240 get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
2241 /* Psi(a <=u b, 0, a - b) unsigned Doz */
2243 } else if (is_Const(cr) && is_Const_null(cr)) {
2244 if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
2245 /* Psi(a <=/>= 0 ? a : -a) Nabs/Abs */
2247 } else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
2248 /* Psi(a <=/>= 0 ? -a : a) Abs/Nabs */
2256 /* all checks passed */
2262 static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const char **c)
2267 /* we already added all our simple flags to the flags modifier list in
2268 * init, so this flag we don't know. */
2269 return ASM_CONSTRAINT_FLAG_INVALID;
2272 static int ia32_is_valid_clobber(const void *self, const char *clobber)
2276 return ia32_get_clobber_register(clobber) != NULL;
2280 * Returns the libFirm configuration parameter for this backend.
2282 static const backend_params *ia32_get_libfirm_params(void) {
2283 static const ir_settings_if_conv_t ifconv = {
2284 4, /* maxdepth, doesn't matter for Psi-conversion */
2285 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2287 static const ir_settings_arch_dep_t ad = {
2288 1, /* also use subs */
2289 4, /* maximum shifts */
2290 31, /* maximum shift amount */
2291 ia32_evaluate_insn, /* evaluate the instruction sequence */
2293 1, /* allow Mulhs */
2294 1, /* allow Mulus */
2295 32 /* Mulh allowed up to 32 bit */
2297 static backend_params p = {
2298 1, /* need dword lowering */
2299 1, /* support inline assembly */
2300 0, /* no immediate floating point mode. */
2301 NULL, /* no additional opcodes */
2302 NULL, /* will be set later */
2303 ia32_create_intrinsic_fkt,
2304 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2305 NULL, /* will be set below */
2306 NULL /* will be set below */
2309 ia32_setup_cg_config();
2311 /* doesn't really belong here, but this is the earliest place the backend
2313 init_asm_constraints();
2316 p.if_conv_info = &ifconv;
2320 static const lc_opt_enum_int_items_t gas_items[] = {
2321 { "elf", GAS_FLAVOUR_ELF },
2322 { "mingw", GAS_FLAVOUR_MINGW },
2323 { "yasm", GAS_FLAVOUR_YASM },
2324 { "macho", GAS_FLAVOUR_MACH_O },
2328 static lc_opt_enum_int_var_t gas_var = {
2329 (int*) &be_gas_flavour, gas_items
2332 #ifdef FIRM_GRGEN_BE
2333 static const lc_opt_enum_int_items_t transformer_items[] = {
2334 { "default", TRANSFORMER_DEFAULT },
2335 { "pbqp", TRANSFORMER_PBQP },
2336 { "random", TRANSFORMER_RAND },
2340 static lc_opt_enum_int_var_t transformer_var = {
2341 (int*)&be_transformer, transformer_items
2345 static const lc_opt_table_entry_t ia32_options[] = {
2346 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2347 #ifdef FIRM_GRGEN_BE
2348 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2350 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2351 &ia32_isa_template.arch_env.stack_alignment),
2355 const arch_isa_if_t ia32_isa_if = {
2358 ia32_get_n_reg_class,
2360 ia32_get_reg_class_for_mode,
2362 ia32_get_code_generator_if,
2363 ia32_get_list_sched_selector,
2364 ia32_get_ilp_sched_selector,
2365 ia32_get_reg_class_alignment,
2366 ia32_get_libfirm_params,
2367 ia32_get_allowed_execution_units,
2371 ia32_parse_asm_constraint,
2372 ia32_is_valid_clobber
2375 void ia32_init_emitter(void);
2376 void ia32_init_finish(void);
2377 void ia32_init_optimize(void);
2378 void ia32_init_transform(void);
2379 void ia32_init_x87(void);
2381 void be_init_arch_ia32(void)
2383 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2384 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2386 lc_opt_add_table(ia32_grp, ia32_options);
2387 be_register_isa_if("ia32", &ia32_isa_if);
2389 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2391 ia32_init_emitter();
2393 ia32_init_optimize();
2394 ia32_init_transform();
2396 ia32_init_architecture();
2399 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);