2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
55 #include "lower_calls.h"
59 #include "../benode.h"
60 #include "../belower.h"
61 #include "../besched.h"
64 #include "../beirgmod.h"
65 #include "../be_dbgout.h"
66 #include "../beblocksched.h"
67 #include "../bemachine.h"
68 #include "../bespillslots.h"
69 #include "../bemodule.h"
70 #include "../begnuas.h"
71 #include "../bestate.h"
72 #include "../beflags.h"
73 #include "../betranshlp.h"
74 #include "../belistsched.h"
75 #include "../beabihelper.h"
77 #include "bearch_ia32_t.h"
79 #include "ia32_new_nodes.h"
80 #include "gen_ia32_regalloc_if.h"
81 #include "gen_ia32_machine.h"
82 #include "ia32_common_transform.h"
83 #include "ia32_transform.h"
84 #include "ia32_emitter.h"
85 #include "ia32_optimize.h"
87 #include "ia32_dbg_stat.h"
88 #include "ia32_finish.h"
90 #include "ia32_architecture.h"
93 #include "ia32_pbqp_transform.h"
95 transformer_t be_transformer = TRANSFORMER_DEFAULT;
98 ir_mode *ia32_mode_fpcw = NULL;
100 /** The current omit-fp state */
101 static ir_type *omit_fp_between_type = NULL;
102 static ir_type *between_type = NULL;
103 static ir_entity *old_bp_ent = NULL;
104 static ir_entity *ret_addr_ent = NULL;
105 static ir_entity *omit_fp_ret_addr_ent = NULL;
108 * The environment for the intrinsic mapping.
110 static ia32_intrinsic_env_t intrinsic_env = {
112 NULL, /* the irg, these entities belong to */
113 NULL, /* entity for __divdi3 library call */
114 NULL, /* entity for __moddi3 library call */
115 NULL, /* entity for __udivdi3 library call */
116 NULL, /* entity for __umoddi3 library call */
120 typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
123 * Used to create per-graph unique pseudo nodes.
125 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
126 create_const_node_func func,
127 const arch_register_t* reg)
129 ir_node *block, *res;
134 block = get_irg_start_block(irg);
135 res = func(NULL, block);
136 arch_set_irn_register(res, reg);
142 /* Creates the unique per irg GP NoReg node. */
143 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
145 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
146 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
147 &ia32_registers[REG_GP_NOREG]);
150 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
152 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
153 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
154 &ia32_registers[REG_VFP_NOREG]);
157 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
159 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
160 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
161 &ia32_registers[REG_XMM_NOREG]);
164 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
166 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
167 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
168 &ia32_registers[REG_FPCW]);
173 * Returns the admissible noreg register node for input register pos of node irn.
175 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
177 ir_graph *irg = get_irn_irg(irn);
178 const arch_register_req_t *req = arch_get_register_req(irn, pos);
180 assert(req != NULL && "Missing register requirements");
181 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
182 return ia32_new_NoReg_gp(irg);
184 if (ia32_cg_config.use_sse2) {
185 return ia32_new_NoReg_xmm(irg);
187 return ia32_new_NoReg_vfp(irg);
191 static arch_irn_class_t ia32_classify(const ir_node *irn)
193 arch_irn_class_t classification = arch_irn_class_none;
195 assert(is_ia32_irn(irn));
197 if (is_ia32_is_reload(irn))
198 classification |= arch_irn_class_reload;
200 if (is_ia32_is_spill(irn))
201 classification |= arch_irn_class_spill;
203 if (is_ia32_is_remat(irn))
204 classification |= arch_irn_class_remat;
206 return classification;
210 * The IA32 ABI callback object.
213 be_abi_call_flags_bits_t flags; /**< The call flags. */
214 ir_graph *irg; /**< The associated graph. */
217 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
219 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
222 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
224 if (is_be_node(node))
225 be_node_set_frame_entity(node, entity);
227 set_ia32_frame_ent(node, entity);
230 static void ia32_set_frame_offset(ir_node *irn, int bias)
232 if (get_ia32_frame_ent(irn) == NULL)
235 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
236 ir_graph *irg = get_irn_irg(irn);
237 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
238 if (layout->sp_relative) {
239 /* Pop nodes modify the stack pointer before calculating the
240 * destination address, so fix this here
245 add_ia32_am_offs_int(irn, bias);
248 static int ia32_get_sp_bias(const ir_node *node)
250 if (is_ia32_Call(node))
251 return -(int)get_ia32_call_attr_const(node)->pop;
253 if (is_ia32_Push(node))
256 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
259 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
260 return SP_BIAS_RESET;
267 * Build the between type and entities if not already build.
269 static void ia32_build_between_type(void)
271 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
272 if (! between_type) {
273 ir_type *old_bp_type = new_type_primitive(mode_Iu);
274 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
276 between_type = new_type_struct(IDENT("ia32_between_type"));
277 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
278 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
280 set_entity_offset(old_bp_ent, 0);
281 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
282 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
283 set_type_state(between_type, layout_fixed);
285 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
286 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
288 set_entity_offset(omit_fp_ret_addr_ent, 0);
289 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
290 set_type_state(omit_fp_between_type, layout_fixed);
296 * Produces the type which sits between the stack args and the locals on the stack.
297 * it will contain the return address and space to store the old base pointer.
298 * @return The Firm type modeling the ABI between type.
300 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
302 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
303 ia32_build_between_type();
304 return layout->sp_relative ? omit_fp_between_type : between_type;
308 * Return the stack entity that contains the return address.
310 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
312 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
313 ia32_build_between_type();
314 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
318 * Return the stack entity that contains the frame address.
320 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
322 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
323 ia32_build_between_type();
324 return layout->sp_relative ? NULL : old_bp_ent;
328 * Get the estimated cycle count for @p irn.
330 * @param self The this pointer.
331 * @param irn The node.
333 * @return The estimated cycle count for this operation
335 static int ia32_get_op_estimated_cost(const ir_node *irn)
338 ia32_op_type_t op_tp;
342 if (!is_ia32_irn(irn))
345 assert(is_ia32_irn(irn));
347 cost = get_ia32_latency(irn);
348 op_tp = get_ia32_op_type(irn);
350 if (is_ia32_CopyB(irn)) {
353 else if (is_ia32_CopyB_i(irn)) {
354 int size = get_ia32_copyb_size(irn);
355 cost = 20 + (int)ceil((4/3) * size);
357 /* in case of address mode operations add additional cycles */
358 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
360 In case of stack access and access to fixed addresses add 5 cycles
361 (we assume they are in cache), other memory operations cost 20
364 if (is_ia32_use_frame(irn) || (
365 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
366 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
378 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
380 * @param irn The original operation
381 * @param i Index of the argument we want the inverse operation to yield
382 * @param inverse struct to be filled with the resulting inverse op
383 * @param obstack The obstack to use for allocation of the returned nodes array
384 * @return The inverse operation or NULL if operation invertible
386 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
397 ir_node *block, *noreg, *nomem;
400 /* we cannot invert non-ia32 irns */
401 if (! is_ia32_irn(irn))
404 /* operand must always be a real operand (not base, index or mem) */
405 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
408 /* we don't invert address mode operations */
409 if (get_ia32_op_type(irn) != ia32_Normal)
412 /* TODO: adjust for new immediates... */
413 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
417 block = get_nodes_block(irn);
418 mode = get_irn_mode(irn);
419 irn_mode = get_irn_mode(irn);
420 noreg = get_irn_n(irn, 0);
421 nomem = get_irg_no_mem(irg);
422 dbgi = get_irn_dbg_info(irn);
424 /* initialize structure */
425 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
429 switch (get_ia32_irn_opcode(irn)) {
431 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
432 /* we have an add with a const here */
433 /* invers == add with negated const */
434 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
436 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
437 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
438 set_ia32_commutative(inverse->nodes[0]);
440 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
441 /* we have an add with a symconst here */
442 /* invers == sub with const */
443 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
445 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
448 /* normal add: inverse == sub */
449 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
454 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
455 /* we have a sub with a const/symconst here */
456 /* invers == add with this const */
457 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
458 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
459 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
463 if (i == n_ia32_binary_left) {
464 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
467 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
473 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
474 /* xor with const: inverse = xor */
475 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
476 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
477 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
481 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
486 inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
491 inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
496 /* inverse operation not supported */
504 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
506 if (mode_is_float(mode))
513 * Get the mode that should be used for spilling value node
515 static ir_mode *get_spill_mode(const ir_node *node)
517 ir_mode *mode = get_irn_mode(node);
518 return get_spill_mode_mode(mode);
522 * Checks whether an addressmode reload for a node with mode mode is compatible
523 * with a spillslot of mode spill_mode
525 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
527 return !mode_is_float(mode) || mode == spillmode;
531 * Check if irn can load its operand at position i from memory (source addressmode).
532 * @param irn The irn to be checked
533 * @param i The operands position
534 * @return Non-Zero if operand can be loaded
536 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
538 ir_node *op = get_irn_n(irn, i);
539 const ir_mode *mode = get_irn_mode(op);
540 const ir_mode *spillmode = get_spill_mode(op);
542 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
543 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
544 !ia32_is_spillmode_compatible(mode, spillmode) ||
545 is_ia32_use_frame(irn)) /* must not already use frame */
548 switch (get_ia32_am_support(irn)) {
553 if (i != n_ia32_unary_op)
559 case n_ia32_binary_left: {
560 const arch_register_req_t *req;
561 if (!is_ia32_commutative(irn))
564 /* we can't swap left/right for limited registers
565 * (As this (currently) breaks constraint handling copies)
567 req = arch_get_in_register_req(irn, n_ia32_binary_left);
568 if (req->type & arch_register_req_type_limited)
573 case n_ia32_binary_right:
582 panic("Unknown AM type");
585 /* HACK: must not already use "real" memory.
586 * This can happen for Call and Div */
587 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
593 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
597 ir_mode *dest_op_mode;
599 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
601 set_ia32_op_type(irn, ia32_AddrModeS);
603 load_mode = get_irn_mode(get_irn_n(irn, i));
604 dest_op_mode = get_ia32_ls_mode(irn);
605 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
606 set_ia32_ls_mode(irn, load_mode);
608 set_ia32_use_frame(irn);
609 set_ia32_need_stackent(irn);
611 if (i == n_ia32_binary_left &&
612 get_ia32_am_support(irn) == ia32_am_binary &&
613 /* immediates are only allowed on the right side */
614 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
615 ia32_swap_left_right(irn);
616 i = n_ia32_binary_right;
619 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
621 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
622 set_irn_n(irn, n_ia32_mem, spill);
623 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
624 set_ia32_is_reload(irn);
627 static const be_abi_callbacks_t ia32_abi_callbacks = {
628 ia32_abi_get_between_type,
631 /* register allocator interface */
632 static const arch_irn_ops_t ia32_irn_ops = {
634 ia32_get_frame_entity,
635 ia32_set_frame_offset,
638 ia32_get_op_estimated_cost,
639 ia32_possible_memory_operand,
640 ia32_perform_memory_operand,
643 static ir_entity *mcount = NULL;
644 static int gprof = 0;
646 static void ia32_before_abi(ir_graph *irg)
649 if (mcount == NULL) {
650 ir_type *tp = new_type_method(0, 0);
651 ident *id = new_id_from_str("mcount");
652 mcount = new_entity(get_glob_type(), id, tp);
653 /* FIXME: enter the right ld_ident here */
654 set_entity_ld_ident(mcount, get_entity_ident(mcount));
655 set_entity_visibility(mcount, ir_visibility_external);
657 instrument_initcall(irg, mcount);
662 * Transforms the standard firm graph into
665 static void ia32_prepare_graph(ir_graph *irg)
667 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
670 switch (be_transformer) {
671 case TRANSFORMER_DEFAULT:
672 /* transform remaining nodes into assembler instructions */
673 ia32_transform_graph(irg);
676 case TRANSFORMER_PBQP:
677 case TRANSFORMER_RAND:
678 /* transform nodes into assembler instructions by PBQP magic */
679 ia32_transform_graph_by_pbqp(irg);
683 panic("invalid transformer");
686 ia32_transform_graph(irg);
689 /* do local optimizations (mainly CSE) */
690 optimize_graph_df(irg);
693 dump_ir_graph(irg, "transformed");
695 /* optimize address mode */
696 ia32_optimize_graph(irg);
698 /* do code placement, to optimize the position of constants */
702 dump_ir_graph(irg, "place");
705 ir_node *ia32_turn_back_am(ir_node *node)
707 dbg_info *dbgi = get_irn_dbg_info(node);
708 ir_graph *irg = get_irn_irg(node);
709 ir_node *block = get_nodes_block(node);
710 ir_node *base = get_irn_n(node, n_ia32_base);
711 ir_node *idx = get_irn_n(node, n_ia32_index);
712 ir_node *mem = get_irn_n(node, n_ia32_mem);
715 ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
716 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
718 ia32_copy_am_attrs(load, node);
719 if (is_ia32_is_reload(node))
720 set_ia32_is_reload(load);
721 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
723 switch (get_ia32_am_support(node)) {
725 set_irn_n(node, n_ia32_unary_op, load_res);
729 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
730 set_irn_n(node, n_ia32_binary_left, load_res);
732 set_irn_n(node, n_ia32_binary_right, load_res);
737 panic("Unknown AM type");
739 noreg = ia32_new_NoReg_gp(current_ir_graph);
740 set_irn_n(node, n_ia32_base, noreg);
741 set_irn_n(node, n_ia32_index, noreg);
742 set_ia32_am_offs_int(node, 0);
743 set_ia32_am_sc(node, NULL);
744 set_ia32_am_scale(node, 0);
745 clear_ia32_am_sc_sign(node);
747 /* rewire mem-proj */
748 if (get_irn_mode(node) == mode_T) {
749 const ir_edge_t *edge;
750 foreach_out_edge(node, edge) {
751 ir_node *out = get_edge_src_irn(edge);
752 if (get_irn_mode(out) == mode_M) {
753 set_Proj_pred(out, load);
754 set_Proj_proj(out, pn_ia32_Load_M);
760 set_ia32_op_type(node, ia32_Normal);
761 if (sched_is_scheduled(node))
762 sched_add_before(node, load);
767 static ir_node *flags_remat(ir_node *node, ir_node *after)
769 /* we should turn back source address mode when rematerializing nodes */
774 if (is_Block(after)) {
777 block = get_nodes_block(after);
780 type = get_ia32_op_type(node);
783 ia32_turn_back_am(node);
787 /* TODO implement this later... */
788 panic("found DestAM with flag user %+F this should not happen", node);
790 default: assert(type == ia32_Normal); break;
793 copy = exact_copy(node);
794 set_nodes_block(copy, block);
795 sched_add_after(after, copy);
801 * Called before the register allocator.
803 static void ia32_before_ra(ir_graph *irg)
805 /* setup fpu rounding modes */
806 ia32_setup_fpu_mode(irg);
809 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
812 be_add_missing_keeps(irg);
817 * Transforms a be_Reload into a ia32 Load.
819 static void transform_to_Load(ir_node *node)
821 ir_graph *irg = get_irn_irg(node);
822 dbg_info *dbgi = get_irn_dbg_info(node);
823 ir_node *block = get_nodes_block(node);
824 ir_entity *ent = be_get_frame_entity(node);
825 ir_mode *mode = get_irn_mode(node);
826 ir_mode *spillmode = get_spill_mode(node);
827 ir_node *noreg = ia32_new_NoReg_gp(irg);
828 ir_node *sched_point = NULL;
829 ir_node *ptr = get_irg_frame(irg);
830 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
831 ir_node *new_op, *proj;
832 const arch_register_t *reg;
834 if (sched_is_scheduled(node)) {
835 sched_point = sched_prev(node);
838 if (mode_is_float(spillmode)) {
839 if (ia32_cg_config.use_sse2)
840 new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
842 new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
844 else if (get_mode_size_bits(spillmode) == 128) {
845 /* Reload 128 bit SSE registers */
846 new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
849 new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
851 set_ia32_op_type(new_op, ia32_AddrModeS);
852 set_ia32_ls_mode(new_op, spillmode);
853 set_ia32_frame_ent(new_op, ent);
854 set_ia32_use_frame(new_op);
855 set_ia32_is_reload(new_op);
857 DBG_OPT_RELOAD2LD(node, new_op);
859 proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
862 sched_add_after(sched_point, new_op);
866 /* copy the register from the old node to the new Load */
867 reg = arch_get_irn_register(node);
868 arch_set_irn_register(proj, reg);
870 SET_IA32_ORIG_NODE(new_op, node);
872 exchange(node, proj);
876 * Transforms a be_Spill node into a ia32 Store.
878 static void transform_to_Store(ir_node *node)
880 ir_graph *irg = get_irn_irg(node);
881 dbg_info *dbgi = get_irn_dbg_info(node);
882 ir_node *block = get_nodes_block(node);
883 ir_entity *ent = be_get_frame_entity(node);
884 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
885 ir_mode *mode = get_spill_mode(spillval);
886 ir_node *noreg = ia32_new_NoReg_gp(irg);
887 ir_node *nomem = get_irg_no_mem(irg);
888 ir_node *ptr = get_irg_frame(irg);
889 ir_node *val = get_irn_n(node, n_be_Spill_val);
892 ir_node *sched_point = NULL;
894 if (sched_is_scheduled(node)) {
895 sched_point = sched_prev(node);
898 if (mode_is_float(mode)) {
899 if (ia32_cg_config.use_sse2) {
900 store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
901 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
903 store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
904 res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
906 } else if (get_mode_size_bits(mode) == 128) {
907 /* Spill 128 bit SSE registers */
908 store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
909 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
910 } else if (get_mode_size_bits(mode) == 8) {
911 store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
912 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
914 store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
915 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
918 set_ia32_op_type(store, ia32_AddrModeD);
919 set_ia32_ls_mode(store, mode);
920 set_ia32_frame_ent(store, ent);
921 set_ia32_use_frame(store);
922 set_ia32_is_spill(store);
923 SET_IA32_ORIG_NODE(store, node);
924 DBG_OPT_SPILL2ST(node, store);
927 sched_add_after(sched_point, store);
934 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
936 dbg_info *dbgi = get_irn_dbg_info(node);
937 ir_node *block = get_nodes_block(node);
938 ir_graph *irg = get_irn_irg(node);
939 ir_node *noreg = ia32_new_NoReg_gp(irg);
940 ir_node *frame = get_irg_frame(irg);
942 ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
944 set_ia32_frame_ent(push, ent);
945 set_ia32_use_frame(push);
946 set_ia32_op_type(push, ia32_AddrModeS);
947 set_ia32_ls_mode(push, mode_Is);
948 set_ia32_is_spill(push);
950 sched_add_before(schedpoint, push);
954 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
956 dbg_info *dbgi = get_irn_dbg_info(node);
957 ir_node *block = get_nodes_block(node);
958 ir_graph *irg = get_irn_irg(node);
959 ir_node *noreg = ia32_new_NoReg_gp(irg);
960 ir_node *frame = get_irg_frame(irg);
962 ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
963 get_irg_no_mem(irg), sp);
965 set_ia32_frame_ent(pop, ent);
966 set_ia32_use_frame(pop);
967 set_ia32_op_type(pop, ia32_AddrModeD);
968 set_ia32_ls_mode(pop, mode_Is);
969 set_ia32_is_reload(pop);
971 sched_add_before(schedpoint, pop);
976 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
978 dbg_info *dbgi = get_irn_dbg_info(node);
979 ir_mode *spmode = mode_Iu;
980 const arch_register_t *spreg = &ia32_registers[REG_ESP];
983 sp = new_rd_Proj(dbgi, pred, spmode, pos);
984 arch_set_irn_register(sp, spreg);
990 * Transform MemPerm, currently we do this the ugly way and produce
991 * push/pop into/from memory cascades. This is possible without using
994 static void transform_MemPerm(ir_node *node)
996 ir_node *block = get_nodes_block(node);
997 ir_graph *irg = get_irn_irg(node);
998 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
999 int arity = be_get_MemPerm_entity_arity(node);
1000 ir_node **pops = ALLOCAN(ir_node*, arity);
1004 const ir_edge_t *edge;
1005 const ir_edge_t *next;
1008 for (i = 0; i < arity; ++i) {
1009 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1010 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1011 ir_type *enttype = get_entity_type(inent);
1012 unsigned entsize = get_type_size_bytes(enttype);
1013 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1014 ir_node *mem = get_irn_n(node, i + 1);
1017 /* work around cases where entities have different sizes */
1018 if (entsize2 < entsize)
1020 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1022 push = create_push(node, node, sp, mem, inent);
1023 sp = create_spproj(node, push, pn_ia32_Push_stack);
1025 /* add another push after the first one */
1026 push = create_push(node, node, sp, mem, inent);
1027 add_ia32_am_offs_int(push, 4);
1028 sp = create_spproj(node, push, pn_ia32_Push_stack);
1031 set_irn_n(node, i, new_r_Bad(irg, mode_X));
1035 for (i = arity - 1; i >= 0; --i) {
1036 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1037 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1038 ir_type *enttype = get_entity_type(outent);
1039 unsigned entsize = get_type_size_bytes(enttype);
1040 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1043 /* work around cases where entities have different sizes */
1044 if (entsize2 < entsize)
1046 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1048 pop = create_pop(node, node, sp, outent);
1049 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1051 add_ia32_am_offs_int(pop, 4);
1053 /* add another pop after the first one */
1054 pop = create_pop(node, node, sp, outent);
1055 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1062 keep = be_new_Keep(block, 1, in);
1063 sched_add_before(node, keep);
1065 /* exchange memprojs */
1066 foreach_out_edge_safe(node, edge, next) {
1067 ir_node *proj = get_edge_src_irn(edge);
1068 int p = get_Proj_proj(proj);
1072 set_Proj_pred(proj, pops[p]);
1073 set_Proj_proj(proj, pn_ia32_Pop_M);
1076 /* remove memperm */
1082 * Block-Walker: Calls the transform functions Spill and Reload.
1084 static void ia32_after_ra_walker(ir_node *block, void *env)
1086 ir_node *node, *prev;
1089 /* beware: the schedule is changed here */
1090 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1091 prev = sched_prev(node);
1093 if (be_is_Reload(node)) {
1094 transform_to_Load(node);
1095 } else if (be_is_Spill(node)) {
1096 transform_to_Store(node);
1097 } else if (be_is_MemPerm(node)) {
1098 transform_MemPerm(node);
1104 * Collects nodes that need frame entities assigned.
1106 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1108 be_fec_env_t *env = (be_fec_env_t*)data;
1109 const ir_mode *mode;
1112 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1113 mode = get_spill_mode_mode(get_irn_mode(node));
1114 align = get_mode_size_bytes(mode);
1115 } else if (is_ia32_irn(node) &&
1116 get_ia32_frame_ent(node) == NULL &&
1117 is_ia32_use_frame(node)) {
1118 if (is_ia32_need_stackent(node))
1121 switch (get_ia32_irn_opcode(node)) {
1123 case iro_ia32_Load: {
1124 const ia32_attr_t *attr = get_ia32_attr_const(node);
1126 if (attr->data.need_32bit_stackent) {
1128 } else if (attr->data.need_64bit_stackent) {
1131 mode = get_ia32_ls_mode(node);
1132 if (is_ia32_is_reload(node))
1133 mode = get_spill_mode_mode(mode);
1135 align = get_mode_size_bytes(mode);
1139 case iro_ia32_vfild:
1141 case iro_ia32_xLoad: {
1142 mode = get_ia32_ls_mode(node);
1147 case iro_ia32_FldCW: {
1148 /* although 2 byte would be enough 4 byte performs best */
1156 panic("unexpected frame user while collection frame entity nodes");
1158 case iro_ia32_FnstCW:
1159 case iro_ia32_Store8Bit:
1160 case iro_ia32_Store:
1163 case iro_ia32_vfist:
1164 case iro_ia32_vfisttp:
1166 case iro_ia32_xStore:
1167 case iro_ia32_xStoreSimple:
1174 be_node_needs_frame_entity(env, node, mode, align);
1177 static int determine_ebp_input(ir_node *ret)
1179 const arch_register_t *bp = &ia32_registers[REG_EBP];
1180 int arity = get_irn_arity(ret);
1183 for (i = 0; i < arity; ++i) {
1184 ir_node *input = get_irn_n(ret, i);
1185 if (arch_get_irn_register(input) == bp)
1188 panic("no ebp input found at %+F", ret);
1191 static void introduce_epilog(ir_node *ret)
1193 const arch_register_t *sp = &ia32_registers[REG_ESP];
1194 const arch_register_t *bp = &ia32_registers[REG_EBP];
1195 ir_graph *irg = get_irn_irg(ret);
1196 ir_type *frame_type = get_irg_frame_type(irg);
1197 unsigned frame_size = get_type_size_bytes(frame_type);
1198 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1199 ir_node *block = get_nodes_block(ret);
1200 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1201 ir_node *curr_sp = first_sp;
1202 ir_mode *mode_gp = mode_Iu;
1204 if (!layout->sp_relative) {
1205 int n_ebp = determine_ebp_input(ret);
1206 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1207 if (ia32_cg_config.use_leave) {
1208 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1209 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1210 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1211 arch_set_irn_register(curr_bp, bp);
1212 arch_set_irn_register(curr_sp, sp);
1213 sched_add_before(ret, leave);
1216 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1217 /* copy ebp to esp */
1218 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1219 arch_set_irn_register(curr_sp, sp);
1220 sched_add_before(ret, curr_sp);
1223 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1224 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1225 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1226 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1227 arch_set_irn_register(curr_bp, bp);
1228 arch_set_irn_register(curr_sp, sp);
1229 sched_add_before(ret, pop);
1231 set_irn_n(ret, n_be_Return_mem, curr_mem);
1233 set_irn_n(ret, n_ebp, curr_bp);
1235 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1236 sched_add_before(ret, incsp);
1239 set_irn_n(ret, n_be_Return_sp, curr_sp);
1241 /* keep verifier happy... */
1242 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1243 kill_node(first_sp);
1248 * put the Prolog code at the beginning, epilog code before each return
1250 static void introduce_prolog_epilog(ir_graph *irg)
1252 const arch_register_t *sp = &ia32_registers[REG_ESP];
1253 const arch_register_t *bp = &ia32_registers[REG_EBP];
1254 ir_node *start = get_irg_start(irg);
1255 ir_node *block = get_nodes_block(start);
1256 ir_type *frame_type = get_irg_frame_type(irg);
1257 unsigned frame_size = get_type_size_bytes(frame_type);
1258 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1259 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1260 ir_node *curr_sp = initial_sp;
1261 ir_mode *mode_gp = mode_Iu;
1263 if (!layout->sp_relative) {
1265 ir_node *mem = get_irg_initial_mem(irg);
1266 ir_node *noreg = ia32_new_NoReg_gp(irg);
1267 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1268 ir_node *curr_bp = initial_bp;
1269 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
1272 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1273 mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
1274 arch_set_irn_register(curr_sp, sp);
1275 sched_add_after(start, push);
1277 /* move esp to ebp */
1278 curr_bp = be_new_Copy(bp->reg_class, block, curr_sp);
1279 sched_add_after(push, curr_bp);
1280 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1281 curr_sp = be_new_CopyKeep_single(sp->reg_class, block, curr_sp, curr_bp, mode_gp);
1282 sched_add_after(curr_bp, curr_sp);
1283 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1284 edges_reroute(initial_bp, curr_bp);
1285 set_irn_n(push, n_ia32_Push_val, initial_bp);
1287 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1288 edges_reroute(initial_sp, incsp);
1289 set_irn_n(push, n_ia32_Push_stack, initial_sp);
1290 sched_add_after(curr_sp, incsp);
1292 layout->initial_bias = -4;
1294 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1295 edges_reroute(initial_sp, incsp);
1296 be_set_IncSP_pred(incsp, curr_sp);
1297 sched_add_after(start, incsp);
1300 /* introduce epilog for every return node */
1302 ir_node *end_block = get_irg_end_block(irg);
1303 int arity = get_irn_arity(end_block);
1306 for (i = 0; i < arity; ++i) {
1307 ir_node *ret = get_irn_n(end_block, i);
1308 assert(be_is_Return(ret));
1309 introduce_epilog(ret);
1315 * We transform Spill and Reload here. This needs to be done before
1316 * stack biasing otherwise we would miss the corrected offset for these nodes.
1318 static void ia32_after_ra(ir_graph *irg)
1320 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1321 bool at_begin = stack_layout->sp_relative ? true : false;
1322 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1324 /* create and coalesce frame entities */
1325 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1326 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1327 be_free_frame_entity_coalescer(fec_env);
1329 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1331 introduce_prolog_epilog(irg);
1335 * Last touchups for the graph before emit: x87 simulation to replace the
1336 * virtual with real x87 instructions, creating a block schedule and peephole
1339 static void ia32_finish(ir_graph *irg)
1341 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1343 ia32_finish_irg(irg);
1345 /* we might have to rewrite x87 virtual registers */
1346 if (irg_data->do_x87_sim) {
1347 ia32_x87_simulate_graph(irg);
1350 /* do peephole optimisations */
1351 ia32_peephole_optimization(irg);
1353 /* create block schedule, this also removes empty blocks which might
1354 * produce critical edges */
1355 irg_data->blk_sched = be_create_block_schedule(irg);
1359 * Emits the code, closes the output file and frees
1360 * the code generator interface.
1362 static void ia32_emit(ir_graph *irg)
1364 if (ia32_cg_config.emit_machcode) {
1365 ia32_gen_binary_routine(irg);
1367 ia32_gen_routine(irg);
1372 * Returns the node representing the PIC base.
1374 static ir_node *ia32_get_pic_base(ir_graph *irg)
1376 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1378 ir_node *get_eip = irg_data->get_eip;
1379 if (get_eip != NULL)
1382 block = get_irg_start_block(irg);
1383 get_eip = new_bd_ia32_GetEIP(NULL, block);
1384 irg_data->get_eip = get_eip;
1390 * Initializes a IA32 code generator.
1392 static void ia32_init_graph(ir_graph *irg)
1394 struct obstack *obst = be_get_be_obst(irg);
1395 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1397 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1400 /* Linux gprof implementation needs base pointer */
1401 be_get_irg_options(irg)->omit_fp = 0;
1404 be_birg_from_irg(irg)->isa_link = irg_data;
1409 * Set output modes for GCC
1411 static const tarval_mode_info mo_integer = {
1418 * set the tarval output mode of all integer modes to decimal
1420 static void set_tarval_output_modes(void)
1424 for (i = get_irp_n_modes(); i > 0;) {
1425 ir_mode *mode = get_irp_mode(--i);
1427 if (mode_is_int(mode))
1428 set_tarval_mode_output_option(mode, &mo_integer);
1432 extern const arch_isa_if_t ia32_isa_if;
1435 * The template that generates a new ISA object.
1436 * Note that this template can be changed by command line
1439 static ia32_isa_t ia32_isa_template = {
1441 &ia32_isa_if, /* isa interface implementation */
1446 &ia32_registers[REG_ESP], /* stack pointer register */
1447 &ia32_registers[REG_EBP], /* base pointer register */
1448 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1449 2, /* power of two stack alignment, 2^2 == 4 */
1450 NULL, /* main environment */
1451 7, /* costs for a spill instruction */
1452 5, /* costs for a reload instruction */
1453 false, /* no custom abi handling */
1457 NULL, /* abstract machine */
1460 static void init_asm_constraints(void)
1462 be_init_default_asm_constraint_flags();
1464 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1465 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1466 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1467 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1468 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1469 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1470 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1471 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1472 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1473 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1474 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1475 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1476 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1477 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1478 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1479 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1480 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1481 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1482 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1483 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1485 /* no support for autodecrement/autoincrement */
1486 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1487 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1488 /* no float consts */
1489 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1490 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1491 /* makes no sense on x86 */
1492 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1493 /* no support for sse consts yet */
1494 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1495 /* no support for x87 consts yet */
1496 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1497 /* no support for mmx registers yet */
1498 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1499 /* not available in 32bit mode */
1500 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1501 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1503 /* no code yet to determine register class needed... */
1504 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1508 * Initializes the backend ISA.
1510 static arch_env_t *ia32_init(FILE *file_handle)
1512 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1514 set_tarval_output_modes();
1516 *isa = ia32_isa_template;
1518 if (ia32_mode_fpcw == NULL) {
1519 ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1522 ia32_register_init();
1523 ia32_create_opcodes(&ia32_irn_ops);
1525 be_emit_init(file_handle);
1526 isa->types = pmap_create();
1527 isa->tv_ent = pmap_create();
1528 isa->cpu = ia32_init_machine_description();
1530 /* enter the ISA object into the intrinsic environment */
1531 intrinsic_env.isa = isa;
1539 * Closes the output file and frees the ISA structure.
1541 static void ia32_done(void *self)
1543 ia32_isa_t *isa = (ia32_isa_t*)self;
1545 /* emit now all global declarations */
1546 be_gas_emit_decls(isa->base.main_env);
1548 pmap_destroy(isa->tv_ent);
1549 pmap_destroy(isa->types);
1558 * Get the register class which shall be used to store a value of a given mode.
1559 * @param self The this pointer.
1560 * @param mode The mode in question.
1561 * @return A register class which can hold values of the given mode.
1563 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1565 if (mode_is_float(mode)) {
1566 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1569 return &ia32_reg_classes[CLASS_ia32_gp];
1573 * Returns the register for parameter nr.
1575 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1576 const ir_mode *mode)
1578 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1579 &ia32_registers[REG_ECX],
1580 &ia32_registers[REG_EDX],
1583 static const unsigned MAXNUM_GPREG_ARGS = 3;
1585 static const arch_register_t *gpreg_param_reg_regparam[] = {
1586 &ia32_registers[REG_EAX],
1587 &ia32_registers[REG_EDX],
1588 &ia32_registers[REG_ECX]
1591 static const arch_register_t *gpreg_param_reg_this[] = {
1592 &ia32_registers[REG_ECX],
1597 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1598 &ia32_registers[REG_XMM0],
1599 &ia32_registers[REG_XMM1],
1600 &ia32_registers[REG_XMM2],
1601 &ia32_registers[REG_XMM3],
1602 &ia32_registers[REG_XMM4],
1603 &ia32_registers[REG_XMM5],
1604 &ia32_registers[REG_XMM6],
1605 &ia32_registers[REG_XMM7]
1608 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1609 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1611 static const unsigned MAXNUM_SSE_ARGS = 8;
1613 if ((cc & cc_this_call) && nr == 0)
1614 return gpreg_param_reg_this[0];
1616 if (! (cc & cc_reg_param))
1619 if (mode_is_float(mode)) {
1620 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1622 if (nr >= MAXNUM_SSE_ARGS)
1625 if (cc & cc_this_call) {
1626 return fpreg_sse_param_reg_this[nr];
1628 return fpreg_sse_param_reg_std[nr];
1629 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1630 unsigned num_regparam;
1632 if (get_mode_size_bits(mode) > 32)
1635 if (nr >= MAXNUM_GPREG_ARGS)
1638 if (cc & cc_this_call) {
1639 return gpreg_param_reg_this[nr];
1641 num_regparam = cc & ~cc_bits;
1642 if (num_regparam == 0) {
1643 /* default fastcall */
1644 return gpreg_param_reg_fastcall[nr];
1646 if (nr < num_regparam)
1647 return gpreg_param_reg_regparam[nr];
1651 panic("unknown argument mode");
1655 * Get the ABI restrictions for procedure calls.
1656 * @param self The this pointer.
1657 * @param method_type The type of the method (procedure) in question.
1658 * @param abi The abi object to be modified
1660 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1666 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1670 /* set abi flags for calls */
1671 call_flags.bits.store_args_sequential = 0;
1672 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1673 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1674 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1676 /* set parameter passing style */
1677 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1679 cc = get_method_calling_convention(method_type);
1680 if (get_method_variadicity(method_type) == variadicity_variadic) {
1681 /* pass all parameters of a variadic function on the stack */
1682 cc = cc_cdecl_set | (cc & cc_this_call);
1684 if (get_method_additional_properties(method_type) & mtp_property_private &&
1685 ia32_cg_config.optimize_cc) {
1686 /* set the fast calling conventions (allowing up to 3) */
1687 cc = SET_FASTCALL(cc) | 3;
1691 /* we have to pop the shadow parameter ourself for compound calls */
1692 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1693 && !(cc & cc_reg_param)) {
1694 pop_amount += get_mode_size_bytes(mode_P_data);
1697 n = get_method_n_params(method_type);
1698 for (i = regnum = 0; i < n; i++) {
1699 const arch_register_t *reg = NULL;
1700 ir_type *tp = get_method_param_type(method_type, i);
1701 ir_mode *mode = get_type_mode(tp);
1704 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1707 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1710 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1711 * movl has a shorter opcode than mov[sz][bw]l */
1712 ir_mode *load_mode = mode;
1715 unsigned size = get_mode_size_bytes(mode);
1717 if (cc & cc_callee_clear_stk) {
1718 pop_amount += (size + 3U) & ~3U;
1721 if (size < 4) load_mode = mode_Iu;
1724 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1728 be_abi_call_set_pop(abi, pop_amount);
1730 /* set return registers */
1731 n = get_method_n_ress(method_type);
1733 assert(n <= 2 && "more than two results not supported");
1735 /* In case of 64bit returns, we will have two 32bit values */
1737 ir_type *tp = get_method_res_type(method_type, 0);
1738 ir_mode *mode = get_type_mode(tp);
1740 assert(!mode_is_float(mode) && "two FP results not supported");
1742 tp = get_method_res_type(method_type, 1);
1743 mode = get_type_mode(tp);
1745 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1747 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1748 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1751 ir_type *tp = get_method_res_type(method_type, 0);
1752 ir_mode *mode = get_type_mode(tp);
1753 const arch_register_t *reg;
1754 assert(is_atomic_type(tp));
1756 reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
1758 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1763 * Returns the necessary byte alignment for storing a register of given class.
1765 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1767 ir_mode *mode = arch_register_class_mode(cls);
1768 int bytes = get_mode_size_bytes(mode);
1770 if (mode_is_float(mode) && bytes > 8)
1776 * Return irp irgs in the desired order.
1778 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1785 static void ia32_mark_remat(ir_node *node)
1787 if (is_ia32_irn(node)) {
1788 set_ia32_is_remat(node);
1793 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1795 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1800 ir_relation relation;
1805 cmp_l = get_Cmp_left(sel);
1806 cmp_r = get_Cmp_right(sel);
1807 if (!mode_is_float(get_irn_mode(cmp_l)))
1810 /* check for min/max. They're defined as (C-Semantik):
1811 * min(a, b) = a < b ? a : b
1812 * or min(a, b) = a <= b ? a : b
1813 * max(a, b) = a > b ? a : b
1814 * or max(a, b) = a >= b ? a : b
1815 * (Note we only handle float min/max here)
1817 relation = get_Cmp_relation(sel);
1819 case ir_relation_greater_equal:
1820 case ir_relation_greater:
1822 if (cmp_l == mux_true && cmp_r == mux_false)
1825 case ir_relation_less_equal:
1826 case ir_relation_less:
1828 if (cmp_l == mux_true && cmp_r == mux_false)
1831 case ir_relation_unordered_greater_equal:
1832 case ir_relation_unordered_greater:
1834 if (cmp_l == mux_false && cmp_r == mux_true)
1837 case ir_relation_unordered_less_equal:
1838 case ir_relation_unordered_less:
1840 if (cmp_l == mux_false && cmp_r == mux_true)
1851 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1853 ir_mode *mode = get_irn_mode(mux_true);
1856 if (!mode_is_int(mode) && !mode_is_reference(mode)
1860 if (is_Const(mux_true) && is_Const(mux_false)) {
1861 /* we can create a set plus up two 3 instructions for any combination
1869 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1874 if (!mode_is_float(get_irn_mode(mux_true)))
1877 return is_Const(mux_true) && is_Const(mux_false);
1880 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1887 ir_relation relation;
1892 mode = get_irn_mode(mux_true);
1893 if (mode_is_signed(mode) || mode_is_float(mode))
1896 relation = get_Cmp_relation(sel);
1897 cmp_left = get_Cmp_left(sel);
1898 cmp_right = get_Cmp_right(sel);
1900 /* "move" zero constant to false input */
1901 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1902 ir_node *tmp = mux_false;
1903 mux_false = mux_true;
1905 relation = get_negated_relation(relation);
1907 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1909 if (!is_Sub(mux_true))
1911 sub_left = get_Sub_left(mux_true);
1912 sub_right = get_Sub_right(mux_true);
1914 /* Mux(a >=u b, 0, a-b) */
1915 if ((relation & ir_relation_greater)
1916 && sub_left == cmp_left && sub_right == cmp_right)
1918 /* Mux(a <=u b, 0, b-a) */
1919 if ((relation & ir_relation_less)
1920 && sub_left == cmp_right && sub_right == cmp_left)
1926 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1931 /* we can handle Set for all modes and compares */
1932 if (mux_is_set(sel, mux_true, mux_false))
1934 /* SSE has own min/max operations */
1935 if (ia32_cg_config.use_sse2
1936 && mux_is_float_min_max(sel, mux_true, mux_false))
1938 /* we can handle Mux(?, Const[f], Const[f]) */
1939 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1940 #ifdef FIRM_GRGEN_BE
1941 /* well, some code selectors can't handle it */
1942 if (be_transformer != TRANSFORMER_PBQP
1943 || be_transformer != TRANSFORMER_RAND)
1950 /* no support for 64bit inputs to cmov */
1951 mode = get_irn_mode(mux_true);
1952 if (get_mode_size_bits(mode) > 32)
1954 /* we can handle Abs for all modes and compares (except 64bit) */
1955 if (ir_mux_is_abs(sel, mux_true, mux_false) != 0)
1957 /* we can't handle MuxF yet */
1958 if (mode_is_float(mode))
1961 if (mux_is_doz(sel, mux_true, mux_false))
1964 /* Check Cmp before the node */
1966 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1968 /* we can't handle 64bit compares */
1969 if (get_mode_size_bits(cmp_mode) > 32)
1972 /* we can't handle float compares */
1973 if (mode_is_float(cmp_mode))
1977 /* did we disable cmov generation? */
1978 if (!ia32_cg_config.use_cmov)
1981 /* we can use a cmov */
1985 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
1989 /* we already added all our simple flags to the flags modifier list in
1990 * init, so this flag we don't know. */
1991 return ASM_CONSTRAINT_FLAG_INVALID;
1994 static int ia32_is_valid_clobber(const char *clobber)
1996 return ia32_get_clobber_register(clobber) != NULL;
1999 static ir_node *ia32_create_set(ir_node *cond)
2001 /* ia32-set function produces 8-bit results which have to be converted */
2002 ir_node *set = ir_create_mux_set(cond, mode_Bu);
2003 ir_node *block = get_nodes_block(set);
2004 return new_r_Conv(block, set, mode_Iu);
2007 static void ia32_lower_for_target(void)
2009 size_t i, n_irgs = get_irp_n_irgs();
2010 lower_mode_b_config_t lower_mode_b_config = {
2011 mode_Iu, /* lowered mode */
2013 0, /* don't lower direct compares */
2016 /* perform doubleword lowering */
2017 lwrdw_param_t lower_dw_params = {
2018 1, /* little endian */
2019 64, /* doubleword size */
2020 ia32_create_intrinsic_fkt,
2024 /* lower compound param handling */
2025 lower_calls_with_compounds(LF_RETURN_HIDDEN);
2027 ir_prepare_dw_lowering(&lower_dw_params);
2030 for (i = 0; i < n_irgs; ++i) {
2031 ir_graph *irg = get_irp_irg(i);
2032 /* lower for mode_b stuff */
2033 ir_lower_mode_b(irg, &lower_mode_b_config);
2034 /* break up switches with wide ranges */
2035 lower_switch(irg, 4, 256, false);
2040 * Create the trampoline code.
2042 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2044 ir_graph *irg = get_irn_irg(block);
2045 ir_node *p = trampoline;
2046 ir_mode *mode = get_irn_mode(p);
2050 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
2051 mem = new_r_Proj(st, mode_M, pn_Store_M);
2052 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2053 st = new_r_Store(block, mem, p, env, cons_none);
2054 mem = new_r_Proj(st, mode_M, pn_Store_M);
2055 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2057 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
2058 mem = new_r_Proj(st, mode_M, pn_Store_M);
2059 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2060 st = new_r_Store(block, mem, p, callee, cons_none);
2061 mem = new_r_Proj(st, mode_M, pn_Store_M);
2062 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2068 * Returns the libFirm configuration parameter for this backend.
2070 static const backend_params *ia32_get_libfirm_params(void)
2072 static const ir_settings_arch_dep_t ad = {
2073 1, /* also use subs */
2074 4, /* maximum shifts */
2075 63, /* maximum shift amount */
2076 ia32_evaluate_insn, /* evaluate the instruction sequence */
2078 1, /* allow Mulhs */
2079 1, /* allow Mulus */
2080 32, /* Mulh allowed up to 32 bit */
2082 static backend_params p = {
2083 1, /* support inline assembly */
2084 1, /* support Rotl nodes */
2085 0, /* little endian */
2086 NULL, /* will be set later */
2087 ia32_is_mux_allowed,
2088 32, /* machine_size */
2089 NULL, /* float arithmetic mode, will be set below */
2090 0, /* size of long double */
2091 12, /* size of trampoline code */
2092 4, /* alignment of trampoline code */
2093 ia32_create_trampoline_fkt,
2094 4 /* alignment of stack parameter */
2097 ia32_setup_cg_config();
2099 /* doesn't really belong here, but this is the earliest place the backend
2101 init_asm_constraints();
2104 if (! ia32_cg_config.use_sse2) {
2105 p.mode_float_arithmetic = mode_E;
2106 p.long_double_size = 96;
2108 p.mode_float_arithmetic = NULL;
2109 p.long_double_size = 64;
2115 * Check if the given register is callee or caller save.
2117 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
2120 /* check for callee saved */
2121 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2122 switch (reg->index) {
2133 /* check for caller saved */
2134 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2135 switch (reg->index) {
2143 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
2144 /* all XMM registers are caller save */
2145 return reg->index != REG_XMM_NOREG;
2146 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
2147 /* all VFP registers are caller save */
2148 return reg->index != REG_VFP_NOREG;
2154 static const lc_opt_enum_int_items_t gas_items[] = {
2155 { "elf", OBJECT_FILE_FORMAT_ELF },
2156 { "mingw", OBJECT_FILE_FORMAT_COFF },
2157 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2161 static lc_opt_enum_int_var_t gas_var = {
2162 (int*) &be_gas_object_file_format, gas_items
2165 #ifdef FIRM_GRGEN_BE
2166 static const lc_opt_enum_int_items_t transformer_items[] = {
2167 { "default", TRANSFORMER_DEFAULT },
2168 { "pbqp", TRANSFORMER_PBQP },
2169 { "random", TRANSFORMER_RAND },
2173 static lc_opt_enum_int_var_t transformer_var = {
2174 (int*)&be_transformer, transformer_items
2178 static const lc_opt_table_entry_t ia32_options[] = {
2179 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2180 #ifdef FIRM_GRGEN_BE
2181 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2183 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2184 &ia32_isa_template.base.stack_alignment),
2185 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2189 const arch_isa_if_t ia32_isa_if = {
2191 ia32_lower_for_target,
2193 ia32_handle_intrinsics,
2194 ia32_get_reg_class_for_mode,
2196 ia32_get_reg_class_alignment,
2197 ia32_get_libfirm_params,
2200 ia32_parse_asm_constraint,
2201 ia32_is_valid_clobber,
2204 ia32_get_pic_base, /* return node used as base in pic code addresses */
2205 ia32_before_abi, /* before abi introduce hook */
2207 ia32_before_ra, /* before register allocation hook */
2208 ia32_after_ra, /* after register allocation hook */
2209 ia32_finish, /* called before codegen */
2210 ia32_emit, /* emit && done */
2211 ia32_register_saved_by,
2214 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2215 void be_init_arch_ia32(void)
2217 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2218 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2220 lc_opt_add_table(ia32_grp, ia32_options);
2221 be_register_isa_if("ia32", &ia32_isa_if);
2223 ia32_init_emitter();
2225 ia32_init_optimize();
2226 ia32_init_transform();
2228 ia32_init_architecture();