2 * This is the main ia32 firm backend driver.
17 #include "pseudo_irg.h"
21 #include "iredges_t.h"
29 #include "../beabi.h" /* the general register allocator interface */
30 #include "../benode_t.h"
31 #include "../belower.h"
32 #include "../besched_t.h"
34 #include "bearch_ia32_t.h"
36 #include "ia32_new_nodes.h" /* ia32 nodes interface */
37 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
38 #include "ia32_gen_decls.h" /* interface declaration emitter */
39 #include "ia32_transform.h"
40 #include "ia32_emitter.h"
41 #include "ia32_map_regs.h"
42 #include "ia32_optimize.h"
44 #define DEBUG_MODULE "firm.be.ia32.isa"
47 static set *cur_reg_set = NULL;
50 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
52 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
53 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_XXX]);
56 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
57 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_fp_regs[REG_XXXX]);
60 /**************************************************
63 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
64 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
65 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
66 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
69 **************************************************/
71 static ir_node *my_skip_proj(const ir_node *n) {
79 * Return register requirements for an ia32 node.
80 * If the node returns a tuple (mode_T) then the proj's
81 * will be asked for this information.
83 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
84 const ia32_register_req_t *irn_req;
85 long node_pos = pos == -1 ? 0 : pos;
86 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
87 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
89 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
90 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
94 if (mode == mode_T && pos < 0) {
95 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
99 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
104 node_pos = ia32_translate_proj_pos(irn);
110 irn = my_skip_proj(irn);
112 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
115 if (is_ia32_irn(irn)) {
117 irn_req = get_ia32_in_req(irn, pos);
120 irn_req = get_ia32_out_req(irn, node_pos);
123 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
125 memcpy(req, &(irn_req->req), sizeof(*req));
127 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
128 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
129 req->other_same = get_irn_n(irn, irn_req->same_pos);
132 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
133 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
134 req->other_different = get_irn_n(irn, irn_req->different_pos);
138 /* treat Phi like Const with default requirements */
140 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
141 if (mode_is_float(mode))
142 memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req));
143 else if (mode_is_int(mode) || mode_is_reference(mode))
144 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
145 else if (mode == mode_T || mode == mode_M) {
146 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
150 assert(0 && "unsupported Phi-Mode");
153 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
161 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
163 const ia32_irn_ops_t *ops = self;
165 if (get_irn_mode(irn) == mode_X) {
169 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
172 pos = ia32_translate_proj_pos(irn);
173 irn = my_skip_proj(irn);
176 if (is_ia32_irn(irn)) {
177 const arch_register_t **slots;
179 slots = get_ia32_slots(irn);
183 ia32_set_firm_reg(irn, reg, cur_reg_set);
187 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
189 const arch_register_t *reg = NULL;
193 if (get_irn_mode(irn) == mode_X) {
197 pos = ia32_translate_proj_pos(irn);
198 irn = my_skip_proj(irn);
201 if (is_ia32_irn(irn)) {
202 const arch_register_t **slots;
203 slots = get_ia32_slots(irn);
207 reg = ia32_get_firm_reg(irn, cur_reg_set);
213 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
214 irn = my_skip_proj(irn);
216 return arch_irn_class_branch;
217 else if (is_ia32_irn(irn))
218 return arch_irn_class_normal;
223 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
224 irn = my_skip_proj(irn);
225 if (is_ia32_irn(irn))
226 return get_ia32_flags(irn);
232 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
233 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
236 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
238 const ia32_irn_ops_t *ops = self;
240 if (is_ia32_use_frame(irn) && bias != 0) {
241 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
243 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
244 snprintf(buf, sizeof(buf), "%d", bias);
245 add_ia32_am_offs(irn, buf);
247 set_ia32_am_flavour(irn, am_flav);
252 be_abi_call_flags_bits_t flags;
253 const arch_isa_t *isa;
257 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
259 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
260 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
261 env->flags = fl.bits;
263 env->isa = aenv->isa;
267 static void ia32_abi_dont_save_regs(void *self, pset *s)
269 ia32_abi_env_t *env = self;
270 if(env->flags.try_omit_fp)
271 pset_insert_ptr(s, env->isa->bp);
274 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
276 ia32_abi_env_t *env = self;
277 const arch_register_t *frame_reg = env->isa->sp;
279 if(!env->flags.try_omit_fp) {
280 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
281 ir_node *bl = get_irg_start_block(env->irg);
282 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
283 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
284 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_XXX]);
287 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_expand);
288 store_bp = new_rd_ia32_Store(NULL, env->irg, bl, curr_sp, curr_no_reg, curr_bp, *mem, mode_T);
289 set_ia32_am_support(store_bp, ia32_am_Dest);
290 set_ia32_am_flavour(store_bp, ia32_B);
291 set_ia32_op_type(store_bp, ia32_AddrModeD);
292 *mem = new_r_Proj(env->irg, bl, store_bp, mode_M, 0);
293 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
294 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
295 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
297 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
298 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
304 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
306 ia32_abi_env_t *env = self;
307 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
308 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
309 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_XXX]);
311 if(env->flags.try_omit_fp) {
312 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
317 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
319 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
320 load_bp = new_rd_ia32_Load(NULL, env->irg, bl, curr_sp, curr_no_reg, *mem, mode_T);
321 set_ia32_am_support(load_bp, ia32_am_Source);
322 set_ia32_am_flavour(load_bp, ia32_B);
323 set_ia32_op_type(load_bp, ia32_AddrModeS);
324 set_ia32_ls_mode(load_bp, mode_bp);
325 curr_bp = new_r_Proj(env->irg, bl, load_bp, mode_bp, 0);
326 *mem = new_r_Proj(env->irg, bl, load_bp, mode_M, 1);
329 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
330 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
334 * Produces the type which sits between the stack args and the locals on the stack.
335 * it will contain the return address and space to store the old base pointer.
336 * @return The Firm type modeling the ABI between type.
338 static ir_type *ia32_abi_get_between_type(void *self)
340 static ir_type *omit_fp_between_type = NULL;
341 static ir_type *between_type = NULL;
343 ia32_abi_env_t *env = self;
347 entity *ret_addr_ent;
348 entity *omit_fp_ret_addr_ent;
350 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
351 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
353 between_type = new_type_class(new_id_from_str("ia32_between_type"));
354 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
355 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
357 set_entity_offset_bytes(old_bp_ent, 0);
358 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
359 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
361 omit_fp_between_type = new_type_class(new_id_from_str("ia32_between_type_omit_fp"));
362 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, new_id_from_str("ret_addr"), ret_addr_type);
364 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
365 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
368 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
371 static const be_abi_callbacks_t ia32_abi_callbacks = {
374 ia32_abi_get_between_type,
375 ia32_abi_dont_save_regs,
380 /* fill register allocator interface */
382 static const arch_irn_ops_if_t ia32_irn_ops_if = {
383 ia32_get_irn_reg_req,
388 ia32_get_frame_entity,
392 ia32_irn_ops_t ia32_irn_ops = {
399 /**************************************************
402 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
403 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
404 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
405 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
408 **************************************************/
411 * Transforms the standard firm graph into
414 static void ia32_prepare_graph(void *self) {
415 ia32_code_gen_t *cg = self;
416 firm_dbg_module_t *old_mod = cg->mod;
418 cg->mod = firm_dbg_register("firm.be.ia32.transform");
419 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
420 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
425 edges_deactivate(cg->irg);
426 //dead_node_elimination(cg->irg);
427 edges_activate(cg->irg);
429 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
430 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
436 * Insert copies for all ia32 nodes where the should_be_same requirement
438 * Transform Sub into Neg -- Add if IN2 == OUT
440 static void ia32_finish_irg_walker(ir_node *irn, void *env) {
441 ia32_code_gen_t *cg = env;
442 const ia32_register_req_t **reqs;
443 const arch_register_t *out_reg, *in_reg;
445 ir_node *copy, *in_node, *block;
446 ia32_op_type_t op_tp;
448 if (! is_ia32_irn(irn))
451 /* AM Dest nodes don't produce any values */
452 op_tp = get_ia32_op_type(irn);
453 if (op_tp == ia32_AddrModeD)
456 reqs = get_ia32_out_req_all(irn);
457 n_res = get_ia32_n_res(irn);
458 block = get_nodes_block(irn);
460 /* check all OUT requirements, if there is a should_be_same */
461 if (op_tp == ia32_Normal) {
462 for (i = 0; i < n_res; i++) {
463 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
464 /* get in and out register */
465 out_reg = get_ia32_out_reg(irn, i);
466 in_node = get_irn_n(irn, reqs[i]->same_pos);
467 in_reg = arch_get_irn_register(cg->arch_env, in_node);
469 /* don't copy ignore nodes */
470 if (arch_irn_is(cg->arch_env, in_node, ignore))
473 /* check if in and out register are equal */
474 if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
475 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
477 /* create copy from in register */
478 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
480 /* destination is the out register */
481 arch_set_irn_register(cg->arch_env, copy, out_reg);
483 /* insert copy before the node into the schedule */
484 sched_add_before(irn, copy);
487 set_irn_n(irn, reqs[i]->same_pos, copy);
493 /* check if there is a sub which need to be transformed */
494 ia32_transform_sub_to_neg_add(irn, cg);
496 /* transform a LEA into an Add if possible */
497 ia32_transform_lea_to_add(irn, cg);
499 /* check for peephole optimization */
500 ia32_peephole_optimization(irn, cg);
504 * Add Copy nodes for not fulfilled should_be_equal constraints
506 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
507 irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
513 * Dummy functions for hooks we don't need but which must be filled.
515 static void ia32_before_sched(void *self) {
518 static void ia32_before_ra(void *self) {
524 * Transforms a be node into a Load.
526 static void transform_to_Load(ia32_transform_env_t *env) {
527 ir_node *irn = env->irn;
528 entity *ent = be_get_frame_entity(irn);
529 ir_mode *mode = env->mode;
530 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
531 ir_node *nomem = new_rd_NoMem(env->irg);
532 ir_node *sched_point = NULL;
533 ir_node *ptr = get_irn_n(irn, 0);
534 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
535 ir_node *new_op, *proj;
536 const arch_register_t *reg;
538 if (sched_is_scheduled(irn)) {
539 sched_point = sched_prev(irn);
542 if (mode_is_float(mode)) {
543 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
546 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
549 set_ia32_am_support(new_op, ia32_am_Source);
550 set_ia32_op_type(new_op, ia32_AddrModeS);
551 set_ia32_am_flavour(new_op, ia32_B);
552 set_ia32_ls_mode(new_op, mode);
553 set_ia32_frame_ent(new_op, ent);
554 set_ia32_use_frame(new_op);
556 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
559 sched_add_after(sched_point, new_op);
560 sched_add_after(new_op, proj);
565 /* copy the register from the old node to the new Load */
566 reg = arch_get_irn_register(env->cg->arch_env, irn);
567 arch_set_irn_register(env->cg->arch_env, new_op, reg);
574 * Transforms a be node into a Store.
576 static void transform_to_Store(ia32_transform_env_t *env) {
577 ir_node *irn = env->irn;
578 entity *ent = be_get_frame_entity(irn);
579 ir_mode *mode = env->mode;
580 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
581 ir_node *nomem = new_rd_NoMem(env->irg);
582 ir_node *ptr = get_irn_n(irn, 0);
583 ir_node *val = get_irn_n(irn, 1);
584 ir_node *new_op, *proj;
585 ir_node *sched_point = NULL;
587 if (sched_is_scheduled(irn)) {
588 sched_point = sched_prev(irn);
591 if (mode_is_float(mode)) {
592 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
594 else if (get_mode_size_bits(mode) == 8) {
595 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
598 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
601 set_ia32_am_support(new_op, ia32_am_Dest);
602 set_ia32_op_type(new_op, ia32_AddrModeD);
603 set_ia32_am_flavour(new_op, ia32_B);
604 set_ia32_ls_mode(new_op, get_irn_mode(val));
605 set_ia32_frame_ent(new_op, ent);
606 set_ia32_use_frame(new_op);
608 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
611 sched_add_after(sched_point, new_op);
612 sched_add_after(new_op, proj);
622 * Calls the transform functions for StackParam, Spill and Reload.
624 static void ia32_after_ra_walker(ir_node *node, void *env) {
625 ia32_code_gen_t *cg = env;
626 ia32_transform_env_t tenv;
631 tenv.block = get_nodes_block(node);
632 tenv.dbg = get_irn_dbg_info(node);
633 tenv.irg = current_ir_graph;
636 tenv.mode = get_irn_mode(node);
639 /* be_is_StackParam(node) || */
640 if (be_is_Reload(node)) {
641 transform_to_Load(&tenv);
643 else if (be_is_Spill(node)) {
644 transform_to_Store(&tenv);
649 * We transform StackParam, Spill and Reload here. This needs to be done before
650 * stack biasing otherwise we would miss the corrected offset for these nodes.
652 static void ia32_after_ra(void *self) {
653 ia32_code_gen_t *cg = self;
654 irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
659 * Emits the code, closes the output file and frees
660 * the code generator interface.
662 static void ia32_codegen(void *self) {
663 ia32_code_gen_t *cg = self;
664 ir_graph *irg = cg->irg;
667 if (cg->emit_decls) {
668 ia32_gen_decls(cg->out);
672 ia32_finish_irg(irg, cg);
673 be_dump(irg, "-finished", dump_ir_block_graph_sched);
674 ia32_gen_routine(out, irg, cg);
678 pmap_destroy(cg->tv_ent);
679 pmap_destroy(cg->types);
681 /* de-allocate code generator */
682 del_set(cg->reg_set);
686 static void *ia32_cg_init(FILE *F, const be_irg_t *birg);
688 static const arch_code_generator_if_t ia32_code_gen_if = {
690 NULL, /* before abi introduce hook */
692 ia32_before_sched, /* before scheduling hook */
693 ia32_before_ra, /* before register allocation hook */
694 ia32_after_ra, /* after register allocation hook */
695 ia32_codegen /* emit && done */
699 * Initializes the code generator.
701 static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
702 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
703 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
705 cg->impl = &ia32_code_gen_if;
707 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
708 cg->mod = firm_dbg_register("firm.be.ia32.cg");
710 cg->arch_env = birg->main_env->arch_env;
711 cg->types = pmap_create();
712 cg->tv_ent = pmap_create();
715 /* set optimizations */
718 cg->opt.placecnst = 1;
723 if (isa->name_obst_size) {
724 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
725 isa->name_obst_size = 0;
726 obstack_free(isa->name_obst, NULL);
727 obstack_init(isa->name_obst);
733 if (isa->num_codegens > 1)
738 cur_reg_set = cg->reg_set;
740 ia32_irn_ops.cg = cg;
742 return (arch_code_generator_t *)cg;
747 /*****************************************************************
748 * ____ _ _ _____ _____
749 * | _ \ | | | | |_ _|/ ____| /\
750 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
751 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
752 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
753 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
755 *****************************************************************/
757 static ia32_isa_t ia32_isa_template = {
758 &ia32_isa_if, /* isa interface implementation */
759 &ia32_gp_regs[REG_ESP], /* stack pointer register */
760 &ia32_gp_regs[REG_EBP], /* base pointer register */
761 -1, /* stack direction */
762 0, /* number of code generator objects so far */
763 NULL, /* 16bit register names */
764 NULL, /* 8bit register names */
766 NULL, /* name obstack */
767 0 /* name obst size */
772 * Initializes the backend ISA.
774 static void *ia32_init(void) {
775 static int inited = 0;
781 isa = xcalloc(1, sizeof(*isa));
782 memcpy(isa, &ia32_isa_template, sizeof(*isa));
784 ia32_register_init(isa);
785 ia32_create_opcodes();
786 ia32_register_copy_attr_func();
788 isa->regs_16bit = pmap_create();
789 isa->regs_8bit = pmap_create();
791 ia32_build_16bit_reg_map(isa->regs_16bit);
792 ia32_build_8bit_reg_map(isa->regs_8bit);
795 isa->name_obst = xcalloc(1, sizeof(*(isa->name_obst)));
796 obstack_init(isa->name_obst);
797 isa->name_obst_size = 0;
808 * Closes the output file and frees the ISA structure.
810 static void ia32_done(void *self) {
811 ia32_isa_t *isa = self;
813 pmap_destroy(isa->regs_16bit);
814 pmap_destroy(isa->regs_8bit);
817 //printf("name obst size = %d bytes\n", isa->name_obst_size);
818 obstack_free(isa->name_obst, NULL);
826 static int ia32_get_n_reg_class(const void *self) {
830 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
831 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
832 return &ia32_reg_classes[i];
836 * Get the register class which shall be used to store a value of a given mode.
837 * @param self The this pointer.
838 * @param mode The mode in question.
839 * @return A register class which can hold values of the given mode.
841 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
842 if (mode_is_float(mode))
843 return &ia32_reg_classes[CLASS_ia32_fp];
845 return &ia32_reg_classes[CLASS_ia32_gp];
849 * Get the ABI restrictions for procedure calls.
850 * @param self The this pointer.
851 * @param method_type The type of the method (procedure) in question.
852 * @param abi The abi object to be modified
854 void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
857 unsigned cc = get_method_calling_convention(method_type);
858 int n = get_method_n_params(method_type);
861 int i, ignore_1, ignore_2;
863 const arch_register_t *reg;
864 be_abi_call_flags_t call_flags;
866 /* set abi flags for calls */
867 call_flags.bits.left_to_right = 0;
868 call_flags.bits.store_args_sequential = 0;
869 call_flags.bits.try_omit_fp = 1;
870 call_flags.bits.fp_free = 0;
871 call_flags.bits.call_has_imm = 1;
873 /* set stack parameter passing style */
874 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
876 /* collect the mode for each type */
877 modes = alloca(n * sizeof(modes[0]));
879 for (i = 0; i < n; i++) {
880 tp = get_method_param_type(method_type, i);
881 modes[i] = get_type_mode(tp);
884 /* set register parameters */
885 if (cc & cc_reg_param) {
886 /* determine the number of parameters passed via registers */
887 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
889 /* loop over all parameters and set the register requirements */
890 for (i = 0; i <= biggest_n; i++) {
891 reg = ia32_get_RegParam_reg(n, modes, i, cc);
892 assert(reg && "kaputt");
893 be_abi_call_param_reg(abi, i, reg);
900 /* set stack parameters */
901 for (i = stack_idx; i < n; i++) {
902 be_abi_call_param_stack(abi, i, 1, 0, 0);
906 /* set return registers */
907 n = get_method_n_ress(method_type);
909 assert(n <= 2 && "more than two results not supported");
911 /* In case of 64bit returns, we will have two 32bit values */
913 tp = get_method_res_type(method_type, 0);
914 mode = get_type_mode(tp);
916 assert(!mode_is_float(mode) && "two FP results not supported");
918 tp = get_method_res_type(method_type, 1);
919 mode = get_type_mode(tp);
921 assert(!mode_is_float(mode) && "two FP results not supported");
923 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
924 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
927 tp = get_method_res_type(method_type, 0);
928 assert(is_atomic_type(tp));
929 mode = get_type_mode(tp);
931 be_abi_call_res_reg(abi, 0, mode_is_float(mode) ? &ia32_fp_regs[REG_XMM0] : &ia32_gp_regs[REG_EAX]);
936 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
937 return &ia32_irn_ops;
940 const arch_irn_handler_t ia32_irn_handler = {
944 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
945 return &ia32_irn_handler;
948 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
949 return is_ia32_irn(irn);
953 * Initializes the code generator interface.
955 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
956 return &ia32_code_gen_if;
959 list_sched_selector_t ia32_sched_selector;
962 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
964 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
965 memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
966 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
967 return &ia32_sched_selector;
971 static void ia32_register_options(lc_opt_entry_t *ent)
974 #endif /* WITH_LIBCORE */
976 const arch_isa_if_t ia32_isa_if = {
978 ia32_register_options,
982 ia32_get_n_reg_class,
984 ia32_get_reg_class_for_mode,
986 ia32_get_irn_handler,
987 ia32_get_code_generator_if,
988 ia32_get_list_sched_selector