2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
26 #include "pseudo_irg.h"
30 #include "iredges_t.h"
39 #include "../beabi.h" /* the general register allocator interface */
40 #include "../benode_t.h"
41 #include "../belower.h"
42 #include "../besched_t.h"
45 #include "../beirgmod.h"
46 #include "../be_dbgout.h"
47 #include "../beblocksched.h"
48 #include "../bemachine.h"
49 #include "../beilpsched.h"
50 #include "../bespillslots.h"
51 #include "../bemodule.h"
53 #include "bearch_ia32_t.h"
55 #include "ia32_new_nodes.h" /* ia32 nodes interface */
56 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
57 #include "gen_ia32_machine.h"
58 #include "ia32_gen_decls.h" /* interface declaration emitter */
59 #include "ia32_transform.h"
60 #include "ia32_emitter.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_optimize.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_finish.h"
66 #include "ia32_util.h"
68 #define DEBUG_MODULE "firm.be.ia32.isa"
71 static set *cur_reg_set = NULL;
73 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
75 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
76 create_const_node_func func, arch_register_t* reg)
84 block = get_irg_start_block(cg->irg);
85 res = func(NULL, cg->irg, block);
86 arch_set_irn_register(cg->arch_env, res, reg);
89 startnode = get_irg_start(cg->irg);
90 if(sched_is_scheduled(startnode)) {
91 sched_add_before(startnode, res);
97 /* Creates the unique per irg GP NoReg node. */
98 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
99 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
100 &ia32_gp_regs[REG_GP_NOREG]);
103 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
104 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
105 &ia32_vfp_regs[REG_VFP_NOREG]);
108 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
109 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
110 &ia32_xmm_regs[REG_XMM_NOREG]);
113 /* Creates the unique per irg FP NoReg node. */
114 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
115 return USE_SSE2(cg) ? ia32_new_NoReg_xmm(cg) : ia32_new_NoReg_vfp(cg);
118 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
119 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
120 &ia32_gp_regs[REG_GP_UKNWN]);
123 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
124 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
125 &ia32_vfp_regs[REG_VFP_UKNWN]);
128 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
129 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
130 &ia32_xmm_regs[REG_XMM_UKNWN]);
135 * Returns gp_noreg or fp_noreg, depending in input requirements.
137 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
138 arch_register_req_t req;
139 const arch_register_req_t *p_req;
141 p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
142 assert(p_req && "Missing register requirements");
143 if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
144 return ia32_new_NoReg_gp(cg);
146 return ia32_new_NoReg_fp(cg);
149 /**************************************************
152 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
153 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
154 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
155 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
158 **************************************************/
161 * Return register requirements for an ia32 node.
162 * If the node returns a tuple (mode_T) then the proj's
163 * will be asked for this information.
165 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
166 const ia32_irn_ops_t *ops = self;
167 const ia32_register_req_t *irn_req;
168 long node_pos = pos == -1 ? 0 : pos;
169 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
170 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
172 if (is_Block(irn) || mode == mode_X) {
173 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
177 if (mode == mode_T && pos < 0) {
178 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
182 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
189 DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
193 node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
194 irn = skip_Proj_const(irn);
196 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
199 if (is_ia32_irn(irn)) {
200 irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
201 if (irn_req == NULL) {
202 /* no requirements */
206 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
208 memcpy(req, &(irn_req->req), sizeof(*req));
210 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
211 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
212 req->other_same = get_irn_n(irn, irn_req->same_pos);
215 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
216 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
217 req->other_different = get_irn_n(irn, irn_req->different_pos);
221 /* treat Unknowns like Const with default requirements */
222 if (is_Unknown(irn)) {
223 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
224 if (mode_is_float(mode)) {
225 if (USE_SSE2(ops->cg))
226 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
228 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
230 else if (mode_is_int(mode) || mode_is_reference(mode))
231 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
232 else if (mode == mode_T || mode == mode_M) {
233 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
237 assert(0 && "unsupported Unknown-Mode");
240 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
248 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
250 const ia32_irn_ops_t *ops = self;
252 if (get_irn_mode(irn) == mode_X) {
256 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
259 pos = get_Proj_proj(irn);
260 irn = skip_Proj(irn);
263 if (is_ia32_irn(irn)) {
264 const arch_register_t **slots;
266 slots = get_ia32_slots(irn);
270 ia32_set_firm_reg(irn, reg, cur_reg_set);
274 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
276 const arch_register_t *reg = NULL;
280 if (get_irn_mode(irn) == mode_X) {
284 pos = get_Proj_proj(irn);
285 irn = skip_Proj_const(irn);
288 if (is_ia32_irn(irn)) {
289 const arch_register_t **slots;
290 slots = get_ia32_slots(irn);
294 reg = ia32_get_firm_reg(irn, cur_reg_set);
300 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
301 arch_irn_class_t classification = arch_irn_class_normal;
303 irn = skip_Proj_const(irn);
306 classification |= arch_irn_class_branch;
308 if (! is_ia32_irn(irn))
309 return classification & ~arch_irn_class_normal;
311 if (is_ia32_Cnst(irn))
312 classification |= arch_irn_class_const;
315 classification |= arch_irn_class_load;
317 if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
318 classification |= arch_irn_class_store;
320 if (is_ia32_got_reload(irn))
321 classification |= arch_irn_class_reload;
323 return classification;
326 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
327 arch_irn_flags_t flags = arch_irn_flags_none;
330 return arch_irn_flags_ignore;
332 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
333 ir_node *pred = get_Proj_pred(irn);
335 if(is_ia32_irn(pred)) {
336 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
342 if (is_ia32_irn(irn)) {
343 flags |= get_ia32_flags(irn);
350 * The IA32 ABI callback object.
353 be_abi_call_flags_bits_t flags; /**< The call flags. */
354 const arch_isa_t *isa; /**< The ISA handle. */
355 const arch_env_t *aenv; /**< The architecture environment. */
356 ir_graph *irg; /**< The associated graph. */
359 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
360 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
363 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
364 set_ia32_frame_ent(irn, ent);
367 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
368 const ia32_irn_ops_t *ops = self;
370 if (get_ia32_frame_ent(irn)) {
371 if(is_ia32_Pop(irn)) {
372 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
374 /* Pop nodes modify the stack pointer before calculating the destination
375 * address, so fix this here
381 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
383 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
385 set_ia32_am_flavour(irn, am_flav);
387 add_ia32_am_offs_int(irn, bias);
391 static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
393 long proj = get_Proj_proj(irn);
394 ir_node *pred = get_Proj_pred(irn);
396 if (is_ia32_Push(pred) && proj == pn_ia32_Push_stack)
398 if (is_ia32_Pop(pred) && proj == pn_ia32_Pop_stack)
406 * Put all registers which are saved by the prologue/epilogue in a set.
408 * @param self The callback object.
409 * @param s The result set.
411 static void ia32_abi_dont_save_regs(void *self, pset *s)
413 ia32_abi_env_t *env = self;
414 if(env->flags.try_omit_fp)
415 pset_insert_ptr(s, env->isa->bp);
419 * Generate the routine prologue.
421 * @param self The callback object.
422 * @param mem A pointer to the mem node. Update this if you define new memory.
423 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
425 * @return The register which shall be used as a stack frame base.
427 * All nodes which define registers in @p reg_map must keep @p reg_map current.
429 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
431 ia32_abi_env_t *env = self;
432 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
433 ia32_code_gen_t *cg = isa->cg;
435 if (! env->flags.try_omit_fp) {
436 ir_node *bl = get_irg_start_block(env->irg);
437 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
438 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
439 ir_node *noreg = ia32_new_NoReg_gp(cg);
443 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
444 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
445 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
447 /* the push must have SP out register */
448 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
449 set_ia32_flags(push, arch_irn_flags_ignore);
451 /* move esp to ebp */
452 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
453 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
454 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
455 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
457 /* beware: the copy must be done before any other sp use */
458 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
459 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
460 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
461 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
463 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
464 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
473 * Generate the routine epilogue.
474 * @param self The callback object.
475 * @param bl The block for the epilog
476 * @param mem A pointer to the mem node. Update this if you define new memory.
477 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
478 * @return The register which shall be used as a stack frame base.
480 * All nodes which define registers in @p reg_map must keep @p reg_map current.
482 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
484 ia32_abi_env_t *env = self;
485 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
486 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
488 if (env->flags.try_omit_fp) {
489 /* simply remove the stack frame here */
490 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
491 add_irn_dep(curr_sp, *mem);
493 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
494 ia32_code_gen_t *cg = isa->cg;
495 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
497 /* gcc always emits a leave at the end of a routine */
498 if (1 || ARCH_AMD(isa->opt_arch)) {
502 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
503 set_ia32_flags(leave, arch_irn_flags_ignore);
504 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
505 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
507 ir_node *noreg = ia32_new_NoReg_gp(cg);
510 /* copy ebp to esp */
511 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
514 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
515 set_ia32_flags(pop, arch_irn_flags_ignore);
516 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
517 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
519 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
521 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
522 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
525 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
526 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
530 * Initialize the callback object.
531 * @param call The call object.
532 * @param aenv The architecture environment.
533 * @param irg The graph with the method.
534 * @return Some pointer. This pointer is passed to all other callback functions as self object.
536 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
538 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
539 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
540 env->flags = fl.bits;
543 env->isa = aenv->isa;
548 * Destroy the callback object.
549 * @param self The callback object.
551 static void ia32_abi_done(void *self) {
556 * Produces the type which sits between the stack args and the locals on the stack.
557 * it will contain the return address and space to store the old base pointer.
558 * @return The Firm type modeling the ABI between type.
560 static ir_type *ia32_abi_get_between_type(void *self)
562 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
563 static ir_type *omit_fp_between_type = NULL;
564 static ir_type *between_type = NULL;
566 ia32_abi_env_t *env = self;
568 if (! between_type) {
569 ir_entity *old_bp_ent;
570 ir_entity *ret_addr_ent;
571 ir_entity *omit_fp_ret_addr_ent;
573 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
574 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
576 between_type = new_type_struct(IDENT("ia32_between_type"));
577 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
578 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
580 set_entity_offset(old_bp_ent, 0);
581 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
582 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
583 set_type_state(between_type, layout_fixed);
585 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
586 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
588 set_entity_offset(omit_fp_ret_addr_ent, 0);
589 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
590 set_type_state(omit_fp_between_type, layout_fixed);
593 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
598 * Get the estimated cycle count for @p irn.
600 * @param self The this pointer.
601 * @param irn The node.
603 * @return The estimated cycle count for this operation
605 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
608 ia32_op_type_t op_tp;
609 const ia32_irn_ops_t *ops = self;
613 if (!is_ia32_irn(irn))
616 assert(is_ia32_irn(irn));
618 cost = get_ia32_latency(irn);
619 op_tp = get_ia32_op_type(irn);
621 if (is_ia32_CopyB(irn)) {
623 if (ARCH_INTEL(ops->cg->arch))
626 else if (is_ia32_CopyB_i(irn)) {
627 int size = get_tarval_long(get_ia32_Immop_tarval(irn));
628 cost = 20 + (int)ceil((4/3) * size);
629 if (ARCH_INTEL(ops->cg->arch))
632 /* in case of address mode operations add additional cycles */
633 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
635 In case of stack access add 5 cycles (we assume stack is in cache),
636 other memory operations cost 20 cycles.
638 cost += is_ia32_use_frame(irn) ? 5 : 20;
645 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
647 * @param irn The original operation
648 * @param i Index of the argument we want the inverse operation to yield
649 * @param inverse struct to be filled with the resulting inverse op
650 * @param obstack The obstack to use for allocation of the returned nodes array
651 * @return The inverse operation or NULL if operation invertible
653 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
657 ir_node *block, *noreg, *nomem;
660 /* we cannot invert non-ia32 irns */
661 if (! is_ia32_irn(irn))
664 /* operand must always be a real operand (not base, index or mem) */
665 if (i != 2 && i != 3)
668 /* we don't invert address mode operations */
669 if (get_ia32_op_type(irn) != ia32_Normal)
672 irg = get_irn_irg(irn);
673 block = get_nodes_block(irn);
674 mode = get_irn_mode(irn);
675 irn_mode = get_irn_mode(irn);
676 noreg = get_irn_n(irn, 0);
677 nomem = new_r_NoMem(irg);
678 dbg = get_irn_dbg_info(irn);
680 /* initialize structure */
681 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
685 switch (get_ia32_irn_opcode(irn)) {
687 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
688 /* we have an add with a const here */
689 /* invers == add with negated const */
690 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
692 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
693 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
694 set_ia32_commutative(inverse->nodes[0]);
696 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
697 /* we have an add with a symconst here */
698 /* invers == sub with const */
699 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
701 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
704 /* normal add: inverse == sub */
705 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, i ^ 1), nomem);
710 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
711 /* we have a sub with a const/symconst here */
712 /* invers == add with this const */
713 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
714 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
715 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
720 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, 3), nomem);
723 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, 2), (ir_node*) irn, nomem);
729 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
730 /* xor with const: inverse = xor */
731 inverse->nodes[0] = new_rd_ia32_Eor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
732 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
733 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
737 inverse->nodes[0] = new_rd_ia32_Eor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem);
742 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
746 case iro_ia32_Minus: {
747 inverse->nodes[0] = new_rd_ia32_Minus(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
752 /* inverse operation not supported */
760 * Get the mode that should be used for spilling value node
762 static ir_mode *get_spill_mode(ia32_code_gen_t *cg, const ir_node *node)
764 ir_mode *mode = get_irn_mode(node);
765 if (mode_is_float(mode)) {
767 // super exact spilling...
784 * Checks wether an addressmode reload for a node with mode mode is compatible
785 * with a spillslot of mode spill_mode
787 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
789 if(mode_is_float(mode)) {
790 return mode == spillmode;
797 * Check if irn can load it's operand at position i from memory (source addressmode).
798 * @param self Pointer to irn ops itself
799 * @param irn The irn to be checked
800 * @param i The operands position
801 * @return Non-Zero if operand can be loaded
803 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
804 const ia32_irn_ops_t *ops = self;
805 ia32_code_gen_t *cg = ops->cg;
806 ir_node *op = get_irn_n(irn, i);
807 const ir_mode *mode = get_irn_mode(op);
808 const ir_mode *spillmode = get_spill_mode(cg, op);
810 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
811 get_irn_arity(irn) != 5 || /* must be a binary operation */
812 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
813 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
814 ! ia32_is_spillmode_compatible(mode, spillmode) ||
815 (i != 2 && i != 3) || /* a "real" operand position must be requested */
816 (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
817 is_ia32_use_frame(irn)) /* must not already use frame */
823 static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
824 const ia32_irn_ops_t *ops = self;
825 ia32_code_gen_t *cg = ops->cg;
827 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
830 ir_node *tmp = get_irn_n(irn, 3);
831 set_irn_n(irn, 3, get_irn_n(irn, 2));
832 set_irn_n(irn, 2, tmp);
835 set_ia32_am_support(irn, ia32_am_Source);
836 set_ia32_op_type(irn, ia32_AddrModeS);
837 set_ia32_am_flavour(irn, ia32_B);
838 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
839 set_ia32_use_frame(irn);
840 set_ia32_got_reload(irn);
842 set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
843 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
844 set_irn_n(irn, 4, spill);
846 //FIXME DBG_OPT_AM_S(reload, irn);
849 static const be_abi_callbacks_t ia32_abi_callbacks = {
852 ia32_abi_get_between_type,
853 ia32_abi_dont_save_regs,
858 /* fill register allocator interface */
860 static const arch_irn_ops_if_t ia32_irn_ops_if = {
861 ia32_get_irn_reg_req,
866 ia32_get_frame_entity,
867 ia32_set_frame_entity,
868 ia32_set_frame_offset,
871 ia32_get_op_estimated_cost,
872 ia32_possible_memory_operand,
873 ia32_perform_memory_operand,
876 ia32_irn_ops_t ia32_irn_ops = {
883 /**************************************************
886 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
887 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
888 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
889 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
892 **************************************************/
895 * Transform the Thread Local Store base.
897 static void transform_tls(ir_graph *irg) {
898 ir_node *irn = get_irg_tls(irg);
901 dbg_info *dbg = get_irn_dbg_info(irn);
902 ir_node *blk = get_nodes_block(irn);
904 newn = new_rd_ia32_LdTls(dbg, irg, blk, get_irn_mode(irn));
907 set_irg_tls(irg, newn);
912 * Transforms the standard firm graph into
915 static void ia32_prepare_graph(void *self) {
916 ia32_code_gen_t *cg = self;
917 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
919 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
921 /* 1st: transform constants and psi condition trees */
922 ia32_pre_transform_phase(cg);
924 /* 2nd: transform all remaining nodes */
925 transform_tls(cg->irg);
926 ia32_transform_graph(cg);
927 // Matze: disabled for now. Because after transformation start block has no
928 // self-loop anymore so it will probably melt with its successor block.
930 // This will bring several nodes to the startblock and we still can't
931 // handle spill before the initial IncSP nicely
932 //local_optimize_graph(cg->irg);
935 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
937 /* 3rd: optimize address mode */
938 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
939 ia32_optimize_addressmode(cg);
942 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
944 DEBUG_ONLY(cg->mod = old_mod;)
948 * Dummy functions for hooks we don't need but which must be filled.
950 static void ia32_before_sched(void *self) {
953 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
956 ir_node *mem_proj = NULL;
961 mode = get_irn_mode(irn);
963 /* check if we already saw this node or the node has more than one user */
964 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) {
968 /* mark irn visited */
969 bitset_add_irn(already_visited, irn);
971 /* non-Tuple nodes with one user: ok, return */
972 if (get_irn_n_edges(irn) >= 1 && mode != mode_T) {
976 /* tuple node has one user which is not the mem proj-> ok */
977 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
978 mem_proj = ia32_get_proj_for_mode(irn, mode_M);
979 if (mem_proj == NULL) {
984 arity = get_irn_arity(irn);
985 for (i = 0; i < arity; ++i) {
986 ir_node *pred = get_irn_n(irn, i);
988 /* do not follow memory edges or we will accidentally remove stores */
989 if (get_irn_mode(pred) == mode_M) {
990 if(mem_proj != NULL) {
991 edges_reroute(mem_proj, pred, get_irn_irg(mem_proj));
997 set_irn_n(irn, i, new_Bad());
1000 The current node is about to be removed: if the predecessor
1001 has only this node as user, it need to be removed as well.
1003 if (get_irn_n_edges(pred) <= 1)
1004 remove_unused_nodes(pred, already_visited);
1007 // we need to set the presd to Bad again to also get the memory edges
1008 arity = get_irn_arity(irn);
1009 for (i = 0; i < arity; ++i) {
1010 set_irn_n(irn, i, new_Bad());
1013 if (sched_is_scheduled(irn)) {
1018 static void remove_unused_loads_walker(ir_node *irn, void *env) {
1019 bitset_t *already_visited = env;
1020 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
1021 remove_unused_nodes(irn, env);
1025 * Called before the register allocator.
1026 * Calculate a block schedule here. We need it for the x87
1027 * simulator and the emitter.
1029 static void ia32_before_ra(void *self) {
1030 ia32_code_gen_t *cg = self;
1031 bitset_t *already_visited = bitset_irg_alloca(cg->irg);
1034 Handle special case:
1035 There are sometimes unused loads, only pinned by memory.
1036 We need to remove those Loads and all other nodes which won't be used
1037 after removing the Load from schedule.
1039 irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
1044 * Transforms a be_Reload into a ia32 Load.
1046 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1047 ir_graph *irg = get_irn_irg(node);
1048 dbg_info *dbg = get_irn_dbg_info(node);
1049 ir_node *block = get_nodes_block(node);
1050 ir_entity *ent = be_get_frame_entity(node);
1051 ir_mode *mode = get_irn_mode(node);
1052 ir_mode *spillmode = get_spill_mode(cg, node);
1053 ir_node *noreg = ia32_new_NoReg_gp(cg);
1054 ir_node *sched_point = NULL;
1055 ir_node *ptr = get_irg_frame(irg);
1056 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1057 ir_node *new_op, *proj;
1058 const arch_register_t *reg;
1060 if (sched_is_scheduled(node)) {
1061 sched_point = sched_prev(node);
1064 if (mode_is_float(spillmode)) {
1066 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem);
1068 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem);
1071 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1073 set_ia32_am_support(new_op, ia32_am_Source);
1074 set_ia32_op_type(new_op, ia32_AddrModeS);
1075 set_ia32_am_flavour(new_op, ia32_B);
1076 set_ia32_ls_mode(new_op, spillmode);
1077 set_ia32_frame_ent(new_op, ent);
1078 set_ia32_use_frame(new_op);
1080 DBG_OPT_RELOAD2LD(node, new_op);
1082 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1085 sched_add_after(sched_point, new_op);
1086 sched_add_after(new_op, proj);
1091 /* copy the register from the old node to the new Load */
1092 reg = arch_get_irn_register(cg->arch_env, node);
1093 arch_set_irn_register(cg->arch_env, new_op, reg);
1095 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1097 exchange(node, proj);
1101 * Transforms a be_Spill node into a ia32 Store.
1103 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1104 ir_graph *irg = get_irn_irg(node);
1105 dbg_info *dbg = get_irn_dbg_info(node);
1106 ir_node *block = get_nodes_block(node);
1107 ir_entity *ent = be_get_frame_entity(node);
1108 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1109 ir_mode *mode = get_spill_mode(cg, spillval);
1110 ir_node *noreg = ia32_new_NoReg_gp(cg);
1111 ir_node *nomem = new_rd_NoMem(irg);
1112 ir_node *ptr = get_irg_frame(irg);
1113 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1115 ir_node *sched_point = NULL;
1117 if (sched_is_scheduled(node)) {
1118 sched_point = sched_prev(node);
1121 if (mode_is_float(mode)) {
1123 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem);
1125 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem);
1127 else if (get_mode_size_bits(mode) == 8) {
1128 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem);
1131 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem);
1134 set_ia32_am_support(store, ia32_am_Dest);
1135 set_ia32_op_type(store, ia32_AddrModeD);
1136 set_ia32_am_flavour(store, ia32_B);
1137 set_ia32_ls_mode(store, mode);
1138 set_ia32_frame_ent(store, ent);
1139 set_ia32_use_frame(store);
1141 DBG_OPT_SPILL2ST(node, store);
1142 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1145 sched_add_after(sched_point, store);
1149 exchange(node, store);
1152 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1153 ir_graph *irg = get_irn_irg(node);
1154 dbg_info *dbg = get_irn_dbg_info(node);
1155 ir_node *block = get_nodes_block(node);
1156 ir_node *noreg = ia32_new_NoReg_gp(cg);
1157 ir_node *frame = get_irg_frame(irg);
1159 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, noreg, sp, mem);
1161 set_ia32_frame_ent(push, ent);
1162 set_ia32_use_frame(push);
1163 set_ia32_op_type(push, ia32_AddrModeS);
1164 set_ia32_am_flavour(push, ia32_B);
1165 set_ia32_ls_mode(push, mode_Is);
1167 sched_add_before(schedpoint, push);
1171 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1172 ir_graph *irg = get_irn_irg(node);
1173 dbg_info *dbg = get_irn_dbg_info(node);
1174 ir_node *block = get_nodes_block(node);
1175 ir_node *noreg = ia32_new_NoReg_gp(cg);
1176 ir_node *frame = get_irg_frame(irg);
1178 ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, sp, new_NoMem());
1180 set_ia32_frame_ent(pop, ent);
1181 set_ia32_use_frame(pop);
1182 set_ia32_op_type(pop, ia32_AddrModeD);
1183 set_ia32_am_flavour(pop, ia32_am_OB);
1184 set_ia32_ls_mode(pop, mode_Is);
1186 sched_add_before(schedpoint, pop);
1191 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos, ir_node *schedpoint) {
1192 ir_graph *irg = get_irn_irg(node);
1193 dbg_info *dbg = get_irn_dbg_info(node);
1194 ir_node *block = get_nodes_block(node);
1195 ir_mode *spmode = mode_Iu;
1196 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1199 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1200 arch_set_irn_register(cg->arch_env, sp, spreg);
1201 sched_add_before(schedpoint, sp);
1207 * Transform memperm, currently we do this the ugly way and produce
1208 * push/pop into/from memory cascades. This is possible without using
1211 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1212 ir_graph *irg = get_irn_irg(node);
1213 ir_node *block = get_nodes_block(node);
1217 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1218 const ir_edge_t *edge;
1219 const ir_edge_t *next;
1222 arity = be_get_MemPerm_entity_arity(node);
1223 pops = alloca(arity * sizeof(pops[0]));
1226 for(i = 0; i < arity; ++i) {
1227 ir_entity *ent = be_get_MemPerm_in_entity(node, i);
1228 ir_type *enttype = get_entity_type(ent);
1229 int entbits = get_type_size_bits(enttype);
1230 ir_node *mem = get_irn_n(node, i + 1);
1233 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1235 push = create_push(cg, node, node, sp, mem, ent);
1236 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1238 // add another push after the first one
1239 push = create_push(cg, node, node, sp, mem, ent);
1240 add_ia32_am_offs_int(push, 4);
1241 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1244 set_irn_n(node, i, new_Bad());
1248 for(i = arity - 1; i >= 0; --i) {
1249 ir_entity *ent = be_get_MemPerm_out_entity(node, i);
1250 ir_type *enttype = get_entity_type(ent);
1251 int entbits = get_type_size_bits(enttype);
1255 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1257 pop = create_pop(cg, node, node, sp, ent);
1258 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1260 add_ia32_am_offs_int(pop, 4);
1262 // add another pop after the first one
1263 pop = create_pop(cg, node, node, sp, ent);
1264 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1271 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1272 sched_add_before(node, keep);
1274 // exchange memprojs
1275 foreach_out_edge_safe(node, edge, next) {
1276 ir_node *proj = get_edge_src_irn(edge);
1277 int p = get_Proj_proj(proj);
1281 set_Proj_pred(proj, pops[p]);
1282 set_Proj_proj(proj, 3);
1286 arity = get_irn_arity(node);
1287 for(i = 0; i < arity; ++i) {
1288 set_irn_n(node, i, new_Bad());
1294 * Block-Walker: Calls the transform functions Spill and Reload.
1296 static void ia32_after_ra_walker(ir_node *block, void *env) {
1297 ir_node *node, *prev;
1298 ia32_code_gen_t *cg = env;
1300 /* beware: the schedule is changed here */
1301 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1302 prev = sched_prev(node);
1304 if (be_is_Reload(node)) {
1305 transform_to_Load(cg, node);
1306 } else if (be_is_Spill(node)) {
1307 transform_to_Store(cg, node);
1308 } else if(be_is_MemPerm(node)) {
1309 transform_MemPerm(cg, node);
1315 * Collects nodes that need frame entities assigned.
1317 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1319 be_fec_env_t *env = data;
1321 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1322 const ir_mode *mode = get_irn_mode(node);
1323 int align = get_mode_size_bytes(mode);
1324 be_node_needs_frame_entity(env, node, mode, align);
1325 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1326 && is_ia32_use_frame(node)) {
1327 if (is_ia32_Load(node)) {
1328 const ir_mode *mode = get_ia32_ls_mode(node);
1329 int align = get_mode_size_bytes(mode);
1330 be_node_needs_frame_entity(env, node, mode, align);
1331 } else if (is_ia32_vfild(node)) {
1332 const ir_mode *mode = get_ia32_ls_mode(node);
1334 be_node_needs_frame_entity(env, node, mode, align);
1335 } else if (is_ia32_SetST0(node)) {
1336 const ir_mode *mode = get_ia32_ls_mode(node);
1338 be_node_needs_frame_entity(env, node, mode, align);
1341 if(!is_ia32_Store(node)
1342 && !is_ia32_xStore(node)
1343 && !is_ia32_xStoreSimple(node)
1344 && !is_ia32_vfist(node)) {
1353 * We transform Spill and Reload here. This needs to be done before
1354 * stack biasing otherwise we would miss the corrected offset for these nodes.
1356 static void ia32_after_ra(void *self) {
1357 ia32_code_gen_t *cg = self;
1358 ir_graph *irg = cg->irg;
1359 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1361 /* create and coalesce frame entities */
1362 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1363 be_assign_entities(fec_env);
1364 be_free_frame_entity_coalescer(fec_env);
1366 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1368 ia32_finish_irg(irg, cg);
1372 * Last touchups for the graph before emit: x87 simulation to replace the
1373 * virtual with real x87 instructions, creating a block schedule and peephole
1376 static void ia32_finish(void *self) {
1377 ia32_code_gen_t *cg = self;
1378 ir_graph *irg = cg->irg;
1380 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1381 if (cg->used_fp == fp_x87 || cg->force_sim) {
1382 x87_simulate_graph(cg->arch_env, cg->birg);
1385 /* create block schedule, this also removes empty blocks which might
1386 * produce critical edges */
1387 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1389 /* do peephole optimisations */
1390 ia32_peephole_optimization(irg, cg);
1394 * Emits the code, closes the output file and frees
1395 * the code generator interface.
1397 static void ia32_codegen(void *self) {
1398 ia32_code_gen_t *cg = self;
1399 ir_graph *irg = cg->irg;
1401 ia32_gen_routine(cg->isa->out, irg, cg);
1405 /* remove it from the isa */
1408 /* de-allocate code generator */
1409 del_set(cg->reg_set);
1413 static void *ia32_cg_init(be_irg_t *birg);
1415 static const arch_code_generator_if_t ia32_code_gen_if = {
1417 NULL, /* before abi introduce hook */
1420 ia32_before_sched, /* before scheduling hook */
1421 ia32_before_ra, /* before register allocation hook */
1422 ia32_after_ra, /* after register allocation hook */
1423 ia32_finish, /* called before codegen */
1424 ia32_codegen /* emit && done */
1428 * Initializes a IA32 code generator.
1430 static void *ia32_cg_init(be_irg_t *birg) {
1431 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1432 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1434 cg->impl = &ia32_code_gen_if;
1435 cg->irg = birg->irg;
1436 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1437 cg->arch_env = birg->main_env->arch_env;
1440 cg->blk_sched = NULL;
1441 cg->fp_kind = isa->fp_kind;
1442 cg->used_fp = fp_none;
1443 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1445 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1447 /* copy optimizations from isa for easier access */
1449 cg->arch = isa->arch;
1450 cg->opt_arch = isa->opt_arch;
1456 if (isa->name_obst) {
1457 obstack_free(isa->name_obst, NULL);
1458 obstack_init(isa->name_obst);
1462 cur_reg_set = cg->reg_set;
1464 ia32_irn_ops.cg = cg;
1466 return (arch_code_generator_t *)cg;
1471 /*****************************************************************
1472 * ____ _ _ _____ _____
1473 * | _ \ | | | | |_ _|/ ____| /\
1474 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1475 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1476 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1477 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1479 *****************************************************************/
1482 * Set output modes for GCC
1484 static const tarval_mode_info mo_integer = {
1491 * set the tarval output mode of all integer modes to decimal
1493 static void set_tarval_output_modes(void)
1497 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1498 ir_mode *mode = get_irp_mode(i);
1500 if (mode_is_int(mode))
1501 set_tarval_mode_output_option(mode, &mo_integer);
1505 const arch_isa_if_t ia32_isa_if;
1508 * The template that generates a new ISA object.
1509 * Note that this template can be changed by command line
1512 static ia32_isa_t ia32_isa_template = {
1514 &ia32_isa_if, /* isa interface implementation */
1515 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1516 &ia32_gp_regs[REG_EBP], /* base pointer register */
1517 -1, /* stack direction */
1518 NULL, /* main environment */
1520 NULL, /* 16bit register names */
1521 NULL, /* 8bit register names */
1525 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1526 IA32_OPT_DOAM | /* optimize address mode default: on */
1527 IA32_OPT_LEA | /* optimize for LEAs default: on */
1528 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1529 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1530 IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
1531 arch_pentium_4, /* instruction architecture */
1532 arch_pentium_4, /* optimize for architecture */
1533 fp_sse2, /* use sse2 unit */
1534 NULL, /* current code generator */
1535 NULL, /* output file */
1537 NULL, /* name obstack */
1538 0 /* name obst size */
1543 * Initializes the backend ISA.
1545 static void *ia32_init(FILE *file_handle) {
1546 static int inited = 0;
1552 set_tarval_output_modes();
1554 isa = xmalloc(sizeof(*isa));
1555 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1557 ia32_register_init(isa);
1558 ia32_create_opcodes();
1559 ia32_register_copy_attr_func();
1561 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1562 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1563 /* no SSE2 for these cpu's */
1564 isa->fp_kind = fp_x87;
1566 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1567 /* Pentium 4 don't like inc and dec instructions */
1568 isa->opt &= ~IA32_OPT_INCDEC;
1571 isa->regs_16bit = pmap_create();
1572 isa->regs_8bit = pmap_create();
1573 isa->types = pmap_create();
1574 isa->tv_ent = pmap_create();
1575 isa->out = file_handle;
1576 isa->cpu = ia32_init_machine_description();
1578 ia32_build_16bit_reg_map(isa->regs_16bit);
1579 ia32_build_8bit_reg_map(isa->regs_8bit);
1581 /* patch register names of x87 registers */
1582 ia32_st_regs[0].name = "st";
1583 ia32_st_regs[1].name = "st(1)";
1584 ia32_st_regs[2].name = "st(2)";
1585 ia32_st_regs[3].name = "st(3)";
1586 ia32_st_regs[4].name = "st(4)";
1587 ia32_st_regs[5].name = "st(5)";
1588 ia32_st_regs[6].name = "st(6)";
1589 ia32_st_regs[7].name = "st(7)";
1592 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1593 obstack_init(isa->name_obst);
1596 ia32_handle_intrinsics();
1597 ia32_switch_section(isa->out, NO_SECTION);
1598 fprintf(isa->out, "\t.intel_syntax\n");
1600 /* needed for the debug support */
1601 ia32_switch_section(isa->out, SECTION_TEXT);
1602 fprintf(isa->out, ".Ltext0:\n");
1612 * Closes the output file and frees the ISA structure.
1614 static void ia32_done(void *self) {
1615 ia32_isa_t *isa = self;
1617 /* emit now all global declarations */
1618 ia32_gen_decls(isa->out, isa->arch_isa.main_env);
1620 pmap_destroy(isa->regs_16bit);
1621 pmap_destroy(isa->regs_8bit);
1622 pmap_destroy(isa->tv_ent);
1623 pmap_destroy(isa->types);
1626 obstack_free(isa->name_obst, NULL);
1634 * Return the number of register classes for this architecture.
1635 * We report always these:
1636 * - the general purpose registers
1637 * - the SSE floating point register set
1638 * - the virtual floating point registers
1640 static int ia32_get_n_reg_class(const void *self) {
1645 * Return the register class for index i.
1647 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1648 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1650 return &ia32_reg_classes[CLASS_ia32_gp];
1652 return &ia32_reg_classes[CLASS_ia32_xmm];
1654 return &ia32_reg_classes[CLASS_ia32_vfp];
1658 * Get the register class which shall be used to store a value of a given mode.
1659 * @param self The this pointer.
1660 * @param mode The mode in question.
1661 * @return A register class which can hold values of the given mode.
1663 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1664 const ia32_isa_t *isa = self;
1665 if (mode_is_float(mode)) {
1666 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1669 return &ia32_reg_classes[CLASS_ia32_gp];
1673 * Get the ABI restrictions for procedure calls.
1674 * @param self The this pointer.
1675 * @param method_type The type of the method (procedure) in question.
1676 * @param abi The abi object to be modified
1678 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1679 const ia32_isa_t *isa = self;
1682 unsigned cc = get_method_calling_convention(method_type);
1683 int n = get_method_n_params(method_type);
1686 int i, ignore_1, ignore_2;
1688 const arch_register_t *reg;
1689 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1691 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1693 /* set abi flags for calls */
1694 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1695 call_flags.bits.store_args_sequential = use_push;
1696 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1697 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1698 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1700 /* set stack parameter passing style */
1701 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1703 /* collect the mode for each type */
1704 modes = alloca(n * sizeof(modes[0]));
1706 for (i = 0; i < n; i++) {
1707 tp = get_method_param_type(method_type, i);
1708 modes[i] = get_type_mode(tp);
1711 /* set register parameters */
1712 if (cc & cc_reg_param) {
1713 /* determine the number of parameters passed via registers */
1714 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1716 /* loop over all parameters and set the register requirements */
1717 for (i = 0; i <= biggest_n; i++) {
1718 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1719 assert(reg && "kaputt");
1720 be_abi_call_param_reg(abi, i, reg);
1727 /* set stack parameters */
1728 for (i = stack_idx; i < n; i++) {
1729 /* parameters on the stack are 32 bit aligned */
1730 be_abi_call_param_stack(abi, i, 4, 0, 0);
1734 /* set return registers */
1735 n = get_method_n_ress(method_type);
1737 assert(n <= 2 && "more than two results not supported");
1739 /* In case of 64bit returns, we will have two 32bit values */
1741 tp = get_method_res_type(method_type, 0);
1742 mode = get_type_mode(tp);
1744 assert(!mode_is_float(mode) && "two FP results not supported");
1746 tp = get_method_res_type(method_type, 1);
1747 mode = get_type_mode(tp);
1749 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1751 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1752 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1755 const arch_register_t *reg;
1757 tp = get_method_res_type(method_type, 0);
1758 assert(is_atomic_type(tp));
1759 mode = get_type_mode(tp);
1761 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1763 be_abi_call_res_reg(abi, 0, reg);
1768 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1769 return &ia32_irn_ops;
1772 const arch_irn_handler_t ia32_irn_handler = {
1776 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1777 return &ia32_irn_handler;
1780 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1781 return is_ia32_irn(irn) ? 1 : -1;
1785 * Initializes the code generator interface.
1787 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1788 return &ia32_code_gen_if;
1792 * Returns the estimated execution time of an ia32 irn.
1794 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1795 const arch_env_t *arch_env = env;
1796 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1799 list_sched_selector_t ia32_sched_selector;
1802 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1804 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1805 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1806 ia32_sched_selector.exectime = ia32_sched_exectime;
1807 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1808 return &ia32_sched_selector;
1811 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self) {
1816 * Returns the necessary byte alignment for storing a register of given class.
1818 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1819 ir_mode *mode = arch_register_class_mode(cls);
1820 int bytes = get_mode_size_bytes(mode);
1822 if (mode_is_float(mode) && bytes > 8)
1827 static const be_execution_unit_t ***ia32_get_allowed_execution_units(const void *self, const ir_node *irn) {
1828 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1829 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1830 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1833 static const be_execution_unit_t *_allowed_units_ALU[] = {
1834 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU1],
1835 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU2],
1836 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU3],
1837 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU4],
1840 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1841 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY1],
1842 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY2],
1843 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY3],
1844 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY4],
1847 static const be_execution_unit_t **_units_callret[] = {
1848 _allowed_units_BRANCH,
1851 static const be_execution_unit_t **_units_other[] = {
1855 static const be_execution_unit_t **_units_dummy[] = {
1856 _allowed_units_DUMMY,
1859 const be_execution_unit_t ***ret;
1861 if (is_ia32_irn(irn)) {
1862 ret = get_ia32_exec_units(irn);
1864 else if (is_be_node(irn)) {
1865 if (be_is_Call(irn) || be_is_Return(irn)) {
1866 ret = _units_callret;
1868 else if (be_is_Barrier(irn)) {
1883 * Return the abstract ia32 machine.
1885 static const be_machine_t *ia32_get_machine(const void *self) {
1886 const ia32_isa_t *isa = self;
1891 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1892 * @return 1 if allowed, 0 otherwise
1894 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
1896 ir_node *cmp, *cmp_a, *phi;
1899 /* we don't want long long an floating point Psi */
1900 #define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
1902 if (get_irn_mode(sel) != mode_b)
1905 cmp = get_Proj_pred(sel);
1906 cmp_a = get_Cmp_left(cmp);
1907 mode = get_irn_mode(cmp_a);
1909 if (IS_BAD_PSI_MODE(mode))
1912 /* check the Phi nodes */
1913 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1914 ir_node *pred_i = get_irn_n(phi, i);
1915 ir_node *pred_j = get_irn_n(phi, j);
1916 ir_mode *mode_i = get_irn_mode(pred_i);
1917 ir_mode *mode_j = get_irn_mode(pred_j);
1919 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1923 #undef IS_BAD_PSI_MODE
1928 static ia32_intrinsic_env_t intrinsic_env = {
1929 NULL, /**< the irg, these entities belong to */
1930 NULL, /**< entity for first div operand (move into FPU) */
1931 NULL, /**< entity for second div operand (move into FPU) */
1932 NULL, /**< entity for converts ll -> d */
1933 NULL, /**< entity for converts d -> ll */
1937 * Returns the libFirm configuration parameter for this backend.
1939 static const backend_params *ia32_get_libfirm_params(void) {
1940 static const opt_if_conv_info_t ifconv = {
1941 4, /* maxdepth, doesn't matter for Psi-conversion */
1942 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
1944 static const arch_dep_params_t ad = {
1945 1, /* also use subs */
1946 4, /* maximum shifts */
1947 31, /* maximum shift amount */
1949 1, /* allow Mulhs */
1950 1, /* allow Mulus */
1951 32 /* Mulh allowed up to 32 bit */
1953 static backend_params p = {
1954 NULL, /* no additional opcodes */
1955 NULL, /* will be set later */
1956 1, /* need dword lowering */
1957 ia32_create_intrinsic_fkt,
1958 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1959 NULL, /* will be set later */
1963 p.if_conv_info = &ifconv;
1968 /* instruction set architectures. */
1969 static const lc_opt_enum_int_items_t arch_items[] = {
1970 { "386", arch_i386, },
1971 { "486", arch_i486, },
1972 { "pentium", arch_pentium, },
1973 { "586", arch_pentium, },
1974 { "pentiumpro", arch_pentium_pro, },
1975 { "686", arch_pentium_pro, },
1976 { "pentiummmx", arch_pentium_mmx, },
1977 { "pentium2", arch_pentium_2, },
1978 { "p2", arch_pentium_2, },
1979 { "pentium3", arch_pentium_3, },
1980 { "p3", arch_pentium_3, },
1981 { "pentium4", arch_pentium_4, },
1982 { "p4", arch_pentium_4, },
1983 { "pentiumm", arch_pentium_m, },
1984 { "pm", arch_pentium_m, },
1985 { "core", arch_core, },
1987 { "athlon", arch_athlon, },
1988 { "athlon64", arch_athlon_64, },
1989 { "opteron", arch_opteron, },
1993 static lc_opt_enum_int_var_t arch_var = {
1994 &ia32_isa_template.arch, arch_items
1997 static lc_opt_enum_int_var_t opt_arch_var = {
1998 &ia32_isa_template.opt_arch, arch_items
2001 static const lc_opt_enum_int_items_t fp_unit_items[] = {
2003 { "sse2", fp_sse2 },
2007 static lc_opt_enum_int_var_t fp_unit_var = {
2008 &ia32_isa_template.fp_kind, fp_unit_items
2011 static const lc_opt_enum_int_items_t gas_items[] = {
2012 { "linux", ASM_LINUX_GAS },
2013 { "mingw", ASM_MINGW_GAS },
2017 static lc_opt_enum_int_var_t gas_var = {
2018 (int *)&asm_flavour, gas_items
2021 static const lc_opt_table_entry_t ia32_options[] = {
2022 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
2023 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
2024 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
2025 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
2026 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
2027 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
2028 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
2029 LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
2030 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2033 #endif /* WITH_LIBCORE */
2035 const arch_isa_if_t ia32_isa_if = {
2038 ia32_get_n_reg_class,
2040 ia32_get_reg_class_for_mode,
2042 ia32_get_irn_handler,
2043 ia32_get_code_generator_if,
2044 ia32_get_list_sched_selector,
2045 ia32_get_ilp_sched_selector,
2046 ia32_get_reg_class_alignment,
2047 ia32_get_libfirm_params,
2048 ia32_get_allowed_execution_units,
2052 void be_init_arch_ia32(void)
2054 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2055 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2057 lc_opt_add_table(ia32_grp, ia32_options);
2058 be_register_isa_if("ia32", &ia32_isa_if);
2061 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);