2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
18 #include <libcore/lc_opts.h>
19 #include <libcore/lc_opts_enum.h>
23 #include "pseudo_irg.h"
27 #include "iredges_t.h"
36 #include "../beabi.h" /* the general register allocator interface */
37 #include "../benode_t.h"
38 #include "../belower.h"
39 #include "../besched_t.h"
42 #include "../beirgmod.h"
43 #include "../be_dbgout.h"
44 #include "../beblocksched.h"
45 #include "../bemachine.h"
46 #include "../beilpsched.h"
47 #include "../bespillslots.h"
48 #include "../bemodule.h"
50 #include "bearch_ia32_t.h"
52 #include "ia32_new_nodes.h" /* ia32 nodes interface */
53 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
54 #include "gen_ia32_machine.h"
55 #include "ia32_gen_decls.h" /* interface declaration emitter */
56 #include "ia32_transform.h"
57 #include "ia32_emitter.h"
58 #include "ia32_map_regs.h"
59 #include "ia32_optimize.h"
61 #include "ia32_dbg_stat.h"
62 #include "ia32_finish.h"
63 #include "ia32_util.h"
65 #define DEBUG_MODULE "firm.be.ia32.isa"
68 static set *cur_reg_set = NULL;
70 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
72 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
73 create_const_node_func func, arch_register_t* reg)
83 block = get_irg_start_block(cg->irg);
84 res = func(NULL, cg->irg, block);
85 arch_set_irn_register(cg->arch_env, res, reg);
88 /* keep the node so it isn't accidently removed when unused ... */
90 keep = be_new_Keep(arch_register_get_class(reg), cg->irg, block, 1, in);
92 /* schedule the node if we already have a scheduled program */
93 startnode = get_irg_start(cg->irg);
94 if(sched_is_scheduled(startnode)) {
95 sched_add_after(startnode, res);
96 sched_add_after(res, keep);
102 /* Creates the unique per irg GP NoReg node. */
103 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
104 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
105 &ia32_gp_regs[REG_GP_NOREG]);
108 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
109 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
110 &ia32_vfp_regs[REG_VFP_NOREG]);
113 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
114 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
115 &ia32_xmm_regs[REG_XMM_NOREG]);
118 /* Creates the unique per irg FP NoReg node. */
119 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
120 return USE_SSE2(cg) ? ia32_new_NoReg_xmm(cg) : ia32_new_NoReg_vfp(cg);
123 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
124 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
125 &ia32_gp_regs[REG_GP_UKNWN]);
128 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
129 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
130 &ia32_vfp_regs[REG_VFP_UKNWN]);
133 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
134 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
135 &ia32_xmm_regs[REG_XMM_UKNWN]);
140 * Returns gp_noreg or fp_noreg, depending in input requirements.
142 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
143 arch_register_req_t req;
144 const arch_register_req_t *p_req;
146 p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
147 assert(p_req && "Missing register requirements");
148 if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
149 return ia32_new_NoReg_gp(cg);
151 return ia32_new_NoReg_fp(cg);
154 /**************************************************
157 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
158 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
159 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
160 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
163 **************************************************/
166 * Return register requirements for an ia32 node.
167 * If the node returns a tuple (mode_T) then the proj's
168 * will be asked for this information.
170 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
171 const ia32_irn_ops_t *ops = self;
172 const ia32_register_req_t *irn_req;
173 long node_pos = pos == -1 ? 0 : pos;
174 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
175 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
177 if (is_Block(irn) || mode == mode_X) {
178 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
182 if (mode == mode_T && pos < 0) {
183 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
187 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
194 DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
198 node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
199 irn = skip_Proj_const(irn);
201 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
204 if (is_ia32_irn(irn)) {
205 irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
206 if (irn_req == NULL) {
207 /* no requirements */
211 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
213 memcpy(req, &(irn_req->req), sizeof(*req));
215 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
216 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
217 req->other_same = get_irn_n(irn, irn_req->same_pos);
220 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
221 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
222 req->other_different = get_irn_n(irn, irn_req->different_pos);
226 /* treat Unknowns like Const with default requirements */
227 if (is_Unknown(irn)) {
228 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
229 if (mode_is_float(mode)) {
230 if (USE_SSE2(ops->cg))
231 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
233 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
235 else if (mode_is_int(mode) || mode_is_reference(mode))
236 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
237 else if (mode == mode_T || mode == mode_M) {
238 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
242 assert(0 && "unsupported Unknown-Mode");
245 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
253 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
255 const ia32_irn_ops_t *ops = self;
257 if (get_irn_mode(irn) == mode_X) {
261 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
264 pos = get_Proj_proj(irn);
265 irn = skip_Proj(irn);
268 if (is_ia32_irn(irn)) {
269 const arch_register_t **slots;
271 slots = get_ia32_slots(irn);
275 ia32_set_firm_reg(irn, reg, cur_reg_set);
279 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
281 const arch_register_t *reg = NULL;
285 if (get_irn_mode(irn) == mode_X) {
289 pos = get_Proj_proj(irn);
290 irn = skip_Proj_const(irn);
293 if (is_ia32_irn(irn)) {
294 const arch_register_t **slots;
295 slots = get_ia32_slots(irn);
299 reg = ia32_get_firm_reg(irn, cur_reg_set);
305 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
306 arch_irn_class_t classification = arch_irn_class_normal;
308 irn = skip_Proj_const(irn);
311 classification |= arch_irn_class_branch;
313 if (! is_ia32_irn(irn))
314 return classification & ~arch_irn_class_normal;
316 if (is_ia32_Cnst(irn))
317 classification |= arch_irn_class_const;
320 classification |= arch_irn_class_load;
322 if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
323 classification |= arch_irn_class_store;
325 if (is_ia32_need_stackent(irn))
326 classification |= arch_irn_class_reload;
328 return classification;
331 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
332 arch_irn_flags_t flags = arch_irn_flags_none;
335 return arch_irn_flags_ignore;
337 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
338 ir_node *pred = get_Proj_pred(irn);
340 if(is_ia32_irn(pred)) {
341 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
347 if (is_ia32_irn(irn)) {
348 flags |= get_ia32_flags(irn);
355 * The IA32 ABI callback object.
358 be_abi_call_flags_bits_t flags; /**< The call flags. */
359 const arch_isa_t *isa; /**< The ISA handle. */
360 const arch_env_t *aenv; /**< The architecture environment. */
361 ir_graph *irg; /**< The associated graph. */
364 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
365 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
368 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
369 set_ia32_frame_ent(irn, ent);
372 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
373 const ia32_irn_ops_t *ops = self;
375 if (get_ia32_frame_ent(irn)) {
376 ia32_am_flavour_t am_flav;
378 if (is_ia32_Pop(irn)) {
379 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
381 /* Pop nodes modify the stack pointer before calculating the destination
382 * address, so fix this here
388 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
390 am_flav = get_ia32_am_flavour(irn);
392 set_ia32_am_flavour(irn, am_flav);
394 add_ia32_am_offs_int(irn, bias);
398 static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
400 long proj = get_Proj_proj(irn);
401 ir_node *pred = get_Proj_pred(irn);
403 if (is_ia32_Push(pred) && proj == pn_ia32_Push_stack)
405 if (is_ia32_Pop(pred) && proj == pn_ia32_Pop_stack)
413 * Put all registers which are saved by the prologue/epilogue in a set.
415 * @param self The callback object.
416 * @param s The result set.
418 static void ia32_abi_dont_save_regs(void *self, pset *s)
420 ia32_abi_env_t *env = self;
421 if(env->flags.try_omit_fp)
422 pset_insert_ptr(s, env->isa->bp);
426 static unsigned count_callee_saves(ia32_code_gen_t *cg)
428 unsigned callee_saves = 0;
429 int c, num_reg_classes;
432 num_reg_classes = arch_isa_get_n_reg_class(isa);
433 for(c = 0; c < num_reg_classes; ++c) {
434 int r, num_registers;
435 arch_register_class_t *regclass = arch_isa_get_reg_class(isa, c);
437 num_registers = arch_register_class_n_regs(regclass);
438 for(r = 0; r < num_registers; ++r) {
439 arch_register_t *reg = arch_register_for_index(regclass, r);
440 if(arch_register_type_is(reg, callee_save))
448 static void create_callee_save_regprojs(ia32_code_gen_t *cg, ir_node *regparams)
450 int c, num_reg_classes;
454 num_reg_classes = arch_isa_get_n_reg_class(isa);
455 cg->initial_regs = obstack_alloc(cg->obst,
456 num_reg_classes * sizeof(cg->initial_regs[0]));
458 for(c = 0; c < num_reg_classes; ++c) {
459 int r, num_registers;
460 ir_node **initial_regclass;
461 arch_register_class_t *regclass = arch_isa_get_reg_class(isa, c);
463 num_registers = arch_register_class_n_regs(regclass);
464 initial_regclass = obstack_alloc(num_registers * sizeof(initial_regclass[0]));
465 for(r = 0; r < num_registers; ++r) {
467 arch_register_t *reg = arch_register_for_index(regclass, r);
468 if(!arch_register_type_is(reg, callee_save))
471 proj = new_r_Proj(irg, start_block, regparams, n);
472 be_set_constr_single_reg(regparams, n, reg);
473 arch_set_irn_register(cg->arch_env, proj, reg);
475 initial_regclass[r] = proj;
478 cg->initial_regs[c] = initial_regclass;
482 static void callee_saves_obstack_grow(ia32_code_gen_t *cg)
484 int c, num_reg_classes;
487 for(c = 0; c < num_reg_classes; ++c) {
488 int r, num_registers;
490 num_registers = arch_register_class_n_regs(regclass);
491 for(r = 0; r < num_registers; ++r) {
493 arch_register_t *reg = arch_register_for_index(regclass, r);
494 if(!arch_register_type_is(reg, callee_save))
497 proj = cg->initial_regs[c][r];
498 obstack_ptr_grow(cg->obst, proj);
503 static unsigned count_parameters_in_regs(ia32_code_gen_t *cg)
508 static void ia32_gen_prologue(ia32_code_gen_t *cg)
510 ir_graph *irg = cg->irg;
511 ir_node *start_block = get_irg_start_block(irg);
516 /* Create the regparams node */
517 n_regparams_out = count_callee_saves(cg) + count_parameters_in_regs(cg);
518 regparams = be_new_RegParams(irg, start_block, n_regparams_out);
520 create_callee_save_regprojs(cg, regparams);
522 /* Setup the stack */
524 ir_node *bl = get_irg_start_block(env->irg);
525 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
526 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
527 ir_node *noreg = ia32_new_NoReg_gp(cg);
531 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
532 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
533 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
535 /* the push must have SP out register */
536 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
537 set_ia32_flags(push, arch_irn_flags_ignore);
539 /* move esp to ebp */
540 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
541 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
542 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
543 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
545 /* beware: the copy must be done before any other sp use */
546 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
547 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
548 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
549 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
551 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
552 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
555 sp = be_new_IncSP(sp, irg, start_block, initialsp, BE_STACK_FRAME_SIZE_EXPAND);
556 set_irg_frame(irg, sp);
559 static void ia32_gen_epilogue(ia32_code_gen_t *cg)
561 int n_callee_saves = count_callee_saves(cg);
562 int n_results_regs = 0;
565 ir_node *end_block = get_irg_end_block(irg);
568 /* We have to make sure that all reloads occur before the stack frame
569 gets destroyed, so we create a barrier for all callee-save and return
571 barrier_size = n_callee_saves + n_results_regs;
572 barrier = be_new_Barrier(irg, end_block, barrier_size,
574 /* simply remove the stack frame here */
575 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
576 add_irn_dep(curr_sp, *mem);
581 * Generate the routine prologue.
583 * @param self The callback object.
584 * @param mem A pointer to the mem node. Update this if you define new memory.
585 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
587 * @return The register which shall be used as a stack frame base.
589 * All nodes which define registers in @p reg_map must keep @p reg_map current.
591 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
593 ia32_abi_env_t *env = self;
594 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
595 ia32_code_gen_t *cg = isa->cg;
597 if (! env->flags.try_omit_fp) {
598 ir_node *bl = get_irg_start_block(env->irg);
599 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
600 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
601 ir_node *noreg = ia32_new_NoReg_gp(cg);
605 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
606 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
607 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
609 /* the push must have SP out register */
610 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
611 set_ia32_flags(push, arch_irn_flags_ignore);
613 /* move esp to ebp */
614 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
615 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
616 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
617 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
619 /* beware: the copy must be done before any other sp use */
620 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
621 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
622 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
623 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
625 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
626 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
635 * Generate the routine epilogue.
636 * @param self The callback object.
637 * @param bl The block for the epilog
638 * @param mem A pointer to the mem node. Update this if you define new memory.
639 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
640 * @return The register which shall be used as a stack frame base.
642 * All nodes which define registers in @p reg_map must keep @p reg_map current.
644 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
646 ia32_abi_env_t *env = self;
647 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
648 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
650 if (env->flags.try_omit_fp) {
651 /* simply remove the stack frame here */
652 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
653 add_irn_dep(curr_sp, *mem);
655 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
656 ia32_code_gen_t *cg = isa->cg;
657 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
659 /* gcc always emits a leave at the end of a routine */
660 if (1 || ARCH_AMD(isa->opt_arch)) {
664 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
665 set_ia32_flags(leave, arch_irn_flags_ignore);
666 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
667 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
669 ir_node *noreg = ia32_new_NoReg_gp(cg);
672 /* copy ebp to esp */
673 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
676 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
677 set_ia32_flags(pop, arch_irn_flags_ignore);
678 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
679 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
681 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
683 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
684 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
687 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
688 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
692 * Initialize the callback object.
693 * @param call The call object.
694 * @param aenv The architecture environment.
695 * @param irg The graph with the method.
696 * @return Some pointer. This pointer is passed to all other callback functions as self object.
698 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
700 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
701 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
702 env->flags = fl.bits;
705 env->isa = aenv->isa;
710 * Destroy the callback object.
711 * @param self The callback object.
713 static void ia32_abi_done(void *self) {
718 * Produces the type which sits between the stack args and the locals on the stack.
719 * it will contain the return address and space to store the old base pointer.
720 * @return The Firm type modeling the ABI between type.
722 static ir_type *ia32_abi_get_between_type(void *self)
724 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
725 static ir_type *omit_fp_between_type = NULL;
726 static ir_type *between_type = NULL;
728 ia32_abi_env_t *env = self;
730 if (! between_type) {
731 ir_entity *old_bp_ent;
732 ir_entity *ret_addr_ent;
733 ir_entity *omit_fp_ret_addr_ent;
735 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
736 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
738 between_type = new_type_struct(IDENT("ia32_between_type"));
739 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
740 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
742 set_entity_offset(old_bp_ent, 0);
743 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
744 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
745 set_type_state(between_type, layout_fixed);
747 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
748 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
750 set_entity_offset(omit_fp_ret_addr_ent, 0);
751 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
752 set_type_state(omit_fp_between_type, layout_fixed);
755 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
760 * Get the estimated cycle count for @p irn.
762 * @param self The this pointer.
763 * @param irn The node.
765 * @return The estimated cycle count for this operation
767 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
770 ia32_op_type_t op_tp;
771 const ia32_irn_ops_t *ops = self;
775 if (!is_ia32_irn(irn))
778 assert(is_ia32_irn(irn));
780 cost = get_ia32_latency(irn);
781 op_tp = get_ia32_op_type(irn);
783 if (is_ia32_CopyB(irn)) {
785 if (ARCH_INTEL(ops->cg->arch))
788 else if (is_ia32_CopyB_i(irn)) {
789 int size = get_tarval_long(get_ia32_Immop_tarval(irn));
790 cost = 20 + (int)ceil((4/3) * size);
791 if (ARCH_INTEL(ops->cg->arch))
794 /* in case of address mode operations add additional cycles */
795 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
797 In case of stack access add 5 cycles (we assume stack is in cache),
798 other memory operations cost 20 cycles.
800 cost += is_ia32_use_frame(irn) ? 5 : 20;
807 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
809 * @param irn The original operation
810 * @param i Index of the argument we want the inverse operation to yield
811 * @param inverse struct to be filled with the resulting inverse op
812 * @param obstack The obstack to use for allocation of the returned nodes array
813 * @return The inverse operation or NULL if operation invertible
815 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
819 ir_node *block, *noreg, *nomem;
822 /* we cannot invert non-ia32 irns */
823 if (! is_ia32_irn(irn))
826 /* operand must always be a real operand (not base, index or mem) */
827 if (i != 2 && i != 3)
830 /* we don't invert address mode operations */
831 if (get_ia32_op_type(irn) != ia32_Normal)
834 irg = get_irn_irg(irn);
835 block = get_nodes_block(irn);
836 mode = get_irn_mode(irn);
837 irn_mode = get_irn_mode(irn);
838 noreg = get_irn_n(irn, 0);
839 nomem = new_r_NoMem(irg);
840 dbg = get_irn_dbg_info(irn);
842 /* initialize structure */
843 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
847 switch (get_ia32_irn_opcode(irn)) {
849 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
850 /* we have an add with a const here */
851 /* invers == add with negated const */
852 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
854 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
855 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
856 set_ia32_commutative(inverse->nodes[0]);
858 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
859 /* we have an add with a symconst here */
860 /* invers == sub with const */
861 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
863 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
866 /* normal add: inverse == sub */
867 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, i ^ 1), nomem);
872 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
873 /* we have a sub with a const/symconst here */
874 /* invers == add with this const */
875 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
876 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
877 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
882 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, 3), nomem);
885 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, 2), (ir_node*) irn, nomem);
891 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
892 /* xor with const: inverse = xor */
893 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
894 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
895 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
899 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem);
904 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
909 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
914 /* inverse operation not supported */
921 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
923 if(mode_is_float(mode))
930 * Get the mode that should be used for spilling value node
932 static ir_mode *get_spill_mode(const ir_node *node)
934 ir_mode *mode = get_irn_mode(node);
935 return get_spill_mode_mode(mode);
939 * Checks wether an addressmode reload for a node with mode mode is compatible
940 * with a spillslot of mode spill_mode
942 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
944 if(mode_is_float(mode)) {
945 return mode == spillmode;
952 * Check if irn can load it's operand at position i from memory (source addressmode).
953 * @param self Pointer to irn ops itself
954 * @param irn The irn to be checked
955 * @param i The operands position
956 * @return Non-Zero if operand can be loaded
958 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
959 ir_node *op = get_irn_n(irn, i);
960 const ir_mode *mode = get_irn_mode(op);
961 const ir_mode *spillmode = get_spill_mode(op);
963 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
964 get_irn_arity(irn) != 5 || /* must be a binary operation */
965 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
966 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
967 ! ia32_is_spillmode_compatible(mode, spillmode) ||
968 (i != 2 && i != 3) || /* a "real" operand position must be requested */
969 (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
970 is_ia32_use_frame(irn)) /* must not already use frame */
976 static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
977 const ia32_irn_ops_t *ops = self;
978 ia32_code_gen_t *cg = ops->cg;
980 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
983 ir_node *tmp = get_irn_n(irn, 3);
984 set_irn_n(irn, 3, get_irn_n(irn, 2));
985 set_irn_n(irn, 2, tmp);
988 set_ia32_am_support(irn, ia32_am_Source);
989 set_ia32_op_type(irn, ia32_AddrModeS);
990 set_ia32_am_flavour(irn, ia32_B);
991 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
992 set_ia32_use_frame(irn);
993 set_ia32_need_stackent(irn);
995 set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
996 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
997 set_irn_n(irn, 4, spill);
999 //FIXME DBG_OPT_AM_S(reload, irn);
1002 static const be_abi_callbacks_t ia32_abi_callbacks = {
1005 ia32_abi_get_between_type,
1006 ia32_abi_dont_save_regs,
1011 /* fill register allocator interface */
1013 static const arch_irn_ops_if_t ia32_irn_ops_if = {
1014 ia32_get_irn_reg_req,
1019 ia32_get_frame_entity,
1020 ia32_set_frame_entity,
1021 ia32_set_frame_offset,
1024 ia32_get_op_estimated_cost,
1025 ia32_possible_memory_operand,
1026 ia32_perform_memory_operand,
1029 ia32_irn_ops_t ia32_irn_ops = {
1036 /**************************************************
1039 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
1040 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
1041 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
1042 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
1045 **************************************************/
1048 * Transforms the standard firm graph into
1049 * an ia32 firm graph
1051 static void ia32_prepare_graph(void *self) {
1052 ia32_code_gen_t *cg = self;
1053 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
1055 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
1057 /* 1st: transform psi condition trees */
1058 ia32_pre_transform_phase(cg);
1060 /* 2nd: transform all remaining nodes */
1061 ia32_transform_graph(cg);
1062 // Matze: disabled for now. Because after transformation start block has no
1063 // self-loop anymore so it might be merged with its successor block. This
1064 // will bring several nodes to the startblock which sometimes get scheduled
1065 // before the initial IncSP/Barrier
1066 //local_optimize_graph(cg->irg);
1069 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
1071 /* 3rd: optimize address mode */
1072 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
1073 ia32_optimize_addressmode(cg);
1076 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
1078 DEBUG_ONLY(cg->mod = old_mod;)
1082 * Dummy functions for hooks we don't need but which must be filled.
1084 static void ia32_before_sched(void *self) {
1087 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
1090 ir_node *mem_proj = NULL;
1095 mode = get_irn_mode(irn);
1097 /* check if we already saw this node or the node has more than one user */
1098 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) {
1102 /* mark irn visited */
1103 bitset_add_irn(already_visited, irn);
1105 /* non-Tuple nodes with one user: ok, return */
1106 if (get_irn_n_edges(irn) >= 1 && mode != mode_T) {
1110 /* tuple node has one user which is not the mem proj-> ok */
1111 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
1112 mem_proj = ia32_get_proj_for_mode(irn, mode_M);
1113 if (mem_proj == NULL) {
1118 arity = get_irn_arity(irn);
1119 for (i = 0; i < arity; ++i) {
1120 ir_node *pred = get_irn_n(irn, i);
1122 /* do not follow memory edges or we will accidentally remove stores */
1123 if (get_irn_mode(pred) == mode_M) {
1124 if(mem_proj != NULL) {
1125 edges_reroute(mem_proj, pred, get_irn_irg(mem_proj));
1131 set_irn_n(irn, i, new_Bad());
1134 The current node is about to be removed: if the predecessor
1135 has only this node as user, it need to be removed as well.
1137 if (get_irn_n_edges(pred) <= 1)
1138 remove_unused_nodes(pred, already_visited);
1141 // we need to set the presd to Bad again to also get the memory edges
1142 arity = get_irn_arity(irn);
1143 for (i = 0; i < arity; ++i) {
1144 set_irn_n(irn, i, new_Bad());
1147 if (sched_is_scheduled(irn)) {
1152 static void remove_unused_loads_walker(ir_node *irn, void *env) {
1153 bitset_t *already_visited = env;
1154 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
1155 remove_unused_nodes(irn, env);
1159 * Called before the register allocator.
1160 * Calculate a block schedule here. We need it for the x87
1161 * simulator and the emitter.
1163 static void ia32_before_ra(void *self) {
1164 ia32_code_gen_t *cg = self;
1165 bitset_t *already_visited = bitset_irg_alloca(cg->irg);
1168 Handle special case:
1169 There are sometimes unused loads, only pinned by memory.
1170 We need to remove those Loads and all other nodes which won't be used
1171 after removing the Load from schedule.
1173 irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
1178 * Transforms a be_Reload into a ia32 Load.
1180 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1181 ir_graph *irg = get_irn_irg(node);
1182 dbg_info *dbg = get_irn_dbg_info(node);
1183 ir_node *block = get_nodes_block(node);
1184 ir_entity *ent = be_get_frame_entity(node);
1185 ir_mode *mode = get_irn_mode(node);
1186 ir_mode *spillmode = get_spill_mode(node);
1187 ir_node *noreg = ia32_new_NoReg_gp(cg);
1188 ir_node *sched_point = NULL;
1189 ir_node *ptr = get_irg_frame(irg);
1190 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1191 ir_node *new_op, *proj;
1192 const arch_register_t *reg;
1194 if (sched_is_scheduled(node)) {
1195 sched_point = sched_prev(node);
1198 if (mode_is_float(spillmode)) {
1200 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem);
1202 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem);
1204 else if (get_mode_size_bits(spillmode) == 128) {
1205 // Reload 128 bit sse registers
1206 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1209 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1211 set_ia32_am_support(new_op, ia32_am_Source);
1212 set_ia32_op_type(new_op, ia32_AddrModeS);
1213 set_ia32_am_flavour(new_op, ia32_B);
1214 set_ia32_ls_mode(new_op, spillmode);
1215 set_ia32_frame_ent(new_op, ent);
1216 set_ia32_use_frame(new_op);
1218 DBG_OPT_RELOAD2LD(node, new_op);
1220 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1223 sched_add_after(sched_point, new_op);
1224 sched_add_after(new_op, proj);
1229 /* copy the register from the old node to the new Load */
1230 reg = arch_get_irn_register(cg->arch_env, node);
1231 arch_set_irn_register(cg->arch_env, new_op, reg);
1233 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1235 exchange(node, proj);
1239 * Transforms a be_Spill node into a ia32 Store.
1241 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1242 ir_graph *irg = get_irn_irg(node);
1243 dbg_info *dbg = get_irn_dbg_info(node);
1244 ir_node *block = get_nodes_block(node);
1245 ir_entity *ent = be_get_frame_entity(node);
1246 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1247 ir_mode *mode = get_spill_mode(spillval);
1248 ir_node *noreg = ia32_new_NoReg_gp(cg);
1249 ir_node *nomem = new_rd_NoMem(irg);
1250 ir_node *ptr = get_irg_frame(irg);
1251 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1253 ir_node *sched_point = NULL;
1255 if (sched_is_scheduled(node)) {
1256 sched_point = sched_prev(node);
1259 if (mode_is_float(mode)) {
1261 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem);
1263 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem);
1265 else if (get_mode_size_bits(mode) == 128) {
1266 // Spill 128 bit SSE registers
1267 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, val, nomem);
1269 else if (get_mode_size_bits(mode) == 8) {
1270 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem);
1273 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem);
1276 set_ia32_am_support(store, ia32_am_Dest);
1277 set_ia32_op_type(store, ia32_AddrModeD);
1278 set_ia32_am_flavour(store, ia32_B);
1279 set_ia32_ls_mode(store, mode);
1280 set_ia32_frame_ent(store, ent);
1281 set_ia32_use_frame(store);
1283 DBG_OPT_SPILL2ST(node, store);
1284 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1287 sched_add_after(sched_point, store);
1291 exchange(node, store);
1294 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1295 ir_graph *irg = get_irn_irg(node);
1296 dbg_info *dbg = get_irn_dbg_info(node);
1297 ir_node *block = get_nodes_block(node);
1298 ir_node *noreg = ia32_new_NoReg_gp(cg);
1299 ir_node *frame = get_irg_frame(irg);
1301 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, noreg, sp, mem);
1303 set_ia32_frame_ent(push, ent);
1304 set_ia32_use_frame(push);
1305 set_ia32_op_type(push, ia32_AddrModeS);
1306 set_ia32_am_flavour(push, ia32_B);
1307 set_ia32_ls_mode(push, mode_Is);
1309 sched_add_before(schedpoint, push);
1313 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1314 ir_graph *irg = get_irn_irg(node);
1315 dbg_info *dbg = get_irn_dbg_info(node);
1316 ir_node *block = get_nodes_block(node);
1317 ir_node *noreg = ia32_new_NoReg_gp(cg);
1318 ir_node *frame = get_irg_frame(irg);
1320 ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, sp, new_NoMem());
1322 set_ia32_frame_ent(pop, ent);
1323 set_ia32_use_frame(pop);
1324 set_ia32_op_type(pop, ia32_AddrModeD);
1325 set_ia32_am_flavour(pop, ia32_am_OB);
1326 set_ia32_ls_mode(pop, mode_Is);
1328 sched_add_before(schedpoint, pop);
1333 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos, ir_node *schedpoint) {
1334 ir_graph *irg = get_irn_irg(node);
1335 dbg_info *dbg = get_irn_dbg_info(node);
1336 ir_node *block = get_nodes_block(node);
1337 ir_mode *spmode = mode_Iu;
1338 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1341 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1342 arch_set_irn_register(cg->arch_env, sp, spreg);
1343 sched_add_before(schedpoint, sp);
1349 * Transform memperm, currently we do this the ugly way and produce
1350 * push/pop into/from memory cascades. This is possible without using
1353 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1354 ir_graph *irg = get_irn_irg(node);
1355 ir_node *block = get_nodes_block(node);
1359 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1360 const ir_edge_t *edge;
1361 const ir_edge_t *next;
1364 arity = be_get_MemPerm_entity_arity(node);
1365 pops = alloca(arity * sizeof(pops[0]));
1368 for(i = 0; i < arity; ++i) {
1369 ir_entity *ent = be_get_MemPerm_in_entity(node, i);
1370 ir_type *enttype = get_entity_type(ent);
1371 int entbits = get_type_size_bits(enttype);
1372 ir_node *mem = get_irn_n(node, i + 1);
1375 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1377 push = create_push(cg, node, node, sp, mem, ent);
1378 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1380 // add another push after the first one
1381 push = create_push(cg, node, node, sp, mem, ent);
1382 add_ia32_am_offs_int(push, 4);
1383 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1386 set_irn_n(node, i, new_Bad());
1390 for(i = arity - 1; i >= 0; --i) {
1391 ir_entity *ent = be_get_MemPerm_out_entity(node, i);
1392 ir_type *enttype = get_entity_type(ent);
1393 int entbits = get_type_size_bits(enttype);
1397 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1399 pop = create_pop(cg, node, node, sp, ent);
1400 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1402 add_ia32_am_offs_int(pop, 4);
1404 // add another pop after the first one
1405 pop = create_pop(cg, node, node, sp, ent);
1406 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1413 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1414 sched_add_before(node, keep);
1416 // exchange memprojs
1417 foreach_out_edge_safe(node, edge, next) {
1418 ir_node *proj = get_edge_src_irn(edge);
1419 int p = get_Proj_proj(proj);
1423 set_Proj_pred(proj, pops[p]);
1424 set_Proj_proj(proj, 3);
1428 arity = get_irn_arity(node);
1429 for(i = 0; i < arity; ++i) {
1430 set_irn_n(node, i, new_Bad());
1436 * Block-Walker: Calls the transform functions Spill and Reload.
1438 static void ia32_after_ra_walker(ir_node *block, void *env) {
1439 ir_node *node, *prev;
1440 ia32_code_gen_t *cg = env;
1442 /* beware: the schedule is changed here */
1443 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1444 prev = sched_prev(node);
1446 if (be_is_Reload(node)) {
1447 transform_to_Load(cg, node);
1448 } else if (be_is_Spill(node)) {
1449 transform_to_Store(cg, node);
1450 } else if(be_is_MemPerm(node)) {
1451 transform_MemPerm(cg, node);
1457 * Collects nodes that need frame entities assigned.
1459 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1461 be_fec_env_t *env = data;
1463 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1464 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1465 int align = get_mode_size_bytes(mode);
1466 be_node_needs_frame_entity(env, node, mode, align);
1467 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1468 && is_ia32_use_frame(node)) {
1469 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1470 const ir_mode *mode = get_ia32_ls_mode(node);
1471 int align = get_mode_size_bytes(mode);
1472 be_node_needs_frame_entity(env, node, mode, align);
1473 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)) {
1474 const ir_mode *mode = get_ia32_ls_mode(node);
1476 be_node_needs_frame_entity(env, node, mode, align);
1477 } else if (is_ia32_SetST0(node)) {
1478 const ir_mode *mode = get_ia32_ls_mode(node);
1480 be_node_needs_frame_entity(env, node, mode, align);
1483 if(!is_ia32_Store(node)
1484 && !is_ia32_xStore(node)
1485 && !is_ia32_xStoreSimple(node)
1486 && !is_ia32_vfist(node)
1487 && !is_ia32_GetST0(node)) {
1496 * We transform Spill and Reload here. This needs to be done before
1497 * stack biasing otherwise we would miss the corrected offset for these nodes.
1499 static void ia32_after_ra(void *self) {
1500 ia32_code_gen_t *cg = self;
1501 ir_graph *irg = cg->irg;
1502 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1504 /* create and coalesce frame entities */
1505 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1506 be_assign_entities(fec_env);
1507 be_free_frame_entity_coalescer(fec_env);
1509 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1511 ia32_finish_irg(irg, cg);
1515 * Last touchups for the graph before emit: x87 simulation to replace the
1516 * virtual with real x87 instructions, creating a block schedule and peephole
1519 static void ia32_finish(void *self) {
1520 ia32_code_gen_t *cg = self;
1521 ir_graph *irg = cg->irg;
1523 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1524 if (cg->used_fp == fp_x87 || cg->force_sim) {
1525 x87_simulate_graph(cg->arch_env, cg->birg);
1528 /* create block schedule, this also removes empty blocks which might
1529 * produce critical edges */
1530 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1532 /* do peephole optimisations */
1533 ia32_peephole_optimization(irg, cg);
1537 * Emits the code, closes the output file and frees
1538 * the code generator interface.
1540 static void ia32_codegen(void *self) {
1541 ia32_code_gen_t *cg = self;
1542 ir_graph *irg = cg->irg;
1544 ia32_gen_routine(cg, cg->isa->out, irg);
1548 /* remove it from the isa */
1551 /* de-allocate code generator */
1552 del_set(cg->reg_set);
1556 static void *ia32_cg_init(be_irg_t *birg);
1558 static const arch_code_generator_if_t ia32_code_gen_if = {
1560 NULL, /* before abi introduce hook */
1563 ia32_before_sched, /* before scheduling hook */
1564 ia32_before_ra, /* before register allocation hook */
1565 ia32_after_ra, /* after register allocation hook */
1566 ia32_finish, /* called before codegen */
1567 ia32_codegen /* emit && done */
1571 * Initializes a IA32 code generator.
1573 static void *ia32_cg_init(be_irg_t *birg) {
1574 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1575 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1577 cg->impl = &ia32_code_gen_if;
1578 cg->irg = birg->irg;
1579 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1580 cg->arch_env = birg->main_env->arch_env;
1583 cg->blk_sched = NULL;
1584 cg->fp_kind = isa->fp_kind;
1585 cg->used_fp = fp_none;
1586 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1588 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1590 /* copy optimizations from isa for easier access */
1592 cg->arch = isa->arch;
1593 cg->opt_arch = isa->opt_arch;
1599 if (isa->name_obst) {
1600 obstack_free(isa->name_obst, NULL);
1601 obstack_init(isa->name_obst);
1605 cur_reg_set = cg->reg_set;
1607 ia32_irn_ops.cg = cg;
1609 return (arch_code_generator_t *)cg;
1614 /*****************************************************************
1615 * ____ _ _ _____ _____
1616 * | _ \ | | | | |_ _|/ ____| /\
1617 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1618 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1619 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1620 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1622 *****************************************************************/
1625 * Set output modes for GCC
1627 static const tarval_mode_info mo_integer = {
1634 * set the tarval output mode of all integer modes to decimal
1636 static void set_tarval_output_modes(void)
1640 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1641 ir_mode *mode = get_irp_mode(i);
1643 if (mode_is_int(mode))
1644 set_tarval_mode_output_option(mode, &mo_integer);
1648 const arch_isa_if_t ia32_isa_if;
1651 * The template that generates a new ISA object.
1652 * Note that this template can be changed by command line
1655 static ia32_isa_t ia32_isa_template = {
1657 &ia32_isa_if, /* isa interface implementation */
1658 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1659 &ia32_gp_regs[REG_EBP], /* base pointer register */
1660 -1, /* stack direction */
1661 NULL, /* main environment */
1663 NULL, /* 16bit register names */
1664 NULL, /* 8bit register names */
1668 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1669 IA32_OPT_DOAM | /* optimize address mode default: on */
1670 IA32_OPT_LEA | /* optimize for LEAs default: on */
1671 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1672 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1673 IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
1674 arch_pentium_4, /* instruction architecture */
1675 arch_pentium_4, /* optimize for architecture */
1676 fp_sse2, /* use sse2 unit */
1677 NULL, /* current code generator */
1678 NULL, /* output file */
1680 NULL, /* name obstack */
1681 0 /* name obst size */
1686 * Initializes the backend ISA.
1688 static void *ia32_init(FILE *file_handle) {
1689 static int inited = 0;
1695 set_tarval_output_modes();
1697 isa = xmalloc(sizeof(*isa));
1698 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1700 ia32_register_init(isa);
1701 ia32_create_opcodes();
1702 ia32_register_copy_attr_func();
1704 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1705 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1706 /* no SSE2 for these cpu's */
1707 isa->fp_kind = fp_x87;
1709 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1710 /* Pentium 4 don't like inc and dec instructions */
1711 isa->opt &= ~IA32_OPT_INCDEC;
1714 isa->regs_16bit = pmap_create();
1715 isa->regs_8bit = pmap_create();
1716 isa->types = pmap_create();
1717 isa->tv_ent = pmap_create();
1718 isa->out = file_handle;
1719 isa->cpu = ia32_init_machine_description();
1721 ia32_build_16bit_reg_map(isa->regs_16bit);
1722 ia32_build_8bit_reg_map(isa->regs_8bit);
1724 /* patch register names of x87 registers */
1725 ia32_st_regs[0].name = "st";
1726 ia32_st_regs[1].name = "st(1)";
1727 ia32_st_regs[2].name = "st(2)";
1728 ia32_st_regs[3].name = "st(3)";
1729 ia32_st_regs[4].name = "st(4)";
1730 ia32_st_regs[5].name = "st(5)";
1731 ia32_st_regs[6].name = "st(6)";
1732 ia32_st_regs[7].name = "st(7)";
1735 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1736 obstack_init(isa->name_obst);
1739 ia32_handle_intrinsics();
1740 ia32_switch_section(isa->out, NO_SECTION);
1742 /* needed for the debug support */
1743 ia32_switch_section(isa->out, SECTION_TEXT);
1744 fprintf(isa->out, ".Ltext0:\n");
1754 * Closes the output file and frees the ISA structure.
1756 static void ia32_done(void *self) {
1757 ia32_isa_t *isa = self;
1759 /* emit now all global declarations */
1760 ia32_gen_decls(isa->out, isa->arch_isa.main_env);
1762 pmap_destroy(isa->regs_16bit);
1763 pmap_destroy(isa->regs_8bit);
1764 pmap_destroy(isa->tv_ent);
1765 pmap_destroy(isa->types);
1768 obstack_free(isa->name_obst, NULL);
1776 * Return the number of register classes for this architecture.
1777 * We report always these:
1778 * - the general purpose registers
1779 * - the SSE floating point register set
1780 * - the virtual floating point registers
1781 * - the SSE vector register set
1783 static int ia32_get_n_reg_class(const void *self) {
1788 * Return the register class for index i.
1790 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1793 return &ia32_reg_classes[CLASS_ia32_gp];
1795 return &ia32_reg_classes[CLASS_ia32_xmm];
1797 return &ia32_reg_classes[CLASS_ia32_vfp];
1799 assert(0 && "Invalid ia32 register class requested.");
1805 * Get the register class which shall be used to store a value of a given mode.
1806 * @param self The this pointer.
1807 * @param mode The mode in question.
1808 * @return A register class which can hold values of the given mode.
1810 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1811 const ia32_isa_t *isa = self;
1812 if (mode_is_float(mode)) {
1813 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1816 return &ia32_reg_classes[CLASS_ia32_gp];
1820 * Get the ABI restrictions for procedure calls.
1821 * @param self The this pointer.
1822 * @param method_type The type of the method (procedure) in question.
1823 * @param abi The abi object to be modified
1825 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1826 const ia32_isa_t *isa = self;
1829 unsigned cc = get_method_calling_convention(method_type);
1830 int n = get_method_n_params(method_type);
1833 int i, ignore_1, ignore_2;
1835 const arch_register_t *reg;
1836 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1838 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1840 /* set abi flags for calls */
1841 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1842 call_flags.bits.store_args_sequential = use_push;
1843 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1844 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1845 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1847 /* set stack parameter passing style */
1848 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1850 /* collect the mode for each type */
1851 modes = alloca(n * sizeof(modes[0]));
1853 for (i = 0; i < n; i++) {
1854 tp = get_method_param_type(method_type, i);
1855 modes[i] = get_type_mode(tp);
1858 /* set register parameters */
1859 if (cc & cc_reg_param) {
1860 /* determine the number of parameters passed via registers */
1861 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1863 /* loop over all parameters and set the register requirements */
1864 for (i = 0; i <= biggest_n; i++) {
1865 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1866 assert(reg && "kaputt");
1867 be_abi_call_param_reg(abi, i, reg);
1874 /* set stack parameters */
1875 for (i = stack_idx; i < n; i++) {
1876 /* parameters on the stack are 32 bit aligned */
1877 be_abi_call_param_stack(abi, i, 4, 0, 0);
1881 /* set return registers */
1882 n = get_method_n_ress(method_type);
1884 assert(n <= 2 && "more than two results not supported");
1886 /* In case of 64bit returns, we will have two 32bit values */
1888 tp = get_method_res_type(method_type, 0);
1889 mode = get_type_mode(tp);
1891 assert(!mode_is_float(mode) && "two FP results not supported");
1893 tp = get_method_res_type(method_type, 1);
1894 mode = get_type_mode(tp);
1896 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1898 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1899 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1902 const arch_register_t *reg;
1904 tp = get_method_res_type(method_type, 0);
1905 assert(is_atomic_type(tp));
1906 mode = get_type_mode(tp);
1908 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1910 be_abi_call_res_reg(abi, 0, reg);
1915 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1916 return &ia32_irn_ops;
1919 const arch_irn_handler_t ia32_irn_handler = {
1923 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1924 return &ia32_irn_handler;
1927 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1928 return is_ia32_irn(irn) ? 1 : -1;
1932 * Initializes the code generator interface.
1934 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1935 return &ia32_code_gen_if;
1939 * Returns the estimated execution time of an ia32 irn.
1941 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1942 const arch_env_t *arch_env = env;
1943 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1946 list_sched_selector_t ia32_sched_selector;
1949 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1951 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1952 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1953 ia32_sched_selector.exectime = ia32_sched_exectime;
1954 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1955 return &ia32_sched_selector;
1958 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self) {
1963 * Returns the necessary byte alignment for storing a register of given class.
1965 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1966 ir_mode *mode = arch_register_class_mode(cls);
1967 int bytes = get_mode_size_bytes(mode);
1969 if (mode_is_float(mode) && bytes > 8)
1974 static const be_execution_unit_t ***ia32_get_allowed_execution_units(const void *self, const ir_node *irn) {
1975 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1976 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1977 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1980 static const be_execution_unit_t *_allowed_units_GP[] = {
1981 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1982 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1983 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1984 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1985 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1986 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1987 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1990 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1991 &be_machine_execution_units_DUMMY[0],
1994 static const be_execution_unit_t **_units_callret[] = {
1995 _allowed_units_BRANCH,
1998 static const be_execution_unit_t **_units_other[] = {
2002 static const be_execution_unit_t **_units_dummy[] = {
2003 _allowed_units_DUMMY,
2006 const be_execution_unit_t ***ret;
2008 if (is_ia32_irn(irn)) {
2009 ret = get_ia32_exec_units(irn);
2011 else if (is_be_node(irn)) {
2012 if (be_is_Call(irn) || be_is_Return(irn)) {
2013 ret = _units_callret;
2015 else if (be_is_Barrier(irn)) {
2030 * Return the abstract ia32 machine.
2032 static const be_machine_t *ia32_get_machine(const void *self) {
2033 const ia32_isa_t *isa = self;
2038 * Return irp irgs in the desired order.
2040 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list) {
2045 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2046 * @return 1 if allowed, 0 otherwise
2048 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2050 ir_node *cmp, *cmp_a, *phi;
2053 /* we don't want long long an floating point Psi */
2054 #define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2056 if (get_irn_mode(sel) != mode_b)
2059 cmp = get_Proj_pred(sel);
2060 cmp_a = get_Cmp_left(cmp);
2061 mode = get_irn_mode(cmp_a);
2063 if (IS_BAD_PSI_MODE(mode))
2066 /* check the Phi nodes */
2067 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
2068 ir_node *pred_i = get_irn_n(phi, i);
2069 ir_node *pred_j = get_irn_n(phi, j);
2070 ir_mode *mode_i = get_irn_mode(pred_i);
2071 ir_mode *mode_j = get_irn_mode(pred_j);
2073 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
2077 #undef IS_BAD_PSI_MODE
2082 static ia32_intrinsic_env_t intrinsic_env = {
2083 NULL, /**< the irg, these entities belong to */
2084 NULL, /**< entity for first div operand (move into FPU) */
2085 NULL, /**< entity for second div operand (move into FPU) */
2086 NULL, /**< entity for converts ll -> d */
2087 NULL, /**< entity for converts d -> ll */
2091 * Returns the libFirm configuration parameter for this backend.
2093 static const backend_params *ia32_get_libfirm_params(void) {
2094 static const opt_if_conv_info_t ifconv = {
2095 4, /* maxdepth, doesn't matter for Psi-conversion */
2096 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2098 static const arch_dep_params_t ad = {
2099 1, /* also use subs */
2100 4, /* maximum shifts */
2101 31, /* maximum shift amount */
2103 1, /* allow Mulhs */
2104 1, /* allow Mulus */
2105 32 /* Mulh allowed up to 32 bit */
2107 static backend_params p = {
2108 NULL, /* no additional opcodes */
2109 NULL, /* will be set later */
2110 1, /* need dword lowering */
2111 ia32_create_intrinsic_fkt,
2112 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2113 NULL, /* will be set later */
2117 p.if_conv_info = &ifconv;
2121 /* instruction set architectures. */
2122 static const lc_opt_enum_int_items_t arch_items[] = {
2123 { "386", arch_i386, },
2124 { "486", arch_i486, },
2125 { "pentium", arch_pentium, },
2126 { "586", arch_pentium, },
2127 { "pentiumpro", arch_pentium_pro, },
2128 { "686", arch_pentium_pro, },
2129 { "pentiummmx", arch_pentium_mmx, },
2130 { "pentium2", arch_pentium_2, },
2131 { "p2", arch_pentium_2, },
2132 { "pentium3", arch_pentium_3, },
2133 { "p3", arch_pentium_3, },
2134 { "pentium4", arch_pentium_4, },
2135 { "p4", arch_pentium_4, },
2136 { "pentiumm", arch_pentium_m, },
2137 { "pm", arch_pentium_m, },
2138 { "core", arch_core, },
2140 { "athlon", arch_athlon, },
2141 { "athlon64", arch_athlon_64, },
2142 { "opteron", arch_opteron, },
2146 static lc_opt_enum_int_var_t arch_var = {
2147 &ia32_isa_template.arch, arch_items
2150 static lc_opt_enum_int_var_t opt_arch_var = {
2151 &ia32_isa_template.opt_arch, arch_items
2154 static const lc_opt_enum_int_items_t fp_unit_items[] = {
2156 { "sse2", fp_sse2 },
2160 static lc_opt_enum_int_var_t fp_unit_var = {
2161 &ia32_isa_template.fp_kind, fp_unit_items
2164 static const lc_opt_enum_int_items_t gas_items[] = {
2165 { "linux", ASM_LINUX_GAS },
2166 { "mingw", ASM_MINGW_GAS },
2170 static lc_opt_enum_int_var_t gas_var = {
2171 (int *)&asm_flavour, gas_items
2174 static const lc_opt_table_entry_t ia32_options[] = {
2175 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
2176 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
2177 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
2178 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
2179 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
2180 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
2181 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
2182 LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
2183 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2187 const arch_isa_if_t ia32_isa_if = {
2190 ia32_get_n_reg_class,
2192 ia32_get_reg_class_for_mode,
2194 ia32_get_irn_handler,
2195 ia32_get_code_generator_if,
2196 ia32_get_list_sched_selector,
2197 ia32_get_ilp_sched_selector,
2198 ia32_get_reg_class_alignment,
2199 ia32_get_libfirm_params,
2200 ia32_get_allowed_execution_units,
2205 void be_init_arch_ia32(void)
2207 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2208 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2210 lc_opt_add_table(ia32_grp, ia32_options);
2211 be_register_isa_if("ia32", &ia32_isa_if);
2214 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);