2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
28 #include "lc_opts_enum.h"
36 #include "iredges_t.h"
50 #include "iroptimize.h"
51 #include "instrument.h"
54 #include "lower_calls.h"
55 #include "lower_mode_b.h"
56 #include "lower_softfloat.h"
66 #include "be_dbgout.h"
67 #include "beblocksched.h"
68 #include "bespillutil.h"
69 #include "bespillslots.h"
74 #include "betranshlp.h"
75 #include "belistsched.h"
76 #include "beabihelper.h"
79 #include "bearch_ia32_t.h"
81 #include "ia32_new_nodes.h"
82 #include "gen_ia32_regalloc_if.h"
83 #include "ia32_common_transform.h"
84 #include "ia32_transform.h"
85 #include "ia32_emitter.h"
86 #include "ia32_optimize.h"
88 #include "ia32_dbg_stat.h"
89 #include "ia32_finish.h"
91 #include "ia32_architecture.h"
94 #include "ia32_pbqp_transform.h"
96 transformer_t be_transformer = TRANSFORMER_DEFAULT;
99 ir_mode *ia32_mode_fpcw;
100 ir_mode *ia32_mode_E;
101 ir_type *ia32_type_E;
103 /** The current omit-fp state */
104 static ir_type *omit_fp_between_type = NULL;
105 static ir_type *between_type = NULL;
106 static ir_entity *old_bp_ent = NULL;
107 static ir_entity *ret_addr_ent = NULL;
108 static ir_entity *omit_fp_ret_addr_ent = NULL;
111 * The environment for the intrinsic mapping.
113 static ia32_intrinsic_env_t intrinsic_env = {
115 NULL, /* the irg, these entities belong to */
116 NULL, /* entity for __divdi3 library call */
117 NULL, /* entity for __moddi3 library call */
118 NULL, /* entity for __udivdi3 library call */
119 NULL, /* entity for __umoddi3 library call */
123 typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
126 * Used to create per-graph unique pseudo nodes.
128 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
129 create_const_node_func func,
130 const arch_register_t* reg)
132 ir_node *block, *res;
137 block = get_irg_start_block(irg);
138 res = func(NULL, block);
139 arch_set_irn_register(res, reg);
145 /* Creates the unique per irg GP NoReg node. */
146 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
148 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
149 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
150 &ia32_registers[REG_GP_NOREG]);
153 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
155 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
156 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
157 &ia32_registers[REG_VFP_NOREG]);
160 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
162 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
163 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
164 &ia32_registers[REG_XMM_NOREG]);
167 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
169 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
170 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
171 &ia32_registers[REG_FPCW]);
176 * Returns the admissible noreg register node for input register pos of node irn.
178 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
180 ir_graph *irg = get_irn_irg(irn);
181 const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
183 assert(req != NULL && "Missing register requirements");
184 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
185 return ia32_new_NoReg_gp(irg);
187 if (ia32_cg_config.use_sse2) {
188 return ia32_new_NoReg_xmm(irg);
190 return ia32_new_NoReg_vfp(irg);
195 * The IA32 ABI callback object.
198 be_abi_call_flags_bits_t flags; /**< The call flags. */
199 ir_graph *irg; /**< The associated graph. */
202 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
204 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
207 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
209 if (is_be_node(node))
210 be_node_set_frame_entity(node, entity);
212 set_ia32_frame_ent(node, entity);
215 static void ia32_set_frame_offset(ir_node *irn, int bias)
217 if (get_ia32_frame_ent(irn) == NULL)
220 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
221 ir_graph *irg = get_irn_irg(irn);
222 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
223 if (layout->sp_relative) {
224 /* Pop nodes modify the stack pointer before calculating the
225 * destination address, so fix this here
230 add_ia32_am_offs_int(irn, bias);
233 static int ia32_get_sp_bias(const ir_node *node)
235 if (is_ia32_Call(node))
236 return -(int)get_ia32_call_attr_const(node)->pop;
238 if (is_ia32_Push(node))
241 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
244 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
245 return SP_BIAS_RESET;
252 * Build the between type and entities if not already build.
254 static void ia32_build_between_type(void)
256 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
257 if (! between_type) {
258 ir_type *old_bp_type = new_type_primitive(mode_Iu);
259 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
261 between_type = new_type_struct(IDENT("ia32_between_type"));
262 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
263 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
265 set_entity_offset(old_bp_ent, 0);
266 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
267 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
268 set_type_state(between_type, layout_fixed);
270 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
271 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
273 set_entity_offset(omit_fp_ret_addr_ent, 0);
274 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
275 set_type_state(omit_fp_between_type, layout_fixed);
281 * Produces the type which sits between the stack args and the locals on the stack.
282 * it will contain the return address and space to store the old base pointer.
283 * @return The Firm type modeling the ABI between type.
285 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
287 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
288 ia32_build_between_type();
289 return layout->sp_relative ? omit_fp_between_type : between_type;
293 * Return the stack entity that contains the return address.
295 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
297 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
298 ia32_build_between_type();
299 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
303 * Return the stack entity that contains the frame address.
305 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
307 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
308 ia32_build_between_type();
309 return layout->sp_relative ? NULL : old_bp_ent;
313 * Get the estimated cycle count for @p irn.
315 * @param self The this pointer.
316 * @param irn The node.
318 * @return The estimated cycle count for this operation
320 static int ia32_get_op_estimated_cost(const ir_node *irn)
323 ia32_op_type_t op_tp;
327 if (!is_ia32_irn(irn))
330 assert(is_ia32_irn(irn));
332 cost = get_ia32_latency(irn);
333 op_tp = get_ia32_op_type(irn);
335 if (is_ia32_CopyB(irn)) {
338 else if (is_ia32_CopyB_i(irn)) {
339 int size = get_ia32_copyb_size(irn);
340 cost = 20 + (int)ceil((4/3) * size);
342 /* in case of address mode operations add additional cycles */
343 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
345 In case of stack access and access to fixed addresses add 5 cycles
346 (we assume they are in cache), other memory operations cost 20
349 if (is_ia32_use_frame(irn) || (
350 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
351 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
363 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
365 * @param irn The original operation
366 * @param i Index of the argument we want the inverse operation to yield
367 * @param inverse struct to be filled with the resulting inverse op
368 * @param obstack The obstack to use for allocation of the returned nodes array
369 * @return The inverse operation or NULL if operation invertible
371 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
382 ir_node *block, *noreg, *nomem;
385 /* we cannot invert non-ia32 irns */
386 if (! is_ia32_irn(irn))
389 /* operand must always be a real operand (not base, index or mem) */
390 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
393 /* we don't invert address mode operations */
394 if (get_ia32_op_type(irn) != ia32_Normal)
397 /* TODO: adjust for new immediates... */
398 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
402 block = get_nodes_block(irn);
403 mode = get_irn_mode(irn);
404 irn_mode = get_irn_mode(irn);
405 noreg = get_irn_n(irn, 0);
406 nomem = get_irg_no_mem(irg);
407 dbgi = get_irn_dbg_info(irn);
409 /* initialize structure */
410 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
414 switch (get_ia32_irn_opcode(irn)) {
416 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
417 /* we have an add with a const here */
418 /* invers == add with negated const */
419 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
421 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
422 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
423 set_ia32_commutative(inverse->nodes[0]);
425 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
426 /* we have an add with a symconst here */
427 /* invers == sub with const */
428 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
430 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
433 /* normal add: inverse == sub */
434 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
439 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
440 /* we have a sub with a const/symconst here */
441 /* invers == add with this const */
442 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
443 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
444 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
448 if (i == n_ia32_binary_left) {
449 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
452 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
458 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
459 /* xor with const: inverse = xor */
460 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
461 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
462 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
466 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
471 inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
476 inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
481 /* inverse operation not supported */
489 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
491 if (mode_is_float(mode))
498 * Get the mode that should be used for spilling value node
500 static ir_mode *get_spill_mode(const ir_node *node)
502 ir_mode *mode = get_irn_mode(node);
503 return get_spill_mode_mode(mode);
507 * Checks whether an addressmode reload for a node with mode mode is compatible
508 * with a spillslot of mode spill_mode
510 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
512 return !mode_is_float(mode) || mode == spillmode;
516 * Check if irn can load its operand at position i from memory (source addressmode).
517 * @param irn The irn to be checked
518 * @param i The operands position
519 * @return Non-Zero if operand can be loaded
521 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
523 ir_node *op = get_irn_n(irn, i);
524 const ir_mode *mode = get_irn_mode(op);
525 const ir_mode *spillmode = get_spill_mode(op);
527 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
528 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
529 !ia32_is_spillmode_compatible(mode, spillmode) ||
530 is_ia32_use_frame(irn)) /* must not already use frame */
533 switch (get_ia32_am_support(irn)) {
538 if (i != n_ia32_unary_op)
544 case n_ia32_binary_left: {
545 const arch_register_req_t *req;
546 if (!is_ia32_commutative(irn))
549 /* we can't swap left/right for limited registers
550 * (As this (currently) breaks constraint handling copies)
552 req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
553 if (req->type & arch_register_req_type_limited)
558 case n_ia32_binary_right:
567 panic("Unknown AM type");
570 /* HACK: must not already use "real" memory.
571 * This can happen for Call and Div */
572 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
578 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
582 ir_mode *dest_op_mode;
584 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
586 set_ia32_op_type(irn, ia32_AddrModeS);
588 load_mode = get_irn_mode(get_irn_n(irn, i));
589 dest_op_mode = get_ia32_ls_mode(irn);
590 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
591 set_ia32_ls_mode(irn, load_mode);
593 set_ia32_use_frame(irn);
594 set_ia32_need_stackent(irn);
596 if (i == n_ia32_binary_left &&
597 get_ia32_am_support(irn) == ia32_am_binary &&
598 /* immediates are only allowed on the right side */
599 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
600 ia32_swap_left_right(irn);
601 i = n_ia32_binary_right;
604 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
606 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
607 set_irn_n(irn, n_ia32_mem, spill);
608 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
609 set_ia32_is_reload(irn);
612 static const be_abi_callbacks_t ia32_abi_callbacks = {
613 ia32_abi_get_between_type,
616 /* register allocator interface */
617 static const arch_irn_ops_t ia32_irn_ops = {
618 ia32_get_frame_entity,
619 ia32_set_frame_offset,
622 ia32_get_op_estimated_cost,
623 ia32_possible_memory_operand,
624 ia32_perform_memory_operand,
627 static ir_entity *mcount = NULL;
628 static int gprof = 0;
630 static void ia32_before_abi(ir_graph *irg)
633 if (mcount == NULL) {
634 ir_type *tp = new_type_method(0, 0);
635 ident *id = new_id_from_str("mcount");
636 mcount = new_entity(get_glob_type(), id, tp);
637 /* FIXME: enter the right ld_ident here */
638 set_entity_ld_ident(mcount, get_entity_ident(mcount));
639 set_entity_visibility(mcount, ir_visibility_external);
641 instrument_initcall(irg, mcount);
646 * Transforms the standard firm graph into
649 static void ia32_prepare_graph(ir_graph *irg)
651 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
654 switch (be_transformer) {
655 case TRANSFORMER_DEFAULT:
656 /* transform remaining nodes into assembler instructions */
657 ia32_transform_graph(irg);
660 case TRANSFORMER_PBQP:
661 case TRANSFORMER_RAND:
662 /* transform nodes into assembler instructions by PBQP magic */
663 ia32_transform_graph_by_pbqp(irg);
667 panic("invalid transformer");
670 ia32_transform_graph(irg);
673 /* do local optimizations (mainly CSE) */
674 optimize_graph_df(irg);
675 /* backend code expects that outedges are always enabled */
679 dump_ir_graph(irg, "transformed");
681 /* optimize address mode */
682 ia32_optimize_graph(irg);
684 /* do code placement, to optimize the position of constants */
686 /* backend code expects that outedges are always enabled */
690 dump_ir_graph(irg, "place");
693 ir_node *ia32_turn_back_am(ir_node *node)
695 dbg_info *dbgi = get_irn_dbg_info(node);
696 ir_graph *irg = get_irn_irg(node);
697 ir_node *block = get_nodes_block(node);
698 ir_node *base = get_irn_n(node, n_ia32_base);
699 ir_node *idx = get_irn_n(node, n_ia32_index);
700 ir_node *mem = get_irn_n(node, n_ia32_mem);
703 ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
704 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
706 ia32_copy_am_attrs(load, node);
707 if (is_ia32_is_reload(node))
708 set_ia32_is_reload(load);
709 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
711 switch (get_ia32_am_support(node)) {
713 set_irn_n(node, n_ia32_unary_op, load_res);
717 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
718 set_irn_n(node, n_ia32_binary_left, load_res);
720 set_irn_n(node, n_ia32_binary_right, load_res);
725 panic("Unknown AM type");
727 noreg = ia32_new_NoReg_gp(current_ir_graph);
728 set_irn_n(node, n_ia32_base, noreg);
729 set_irn_n(node, n_ia32_index, noreg);
730 set_ia32_am_offs_int(node, 0);
731 set_ia32_am_sc(node, NULL);
732 set_ia32_am_scale(node, 0);
733 clear_ia32_am_sc_sign(node);
735 /* rewire mem-proj */
736 if (get_irn_mode(node) == mode_T) {
737 const ir_edge_t *edge;
738 foreach_out_edge(node, edge) {
739 ir_node *out = get_edge_src_irn(edge);
740 if (get_irn_mode(out) == mode_M) {
741 set_Proj_pred(out, load);
742 set_Proj_proj(out, pn_ia32_Load_M);
748 set_ia32_op_type(node, ia32_Normal);
749 if (sched_is_scheduled(node))
750 sched_add_before(node, load);
755 static ir_node *flags_remat(ir_node *node, ir_node *after)
757 /* we should turn back source address mode when rematerializing nodes */
762 if (is_Block(after)) {
765 block = get_nodes_block(after);
768 type = get_ia32_op_type(node);
771 ia32_turn_back_am(node);
775 /* TODO implement this later... */
776 panic("found DestAM with flag user %+F this should not happen", node);
778 default: assert(type == ia32_Normal); break;
781 copy = exact_copy(node);
782 set_nodes_block(copy, block);
783 sched_add_after(after, copy);
789 * Called before the register allocator.
791 static void ia32_before_ra(ir_graph *irg)
793 /* setup fpu rounding modes */
794 ia32_setup_fpu_mode(irg);
797 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
800 be_add_missing_keeps(irg);
805 * Transforms a be_Reload into a ia32 Load.
807 static void transform_to_Load(ir_node *node)
809 ir_graph *irg = get_irn_irg(node);
810 dbg_info *dbgi = get_irn_dbg_info(node);
811 ir_node *block = get_nodes_block(node);
812 ir_entity *ent = be_get_frame_entity(node);
813 ir_mode *mode = get_irn_mode(node);
814 ir_mode *spillmode = get_spill_mode(node);
815 ir_node *noreg = ia32_new_NoReg_gp(irg);
816 ir_node *sched_point = NULL;
817 ir_node *ptr = get_irg_frame(irg);
818 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
819 ir_node *new_op, *proj;
820 const arch_register_t *reg;
822 if (sched_is_scheduled(node)) {
823 sched_point = sched_prev(node);
826 if (mode_is_float(spillmode)) {
827 if (ia32_cg_config.use_sse2)
828 new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
830 new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
832 else if (get_mode_size_bits(spillmode) == 128) {
833 /* Reload 128 bit SSE registers */
834 new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
837 new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
839 set_ia32_op_type(new_op, ia32_AddrModeS);
840 set_ia32_ls_mode(new_op, spillmode);
841 set_ia32_frame_ent(new_op, ent);
842 set_ia32_use_frame(new_op);
843 set_ia32_is_reload(new_op);
845 DBG_OPT_RELOAD2LD(node, new_op);
847 proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
850 sched_add_after(sched_point, new_op);
854 /* copy the register from the old node to the new Load */
855 reg = arch_get_irn_register(node);
856 arch_set_irn_register(proj, reg);
858 SET_IA32_ORIG_NODE(new_op, node);
860 exchange(node, proj);
864 * Transforms a be_Spill node into a ia32 Store.
866 static void transform_to_Store(ir_node *node)
868 ir_graph *irg = get_irn_irg(node);
869 dbg_info *dbgi = get_irn_dbg_info(node);
870 ir_node *block = get_nodes_block(node);
871 ir_entity *ent = be_get_frame_entity(node);
872 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
873 ir_mode *mode = get_spill_mode(spillval);
874 ir_node *noreg = ia32_new_NoReg_gp(irg);
875 ir_node *nomem = get_irg_no_mem(irg);
876 ir_node *ptr = get_irg_frame(irg);
877 ir_node *val = get_irn_n(node, n_be_Spill_val);
880 ir_node *sched_point = NULL;
882 if (sched_is_scheduled(node)) {
883 sched_point = sched_prev(node);
886 if (mode_is_float(mode)) {
887 if (ia32_cg_config.use_sse2) {
888 store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
889 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
891 store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
892 res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
894 } else if (get_mode_size_bits(mode) == 128) {
895 /* Spill 128 bit SSE registers */
896 store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
897 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
898 } else if (get_mode_size_bits(mode) == 8) {
899 store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
900 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
902 store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
903 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
906 set_ia32_op_type(store, ia32_AddrModeD);
907 set_ia32_ls_mode(store, mode);
908 set_ia32_frame_ent(store, ent);
909 set_ia32_use_frame(store);
910 set_ia32_is_spill(store);
911 SET_IA32_ORIG_NODE(store, node);
912 DBG_OPT_SPILL2ST(node, store);
915 sched_add_after(sched_point, store);
922 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
924 dbg_info *dbgi = get_irn_dbg_info(node);
925 ir_node *block = get_nodes_block(node);
926 ir_graph *irg = get_irn_irg(node);
927 ir_node *noreg = ia32_new_NoReg_gp(irg);
928 ir_node *frame = get_irg_frame(irg);
930 ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
932 set_ia32_frame_ent(push, ent);
933 set_ia32_use_frame(push);
934 set_ia32_op_type(push, ia32_AddrModeS);
935 set_ia32_ls_mode(push, mode_Is);
936 set_ia32_is_spill(push);
938 sched_add_before(schedpoint, push);
942 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
944 dbg_info *dbgi = get_irn_dbg_info(node);
945 ir_node *block = get_nodes_block(node);
946 ir_graph *irg = get_irn_irg(node);
947 ir_node *noreg = ia32_new_NoReg_gp(irg);
948 ir_node *frame = get_irg_frame(irg);
950 ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
951 get_irg_no_mem(irg), sp);
953 set_ia32_frame_ent(pop, ent);
954 set_ia32_use_frame(pop);
955 set_ia32_op_type(pop, ia32_AddrModeD);
956 set_ia32_ls_mode(pop, mode_Is);
957 set_ia32_is_reload(pop);
959 sched_add_before(schedpoint, pop);
964 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
966 dbg_info *dbgi = get_irn_dbg_info(node);
967 ir_mode *spmode = mode_Iu;
968 const arch_register_t *spreg = &ia32_registers[REG_ESP];
971 sp = new_rd_Proj(dbgi, pred, spmode, pos);
972 arch_set_irn_register(sp, spreg);
978 * Transform MemPerm, currently we do this the ugly way and produce
979 * push/pop into/from memory cascades. This is possible without using
982 static void transform_MemPerm(ir_node *node)
984 ir_node *block = get_nodes_block(node);
985 ir_graph *irg = get_irn_irg(node);
986 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
987 int arity = be_get_MemPerm_entity_arity(node);
988 ir_node **pops = ALLOCAN(ir_node*, arity);
992 const ir_edge_t *edge;
993 const ir_edge_t *next;
996 for (i = 0; i < arity; ++i) {
997 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
998 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
999 ir_type *enttype = get_entity_type(inent);
1000 unsigned entsize = get_type_size_bytes(enttype);
1001 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1002 ir_node *mem = get_irn_n(node, i + 1);
1005 /* work around cases where entities have different sizes */
1006 if (entsize2 < entsize)
1008 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1010 push = create_push(node, node, sp, mem, inent);
1011 sp = create_spproj(node, push, pn_ia32_Push_stack);
1013 /* add another push after the first one */
1014 push = create_push(node, node, sp, mem, inent);
1015 add_ia32_am_offs_int(push, 4);
1016 sp = create_spproj(node, push, pn_ia32_Push_stack);
1019 set_irn_n(node, i, new_r_Bad(irg, mode_X));
1023 for (i = arity - 1; i >= 0; --i) {
1024 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1025 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1026 ir_type *enttype = get_entity_type(outent);
1027 unsigned entsize = get_type_size_bytes(enttype);
1028 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1031 /* work around cases where entities have different sizes */
1032 if (entsize2 < entsize)
1034 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1036 pop = create_pop(node, node, sp, outent);
1037 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1039 add_ia32_am_offs_int(pop, 4);
1041 /* add another pop after the first one */
1042 pop = create_pop(node, node, sp, outent);
1043 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1050 keep = be_new_Keep(block, 1, in);
1051 sched_add_before(node, keep);
1053 /* exchange memprojs */
1054 foreach_out_edge_safe(node, edge, next) {
1055 ir_node *proj = get_edge_src_irn(edge);
1056 int p = get_Proj_proj(proj);
1060 set_Proj_pred(proj, pops[p]);
1061 set_Proj_proj(proj, pn_ia32_Pop_M);
1064 /* remove memperm */
1070 * Block-Walker: Calls the transform functions Spill and Reload.
1072 static void ia32_after_ra_walker(ir_node *block, void *env)
1074 ir_node *node, *prev;
1077 /* beware: the schedule is changed here */
1078 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1079 prev = sched_prev(node);
1081 if (be_is_Reload(node)) {
1082 transform_to_Load(node);
1083 } else if (be_is_Spill(node)) {
1084 transform_to_Store(node);
1085 } else if (be_is_MemPerm(node)) {
1086 transform_MemPerm(node);
1092 * Collects nodes that need frame entities assigned.
1094 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1096 be_fec_env_t *env = (be_fec_env_t*)data;
1097 const ir_mode *mode;
1100 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1101 mode = get_spill_mode_mode(get_irn_mode(node));
1102 align = get_mode_size_bytes(mode);
1103 } else if (is_ia32_irn(node) &&
1104 get_ia32_frame_ent(node) == NULL &&
1105 is_ia32_use_frame(node)) {
1106 if (is_ia32_need_stackent(node))
1109 switch (get_ia32_irn_opcode(node)) {
1111 case iro_ia32_Load: {
1112 const ia32_attr_t *attr = get_ia32_attr_const(node);
1114 if (attr->data.need_32bit_stackent) {
1116 } else if (attr->data.need_64bit_stackent) {
1119 mode = get_ia32_ls_mode(node);
1120 if (is_ia32_is_reload(node))
1121 mode = get_spill_mode_mode(mode);
1123 align = get_mode_size_bytes(mode);
1127 case iro_ia32_vfild:
1129 case iro_ia32_xLoad: {
1130 mode = get_ia32_ls_mode(node);
1135 case iro_ia32_FldCW: {
1136 /* although 2 byte would be enough 4 byte performs best */
1144 panic("unexpected frame user while collection frame entity nodes");
1146 case iro_ia32_FnstCW:
1147 case iro_ia32_Store8Bit:
1148 case iro_ia32_Store:
1151 case iro_ia32_vfist:
1152 case iro_ia32_vfisttp:
1154 case iro_ia32_xStore:
1155 case iro_ia32_xStoreSimple:
1162 be_node_needs_frame_entity(env, node, mode, align);
1165 static int determine_ebp_input(ir_node *ret)
1167 const arch_register_t *bp = &ia32_registers[REG_EBP];
1168 int arity = get_irn_arity(ret);
1171 for (i = 0; i < arity; ++i) {
1172 ir_node *input = get_irn_n(ret, i);
1173 if (arch_get_irn_register(input) == bp)
1176 panic("no ebp input found at %+F", ret);
1179 static void introduce_epilog(ir_node *ret)
1181 const arch_register_t *sp = &ia32_registers[REG_ESP];
1182 const arch_register_t *bp = &ia32_registers[REG_EBP];
1183 ir_graph *irg = get_irn_irg(ret);
1184 ir_type *frame_type = get_irg_frame_type(irg);
1185 unsigned frame_size = get_type_size_bytes(frame_type);
1186 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1187 ir_node *block = get_nodes_block(ret);
1188 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1189 ir_node *curr_sp = first_sp;
1190 ir_mode *mode_gp = mode_Iu;
1192 if (!layout->sp_relative) {
1193 int n_ebp = determine_ebp_input(ret);
1194 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1195 if (ia32_cg_config.use_leave) {
1196 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1197 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1198 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1199 arch_set_irn_register(curr_bp, bp);
1200 arch_set_irn_register(curr_sp, sp);
1201 sched_add_before(ret, leave);
1204 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1205 /* copy ebp to esp */
1206 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1207 arch_set_irn_register(curr_sp, sp);
1208 sched_add_before(ret, curr_sp);
1211 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1212 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1213 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1214 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1215 arch_set_irn_register(curr_bp, bp);
1216 arch_set_irn_register(curr_sp, sp);
1217 sched_add_before(ret, pop);
1219 set_irn_n(ret, n_be_Return_mem, curr_mem);
1221 set_irn_n(ret, n_ebp, curr_bp);
1223 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1224 sched_add_before(ret, incsp);
1227 set_irn_n(ret, n_be_Return_sp, curr_sp);
1229 /* keep verifier happy... */
1230 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1231 kill_node(first_sp);
1236 * put the Prolog code at the beginning, epilog code before each return
1238 static void introduce_prolog_epilog(ir_graph *irg)
1240 const arch_register_t *sp = &ia32_registers[REG_ESP];
1241 const arch_register_t *bp = &ia32_registers[REG_EBP];
1242 ir_node *start = get_irg_start(irg);
1243 ir_node *block = get_nodes_block(start);
1244 ir_type *frame_type = get_irg_frame_type(irg);
1245 unsigned frame_size = get_type_size_bytes(frame_type);
1246 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1247 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1248 ir_node *curr_sp = initial_sp;
1249 ir_mode *mode_gp = mode_Iu;
1251 if (!layout->sp_relative) {
1253 ir_node *mem = get_irg_initial_mem(irg);
1254 ir_node *noreg = ia32_new_NoReg_gp(irg);
1255 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1256 ir_node *curr_bp = initial_bp;
1257 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
1260 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1261 mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
1262 arch_set_irn_register(curr_sp, sp);
1263 sched_add_after(start, push);
1265 /* move esp to ebp */
1266 curr_bp = be_new_Copy(block, curr_sp);
1267 sched_add_after(push, curr_bp);
1268 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1269 curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
1270 sched_add_after(curr_bp, curr_sp);
1271 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1272 edges_reroute(initial_bp, curr_bp);
1273 set_irn_n(push, n_ia32_Push_val, initial_bp);
1275 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1276 edges_reroute(initial_sp, incsp);
1277 set_irn_n(push, n_ia32_Push_stack, initial_sp);
1278 sched_add_after(curr_sp, incsp);
1280 /* make sure the initial IncSP is really used by someone */
1281 if (get_irn_n_edges(incsp) <= 1) {
1282 ir_node *in[] = { incsp };
1283 ir_node *keep = be_new_Keep(block, 1, in);
1284 sched_add_after(incsp, keep);
1287 layout->initial_bias = -4;
1289 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1290 edges_reroute(initial_sp, incsp);
1291 be_set_IncSP_pred(incsp, curr_sp);
1292 sched_add_after(start, incsp);
1295 /* introduce epilog for every return node */
1297 ir_node *end_block = get_irg_end_block(irg);
1298 int arity = get_irn_arity(end_block);
1301 for (i = 0; i < arity; ++i) {
1302 ir_node *ret = get_irn_n(end_block, i);
1303 assert(be_is_Return(ret));
1304 introduce_epilog(ret);
1310 * Last touchups for the graph before emit: x87 simulation to replace the
1311 * virtual with real x87 instructions, creating a block schedule and peephole
1314 static void ia32_finish(ir_graph *irg)
1316 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1317 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1318 bool at_begin = stack_layout->sp_relative ? true : false;
1319 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1321 /* create and coalesce frame entities */
1322 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1323 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1324 be_free_frame_entity_coalescer(fec_env);
1326 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1328 introduce_prolog_epilog(irg);
1330 /* fix stack entity offsets */
1331 be_abi_fix_stack_nodes(irg);
1332 be_abi_fix_stack_bias(irg);
1334 /* fix 2-address code constraints */
1335 ia32_finish_irg(irg);
1337 /* we might have to rewrite x87 virtual registers */
1338 if (irg_data->do_x87_sim) {
1339 ia32_x87_simulate_graph(irg);
1342 /* do peephole optimisations */
1343 ia32_peephole_optimization(irg);
1345 be_remove_dead_nodes_from_schedule(irg);
1347 /* create block schedule, this also removes empty blocks which might
1348 * produce critical edges */
1349 irg_data->blk_sched = be_create_block_schedule(irg);
1353 * Emits the code, closes the output file and frees
1354 * the code generator interface.
1356 static void ia32_emit(ir_graph *irg)
1358 if (ia32_cg_config.emit_machcode) {
1359 ia32_gen_binary_routine(irg);
1361 ia32_gen_routine(irg);
1366 * Returns the node representing the PIC base.
1368 static ir_node *ia32_get_pic_base(ir_graph *irg)
1370 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1372 ir_node *get_eip = irg_data->get_eip;
1373 if (get_eip != NULL)
1376 block = get_irg_start_block(irg);
1377 get_eip = new_bd_ia32_GetEIP(NULL, block);
1378 irg_data->get_eip = get_eip;
1384 * Initializes a IA32 code generator.
1386 static void ia32_init_graph(ir_graph *irg)
1388 struct obstack *obst = be_get_be_obst(irg);
1389 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1391 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1394 /* Linux gprof implementation needs base pointer */
1395 be_get_irg_options(irg)->omit_fp = 0;
1398 be_birg_from_irg(irg)->isa_link = irg_data;
1401 static const tarval_mode_info mo_integer = {
1408 * set the tarval output mode of all integer modes to decimal
1410 static void set_tarval_output_modes(void)
1414 for (i = get_irp_n_modes(); i > 0;) {
1415 ir_mode *mode = get_irp_mode(--i);
1417 if (mode_is_int(mode))
1418 set_tarval_mode_output_option(mode, &mo_integer);
1422 extern const arch_isa_if_t ia32_isa_if;
1424 static void init_asm_constraints(void)
1426 be_init_default_asm_constraint_flags();
1428 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1429 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1430 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1431 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1432 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1433 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1434 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1435 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1436 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1437 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1438 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1439 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1440 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1441 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1442 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1443 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1444 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1445 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1446 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1447 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1449 /* no support for autodecrement/autoincrement */
1450 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1451 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1452 /* no float consts */
1453 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1454 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1455 /* makes no sense on x86 */
1456 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1457 /* no support for sse consts yet */
1458 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1459 /* no support for x87 consts yet */
1460 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1461 /* no support for mmx registers yet */
1462 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1463 /* not available in 32bit mode */
1464 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1465 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1467 /* no code yet to determine register class needed... */
1468 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1472 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1474 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1479 ir_relation relation;
1484 cmp_l = get_Cmp_left(sel);
1485 cmp_r = get_Cmp_right(sel);
1486 if (!mode_is_float(get_irn_mode(cmp_l)))
1489 /* check for min/max. They're defined as (C-Semantik):
1490 * min(a, b) = a < b ? a : b
1491 * or min(a, b) = a <= b ? a : b
1492 * max(a, b) = a > b ? a : b
1493 * or max(a, b) = a >= b ? a : b
1494 * (Note we only handle float min/max here)
1496 relation = get_Cmp_relation(sel);
1498 case ir_relation_greater_equal:
1499 case ir_relation_greater:
1501 if (cmp_l == mux_true && cmp_r == mux_false)
1504 case ir_relation_less_equal:
1505 case ir_relation_less:
1507 if (cmp_l == mux_true && cmp_r == mux_false)
1510 case ir_relation_unordered_greater_equal:
1511 case ir_relation_unordered_greater:
1513 if (cmp_l == mux_false && cmp_r == mux_true)
1516 case ir_relation_unordered_less_equal:
1517 case ir_relation_unordered_less:
1519 if (cmp_l == mux_false && cmp_r == mux_true)
1530 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1532 ir_mode *mode = get_irn_mode(mux_true);
1535 if (!mode_is_int(mode) && !mode_is_reference(mode)
1539 if (is_Const(mux_true) && is_Const(mux_false)) {
1540 /* we can create a set plus up two 3 instructions for any combination
1548 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1553 if (!mode_is_float(get_irn_mode(mux_true)))
1556 return is_Const(mux_true) && is_Const(mux_false);
1559 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1566 ir_relation relation;
1571 mode = get_irn_mode(mux_true);
1572 if (mode_is_signed(mode) || mode_is_float(mode))
1575 relation = get_Cmp_relation(sel);
1576 cmp_left = get_Cmp_left(sel);
1577 cmp_right = get_Cmp_right(sel);
1579 /* "move" zero constant to false input */
1580 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1581 ir_node *tmp = mux_false;
1582 mux_false = mux_true;
1584 relation = get_negated_relation(relation);
1586 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1588 if (!is_Sub(mux_true))
1590 sub_left = get_Sub_left(mux_true);
1591 sub_right = get_Sub_right(mux_true);
1593 /* Mux(a >=u b, 0, a-b) */
1594 if ((relation & ir_relation_greater)
1595 && sub_left == cmp_left && sub_right == cmp_right)
1597 /* Mux(a <=u b, 0, b-a) */
1598 if ((relation & ir_relation_less)
1599 && sub_left == cmp_right && sub_right == cmp_left)
1605 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1610 /* middleend can handle some things */
1611 if (ir_is_optimizable_mux(sel, mux_false, mux_true))
1613 /* we can handle Set for all modes and compares */
1614 if (mux_is_set(sel, mux_true, mux_false))
1616 /* SSE has own min/max operations */
1617 if (ia32_cg_config.use_sse2
1618 && mux_is_float_min_max(sel, mux_true, mux_false))
1620 /* we can handle Mux(?, Const[f], Const[f]) */
1621 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1622 #ifdef FIRM_GRGEN_BE
1623 /* well, some code selectors can't handle it */
1624 if (be_transformer != TRANSFORMER_PBQP
1625 || be_transformer != TRANSFORMER_RAND)
1632 /* no support for 64bit inputs to cmov */
1633 mode = get_irn_mode(mux_true);
1634 if (get_mode_size_bits(mode) > 32)
1636 /* we can handle Abs for all modes and compares (except 64bit) */
1637 if (ir_mux_is_abs(sel, mux_false, mux_true) != 0)
1639 /* we can't handle MuxF yet */
1640 if (mode_is_float(mode))
1643 if (mux_is_doz(sel, mux_true, mux_false))
1646 /* Check Cmp before the node */
1648 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1650 /* we can't handle 64bit compares */
1651 if (get_mode_size_bits(cmp_mode) > 32)
1654 /* we can't handle float compares */
1655 if (mode_is_float(cmp_mode))
1659 /* did we disable cmov generation? */
1660 if (!ia32_cg_config.use_cmov)
1663 /* we can use a cmov */
1668 * Create the trampoline code.
1670 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
1672 ir_graph *const irg = get_irn_irg(block);
1673 ir_node * p = trampoline;
1674 ir_mode *const mode = get_irn_mode(p);
1675 ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
1676 ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
1680 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
1681 mem = new_r_Proj(st, mode_M, pn_Store_M);
1682 p = new_r_Add(block, p, one, mode);
1683 st = new_r_Store(block, mem, p, env, cons_none);
1684 mem = new_r_Proj(st, mode_M, pn_Store_M);
1685 p = new_r_Add(block, p, four, mode);
1687 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
1688 mem = new_r_Proj(st, mode_M, pn_Store_M);
1689 p = new_r_Add(block, p, one, mode);
1690 st = new_r_Store(block, mem, p, callee, cons_none);
1691 mem = new_r_Proj(st, mode_M, pn_Store_M);
1692 p = new_r_Add(block, p, four, mode);
1697 static const ir_settings_arch_dep_t ia32_arch_dep = {
1698 1, /* also use subs */
1699 4, /* maximum shifts */
1700 63, /* maximum shift amount */
1701 ia32_evaluate_insn, /* evaluate the instruction sequence */
1703 1, /* allow Mulhs */
1704 1, /* allow Mulus */
1705 32, /* Mulh allowed up to 32 bit */
1707 static backend_params ia32_backend_params = {
1708 1, /* support inline assembly */
1709 1, /* support Rotl nodes */
1710 0, /* little endian */
1711 1, /* modulo shift efficient */
1712 0, /* non-modulo shift not efficient */
1713 &ia32_arch_dep, /* will be set later */
1714 ia32_is_mux_allowed,
1715 32, /* machine_size */
1716 NULL, /* float arithmetic mode, will be set below */
1717 NULL, /* long long type */
1718 NULL, /* unsigned long long type */
1719 NULL, /* long double type */
1720 12, /* size of trampoline code */
1721 4, /* alignment of trampoline code */
1722 ia32_create_trampoline_fkt,
1723 4 /* alignment of stack parameter */
1727 * Initializes the backend ISA.
1729 static void ia32_init(void)
1731 ir_mode *mode_long_long;
1732 ir_mode *mode_unsigned_long_long;
1733 ir_type *type_long_long;
1734 ir_type *type_unsigned_long_long;
1736 ia32_setup_cg_config();
1738 init_asm_constraints();
1740 set_tarval_output_modes();
1741 ia32_register_init();
1742 ia32_create_opcodes(&ia32_irn_ops);
1744 ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0);
1746 /* note mantissa is 64bit but with explicitely encoded 1 so the really
1747 * usable part as counted by firm is only 63 bits */
1748 ia32_mode_E = new_float_mode("E", irma_x86_extended_float, 15, 63);
1749 ia32_type_E = new_type_primitive(ia32_mode_E);
1750 set_type_size_bytes(ia32_type_E, 12);
1751 set_type_alignment_bytes(ia32_type_E, 16);
1753 mode_long_long = new_int_mode("long long", irma_twos_complement, 64, 1, 64);
1754 type_long_long = new_type_primitive(mode_long_long);
1755 mode_unsigned_long_long
1756 = new_int_mode("unsigned long long", irma_twos_complement, 64, 0, 64);
1757 type_unsigned_long_long = new_type_primitive(mode_unsigned_long_long);
1759 ia32_backend_params.type_long_long = type_long_long;
1760 ia32_backend_params.type_unsigned_long_long = type_unsigned_long_long;
1762 if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
1763 ia32_backend_params.mode_float_arithmetic = NULL;
1764 ia32_backend_params.type_long_double = NULL;
1766 ia32_backend_params.mode_float_arithmetic = ia32_mode_E;
1767 ia32_backend_params.type_long_double = ia32_type_E;
1772 * The template that generates a new ISA object.
1773 * Note that this template can be changed by command line
1776 static ia32_isa_t ia32_isa_template = {
1778 &ia32_isa_if, /* isa interface implementation */
1783 &ia32_registers[REG_ESP], /* stack pointer register */
1784 &ia32_registers[REG_EBP], /* base pointer register */
1785 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1786 2, /* power of two stack alignment, 2^2 == 4 */
1787 NULL, /* main environment */
1788 7, /* costs for a spill instruction */
1789 5, /* costs for a reload instruction */
1790 false, /* no custom abi handling */
1793 IA32_FPU_ARCH_X87, /* FPU architecture */
1796 static arch_env_t *ia32_begin_codegeneration(const be_main_env_t *env)
1798 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1800 *isa = ia32_isa_template;
1801 isa->tv_ent = pmap_create();
1803 /* enter the ISA object into the intrinsic environment */
1804 intrinsic_env.isa = isa;
1806 be_emit_init(env->file_handle);
1807 be_gas_begin_compilation_unit(env);
1813 * Closes the output file and frees the ISA structure.
1815 static void ia32_end_codegeneration(void *self)
1817 ia32_isa_t *isa = (ia32_isa_t*)self;
1819 /* emit now all global declarations */
1820 be_gas_end_compilation_unit(isa->base.main_env);
1824 pmap_destroy(isa->tv_ent);
1829 * Returns the register for parameter nr.
1831 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1832 const ir_mode *mode)
1834 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1835 &ia32_registers[REG_ECX],
1836 &ia32_registers[REG_EDX],
1839 static const unsigned MAXNUM_GPREG_ARGS = 3;
1841 static const arch_register_t *gpreg_param_reg_regparam[] = {
1842 &ia32_registers[REG_EAX],
1843 &ia32_registers[REG_EDX],
1844 &ia32_registers[REG_ECX]
1847 static const arch_register_t *gpreg_param_reg_this[] = {
1848 &ia32_registers[REG_ECX],
1853 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1854 &ia32_registers[REG_XMM0],
1855 &ia32_registers[REG_XMM1],
1856 &ia32_registers[REG_XMM2],
1857 &ia32_registers[REG_XMM3],
1858 &ia32_registers[REG_XMM4],
1859 &ia32_registers[REG_XMM5],
1860 &ia32_registers[REG_XMM6],
1861 &ia32_registers[REG_XMM7]
1864 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1865 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1867 static const unsigned MAXNUM_SSE_ARGS = 8;
1869 if ((cc & cc_this_call) && nr == 0)
1870 return gpreg_param_reg_this[0];
1872 if (! (cc & cc_reg_param))
1875 if (mode_is_float(mode)) {
1876 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1878 if (nr >= MAXNUM_SSE_ARGS)
1881 if (cc & cc_this_call) {
1882 return fpreg_sse_param_reg_this[nr];
1884 return fpreg_sse_param_reg_std[nr];
1885 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1886 unsigned num_regparam;
1888 if (get_mode_size_bits(mode) > 32)
1891 if (nr >= MAXNUM_GPREG_ARGS)
1894 if (cc & cc_this_call) {
1895 return gpreg_param_reg_this[nr];
1897 num_regparam = cc & ~cc_bits;
1898 if (num_regparam == 0) {
1899 /* default fastcall */
1900 return gpreg_param_reg_fastcall[nr];
1902 if (nr < num_regparam)
1903 return gpreg_param_reg_regparam[nr];
1907 panic("unknown argument mode");
1911 * Get the ABI restrictions for procedure calls.
1913 static void ia32_get_call_abi(ir_type *method_type, be_abi_call_t *abi)
1918 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1920 /* set abi flags for calls */
1921 call_flags.bits.store_args_sequential = 0;
1922 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1923 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1924 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1926 /* set parameter passing style */
1927 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1929 cc = get_method_calling_convention(method_type);
1930 if (get_method_variadicity(method_type) == variadicity_variadic) {
1931 /* pass all parameters of a variadic function on the stack */
1932 cc = cc_cdecl_set | (cc & cc_this_call);
1934 if (get_method_additional_properties(method_type) & mtp_property_private &&
1935 ia32_cg_config.optimize_cc) {
1936 /* set the fast calling conventions (allowing up to 3) */
1937 cc = SET_FASTCALL(cc) | 3;
1941 /* we have to pop the shadow parameter ourself for compound calls */
1942 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1943 && !(cc & cc_reg_param)) {
1944 pop_amount += get_mode_size_bytes(mode_P_data);
1947 n = get_method_n_params(method_type);
1948 for (i = regnum = 0; i < n; i++) {
1949 const arch_register_t *reg = NULL;
1950 ir_type *tp = get_method_param_type(method_type, i);
1951 ir_mode *mode = get_type_mode(tp);
1954 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1957 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1960 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1961 * movl has a shorter opcode than mov[sz][bw]l */
1962 ir_mode *load_mode = mode;
1965 unsigned size = get_mode_size_bytes(mode);
1967 if (cc & cc_callee_clear_stk) {
1968 pop_amount += (size + 3U) & ~3U;
1971 if (size < 4) load_mode = mode_Iu;
1974 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1978 be_abi_call_set_pop(abi, pop_amount);
1980 /* set return registers */
1981 n = get_method_n_ress(method_type);
1983 assert(n <= 2 && "more than two results not supported");
1985 /* In case of 64bit returns, we will have two 32bit values */
1987 ir_type *tp = get_method_res_type(method_type, 0);
1988 ir_mode *mode = get_type_mode(tp);
1990 assert(!mode_is_float(mode) && "two FP results not supported");
1992 tp = get_method_res_type(method_type, 1);
1993 mode = get_type_mode(tp);
1995 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1997 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1998 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
2001 ir_type *tp = get_method_res_type(method_type, 0);
2002 ir_mode *mode = get_type_mode(tp);
2003 const arch_register_t *reg;
2004 assert(is_atomic_type(tp));
2006 reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
2008 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
2012 static void ia32_mark_remat(ir_node *node)
2014 if (is_ia32_irn(node)) {
2015 set_ia32_is_remat(node);
2019 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2023 /* we already added all our simple flags to the flags modifier list in
2024 * init, so this flag we don't know. */
2025 return ASM_CONSTRAINT_FLAG_INVALID;
2028 static int ia32_is_valid_clobber(const char *clobber)
2030 return ia32_get_clobber_register(clobber) != NULL;
2033 static void ia32_lower_for_target(void)
2035 size_t i, n_irgs = get_irp_n_irgs();
2037 /* perform doubleword lowering */
2038 lwrdw_param_t lower_dw_params = {
2039 1, /* little endian */
2040 64, /* doubleword size */
2041 ia32_create_intrinsic_fkt,
2045 ia32_create_opcodes(&ia32_irn_ops);
2047 /* lower compound param handling
2048 * Note: we lower compound arguments ourself, since on ia32 we don't
2049 * have hidden parameters but know where to find the structs on the stack.
2050 * (This also forces us to always allocate space for the compound arguments
2051 * on the callframe and we can't just use an arbitrary position on the
2054 lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS);
2056 /* replace floating point operations by function calls */
2057 if (ia32_cg_config.use_softfloat) {
2058 lower_floating_point();
2061 ir_prepare_dw_lowering(&lower_dw_params);
2064 for (i = 0; i < n_irgs; ++i) {
2065 ir_graph *irg = get_irp_irg(i);
2066 /* lower for mode_b stuff */
2067 ir_lower_mode_b(irg, mode_Iu);
2068 /* break up switches with wide ranges */
2069 lower_switch(irg, 4, 256, false);
2072 for (i = 0; i < n_irgs; ++i) {
2073 ir_graph *irg = get_irp_irg(i);
2074 /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
2075 * so we can generate rep movs later, and turn all big CopyBs into
2077 lower_CopyB(irg, 64, 8193, true);
2082 * Returns the libFirm configuration parameter for this backend.
2084 static const backend_params *ia32_get_libfirm_params(void)
2086 return &ia32_backend_params;
2090 * Check if the given register is callee or caller save.
2092 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
2095 /* check for callee saved */
2096 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2097 switch (reg->index) {
2108 /* check for caller saved */
2109 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2110 switch (reg->index) {
2118 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
2119 /* all XMM registers are caller save */
2120 return reg->index != REG_XMM_NOREG;
2121 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
2122 /* all VFP registers are caller save */
2123 return reg->index != REG_VFP_NOREG;
2129 static const lc_opt_enum_int_items_t gas_items[] = {
2130 { "elf", OBJECT_FILE_FORMAT_ELF },
2131 { "mingw", OBJECT_FILE_FORMAT_COFF },
2132 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2136 static lc_opt_enum_int_var_t gas_var = {
2137 (int*) &be_gas_object_file_format, gas_items
2140 #ifdef FIRM_GRGEN_BE
2141 static const lc_opt_enum_int_items_t transformer_items[] = {
2142 { "default", TRANSFORMER_DEFAULT },
2143 { "pbqp", TRANSFORMER_PBQP },
2144 { "random", TRANSFORMER_RAND },
2148 static lc_opt_enum_int_var_t transformer_var = {
2149 (int*)&be_transformer, transformer_items
2153 static const lc_opt_table_entry_t ia32_options[] = {
2154 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2155 #ifdef FIRM_GRGEN_BE
2156 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2158 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2159 &ia32_isa_template.base.stack_alignment),
2160 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2164 const arch_isa_if_t ia32_isa_if = {
2166 ia32_get_libfirm_params,
2167 ia32_lower_for_target,
2168 ia32_parse_asm_constraint,
2169 ia32_is_valid_clobber,
2171 ia32_begin_codegeneration,
2172 ia32_end_codegeneration,
2176 ia32_get_pic_base, /* return node used as base in pic code addresses */
2179 ia32_register_saved_by,
2181 ia32_handle_intrinsics,
2182 ia32_before_abi, /* before abi introduce hook */
2184 ia32_before_ra, /* before register allocation hook */
2185 ia32_finish, /* called before codegen */
2186 ia32_emit, /* emit && done */
2189 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2190 void be_init_arch_ia32(void)
2192 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2193 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2195 lc_opt_add_table(ia32_grp, ia32_options);
2196 be_register_isa_if("ia32", &ia32_isa_if);
2198 ia32_init_emitter();
2200 ia32_init_optimize();
2201 ia32_init_transform();
2203 ia32_init_architecture();