2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
26 #include "pseudo_irg.h"
30 #include "iredges_t.h"
39 #include "../beabi.h" /* the general register allocator interface */
40 #include "../benode_t.h"
41 #include "../belower.h"
42 #include "../besched_t.h"
45 #include "../beirgmod.h"
46 #include "../be_dbgout.h"
47 #include "../beblocksched.h"
48 #include "../bemachine.h"
49 #include "../beilpsched.h"
50 #include "../bespillslots.h"
51 #include "../bemodule.h"
53 #include "bearch_ia32_t.h"
55 #include "ia32_new_nodes.h" /* ia32 nodes interface */
56 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
57 #include "gen_ia32_machine.h"
58 #include "ia32_gen_decls.h" /* interface declaration emitter */
59 #include "ia32_transform.h"
60 #include "ia32_emitter.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_optimize.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_finish.h"
66 #include "ia32_util.h"
68 #define DEBUG_MODULE "firm.be.ia32.isa"
71 static set *cur_reg_set = NULL;
73 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
75 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
76 create_const_node_func func, arch_register_t* reg)
86 block = get_irg_start_block(cg->irg);
87 res = func(NULL, cg->irg, block);
88 arch_set_irn_register(cg->arch_env, res, reg);
91 /* keep the node so it isn't accidently removed when unused ... */
93 keep = be_new_Keep(arch_register_get_class(reg), cg->irg, block, 1, in);
95 /* schedule the node if we already have a scheduled program */
96 startnode = get_irg_start(cg->irg);
97 if(sched_is_scheduled(startnode)) {
98 sched_add_after(startnode, res);
99 sched_add_after(res, keep);
105 /* Creates the unique per irg GP NoReg node. */
106 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
107 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
108 &ia32_gp_regs[REG_GP_NOREG]);
111 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
112 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
113 &ia32_vfp_regs[REG_VFP_NOREG]);
116 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
117 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
118 &ia32_xmm_regs[REG_XMM_NOREG]);
121 /* Creates the unique per irg FP NoReg node. */
122 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
123 return USE_SSE2(cg) ? ia32_new_NoReg_xmm(cg) : ia32_new_NoReg_vfp(cg);
126 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
127 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
128 &ia32_gp_regs[REG_GP_UKNWN]);
131 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
132 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
133 &ia32_vfp_regs[REG_VFP_UKNWN]);
136 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
137 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
138 &ia32_xmm_regs[REG_XMM_UKNWN]);
143 * Returns gp_noreg or fp_noreg, depending in input requirements.
145 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
146 arch_register_req_t req;
147 const arch_register_req_t *p_req;
149 p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
150 assert(p_req && "Missing register requirements");
151 if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
152 return ia32_new_NoReg_gp(cg);
154 return ia32_new_NoReg_fp(cg);
157 /**************************************************
160 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
161 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
162 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
163 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
166 **************************************************/
169 * Return register requirements for an ia32 node.
170 * If the node returns a tuple (mode_T) then the proj's
171 * will be asked for this information.
173 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
174 const ia32_irn_ops_t *ops = self;
175 const ia32_register_req_t *irn_req;
176 long node_pos = pos == -1 ? 0 : pos;
177 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
178 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
180 if (is_Block(irn) || mode == mode_X) {
181 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
185 if (mode == mode_T && pos < 0) {
186 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
190 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
197 DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
201 node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
202 irn = skip_Proj_const(irn);
204 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
207 if (is_ia32_irn(irn)) {
208 irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
209 if (irn_req == NULL) {
210 /* no requirements */
214 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
216 memcpy(req, &(irn_req->req), sizeof(*req));
218 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
219 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
220 req->other_same = get_irn_n(irn, irn_req->same_pos);
223 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
224 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
225 req->other_different = get_irn_n(irn, irn_req->different_pos);
229 /* treat Unknowns like Const with default requirements */
230 if (is_Unknown(irn)) {
231 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
232 if (mode_is_float(mode)) {
233 if (USE_SSE2(ops->cg))
234 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
236 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
238 else if (mode_is_int(mode) || mode_is_reference(mode))
239 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
240 else if (mode == mode_T || mode == mode_M) {
241 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
245 assert(0 && "unsupported Unknown-Mode");
248 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
256 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
258 const ia32_irn_ops_t *ops = self;
260 if (get_irn_mode(irn) == mode_X) {
264 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
267 pos = get_Proj_proj(irn);
268 irn = skip_Proj(irn);
271 if (is_ia32_irn(irn)) {
272 const arch_register_t **slots;
274 slots = get_ia32_slots(irn);
278 ia32_set_firm_reg(irn, reg, cur_reg_set);
282 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
284 const arch_register_t *reg = NULL;
288 if (get_irn_mode(irn) == mode_X) {
292 pos = get_Proj_proj(irn);
293 irn = skip_Proj_const(irn);
296 if (is_ia32_irn(irn)) {
297 const arch_register_t **slots;
298 slots = get_ia32_slots(irn);
302 reg = ia32_get_firm_reg(irn, cur_reg_set);
308 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
309 arch_irn_class_t classification = arch_irn_class_normal;
311 irn = skip_Proj_const(irn);
314 classification |= arch_irn_class_branch;
316 if (! is_ia32_irn(irn))
317 return classification & ~arch_irn_class_normal;
319 if (is_ia32_Cnst(irn))
320 classification |= arch_irn_class_const;
323 classification |= arch_irn_class_load;
325 if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
326 classification |= arch_irn_class_store;
328 if (is_ia32_got_reload(irn))
329 classification |= arch_irn_class_reload;
331 return classification;
334 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
335 arch_irn_flags_t flags = arch_irn_flags_none;
338 return arch_irn_flags_ignore;
340 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
341 ir_node *pred = get_Proj_pred(irn);
343 if(is_ia32_irn(pred)) {
344 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
350 if (is_ia32_irn(irn)) {
351 flags |= get_ia32_flags(irn);
358 * The IA32 ABI callback object.
361 be_abi_call_flags_bits_t flags; /**< The call flags. */
362 const arch_isa_t *isa; /**< The ISA handle. */
363 const arch_env_t *aenv; /**< The architecture environment. */
364 ir_graph *irg; /**< The associated graph. */
367 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
368 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
371 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
372 set_ia32_frame_ent(irn, ent);
375 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
376 const ia32_irn_ops_t *ops = self;
378 if (get_ia32_frame_ent(irn)) {
379 ia32_am_flavour_t am_flav;
381 if (is_ia32_Pop(irn)) {
382 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
384 /* Pop nodes modify the stack pointer before calculating the destination
385 * address, so fix this here
391 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
393 am_flav = get_ia32_am_flavour(irn);
395 set_ia32_am_flavour(irn, am_flav);
397 add_ia32_am_offs_int(irn, bias);
401 static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
403 long proj = get_Proj_proj(irn);
404 ir_node *pred = get_Proj_pred(irn);
406 if (is_ia32_Push(pred) && proj == pn_ia32_Push_stack)
408 if (is_ia32_Pop(pred) && proj == pn_ia32_Pop_stack)
416 * Put all registers which are saved by the prologue/epilogue in a set.
418 * @param self The callback object.
419 * @param s The result set.
421 static void ia32_abi_dont_save_regs(void *self, pset *s)
423 ia32_abi_env_t *env = self;
424 if(env->flags.try_omit_fp)
425 pset_insert_ptr(s, env->isa->bp);
429 * Generate the routine prologue.
431 * @param self The callback object.
432 * @param mem A pointer to the mem node. Update this if you define new memory.
433 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
435 * @return The register which shall be used as a stack frame base.
437 * All nodes which define registers in @p reg_map must keep @p reg_map current.
439 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
441 ia32_abi_env_t *env = self;
442 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
443 ia32_code_gen_t *cg = isa->cg;
445 if (! env->flags.try_omit_fp) {
446 ir_node *bl = get_irg_start_block(env->irg);
447 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
448 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
449 ir_node *noreg = ia32_new_NoReg_gp(cg);
453 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
454 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
455 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
457 /* the push must have SP out register */
458 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
459 set_ia32_flags(push, arch_irn_flags_ignore);
461 /* move esp to ebp */
462 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
463 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
464 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
465 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
467 /* beware: the copy must be done before any other sp use */
468 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
469 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
470 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
471 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
473 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
474 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
483 * Generate the routine epilogue.
484 * @param self The callback object.
485 * @param bl The block for the epilog
486 * @param mem A pointer to the mem node. Update this if you define new memory.
487 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
488 * @return The register which shall be used as a stack frame base.
490 * All nodes which define registers in @p reg_map must keep @p reg_map current.
492 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
494 ia32_abi_env_t *env = self;
495 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
496 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
498 if (env->flags.try_omit_fp) {
499 /* simply remove the stack frame here */
500 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
501 add_irn_dep(curr_sp, *mem);
503 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
504 ia32_code_gen_t *cg = isa->cg;
505 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
507 /* gcc always emits a leave at the end of a routine */
508 if (1 || ARCH_AMD(isa->opt_arch)) {
512 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
513 set_ia32_flags(leave, arch_irn_flags_ignore);
514 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
515 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
517 ir_node *noreg = ia32_new_NoReg_gp(cg);
520 /* copy ebp to esp */
521 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
524 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
525 set_ia32_flags(pop, arch_irn_flags_ignore);
526 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
527 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
529 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
531 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
532 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
535 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
536 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
540 * Initialize the callback object.
541 * @param call The call object.
542 * @param aenv The architecture environment.
543 * @param irg The graph with the method.
544 * @return Some pointer. This pointer is passed to all other callback functions as self object.
546 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
548 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
549 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
550 env->flags = fl.bits;
553 env->isa = aenv->isa;
558 * Destroy the callback object.
559 * @param self The callback object.
561 static void ia32_abi_done(void *self) {
566 * Produces the type which sits between the stack args and the locals on the stack.
567 * it will contain the return address and space to store the old base pointer.
568 * @return The Firm type modeling the ABI between type.
570 static ir_type *ia32_abi_get_between_type(void *self)
572 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
573 static ir_type *omit_fp_between_type = NULL;
574 static ir_type *between_type = NULL;
576 ia32_abi_env_t *env = self;
578 if (! between_type) {
579 ir_entity *old_bp_ent;
580 ir_entity *ret_addr_ent;
581 ir_entity *omit_fp_ret_addr_ent;
583 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
584 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
586 between_type = new_type_struct(IDENT("ia32_between_type"));
587 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
588 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
590 set_entity_offset(old_bp_ent, 0);
591 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
592 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
593 set_type_state(between_type, layout_fixed);
595 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
596 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
598 set_entity_offset(omit_fp_ret_addr_ent, 0);
599 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
600 set_type_state(omit_fp_between_type, layout_fixed);
603 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
608 * Get the estimated cycle count for @p irn.
610 * @param self The this pointer.
611 * @param irn The node.
613 * @return The estimated cycle count for this operation
615 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
618 ia32_op_type_t op_tp;
619 const ia32_irn_ops_t *ops = self;
623 if (!is_ia32_irn(irn))
626 assert(is_ia32_irn(irn));
628 cost = get_ia32_latency(irn);
629 op_tp = get_ia32_op_type(irn);
631 if (is_ia32_CopyB(irn)) {
633 if (ARCH_INTEL(ops->cg->arch))
636 else if (is_ia32_CopyB_i(irn)) {
637 int size = get_tarval_long(get_ia32_Immop_tarval(irn));
638 cost = 20 + (int)ceil((4/3) * size);
639 if (ARCH_INTEL(ops->cg->arch))
642 /* in case of address mode operations add additional cycles */
643 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
645 In case of stack access add 5 cycles (we assume stack is in cache),
646 other memory operations cost 20 cycles.
648 cost += is_ia32_use_frame(irn) ? 5 : 20;
655 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
657 * @param irn The original operation
658 * @param i Index of the argument we want the inverse operation to yield
659 * @param inverse struct to be filled with the resulting inverse op
660 * @param obstack The obstack to use for allocation of the returned nodes array
661 * @return The inverse operation or NULL if operation invertible
663 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
667 ir_node *block, *noreg, *nomem;
670 /* we cannot invert non-ia32 irns */
671 if (! is_ia32_irn(irn))
674 /* operand must always be a real operand (not base, index or mem) */
675 if (i != 2 && i != 3)
678 /* we don't invert address mode operations */
679 if (get_ia32_op_type(irn) != ia32_Normal)
682 irg = get_irn_irg(irn);
683 block = get_nodes_block(irn);
684 mode = get_irn_mode(irn);
685 irn_mode = get_irn_mode(irn);
686 noreg = get_irn_n(irn, 0);
687 nomem = new_r_NoMem(irg);
688 dbg = get_irn_dbg_info(irn);
690 /* initialize structure */
691 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
695 switch (get_ia32_irn_opcode(irn)) {
697 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
698 /* we have an add with a const here */
699 /* invers == add with negated const */
700 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
702 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
703 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
704 set_ia32_commutative(inverse->nodes[0]);
706 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
707 /* we have an add with a symconst here */
708 /* invers == sub with const */
709 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
711 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
714 /* normal add: inverse == sub */
715 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, i ^ 1), nomem);
720 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
721 /* we have a sub with a const/symconst here */
722 /* invers == add with this const */
723 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
724 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
725 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
730 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, 3), nomem);
733 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, 2), (ir_node*) irn, nomem);
739 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
740 /* xor with const: inverse = xor */
741 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
742 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
743 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
747 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem);
752 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
757 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
762 /* inverse operation not supported */
769 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
771 if(mode_is_float(mode))
778 * Get the mode that should be used for spilling value node
780 static ir_mode *get_spill_mode(const ir_node *node)
782 ir_mode *mode = get_irn_mode(node);
783 return get_spill_mode_mode(mode);
787 * Checks wether an addressmode reload for a node with mode mode is compatible
788 * with a spillslot of mode spill_mode
790 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
792 if(mode_is_float(mode)) {
793 return mode == spillmode;
800 * Check if irn can load it's operand at position i from memory (source addressmode).
801 * @param self Pointer to irn ops itself
802 * @param irn The irn to be checked
803 * @param i The operands position
804 * @return Non-Zero if operand can be loaded
806 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
807 ir_node *op = get_irn_n(irn, i);
808 const ir_mode *mode = get_irn_mode(op);
809 const ir_mode *spillmode = get_spill_mode(op);
811 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
812 get_irn_arity(irn) != 5 || /* must be a binary operation */
813 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
814 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
815 ! ia32_is_spillmode_compatible(mode, spillmode) ||
816 (i != 2 && i != 3) || /* a "real" operand position must be requested */
817 (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
818 is_ia32_use_frame(irn)) /* must not already use frame */
824 static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
825 const ia32_irn_ops_t *ops = self;
826 ia32_code_gen_t *cg = ops->cg;
828 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
831 ir_node *tmp = get_irn_n(irn, 3);
832 set_irn_n(irn, 3, get_irn_n(irn, 2));
833 set_irn_n(irn, 2, tmp);
836 set_ia32_am_support(irn, ia32_am_Source);
837 set_ia32_op_type(irn, ia32_AddrModeS);
838 set_ia32_am_flavour(irn, ia32_B);
839 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
840 set_ia32_use_frame(irn);
841 set_ia32_got_reload(irn);
843 set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
844 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
845 set_irn_n(irn, 4, spill);
847 //FIXME DBG_OPT_AM_S(reload, irn);
850 static const be_abi_callbacks_t ia32_abi_callbacks = {
853 ia32_abi_get_between_type,
854 ia32_abi_dont_save_regs,
859 /* fill register allocator interface */
861 static const arch_irn_ops_if_t ia32_irn_ops_if = {
862 ia32_get_irn_reg_req,
867 ia32_get_frame_entity,
868 ia32_set_frame_entity,
869 ia32_set_frame_offset,
872 ia32_get_op_estimated_cost,
873 ia32_possible_memory_operand,
874 ia32_perform_memory_operand,
877 ia32_irn_ops_t ia32_irn_ops = {
884 /**************************************************
887 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
888 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
889 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
890 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
893 **************************************************/
896 * Transforms the standard firm graph into
899 static void ia32_prepare_graph(void *self) {
900 ia32_code_gen_t *cg = self;
901 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
903 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
905 /* 1st: transform psi condition trees */
906 ia32_pre_transform_phase(cg);
908 /* 2nd: transform all remaining nodes */
909 ia32_transform_graph(cg);
910 // Matze: disabled for now. Because after transformation start block has no
911 // self-loop anymore so it might be merged with its successor block. This
912 // will bring several nodes to the startblock which sometimes get scheduled
913 // before the initial IncSP/Barrier
914 //local_optimize_graph(cg->irg);
917 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
919 /* 3rd: optimize address mode */
920 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
921 ia32_optimize_addressmode(cg);
924 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
926 DEBUG_ONLY(cg->mod = old_mod;)
930 * Dummy functions for hooks we don't need but which must be filled.
932 static void ia32_before_sched(void *self) {
935 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
938 ir_node *mem_proj = NULL;
943 mode = get_irn_mode(irn);
945 /* check if we already saw this node or the node has more than one user */
946 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) {
950 /* mark irn visited */
951 bitset_add_irn(already_visited, irn);
953 /* non-Tuple nodes with one user: ok, return */
954 if (get_irn_n_edges(irn) >= 1 && mode != mode_T) {
958 /* tuple node has one user which is not the mem proj-> ok */
959 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
960 mem_proj = ia32_get_proj_for_mode(irn, mode_M);
961 if (mem_proj == NULL) {
966 arity = get_irn_arity(irn);
967 for (i = 0; i < arity; ++i) {
968 ir_node *pred = get_irn_n(irn, i);
970 /* do not follow memory edges or we will accidentally remove stores */
971 if (get_irn_mode(pred) == mode_M) {
972 if(mem_proj != NULL) {
973 edges_reroute(mem_proj, pred, get_irn_irg(mem_proj));
979 set_irn_n(irn, i, new_Bad());
982 The current node is about to be removed: if the predecessor
983 has only this node as user, it need to be removed as well.
985 if (get_irn_n_edges(pred) <= 1)
986 remove_unused_nodes(pred, already_visited);
989 // we need to set the presd to Bad again to also get the memory edges
990 arity = get_irn_arity(irn);
991 for (i = 0; i < arity; ++i) {
992 set_irn_n(irn, i, new_Bad());
995 if (sched_is_scheduled(irn)) {
1000 static void remove_unused_loads_walker(ir_node *irn, void *env) {
1001 bitset_t *already_visited = env;
1002 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
1003 remove_unused_nodes(irn, env);
1007 * Called before the register allocator.
1008 * Calculate a block schedule here. We need it for the x87
1009 * simulator and the emitter.
1011 static void ia32_before_ra(void *self) {
1012 ia32_code_gen_t *cg = self;
1013 bitset_t *already_visited = bitset_irg_alloca(cg->irg);
1016 Handle special case:
1017 There are sometimes unused loads, only pinned by memory.
1018 We need to remove those Loads and all other nodes which won't be used
1019 after removing the Load from schedule.
1021 irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
1026 * Transforms a be_Reload into a ia32 Load.
1028 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1029 ir_graph *irg = get_irn_irg(node);
1030 dbg_info *dbg = get_irn_dbg_info(node);
1031 ir_node *block = get_nodes_block(node);
1032 ir_entity *ent = be_get_frame_entity(node);
1033 ir_mode *mode = get_irn_mode(node);
1034 ir_mode *spillmode = get_spill_mode(node);
1035 ir_node *noreg = ia32_new_NoReg_gp(cg);
1036 ir_node *sched_point = NULL;
1037 ir_node *ptr = get_irg_frame(irg);
1038 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1039 ir_node *new_op, *proj;
1040 const arch_register_t *reg;
1042 if (sched_is_scheduled(node)) {
1043 sched_point = sched_prev(node);
1046 if (mode_is_float(spillmode)) {
1048 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem);
1050 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem);
1053 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1055 set_ia32_am_support(new_op, ia32_am_Source);
1056 set_ia32_op_type(new_op, ia32_AddrModeS);
1057 set_ia32_am_flavour(new_op, ia32_B);
1058 set_ia32_ls_mode(new_op, spillmode);
1059 set_ia32_frame_ent(new_op, ent);
1060 set_ia32_use_frame(new_op);
1062 DBG_OPT_RELOAD2LD(node, new_op);
1064 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1067 sched_add_after(sched_point, new_op);
1068 sched_add_after(new_op, proj);
1073 /* copy the register from the old node to the new Load */
1074 reg = arch_get_irn_register(cg->arch_env, node);
1075 arch_set_irn_register(cg->arch_env, new_op, reg);
1077 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1079 exchange(node, proj);
1083 * Transforms a be_Spill node into a ia32 Store.
1085 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1086 ir_graph *irg = get_irn_irg(node);
1087 dbg_info *dbg = get_irn_dbg_info(node);
1088 ir_node *block = get_nodes_block(node);
1089 ir_entity *ent = be_get_frame_entity(node);
1090 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1091 ir_mode *mode = get_spill_mode(spillval);
1092 ir_node *noreg = ia32_new_NoReg_gp(cg);
1093 ir_node *nomem = new_rd_NoMem(irg);
1094 ir_node *ptr = get_irg_frame(irg);
1095 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1097 ir_node *sched_point = NULL;
1099 if (sched_is_scheduled(node)) {
1100 sched_point = sched_prev(node);
1103 if (mode_is_float(mode)) {
1105 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem);
1107 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem);
1109 else if (get_mode_size_bits(mode) == 8) {
1110 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem);
1113 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem);
1116 set_ia32_am_support(store, ia32_am_Dest);
1117 set_ia32_op_type(store, ia32_AddrModeD);
1118 set_ia32_am_flavour(store, ia32_B);
1119 set_ia32_ls_mode(store, mode);
1120 set_ia32_frame_ent(store, ent);
1121 set_ia32_use_frame(store);
1123 DBG_OPT_SPILL2ST(node, store);
1124 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1127 sched_add_after(sched_point, store);
1131 exchange(node, store);
1134 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1135 ir_graph *irg = get_irn_irg(node);
1136 dbg_info *dbg = get_irn_dbg_info(node);
1137 ir_node *block = get_nodes_block(node);
1138 ir_node *noreg = ia32_new_NoReg_gp(cg);
1139 ir_node *frame = get_irg_frame(irg);
1141 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, noreg, sp, mem);
1143 set_ia32_frame_ent(push, ent);
1144 set_ia32_use_frame(push);
1145 set_ia32_op_type(push, ia32_AddrModeS);
1146 set_ia32_am_flavour(push, ia32_B);
1147 set_ia32_ls_mode(push, mode_Is);
1149 sched_add_before(schedpoint, push);
1153 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1154 ir_graph *irg = get_irn_irg(node);
1155 dbg_info *dbg = get_irn_dbg_info(node);
1156 ir_node *block = get_nodes_block(node);
1157 ir_node *noreg = ia32_new_NoReg_gp(cg);
1158 ir_node *frame = get_irg_frame(irg);
1160 ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, sp, new_NoMem());
1162 set_ia32_frame_ent(pop, ent);
1163 set_ia32_use_frame(pop);
1164 set_ia32_op_type(pop, ia32_AddrModeD);
1165 set_ia32_am_flavour(pop, ia32_am_OB);
1166 set_ia32_ls_mode(pop, mode_Is);
1168 sched_add_before(schedpoint, pop);
1173 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos, ir_node *schedpoint) {
1174 ir_graph *irg = get_irn_irg(node);
1175 dbg_info *dbg = get_irn_dbg_info(node);
1176 ir_node *block = get_nodes_block(node);
1177 ir_mode *spmode = mode_Iu;
1178 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1181 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1182 arch_set_irn_register(cg->arch_env, sp, spreg);
1183 sched_add_before(schedpoint, sp);
1189 * Transform memperm, currently we do this the ugly way and produce
1190 * push/pop into/from memory cascades. This is possible without using
1193 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1194 ir_graph *irg = get_irn_irg(node);
1195 ir_node *block = get_nodes_block(node);
1199 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1200 const ir_edge_t *edge;
1201 const ir_edge_t *next;
1204 arity = be_get_MemPerm_entity_arity(node);
1205 pops = alloca(arity * sizeof(pops[0]));
1208 for(i = 0; i < arity; ++i) {
1209 ir_entity *ent = be_get_MemPerm_in_entity(node, i);
1210 ir_type *enttype = get_entity_type(ent);
1211 int entbits = get_type_size_bits(enttype);
1212 ir_node *mem = get_irn_n(node, i + 1);
1215 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1217 push = create_push(cg, node, node, sp, mem, ent);
1218 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1220 // add another push after the first one
1221 push = create_push(cg, node, node, sp, mem, ent);
1222 add_ia32_am_offs_int(push, 4);
1223 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1226 set_irn_n(node, i, new_Bad());
1230 for(i = arity - 1; i >= 0; --i) {
1231 ir_entity *ent = be_get_MemPerm_out_entity(node, i);
1232 ir_type *enttype = get_entity_type(ent);
1233 int entbits = get_type_size_bits(enttype);
1237 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1239 pop = create_pop(cg, node, node, sp, ent);
1240 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1242 add_ia32_am_offs_int(pop, 4);
1244 // add another pop after the first one
1245 pop = create_pop(cg, node, node, sp, ent);
1246 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1253 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1254 sched_add_before(node, keep);
1256 // exchange memprojs
1257 foreach_out_edge_safe(node, edge, next) {
1258 ir_node *proj = get_edge_src_irn(edge);
1259 int p = get_Proj_proj(proj);
1263 set_Proj_pred(proj, pops[p]);
1264 set_Proj_proj(proj, 3);
1268 arity = get_irn_arity(node);
1269 for(i = 0; i < arity; ++i) {
1270 set_irn_n(node, i, new_Bad());
1276 * Block-Walker: Calls the transform functions Spill and Reload.
1278 static void ia32_after_ra_walker(ir_node *block, void *env) {
1279 ir_node *node, *prev;
1280 ia32_code_gen_t *cg = env;
1282 /* beware: the schedule is changed here */
1283 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1284 prev = sched_prev(node);
1286 if (be_is_Reload(node)) {
1287 transform_to_Load(cg, node);
1288 } else if (be_is_Spill(node)) {
1289 transform_to_Store(cg, node);
1290 } else if(be_is_MemPerm(node)) {
1291 transform_MemPerm(cg, node);
1297 * Collects nodes that need frame entities assigned.
1299 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1301 be_fec_env_t *env = data;
1303 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1304 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1305 int align = get_mode_size_bytes(mode);
1306 be_node_needs_frame_entity(env, node, mode, align);
1307 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1308 && is_ia32_use_frame(node)) {
1309 if (is_ia32_got_reload(node) || is_ia32_Load(node)) {
1310 const ir_mode *mode = get_ia32_ls_mode(node);
1311 int align = get_mode_size_bytes(mode);
1312 be_node_needs_frame_entity(env, node, mode, align);
1313 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)) {
1314 const ir_mode *mode = get_ia32_ls_mode(node);
1316 be_node_needs_frame_entity(env, node, mode, align);
1317 } else if (is_ia32_SetST0(node)) {
1318 const ir_mode *mode = get_ia32_ls_mode(node);
1320 be_node_needs_frame_entity(env, node, mode, align);
1323 if(!is_ia32_Store(node)
1324 && !is_ia32_xStore(node)
1325 && !is_ia32_xStoreSimple(node)
1326 && !is_ia32_vfist(node)
1327 && !is_ia32_GetST0(node)) {
1336 * We transform Spill and Reload here. This needs to be done before
1337 * stack biasing otherwise we would miss the corrected offset for these nodes.
1339 static void ia32_after_ra(void *self) {
1340 ia32_code_gen_t *cg = self;
1341 ir_graph *irg = cg->irg;
1342 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1344 /* create and coalesce frame entities */
1345 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1346 be_assign_entities(fec_env);
1347 be_free_frame_entity_coalescer(fec_env);
1349 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1351 ia32_finish_irg(irg, cg);
1355 * Last touchups for the graph before emit: x87 simulation to replace the
1356 * virtual with real x87 instructions, creating a block schedule and peephole
1359 static void ia32_finish(void *self) {
1360 ia32_code_gen_t *cg = self;
1361 ir_graph *irg = cg->irg;
1363 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1364 if (cg->used_fp == fp_x87 || cg->force_sim) {
1365 x87_simulate_graph(cg->arch_env, cg->birg);
1368 /* create block schedule, this also removes empty blocks which might
1369 * produce critical edges */
1370 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1372 /* do peephole optimisations */
1373 ia32_peephole_optimization(irg, cg);
1377 * Emits the code, closes the output file and frees
1378 * the code generator interface.
1380 static void ia32_codegen(void *self) {
1381 ia32_code_gen_t *cg = self;
1382 ir_graph *irg = cg->irg;
1384 ia32_gen_routine(cg, cg->isa->out, irg);
1388 /* remove it from the isa */
1391 /* de-allocate code generator */
1392 del_set(cg->reg_set);
1396 static void *ia32_cg_init(be_irg_t *birg);
1398 static const arch_code_generator_if_t ia32_code_gen_if = {
1400 NULL, /* before abi introduce hook */
1403 ia32_before_sched, /* before scheduling hook */
1404 ia32_before_ra, /* before register allocation hook */
1405 ia32_after_ra, /* after register allocation hook */
1406 ia32_finish, /* called before codegen */
1407 ia32_codegen /* emit && done */
1411 * Initializes a IA32 code generator.
1413 static void *ia32_cg_init(be_irg_t *birg) {
1414 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1415 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1417 cg->impl = &ia32_code_gen_if;
1418 cg->irg = birg->irg;
1419 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1420 cg->arch_env = birg->main_env->arch_env;
1423 cg->blk_sched = NULL;
1424 cg->fp_kind = isa->fp_kind;
1425 cg->used_fp = fp_none;
1426 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1428 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1430 /* copy optimizations from isa for easier access */
1432 cg->arch = isa->arch;
1433 cg->opt_arch = isa->opt_arch;
1439 if (isa->name_obst) {
1440 obstack_free(isa->name_obst, NULL);
1441 obstack_init(isa->name_obst);
1445 cur_reg_set = cg->reg_set;
1447 ia32_irn_ops.cg = cg;
1449 return (arch_code_generator_t *)cg;
1454 /*****************************************************************
1455 * ____ _ _ _____ _____
1456 * | _ \ | | | | |_ _|/ ____| /\
1457 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1458 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1459 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1460 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1462 *****************************************************************/
1465 * Set output modes for GCC
1467 static const tarval_mode_info mo_integer = {
1474 * set the tarval output mode of all integer modes to decimal
1476 static void set_tarval_output_modes(void)
1480 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1481 ir_mode *mode = get_irp_mode(i);
1483 if (mode_is_int(mode))
1484 set_tarval_mode_output_option(mode, &mo_integer);
1488 const arch_isa_if_t ia32_isa_if;
1491 * The template that generates a new ISA object.
1492 * Note that this template can be changed by command line
1495 static ia32_isa_t ia32_isa_template = {
1497 &ia32_isa_if, /* isa interface implementation */
1498 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1499 &ia32_gp_regs[REG_EBP], /* base pointer register */
1500 -1, /* stack direction */
1501 NULL, /* main environment */
1503 NULL, /* 16bit register names */
1504 NULL, /* 8bit register names */
1508 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1509 IA32_OPT_DOAM | /* optimize address mode default: on */
1510 IA32_OPT_LEA | /* optimize for LEAs default: on */
1511 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1512 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1513 IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
1514 arch_pentium_4, /* instruction architecture */
1515 arch_pentium_4, /* optimize for architecture */
1516 fp_sse2, /* use sse2 unit */
1517 NULL, /* current code generator */
1518 NULL, /* output file */
1520 NULL, /* name obstack */
1521 0 /* name obst size */
1526 * Initializes the backend ISA.
1528 static void *ia32_init(FILE *file_handle) {
1529 static int inited = 0;
1535 set_tarval_output_modes();
1537 isa = xmalloc(sizeof(*isa));
1538 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1540 ia32_register_init(isa);
1541 ia32_create_opcodes();
1542 ia32_register_copy_attr_func();
1544 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1545 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1546 /* no SSE2 for these cpu's */
1547 isa->fp_kind = fp_x87;
1549 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1550 /* Pentium 4 don't like inc and dec instructions */
1551 isa->opt &= ~IA32_OPT_INCDEC;
1554 isa->regs_16bit = pmap_create();
1555 isa->regs_8bit = pmap_create();
1556 isa->types = pmap_create();
1557 isa->tv_ent = pmap_create();
1558 isa->out = file_handle;
1559 isa->cpu = ia32_init_machine_description();
1561 ia32_build_16bit_reg_map(isa->regs_16bit);
1562 ia32_build_8bit_reg_map(isa->regs_8bit);
1564 /* patch register names of x87 registers */
1565 ia32_st_regs[0].name = "st";
1566 ia32_st_regs[1].name = "st(1)";
1567 ia32_st_regs[2].name = "st(2)";
1568 ia32_st_regs[3].name = "st(3)";
1569 ia32_st_regs[4].name = "st(4)";
1570 ia32_st_regs[5].name = "st(5)";
1571 ia32_st_regs[6].name = "st(6)";
1572 ia32_st_regs[7].name = "st(7)";
1575 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1576 obstack_init(isa->name_obst);
1579 ia32_handle_intrinsics();
1580 ia32_switch_section(isa->out, NO_SECTION);
1582 /* needed for the debug support */
1583 ia32_switch_section(isa->out, SECTION_TEXT);
1584 fprintf(isa->out, ".Ltext0:\n");
1594 * Closes the output file and frees the ISA structure.
1596 static void ia32_done(void *self) {
1597 ia32_isa_t *isa = self;
1599 /* emit now all global declarations */
1600 ia32_gen_decls(isa->out, isa->arch_isa.main_env);
1602 pmap_destroy(isa->regs_16bit);
1603 pmap_destroy(isa->regs_8bit);
1604 pmap_destroy(isa->tv_ent);
1605 pmap_destroy(isa->types);
1608 obstack_free(isa->name_obst, NULL);
1616 * Return the number of register classes for this architecture.
1617 * We report always these:
1618 * - the general purpose registers
1619 * - the SSE floating point register set
1620 * - the virtual floating point registers
1622 static int ia32_get_n_reg_class(const void *self) {
1627 * Return the register class for index i.
1629 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1630 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1632 return &ia32_reg_classes[CLASS_ia32_gp];
1634 return &ia32_reg_classes[CLASS_ia32_xmm];
1636 return &ia32_reg_classes[CLASS_ia32_vfp];
1640 * Get the register class which shall be used to store a value of a given mode.
1641 * @param self The this pointer.
1642 * @param mode The mode in question.
1643 * @return A register class which can hold values of the given mode.
1645 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1646 const ia32_isa_t *isa = self;
1647 if (mode_is_float(mode)) {
1648 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1651 return &ia32_reg_classes[CLASS_ia32_gp];
1655 * Get the ABI restrictions for procedure calls.
1656 * @param self The this pointer.
1657 * @param method_type The type of the method (procedure) in question.
1658 * @param abi The abi object to be modified
1660 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1661 const ia32_isa_t *isa = self;
1664 unsigned cc = get_method_calling_convention(method_type);
1665 int n = get_method_n_params(method_type);
1668 int i, ignore_1, ignore_2;
1670 const arch_register_t *reg;
1671 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1673 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1675 /* set abi flags for calls */
1676 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1677 call_flags.bits.store_args_sequential = use_push;
1678 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1679 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1680 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1682 /* set stack parameter passing style */
1683 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1685 /* collect the mode for each type */
1686 modes = alloca(n * sizeof(modes[0]));
1688 for (i = 0; i < n; i++) {
1689 tp = get_method_param_type(method_type, i);
1690 modes[i] = get_type_mode(tp);
1693 /* set register parameters */
1694 if (cc & cc_reg_param) {
1695 /* determine the number of parameters passed via registers */
1696 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1698 /* loop over all parameters and set the register requirements */
1699 for (i = 0; i <= biggest_n; i++) {
1700 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1701 assert(reg && "kaputt");
1702 be_abi_call_param_reg(abi, i, reg);
1709 /* set stack parameters */
1710 for (i = stack_idx; i < n; i++) {
1711 /* parameters on the stack are 32 bit aligned */
1712 be_abi_call_param_stack(abi, i, 4, 0, 0);
1716 /* set return registers */
1717 n = get_method_n_ress(method_type);
1719 assert(n <= 2 && "more than two results not supported");
1721 /* In case of 64bit returns, we will have two 32bit values */
1723 tp = get_method_res_type(method_type, 0);
1724 mode = get_type_mode(tp);
1726 assert(!mode_is_float(mode) && "two FP results not supported");
1728 tp = get_method_res_type(method_type, 1);
1729 mode = get_type_mode(tp);
1731 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1733 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1734 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1737 const arch_register_t *reg;
1739 tp = get_method_res_type(method_type, 0);
1740 assert(is_atomic_type(tp));
1741 mode = get_type_mode(tp);
1743 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1745 be_abi_call_res_reg(abi, 0, reg);
1750 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1751 return &ia32_irn_ops;
1754 const arch_irn_handler_t ia32_irn_handler = {
1758 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1759 return &ia32_irn_handler;
1762 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1763 return is_ia32_irn(irn) ? 1 : -1;
1767 * Initializes the code generator interface.
1769 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1770 return &ia32_code_gen_if;
1774 * Returns the estimated execution time of an ia32 irn.
1776 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1777 const arch_env_t *arch_env = env;
1778 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1781 list_sched_selector_t ia32_sched_selector;
1784 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1786 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1787 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1788 ia32_sched_selector.exectime = ia32_sched_exectime;
1789 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1790 return &ia32_sched_selector;
1793 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self) {
1798 * Returns the necessary byte alignment for storing a register of given class.
1800 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1801 ir_mode *mode = arch_register_class_mode(cls);
1802 int bytes = get_mode_size_bytes(mode);
1804 if (mode_is_float(mode) && bytes > 8)
1809 static const be_execution_unit_t ***ia32_get_allowed_execution_units(const void *self, const ir_node *irn) {
1810 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1811 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1812 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1815 static const be_execution_unit_t *_allowed_units_GP[] = {
1816 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1817 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1818 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1819 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1820 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1821 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1822 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1825 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1826 &be_machine_execution_units_DUMMY[0],
1829 static const be_execution_unit_t **_units_callret[] = {
1830 _allowed_units_BRANCH,
1833 static const be_execution_unit_t **_units_other[] = {
1837 static const be_execution_unit_t **_units_dummy[] = {
1838 _allowed_units_DUMMY,
1841 const be_execution_unit_t ***ret;
1843 if (is_ia32_irn(irn)) {
1844 ret = get_ia32_exec_units(irn);
1846 else if (is_be_node(irn)) {
1847 if (be_is_Call(irn) || be_is_Return(irn)) {
1848 ret = _units_callret;
1850 else if (be_is_Barrier(irn)) {
1865 * Return the abstract ia32 machine.
1867 static const be_machine_t *ia32_get_machine(const void *self) {
1868 const ia32_isa_t *isa = self;
1873 * Return irp irgs in the desired order.
1875 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list) {
1880 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1881 * @return 1 if allowed, 0 otherwise
1883 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
1885 ir_node *cmp, *cmp_a, *phi;
1888 /* we don't want long long an floating point Psi */
1889 #define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
1891 if (get_irn_mode(sel) != mode_b)
1894 cmp = get_Proj_pred(sel);
1895 cmp_a = get_Cmp_left(cmp);
1896 mode = get_irn_mode(cmp_a);
1898 if (IS_BAD_PSI_MODE(mode))
1901 /* check the Phi nodes */
1902 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1903 ir_node *pred_i = get_irn_n(phi, i);
1904 ir_node *pred_j = get_irn_n(phi, j);
1905 ir_mode *mode_i = get_irn_mode(pred_i);
1906 ir_mode *mode_j = get_irn_mode(pred_j);
1908 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1912 #undef IS_BAD_PSI_MODE
1917 static ia32_intrinsic_env_t intrinsic_env = {
1918 NULL, /**< the irg, these entities belong to */
1919 NULL, /**< entity for first div operand (move into FPU) */
1920 NULL, /**< entity for second div operand (move into FPU) */
1921 NULL, /**< entity for converts ll -> d */
1922 NULL, /**< entity for converts d -> ll */
1926 * Returns the libFirm configuration parameter for this backend.
1928 static const backend_params *ia32_get_libfirm_params(void) {
1929 static const opt_if_conv_info_t ifconv = {
1930 4, /* maxdepth, doesn't matter for Psi-conversion */
1931 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
1933 static const arch_dep_params_t ad = {
1934 1, /* also use subs */
1935 4, /* maximum shifts */
1936 31, /* maximum shift amount */
1938 1, /* allow Mulhs */
1939 1, /* allow Mulus */
1940 32 /* Mulh allowed up to 32 bit */
1942 static backend_params p = {
1943 NULL, /* no additional opcodes */
1944 NULL, /* will be set later */
1945 1, /* need dword lowering */
1946 ia32_create_intrinsic_fkt,
1947 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1948 NULL, /* will be set later */
1952 p.if_conv_info = &ifconv;
1957 /* instruction set architectures. */
1958 static const lc_opt_enum_int_items_t arch_items[] = {
1959 { "386", arch_i386, },
1960 { "486", arch_i486, },
1961 { "pentium", arch_pentium, },
1962 { "586", arch_pentium, },
1963 { "pentiumpro", arch_pentium_pro, },
1964 { "686", arch_pentium_pro, },
1965 { "pentiummmx", arch_pentium_mmx, },
1966 { "pentium2", arch_pentium_2, },
1967 { "p2", arch_pentium_2, },
1968 { "pentium3", arch_pentium_3, },
1969 { "p3", arch_pentium_3, },
1970 { "pentium4", arch_pentium_4, },
1971 { "p4", arch_pentium_4, },
1972 { "pentiumm", arch_pentium_m, },
1973 { "pm", arch_pentium_m, },
1974 { "core", arch_core, },
1976 { "athlon", arch_athlon, },
1977 { "athlon64", arch_athlon_64, },
1978 { "opteron", arch_opteron, },
1982 static lc_opt_enum_int_var_t arch_var = {
1983 &ia32_isa_template.arch, arch_items
1986 static lc_opt_enum_int_var_t opt_arch_var = {
1987 &ia32_isa_template.opt_arch, arch_items
1990 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1992 { "sse2", fp_sse2 },
1996 static lc_opt_enum_int_var_t fp_unit_var = {
1997 &ia32_isa_template.fp_kind, fp_unit_items
2000 static const lc_opt_enum_int_items_t gas_items[] = {
2001 { "linux", ASM_LINUX_GAS },
2002 { "mingw", ASM_MINGW_GAS },
2006 static lc_opt_enum_int_var_t gas_var = {
2007 (int *)&asm_flavour, gas_items
2010 static const lc_opt_table_entry_t ia32_options[] = {
2011 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
2012 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
2013 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
2014 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
2015 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
2016 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
2017 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
2018 LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
2019 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2022 #endif /* WITH_LIBCORE */
2024 const arch_isa_if_t ia32_isa_if = {
2027 ia32_get_n_reg_class,
2029 ia32_get_reg_class_for_mode,
2031 ia32_get_irn_handler,
2032 ia32_get_code_generator_if,
2033 ia32_get_list_sched_selector,
2034 ia32_get_ilp_sched_selector,
2035 ia32_get_reg_class_alignment,
2036 ia32_get_libfirm_params,
2037 ia32_get_allowed_execution_units,
2042 void be_init_arch_ia32(void)
2044 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2045 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2047 lc_opt_add_table(ia32_grp, ia32_options);
2048 be_register_isa_if("ia32", &ia32_isa_if);
2051 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);