2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
31 #include "lc_opts_enum.h"
35 #include "pseudo_irg.h"
40 #include "iredges_t.h"
46 #include "irdump_grgen.h"
53 #include "iroptimize.h"
54 #include "instrument.h"
57 #include "../beirg_t.h"
58 #include "../benode_t.h"
59 #include "../belower.h"
60 #include "../besched_t.h"
63 #include "../beirgmod.h"
64 #include "../be_dbgout.h"
65 #include "../beblocksched.h"
66 #include "../bemachine.h"
67 #include "../beilpsched.h"
68 #include "../bespillslots.h"
69 #include "../bemodule.h"
70 #include "../begnuas.h"
71 #include "../bestate.h"
72 #include "../beflags.h"
74 #include "bearch_ia32_t.h"
76 #include "ia32_new_nodes.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "gen_ia32_machine.h"
79 #include "ia32_transform.h"
80 #include "ia32_emitter.h"
81 #include "ia32_map_regs.h"
82 #include "ia32_optimize.h"
84 #include "ia32_dbg_stat.h"
85 #include "ia32_finish.h"
86 #include "ia32_util.h"
88 #include "ia32_architecture.h"
91 #include "ia32_pbqp_transform.h"
94 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
97 static set *cur_reg_set = NULL;
99 ir_mode *mode_fpcw = NULL;
100 ia32_code_gen_t *ia32_current_cg = NULL;
103 * The environment for the intrinsic mapping.
105 static ia32_intrinsic_env_t intrinsic_env = {
107 NULL, /* the irg, these entities belong to */
108 NULL, /* entity for first div operand (move into FPU) */
109 NULL, /* entity for second div operand (move into FPU) */
110 NULL, /* entity for converts ll -> d */
111 NULL, /* entity for converts d -> ll */
112 NULL, /* entity for __divdi3 library call */
113 NULL, /* entity for __moddi3 library call */
114 NULL, /* entity for __udivdi3 library call */
115 NULL, /* entity for __umoddi3 library call */
116 NULL, /* bias value for conversion from float to unsigned 64 */
120 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
122 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
123 create_const_node_func func,
124 const arch_register_t* reg)
126 ir_node *block, *res;
131 block = get_irg_start_block(cg->irg);
132 res = func(NULL, cg->irg, block);
133 arch_set_irn_register(cg->arch_env, res, reg);
136 add_irn_dep(get_irg_end(cg->irg), res);
137 /* add_irn_dep(get_irg_start(cg->irg), res); */
142 /* Creates the unique per irg GP NoReg node. */
143 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
144 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
145 &ia32_gp_regs[REG_GP_NOREG]);
148 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
149 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
150 &ia32_vfp_regs[REG_VFP_NOREG]);
153 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
154 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
155 &ia32_xmm_regs[REG_XMM_NOREG]);
158 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
159 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
160 &ia32_gp_regs[REG_GP_UKNWN]);
163 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
164 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
165 &ia32_vfp_regs[REG_VFP_UKNWN]);
168 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
169 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
170 &ia32_xmm_regs[REG_XMM_UKNWN]);
173 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
174 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
175 &ia32_fp_cw_regs[REG_FPCW]);
180 * Returns the admissible noreg register node for input register pos of node irn.
182 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
183 const arch_register_req_t *req;
185 req = arch_get_register_req(cg->arch_env, irn, pos);
186 assert(req != NULL && "Missing register requirements");
187 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
188 return ia32_new_NoReg_gp(cg);
190 if (ia32_cg_config.use_sse2) {
191 return ia32_new_NoReg_xmm(cg);
193 return ia32_new_NoReg_vfp(cg);
197 /**************************************************
200 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
201 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
202 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
203 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
206 **************************************************/
209 * Return register requirements for an ia32 node.
210 * If the node returns a tuple (mode_T) then the proj's
211 * will be asked for this information.
213 static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node,
216 ir_mode *mode = get_irn_mode(node);
219 if (mode == mode_X || is_Block(node)) {
220 return arch_no_register_req;
223 if (mode == mode_T && pos < 0) {
224 return arch_no_register_req;
227 node_pos = pos == -1 ? 0 : pos;
229 if (mode == mode_M || pos >= 0) {
230 return arch_no_register_req;
233 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
234 node = skip_Proj_const(node);
237 if (is_ia32_irn(node)) {
238 const arch_register_req_t *req;
240 req = get_ia32_in_req(node, pos);
242 req = get_ia32_out_req(node, node_pos);
249 /* unknowns should be transformed already */
250 assert(!is_Unknown(node));
251 return arch_no_register_req;
254 static void ia32_set_irn_reg(ir_node *irn, const arch_register_t *reg)
258 if (get_irn_mode(irn) == mode_X) {
263 pos = get_Proj_proj(irn);
264 irn = skip_Proj(irn);
267 if (is_ia32_irn(irn)) {
268 const arch_register_t **slots;
270 slots = get_ia32_slots(irn);
273 ia32_set_firm_reg(irn, reg, cur_reg_set);
277 static const arch_register_t *ia32_get_irn_reg(const ir_node *irn)
280 const arch_register_t *reg = NULL;
284 if (get_irn_mode(irn) == mode_X) {
288 pos = get_Proj_proj(irn);
289 irn = skip_Proj_const(irn);
292 if (is_ia32_irn(irn)) {
293 const arch_register_t **slots;
294 slots = get_ia32_slots(irn);
295 assert(pos < get_ia32_n_res(irn));
298 reg = ia32_get_firm_reg(irn, cur_reg_set);
304 static arch_irn_class_t ia32_classify(const ir_node *irn) {
305 arch_irn_class_t classification = arch_irn_class_normal;
307 irn = skip_Proj_const(irn);
310 classification |= arch_irn_class_branch;
312 if (! is_ia32_irn(irn))
313 return classification & ~arch_irn_class_normal;
316 classification |= arch_irn_class_load;
319 classification |= arch_irn_class_store;
321 if (is_ia32_need_stackent(irn))
322 classification |= arch_irn_class_reload;
324 return classification;
327 static arch_irn_flags_t ia32_get_flags(const ir_node *irn) {
328 arch_irn_flags_t flags = arch_irn_flags_none;
331 return arch_irn_flags_ignore;
333 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
334 ir_node *pred = get_Proj_pred(irn);
336 if(is_ia32_irn(pred)) {
337 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
343 if (is_ia32_irn(irn)) {
344 flags |= get_ia32_flags(irn);
351 * The IA32 ABI callback object.
354 be_abi_call_flags_bits_t flags; /**< The call flags. */
355 const arch_isa_t *isa; /**< The ISA handle. */
356 const arch_env_t *aenv; /**< The architecture environment. */
357 ir_graph *irg; /**< The associated graph. */
360 static ir_entity *ia32_get_frame_entity(const ir_node *irn) {
361 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
364 static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) {
365 set_ia32_frame_ent(irn, ent);
368 static void ia32_set_frame_offset(ir_node *irn, int bias)
370 if (get_ia32_frame_ent(irn) == NULL)
373 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
374 ia32_code_gen_t *cg = ia32_current_cg;
375 int omit_fp = be_abi_omit_fp(cg->birg->abi);
377 /* Pop nodes modify the stack pointer before calculating the
378 * destination address, so fix this here
383 add_ia32_am_offs_int(irn, bias);
386 static int ia32_get_sp_bias(const ir_node *node)
388 if (is_ia32_Push(node))
391 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
398 * Put all registers which are saved by the prologue/epilogue in a set.
400 * @param self The callback object.
401 * @param s The result set.
403 static void ia32_abi_dont_save_regs(void *self, pset *s)
405 ia32_abi_env_t *env = self;
406 if(env->flags.try_omit_fp)
407 pset_insert_ptr(s, env->isa->bp);
411 * Generate the routine prologue.
413 * @param self The callback object.
414 * @param mem A pointer to the mem node. Update this if you define new memory.
415 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
417 * @return The register which shall be used as a stack frame base.
419 * All nodes which define registers in @p reg_map must keep @p reg_map current.
421 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
423 ia32_abi_env_t *env = self;
424 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
425 ia32_code_gen_t *cg = isa->cg;
427 if (! env->flags.try_omit_fp) {
428 ir_node *bl = get_irg_start_block(env->irg);
429 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
430 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
431 ir_node *noreg = ia32_new_NoReg_gp(cg);
434 /* ALL nodes representing bp must be set to ignore. */
435 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
438 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
439 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
440 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
442 /* the push must have SP out register */
443 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
444 set_ia32_flags(push, arch_irn_flags_ignore);
446 /* move esp to ebp */
447 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
448 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
449 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
450 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
452 /* beware: the copy must be done before any other sp use */
453 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
454 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
455 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
456 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
458 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
459 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
468 * Generate the routine epilogue.
469 * @param self The callback object.
470 * @param bl The block for the epilog
471 * @param mem A pointer to the mem node. Update this if you define new memory.
472 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
473 * @return The register which shall be used as a stack frame base.
475 * All nodes which define registers in @p reg_map must keep @p reg_map current.
477 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
479 ia32_abi_env_t *env = self;
480 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
481 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
483 if (env->flags.try_omit_fp) {
484 /* simply remove the stack frame here */
485 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
486 add_irn_dep(curr_sp, *mem);
488 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
489 ir_graph *irg = current_ir_graph;
491 if (ia32_cg_config.use_leave) {
495 leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
496 set_ia32_flags(leave, arch_irn_flags_ignore);
497 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
498 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
502 /* the old SP is not needed anymore (kill the proj) */
503 assert(is_Proj(curr_sp));
504 be_kill_node(curr_sp);
506 /* copy ebp to esp */
507 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
508 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
509 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
512 pop = new_rd_ia32_Pop(NULL, env->irg, bl, *mem, curr_sp);
513 set_ia32_flags(pop, arch_irn_flags_ignore);
514 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
515 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
517 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
519 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
520 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
523 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
524 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
528 * Initialize the callback object.
529 * @param call The call object.
530 * @param aenv The architecture environment.
531 * @param irg The graph with the method.
532 * @return Some pointer. This pointer is passed to all other callback functions as self object.
534 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
536 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
537 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
538 env->flags = fl.bits;
541 env->isa = aenv->isa;
546 * Destroy the callback object.
547 * @param self The callback object.
549 static void ia32_abi_done(void *self) {
554 * Produces the type which sits between the stack args and the locals on the stack.
555 * it will contain the return address and space to store the old base pointer.
556 * @return The Firm type modeling the ABI between type.
558 static ir_type *ia32_abi_get_between_type(void *self)
560 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
561 static ir_type *omit_fp_between_type = NULL;
562 static ir_type *between_type = NULL;
564 ia32_abi_env_t *env = self;
566 if (! between_type) {
567 ir_entity *old_bp_ent;
568 ir_entity *ret_addr_ent;
569 ir_entity *omit_fp_ret_addr_ent;
571 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
572 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
574 between_type = new_type_struct(IDENT("ia32_between_type"));
575 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
576 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
578 set_entity_offset(old_bp_ent, 0);
579 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
580 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
581 set_type_state(between_type, layout_fixed);
583 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
584 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
586 set_entity_offset(omit_fp_ret_addr_ent, 0);
587 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
588 set_type_state(omit_fp_between_type, layout_fixed);
591 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
596 * Get the estimated cycle count for @p irn.
598 * @param self The this pointer.
599 * @param irn The node.
601 * @return The estimated cycle count for this operation
603 static int ia32_get_op_estimated_cost(const ir_node *irn)
606 ia32_op_type_t op_tp;
610 if (!is_ia32_irn(irn))
613 assert(is_ia32_irn(irn));
615 cost = get_ia32_latency(irn);
616 op_tp = get_ia32_op_type(irn);
618 if (is_ia32_CopyB(irn)) {
621 else if (is_ia32_CopyB_i(irn)) {
622 int size = get_ia32_copyb_size(irn);
623 cost = 20 + (int)ceil((4/3) * size);
625 /* in case of address mode operations add additional cycles */
626 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
628 In case of stack access and access to fixed addresses add 5 cycles
629 (we assume they are in cache), other memory operations cost 20
632 if(is_ia32_use_frame(irn) ||
633 (is_ia32_NoReg_GP(get_irn_n(irn, 0)) &&
634 is_ia32_NoReg_GP(get_irn_n(irn, 1)))) {
645 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
647 * @param irn The original operation
648 * @param i Index of the argument we want the inverse operation to yield
649 * @param inverse struct to be filled with the resulting inverse op
650 * @param obstack The obstack to use for allocation of the returned nodes array
651 * @return The inverse operation or NULL if operation invertible
653 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
657 ir_node *block, *noreg, *nomem;
660 /* we cannot invert non-ia32 irns */
661 if (! is_ia32_irn(irn))
664 /* operand must always be a real operand (not base, index or mem) */
665 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
668 /* we don't invert address mode operations */
669 if (get_ia32_op_type(irn) != ia32_Normal)
672 /* TODO: adjust for new immediates... */
673 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
677 irg = get_irn_irg(irn);
678 block = get_nodes_block(irn);
679 mode = get_irn_mode(irn);
680 irn_mode = get_irn_mode(irn);
681 noreg = get_irn_n(irn, 0);
682 nomem = new_r_NoMem(irg);
683 dbg = get_irn_dbg_info(irn);
685 /* initialize structure */
686 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
690 switch (get_ia32_irn_opcode(irn)) {
693 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
694 /* we have an add with a const here */
695 /* invers == add with negated const */
696 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
698 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
699 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
700 set_ia32_commutative(inverse->nodes[0]);
702 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
703 /* we have an add with a symconst here */
704 /* invers == sub with const */
705 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
707 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
710 /* normal add: inverse == sub */
711 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
718 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
719 /* we have a sub with a const/symconst here */
720 /* invers == add with this const */
721 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
722 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
723 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
727 if (i == n_ia32_binary_left) {
728 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
731 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
739 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
740 /* xor with const: inverse = xor */
741 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
742 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
743 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
747 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
753 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
758 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
763 /* inverse operation not supported */
770 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
772 if(mode_is_float(mode))
779 * Get the mode that should be used for spilling value node
781 static ir_mode *get_spill_mode(const ir_node *node)
783 ir_mode *mode = get_irn_mode(node);
784 return get_spill_mode_mode(mode);
788 * Checks whether an addressmode reload for a node with mode mode is compatible
789 * with a spillslot of mode spill_mode
791 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
793 if(mode_is_float(mode)) {
794 return mode == spillmode;
801 * Check if irn can load its operand at position i from memory (source addressmode).
802 * @param self Pointer to irn ops itself
803 * @param irn The irn to be checked
804 * @param i The operands position
805 * @return Non-Zero if operand can be loaded
807 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i) {
808 ir_node *op = get_irn_n(irn, i);
809 const ir_mode *mode = get_irn_mode(op);
810 const ir_mode *spillmode = get_spill_mode(op);
813 (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
814 ! is_ia32_irn(irn) || /* must be an ia32 irn */
815 get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */
816 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
817 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
818 ! ia32_is_spillmode_compatible(mode, spillmode) ||
819 is_ia32_use_frame(irn)) /* must not already use frame */
822 if (i == n_ia32_binary_left) {
823 const arch_register_req_t *req;
824 if(!is_ia32_commutative(irn))
826 /* we can't swap left/right for limited registers
827 * (As this (currently) breaks constraint handling copies)
829 req = get_ia32_in_req(irn, n_ia32_binary_left);
830 if (req->type & arch_register_req_type_limited) {
838 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
841 ia32_code_gen_t *cg = ia32_current_cg;
843 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
845 if (i == n_ia32_binary_left) {
846 ia32_swap_left_right(irn);
849 set_ia32_op_type(irn, ia32_AddrModeS);
850 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
851 set_ia32_use_frame(irn);
852 set_ia32_need_stackent(irn);
854 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
855 set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
856 set_irn_n(irn, n_ia32_mem, spill);
858 /* immediates are only allowed on the right side */
859 if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
860 ia32_swap_left_right(irn);
864 static const be_abi_callbacks_t ia32_abi_callbacks = {
867 ia32_abi_get_between_type,
868 ia32_abi_dont_save_regs,
873 /* fill register allocator interface */
875 static const arch_irn_ops_t ia32_irn_ops = {
876 ia32_get_irn_reg_req,
881 ia32_get_frame_entity,
882 ia32_set_frame_entity,
883 ia32_set_frame_offset,
886 ia32_get_op_estimated_cost,
887 ia32_possible_memory_operand,
888 ia32_perform_memory_operand,
891 /**************************************************
894 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
895 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
896 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
897 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
900 **************************************************/
902 static ir_entity *mcount = NULL;
904 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
906 static void ia32_before_abi(void *self) {
907 lower_mode_b_config_t lower_mode_b_config = {
908 mode_Iu, /* lowered mode */
909 mode_Bu, /* prefered mode for set */
910 0, /* don't lower direct compares */
912 ia32_code_gen_t *cg = self;
914 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
916 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
918 if (mcount == NULL) {
919 ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
920 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
921 /* FIXME: enter the right ld_ident here */
922 set_entity_ld_ident(mcount, get_entity_ident(mcount));
923 set_entity_visibility(mcount, visibility_external_allocated);
925 instrument_initcall(cg->irg, mcount);
930 * Transforms the standard firm graph into
933 static void ia32_prepare_graph(void *self) {
934 ia32_code_gen_t *cg = self;
936 /* do local optimisations */
937 optimize_graph_df(cg->irg);
939 /* TODO: we often have dead code reachable through out-edges here. So for
940 * now we rebuild edges (as we need correct user count for code selection)
943 edges_deactivate(cg->irg);
944 edges_activate(cg->irg);
948 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
951 /* transform nodes into assembler instructions by PBQP magic */
952 ia32_transform_graph_by_pbqp(cg);
956 be_dump(cg->irg, "-after_pbqp_transform", dump_ir_block_graph_sched);
958 /* transform remaining nodes into assembler instructions */
959 ia32_transform_graph(cg);
961 /* do local optimisations (mainly CSE) */
962 optimize_graph_df(cg->irg);
965 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
967 /* optimize address mode */
968 ia32_optimize_graph(cg);
971 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
973 /* do code placement, to optimize the position of constants */
977 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
981 * Dummy functions for hooks we don't need but which must be filled.
983 static void ia32_before_sched(void *self) {
987 static void turn_back_am(ir_node *node)
989 ir_graph *irg = current_ir_graph;
990 dbg_info *dbgi = get_irn_dbg_info(node);
991 ir_node *block = get_nodes_block(node);
992 ir_node *base = get_irn_n(node, n_ia32_base);
993 ir_node *index = get_irn_n(node, n_ia32_index);
994 ir_node *mem = get_irn_n(node, n_ia32_mem);
995 ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg);
999 const ir_edge_t *edge;
1001 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1002 load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1004 ia32_copy_am_attrs(load, node);
1005 set_irn_n(node, n_ia32_mem, new_NoMem());
1007 switch (get_ia32_am_arity(node)) {
1009 set_irn_n(node, n_ia32_unary_op, load_res);
1012 case ia32_am_binary:
1013 if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
1014 assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) ||
1015 is_ia32_Test(node) || is_ia32_Test8Bit(node));
1016 set_irn_n(node, n_ia32_binary_left, load_res);
1018 set_irn_n(node, n_ia32_binary_right, load_res);
1022 case ia32_am_ternary:
1023 set_irn_n(node, n_ia32_binary_right, load_res);
1028 set_irn_n(node, n_ia32_base, noreg);
1029 set_irn_n(node, n_ia32_index, noreg);
1030 set_ia32_am_offs_int(node, 0);
1031 set_ia32_am_sc(node, NULL);
1032 set_ia32_am_scale(node, 0);
1033 clear_ia32_am_sc_sign(node);
1035 /* rewire mem-proj */
1036 if (get_irn_mode(node) == mode_T) {
1038 foreach_out_edge(node, edge) {
1039 ir_node *out = get_edge_src_irn(edge);
1040 if(get_Proj_proj(out) == pn_ia32_mem) {
1046 if(mem_proj != NULL) {
1047 set_Proj_pred(mem_proj, load);
1048 set_Proj_proj(mem_proj, pn_ia32_Load_M);
1052 set_ia32_op_type(node, ia32_Normal);
1053 if (sched_is_scheduled(node))
1054 sched_add_before(node, load);
1057 static ir_node *flags_remat(ir_node *node, ir_node *after)
1059 /* we should turn back source address mode when rematerializing nodes */
1060 ia32_op_type_t type;
1064 if (is_Block(after)) {
1067 block = get_nodes_block(after);
1070 type = get_ia32_op_type(node);
1072 case ia32_AddrModeS: turn_back_am(node); break;
1074 case ia32_AddrModeD:
1075 /* TODO implement this later... */
1076 panic("found DestAM with flag user %+F this should not happen", node);
1079 default: assert(type == ia32_Normal); break;
1082 copy = exact_copy(node);
1083 set_nodes_block(copy, block);
1084 sched_add_after(after, copy);
1090 * Called before the register allocator.
1091 * Calculate a block schedule here. We need it for the x87
1092 * simulator and the emitter.
1094 static void ia32_before_ra(void *self) {
1095 ia32_code_gen_t *cg = self;
1097 /* setup fpu rounding modes */
1098 ia32_setup_fpu_mode(cg);
1101 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1104 ia32_add_missing_keeps(cg);
1109 * Transforms a be_Reload into a ia32 Load.
1111 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1112 ir_graph *irg = get_irn_irg(node);
1113 dbg_info *dbg = get_irn_dbg_info(node);
1114 ir_node *block = get_nodes_block(node);
1115 ir_entity *ent = be_get_frame_entity(node);
1116 ir_mode *mode = get_irn_mode(node);
1117 ir_mode *spillmode = get_spill_mode(node);
1118 ir_node *noreg = ia32_new_NoReg_gp(cg);
1119 ir_node *sched_point = NULL;
1120 ir_node *ptr = get_irg_frame(irg);
1121 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1122 ir_node *new_op, *proj;
1123 const arch_register_t *reg;
1125 if (sched_is_scheduled(node)) {
1126 sched_point = sched_prev(node);
1129 if (mode_is_float(spillmode)) {
1130 if (ia32_cg_config.use_sse2)
1131 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
1133 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
1135 else if (get_mode_size_bits(spillmode) == 128) {
1136 /* Reload 128 bit SSE registers */
1137 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1140 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1142 set_ia32_op_type(new_op, ia32_AddrModeS);
1143 set_ia32_ls_mode(new_op, spillmode);
1144 set_ia32_frame_ent(new_op, ent);
1145 set_ia32_use_frame(new_op);
1147 DBG_OPT_RELOAD2LD(node, new_op);
1149 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1152 sched_add_after(sched_point, new_op);
1156 /* copy the register from the old node to the new Load */
1157 reg = arch_get_irn_register(cg->arch_env, node);
1158 arch_set_irn_register(cg->arch_env, new_op, reg);
1160 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1162 exchange(node, proj);
1166 * Transforms a be_Spill node into a ia32 Store.
1168 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1169 ir_graph *irg = get_irn_irg(node);
1170 dbg_info *dbg = get_irn_dbg_info(node);
1171 ir_node *block = get_nodes_block(node);
1172 ir_entity *ent = be_get_frame_entity(node);
1173 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1174 ir_mode *mode = get_spill_mode(spillval);
1175 ir_node *noreg = ia32_new_NoReg_gp(cg);
1176 ir_node *nomem = new_rd_NoMem(irg);
1177 ir_node *ptr = get_irg_frame(irg);
1178 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1180 ir_node *sched_point = NULL;
1182 if (sched_is_scheduled(node)) {
1183 sched_point = sched_prev(node);
1186 /* No need to spill unknown values... */
1187 if(is_ia32_Unknown_GP(val) ||
1188 is_ia32_Unknown_VFP(val) ||
1189 is_ia32_Unknown_XMM(val)) {
1194 exchange(node, store);
1198 if (mode_is_float(mode)) {
1199 if (ia32_cg_config.use_sse2)
1200 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
1202 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
1203 } else if (get_mode_size_bits(mode) == 128) {
1204 /* Spill 128 bit SSE registers */
1205 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
1206 } else if (get_mode_size_bits(mode) == 8) {
1207 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
1209 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
1212 set_ia32_op_type(store, ia32_AddrModeD);
1213 set_ia32_ls_mode(store, mode);
1214 set_ia32_frame_ent(store, ent);
1215 set_ia32_use_frame(store);
1216 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1217 DBG_OPT_SPILL2ST(node, store);
1220 sched_add_after(sched_point, store);
1224 exchange(node, store);
1227 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1228 ir_graph *irg = get_irn_irg(node);
1229 dbg_info *dbg = get_irn_dbg_info(node);
1230 ir_node *block = get_nodes_block(node);
1231 ir_node *noreg = ia32_new_NoReg_gp(cg);
1232 ir_node *frame = get_irg_frame(irg);
1234 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
1236 set_ia32_frame_ent(push, ent);
1237 set_ia32_use_frame(push);
1238 set_ia32_op_type(push, ia32_AddrModeS);
1239 set_ia32_ls_mode(push, mode_Is);
1241 sched_add_before(schedpoint, push);
1245 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1246 ir_graph *irg = get_irn_irg(node);
1247 dbg_info *dbg = get_irn_dbg_info(node);
1248 ir_node *block = get_nodes_block(node);
1249 ir_node *noreg = ia32_new_NoReg_gp(cg);
1250 ir_node *frame = get_irg_frame(irg);
1252 ir_node *pop = new_rd_ia32_PopMem(dbg, irg, block, frame, noreg, new_NoMem(), sp);
1254 set_ia32_frame_ent(pop, ent);
1255 set_ia32_use_frame(pop);
1256 set_ia32_op_type(pop, ia32_AddrModeD);
1257 set_ia32_ls_mode(pop, mode_Is);
1259 sched_add_before(schedpoint, pop);
1264 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
1265 ir_graph *irg = get_irn_irg(node);
1266 dbg_info *dbg = get_irn_dbg_info(node);
1267 ir_node *block = get_nodes_block(node);
1268 ir_mode *spmode = mode_Iu;
1269 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1272 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1273 arch_set_irn_register(cg->arch_env, sp, spreg);
1279 * Transform MemPerm, currently we do this the ugly way and produce
1280 * push/pop into/from memory cascades. This is possible without using
1283 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1284 ir_graph *irg = get_irn_irg(node);
1285 ir_node *block = get_nodes_block(node);
1289 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1290 const ir_edge_t *edge;
1291 const ir_edge_t *next;
1294 arity = be_get_MemPerm_entity_arity(node);
1295 pops = alloca(arity * sizeof(pops[0]));
1298 for(i = 0; i < arity; ++i) {
1299 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1300 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1301 ir_type *enttype = get_entity_type(inent);
1302 unsigned entsize = get_type_size_bytes(enttype);
1303 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1304 ir_node *mem = get_irn_n(node, i + 1);
1307 /* work around cases where entities have different sizes */
1308 if(entsize2 < entsize)
1310 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1312 push = create_push(cg, node, node, sp, mem, inent);
1313 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1315 /* add another push after the first one */
1316 push = create_push(cg, node, node, sp, mem, inent);
1317 add_ia32_am_offs_int(push, 4);
1318 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1321 set_irn_n(node, i, new_Bad());
1325 for(i = arity - 1; i >= 0; --i) {
1326 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1327 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1328 ir_type *enttype = get_entity_type(outent);
1329 unsigned entsize = get_type_size_bytes(enttype);
1330 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1333 /* work around cases where entities have different sizes */
1334 if(entsize2 < entsize)
1336 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1338 pop = create_pop(cg, node, node, sp, outent);
1339 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1341 add_ia32_am_offs_int(pop, 4);
1343 /* add another pop after the first one */
1344 pop = create_pop(cg, node, node, sp, outent);
1345 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1352 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1353 sched_add_before(node, keep);
1355 /* exchange memprojs */
1356 foreach_out_edge_safe(node, edge, next) {
1357 ir_node *proj = get_edge_src_irn(edge);
1358 int p = get_Proj_proj(proj);
1362 set_Proj_pred(proj, pops[p]);
1363 set_Proj_proj(proj, pn_ia32_Pop_M);
1366 /* remove memperm */
1367 arity = get_irn_arity(node);
1368 for(i = 0; i < arity; ++i) {
1369 set_irn_n(node, i, new_Bad());
1375 * Block-Walker: Calls the transform functions Spill and Reload.
1377 static void ia32_after_ra_walker(ir_node *block, void *env) {
1378 ir_node *node, *prev;
1379 ia32_code_gen_t *cg = env;
1381 /* beware: the schedule is changed here */
1382 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1383 prev = sched_prev(node);
1385 if (be_is_Reload(node)) {
1386 transform_to_Load(cg, node);
1387 } else if (be_is_Spill(node)) {
1388 transform_to_Store(cg, node);
1389 } else if (be_is_MemPerm(node)) {
1390 transform_MemPerm(cg, node);
1396 * Collects nodes that need frame entities assigned.
1398 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1400 be_fec_env_t *env = data;
1402 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1403 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1404 int align = get_mode_size_bytes(mode);
1405 be_node_needs_frame_entity(env, node, mode, align);
1406 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1407 && is_ia32_use_frame(node)) {
1408 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1409 const ir_mode *mode = get_ia32_ls_mode(node);
1410 const ia32_attr_t *attr = get_ia32_attr_const(node);
1411 int align = get_mode_size_bytes(mode);
1413 if(attr->data.need_64bit_stackent) {
1416 if(attr->data.need_32bit_stackent) {
1419 be_node_needs_frame_entity(env, node, mode, align);
1420 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
1421 || is_ia32_vfld(node)) {
1422 const ir_mode *mode = get_ia32_ls_mode(node);
1424 be_node_needs_frame_entity(env, node, mode, align);
1425 } else if(is_ia32_FldCW(node)) {
1426 /* although 2 byte would be enough 4 byte performs best */
1427 const ir_mode *mode = mode_Iu;
1429 be_node_needs_frame_entity(env, node, mode, align);
1432 assert(is_ia32_St(node) ||
1433 is_ia32_xStoreSimple(node) ||
1434 is_ia32_vfst(node) ||
1435 is_ia32_vfist(node) ||
1436 is_ia32_vfisttp(node) ||
1437 is_ia32_FnstCW(node));
1444 * We transform Spill and Reload here. This needs to be done before
1445 * stack biasing otherwise we would miss the corrected offset for these nodes.
1447 static void ia32_after_ra(void *self) {
1448 ia32_code_gen_t *cg = self;
1449 ir_graph *irg = cg->irg;
1450 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1452 /* create and coalesce frame entities */
1453 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1454 be_assign_entities(fec_env);
1455 be_free_frame_entity_coalescer(fec_env);
1457 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1461 * Last touchups for the graph before emit: x87 simulation to replace the
1462 * virtual with real x87 instructions, creating a block schedule and peephole
1465 static void ia32_finish(void *self) {
1466 ia32_code_gen_t *cg = self;
1467 ir_graph *irg = cg->irg;
1469 ia32_finish_irg(irg, cg);
1471 /* we might have to rewrite x87 virtual registers */
1472 if (cg->do_x87_sim) {
1473 x87_simulate_graph(cg->arch_env, cg->birg);
1476 /* do peephole optimisations */
1477 ia32_peephole_optimization(cg);
1479 /* create block schedule, this also removes empty blocks which might
1480 * produce critical edges */
1481 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1485 * Emits the code, closes the output file and frees
1486 * the code generator interface.
1488 static void ia32_codegen(void *self) {
1489 ia32_code_gen_t *cg = self;
1490 ir_graph *irg = cg->irg;
1492 ia32_gen_routine(cg, irg);
1496 /* remove it from the isa */
1499 assert(ia32_current_cg == cg);
1500 ia32_current_cg = NULL;
1502 /* de-allocate code generator */
1503 del_set(cg->reg_set);
1508 * Returns the node representing the PIC base.
1510 static ir_node *ia32_get_pic_base(void *self) {
1512 ia32_code_gen_t *cg = self;
1513 ir_node *get_eip = cg->get_eip;
1514 if (get_eip != NULL)
1517 block = get_irg_start_block(cg->irg);
1518 get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block);
1519 cg->get_eip = get_eip;
1521 add_irn_dep(get_eip, get_irg_frame(cg->irg));
1526 static void *ia32_cg_init(be_irg_t *birg);
1528 static const arch_code_generator_if_t ia32_code_gen_if = {
1530 ia32_get_pic_base, /* return node used as base in pic code addresses */
1531 ia32_before_abi, /* before abi introduce hook */
1534 ia32_before_sched, /* before scheduling hook */
1535 ia32_before_ra, /* before register allocation hook */
1536 ia32_after_ra, /* after register allocation hook */
1537 ia32_finish, /* called before codegen */
1538 ia32_codegen /* emit && done */
1542 * Initializes a IA32 code generator.
1544 static void *ia32_cg_init(be_irg_t *birg) {
1545 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env.isa;
1546 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1548 cg->impl = &ia32_code_gen_if;
1549 cg->irg = birg->irg;
1550 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1551 cg->arch_env = &birg->main_env->arch_env;
1554 cg->blk_sched = NULL;
1555 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1556 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1559 /* Linux gprof implementation needs base pointer */
1560 birg->main_env->options->omit_fp = 0;
1567 if (isa->name_obst) {
1568 obstack_free(isa->name_obst, NULL);
1569 obstack_init(isa->name_obst);
1573 cur_reg_set = cg->reg_set;
1575 assert(ia32_current_cg == NULL);
1576 ia32_current_cg = cg;
1578 return (arch_code_generator_t *)cg;
1583 /*****************************************************************
1584 * ____ _ _ _____ _____
1585 * | _ \ | | | | |_ _|/ ____| /\
1586 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1587 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1588 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1589 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1591 *****************************************************************/
1594 * Set output modes for GCC
1596 static const tarval_mode_info mo_integer = {
1603 * set the tarval output mode of all integer modes to decimal
1605 static void set_tarval_output_modes(void)
1609 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1610 ir_mode *mode = get_irp_mode(i);
1612 if (mode_is_int(mode))
1613 set_tarval_mode_output_option(mode, &mo_integer);
1617 const arch_isa_if_t ia32_isa_if;
1620 * The template that generates a new ISA object.
1621 * Note that this template can be changed by command line
1624 static ia32_isa_t ia32_isa_template = {
1626 &ia32_isa_if, /* isa interface implementation */
1627 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1628 &ia32_gp_regs[REG_EBP], /* base pointer register */
1629 -1, /* stack direction */
1630 16, /* stack alignment */
1631 NULL, /* main environment */
1632 7, /* costs for a spill instruction */
1633 5, /* costs for a reload instruction */
1635 NULL, /* 16bit register names */
1636 NULL, /* 8bit register names */
1637 NULL, /* 8bit register names high */
1640 NULL, /* current code generator */
1641 NULL, /* abstract machine */
1643 NULL, /* name obstack */
1648 * Initializes the backend ISA.
1650 static void *ia32_init(FILE *file_handle) {
1651 static int inited = 0;
1658 set_tarval_output_modes();
1660 isa = xmalloc(sizeof(*isa));
1661 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1663 if(mode_fpcw == NULL) {
1664 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1667 ia32_register_init();
1668 ia32_create_opcodes(&ia32_irn_ops);
1670 be_emit_init(file_handle);
1671 isa->regs_16bit = pmap_create();
1672 isa->regs_8bit = pmap_create();
1673 isa->regs_8bit_high = pmap_create();
1674 isa->types = pmap_create();
1675 isa->tv_ent = pmap_create();
1676 isa->cpu = ia32_init_machine_description();
1678 ia32_build_16bit_reg_map(isa->regs_16bit);
1679 ia32_build_8bit_reg_map(isa->regs_8bit);
1680 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1683 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1684 obstack_init(isa->name_obst);
1687 /* enter the ISA object into the intrinsic environment */
1688 intrinsic_env.isa = isa;
1689 ia32_handle_intrinsics();
1691 /* needed for the debug support */
1692 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1693 be_emit_cstring(".Ltext0:\n");
1694 be_emit_write_line();
1696 /* we mark referenced global entities, so we can only emit those which
1697 * are actually referenced. (Note: you mustn't use the type visited flag
1698 * elsewhere in the backend)
1700 inc_master_type_visited();
1708 * Closes the output file and frees the ISA structure.
1710 static void ia32_done(void *self) {
1711 ia32_isa_t *isa = self;
1713 /* emit now all global declarations */
1714 be_gas_emit_decls(isa->arch_isa.main_env, 1);
1716 pmap_destroy(isa->regs_16bit);
1717 pmap_destroy(isa->regs_8bit);
1718 pmap_destroy(isa->regs_8bit_high);
1719 pmap_destroy(isa->tv_ent);
1720 pmap_destroy(isa->types);
1723 obstack_free(isa->name_obst, NULL);
1733 * Return the number of register classes for this architecture.
1734 * We report always these:
1735 * - the general purpose registers
1736 * - the SSE floating point register set
1737 * - the virtual floating point registers
1738 * - the SSE vector register set
1740 static unsigned ia32_get_n_reg_class(const void *self) {
1746 * Return the register class for index i.
1748 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1752 assert(i < N_CLASSES);
1753 return &ia32_reg_classes[i];
1757 * Get the register class which shall be used to store a value of a given mode.
1758 * @param self The this pointer.
1759 * @param mode The mode in question.
1760 * @return A register class which can hold values of the given mode.
1762 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1763 const ir_mode *mode)
1767 if (mode_is_float(mode)) {
1768 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1771 return &ia32_reg_classes[CLASS_ia32_gp];
1775 * Get the ABI restrictions for procedure calls.
1776 * @param self The this pointer.
1777 * @param method_type The type of the method (procedure) in question.
1778 * @param abi The abi object to be modified
1780 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1787 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1790 /* set abi flags for calls */
1791 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1792 call_flags.bits.store_args_sequential = 0;
1793 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1794 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1795 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1797 /* set parameter passing style */
1798 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1800 if (get_method_variadicity(method_type) == variadicity_variadic) {
1801 /* pass all parameters of a variadic function on the stack */
1804 cc = get_method_calling_convention(method_type);
1805 if (get_method_additional_properties(method_type) & mtp_property_private
1806 && (ia32_cg_config.optimize_cc)) {
1807 /* set the calling conventions to register parameter */
1808 cc = (cc & ~cc_bits) | cc_reg_param;
1812 /* we have to pop the shadow parameter ourself for compound calls */
1813 if( (get_method_calling_convention(method_type) & cc_compound_ret)
1814 && !(cc & cc_reg_param)) {
1815 be_abi_call_set_pop(abi, get_mode_size_bytes(mode_P_data));
1818 n = get_method_n_params(method_type);
1819 for (i = regnum = 0; i < n; i++) {
1821 const arch_register_t *reg = NULL;
1823 tp = get_method_param_type(method_type, i);
1824 mode = get_type_mode(tp);
1826 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1829 be_abi_call_param_reg(abi, i, reg);
1832 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1833 * movl has a shorter opcode than mov[sz][bw]l */
1834 ir_mode *load_mode = mode;
1835 if (mode != NULL && get_mode_size_bytes(mode) < 4) load_mode = mode_Iu;
1836 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1840 /* set return registers */
1841 n = get_method_n_ress(method_type);
1843 assert(n <= 2 && "more than two results not supported");
1845 /* In case of 64bit returns, we will have two 32bit values */
1847 tp = get_method_res_type(method_type, 0);
1848 mode = get_type_mode(tp);
1850 assert(!mode_is_float(mode) && "two FP results not supported");
1852 tp = get_method_res_type(method_type, 1);
1853 mode = get_type_mode(tp);
1855 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1857 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1858 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1861 const arch_register_t *reg;
1863 tp = get_method_res_type(method_type, 0);
1864 assert(is_atomic_type(tp));
1865 mode = get_type_mode(tp);
1867 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1869 be_abi_call_res_reg(abi, 0, reg);
1873 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1877 if(!is_ia32_irn(irn)) {
1881 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1882 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1883 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1884 || is_ia32_Immediate(irn))
1891 * Initializes the code generator interface.
1893 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1896 return &ia32_code_gen_if;
1900 * Returns the estimated execution time of an ia32 irn.
1902 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1904 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
1907 list_sched_selector_t ia32_sched_selector;
1910 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1912 static const list_sched_selector_t *ia32_get_list_sched_selector(
1913 const void *self, list_sched_selector_t *selector)
1916 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1917 ia32_sched_selector.exectime = ia32_sched_exectime;
1918 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1919 return &ia32_sched_selector;
1922 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1929 * Returns the necessary byte alignment for storing a register of given class.
1931 static int ia32_get_reg_class_alignment(const void *self,
1932 const arch_register_class_t *cls)
1934 ir_mode *mode = arch_register_class_mode(cls);
1935 int bytes = get_mode_size_bytes(mode);
1938 if (mode_is_float(mode) && bytes > 8)
1943 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1944 const void *self, const ir_node *irn)
1946 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1947 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1948 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1951 static const be_execution_unit_t *_allowed_units_GP[] = {
1952 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1953 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1954 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1955 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1956 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1957 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1958 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1961 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1962 &be_machine_execution_units_DUMMY[0],
1965 static const be_execution_unit_t **_units_callret[] = {
1966 _allowed_units_BRANCH,
1969 static const be_execution_unit_t **_units_other[] = {
1973 static const be_execution_unit_t **_units_dummy[] = {
1974 _allowed_units_DUMMY,
1977 const be_execution_unit_t ***ret;
1980 if (is_ia32_irn(irn)) {
1981 ret = get_ia32_exec_units(irn);
1983 else if (is_be_node(irn)) {
1984 if (be_is_Call(irn) || be_is_Return(irn)) {
1985 ret = _units_callret;
1987 else if (be_is_Barrier(irn)) {
2002 * Return the abstract ia32 machine.
2004 static const be_machine_t *ia32_get_machine(const void *self) {
2005 const ia32_isa_t *isa = self;
2010 * Return irp irgs in the desired order.
2012 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2020 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2021 * @return 1 if allowed, 0 otherwise
2023 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2025 ir_node *phi, *left;
2026 ir_node *cmp = NULL;
2029 if (ia32_cg_config.use_cmov) {
2030 /* we can't handle psis with 64bit compares yet */
2032 cmp = get_Proj_pred(sel);
2034 left = get_Cmp_left(cmp);
2035 cmp_mode = get_irn_mode(left);
2036 if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
2043 if (ia32_cg_config.use_sse2 && cmp != NULL) {
2044 pn_Cmp pn = get_Proj_proj(sel);
2045 ir_node *cl = get_Cmp_left(cmp);
2046 ir_node *cr = get_Cmp_right(cmp);
2048 /* check the Phi nodes: no 64bit and no floating point cmov */
2049 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
2050 ir_mode *mode = get_irn_mode(phi);
2052 if (mode_is_float(mode)) {
2053 /* check for Min, Max */
2054 ir_node *t = get_Phi_pred(phi, i);
2055 ir_node *f = get_Phi_pred(phi, j);
2058 /* SSE2 supports Min & Max */
2059 if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2060 if (cl == t && cr == f) {
2061 /* Psi(a <=/>= b, a, b) => MIN, MAX */
2063 } else if (cl == f && cr == t) {
2064 /* Psi(a <=/>= b, b, a) => MAX, MIN */
2071 } else if (get_mode_size_bits(mode) > 32)
2075 /* check the Phi nodes: no 64bit and no floating point cmov */
2076 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
2077 ir_mode *mode = get_irn_mode(phi);
2079 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2089 /* No cmov, only some special cases */
2092 cmp = get_Proj_pred(sel);
2096 left = get_Cmp_left(cmp);
2097 cmp_mode = get_irn_mode(left);
2099 /* Now some supported cases here */
2100 pn = get_Proj_proj(sel);
2101 cl = get_Cmp_left(cmp);
2102 cr = get_Cmp_right(cmp);
2104 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
2105 ir_mode *mode = get_irn_mode(phi);
2109 t = get_Phi_pred(phi, i);
2110 f = get_Phi_pred(phi, j);
2112 /* no floating point and no 64bit yet */
2113 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2116 if (is_Const(t) && is_Const(f)) {
2117 if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
2118 /* always support Psi(x, C1, C2) */
2121 } else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2124 } else if (cl == t && cr == f) {
2125 /* Psi(a <=/>= b, a, b) => Min, Max */
2127 } else if (cl == f && cr == t) {
2128 /* Psi(a <=/>= b, b, a) => Max, Min */
2131 } else if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
2132 is_Const(f) && is_Const_null(f) && is_Sub(t) &&
2133 get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
2134 /* Psi(a >=u b, a - b, 0) unsigned Doz */
2136 } else if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
2137 is_Const(t) && is_Const_null(t) && is_Sub(f) &&
2138 get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
2139 /* Psi(a <=u b, 0, a - b) unsigned Doz */
2141 } else if (is_Const(cr) && is_Const_null(cr)) {
2142 if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
2143 /* Psi(a <=/>= 0 ? a : -a) Nabs/Abs */
2145 } else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
2146 /* Psi(a <=/>= 0 ? -a : a) Abs/Nabs */
2154 /* all checks passed */
2161 * Returns the libFirm configuration parameter for this backend.
2163 static const backend_params *ia32_get_libfirm_params(void) {
2164 static const ir_settings_if_conv_t ifconv = {
2165 4, /* maxdepth, doesn't matter for Psi-conversion */
2166 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2168 static const ir_settings_arch_dep_t ad = {
2169 1, /* also use subs */
2170 4, /* maximum shifts */
2171 31, /* maximum shift amount */
2172 ia32_evaluate_insn, /* evaluate the instruction sequence */
2174 1, /* allow Mulhs */
2175 1, /* allow Mulus */
2176 32 /* Mulh allowed up to 32 bit */
2178 static backend_params p = {
2179 1, /* need dword lowering */
2180 1, /* support inline assembly */
2181 NULL, /* no additional opcodes */
2182 NULL, /* will be set later */
2183 ia32_create_intrinsic_fkt,
2184 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2185 NULL, /* will be set below */
2188 ia32_setup_cg_config();
2191 p.if_conv_info = &ifconv;
2195 static const lc_opt_enum_int_items_t gas_items[] = {
2196 { "elf", GAS_FLAVOUR_ELF },
2197 { "mingw", GAS_FLAVOUR_MINGW },
2198 { "yasm", GAS_FLAVOUR_YASM },
2199 { "macho", GAS_FLAVOUR_MACH_O },
2203 static lc_opt_enum_int_var_t gas_var = {
2204 (int*) &be_gas_flavour, gas_items
2207 static const lc_opt_table_entry_t ia32_options[] = {
2208 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2209 LC_OPT_ENT_INT("stackalign", "set stack alignment for calls",
2210 &ia32_isa_template.arch_isa.stack_alignment),
2214 const arch_isa_if_t ia32_isa_if = {
2217 ia32_get_n_reg_class,
2219 ia32_get_reg_class_for_mode,
2221 ia32_get_code_generator_if,
2222 ia32_get_list_sched_selector,
2223 ia32_get_ilp_sched_selector,
2224 ia32_get_reg_class_alignment,
2225 ia32_get_libfirm_params,
2226 ia32_get_allowed_execution_units,
2231 void ia32_init_emitter(void);
2232 void ia32_init_finish(void);
2233 void ia32_init_optimize(void);
2234 void ia32_init_transform(void);
2235 void ia32_init_x87(void);
2237 void be_init_arch_ia32(void)
2239 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2240 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2242 lc_opt_add_table(ia32_grp, ia32_options);
2243 be_register_isa_if("ia32", &ia32_isa_if);
2245 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2247 ia32_init_emitter();
2249 ia32_init_optimize();
2250 ia32_init_transform();
2252 ia32_init_architecture();
2255 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);