2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
58 #include "../benode.h"
59 #include "../belower.h"
60 #include "../besched.h"
63 #include "../beirgmod.h"
64 #include "../be_dbgout.h"
65 #include "../beblocksched.h"
66 #include "../bemachine.h"
67 #include "../bespillslots.h"
68 #include "../bemodule.h"
69 #include "../begnuas.h"
70 #include "../bestate.h"
71 #include "../beflags.h"
72 #include "../betranshlp.h"
73 #include "../belistsched.h"
74 #include "../beabihelper.h"
76 #include "bearch_ia32_t.h"
78 #include "ia32_new_nodes.h"
79 #include "gen_ia32_regalloc_if.h"
80 #include "gen_ia32_machine.h"
81 #include "ia32_common_transform.h"
82 #include "ia32_transform.h"
83 #include "ia32_emitter.h"
84 #include "ia32_optimize.h"
86 #include "ia32_dbg_stat.h"
87 #include "ia32_finish.h"
89 #include "ia32_architecture.h"
92 #include "ia32_pbqp_transform.h"
94 transformer_t be_transformer = TRANSFORMER_DEFAULT;
97 ir_mode *ia32_mode_fpcw = NULL;
99 /** The current omit-fp state */
100 static ir_type *omit_fp_between_type = NULL;
101 static ir_type *between_type = NULL;
102 static ir_entity *old_bp_ent = NULL;
103 static ir_entity *ret_addr_ent = NULL;
104 static ir_entity *omit_fp_ret_addr_ent = NULL;
107 * The environment for the intrinsic mapping.
109 static ia32_intrinsic_env_t intrinsic_env = {
111 NULL, /* the irg, these entities belong to */
112 NULL, /* entity for __divdi3 library call */
113 NULL, /* entity for __moddi3 library call */
114 NULL, /* entity for __udivdi3 library call */
115 NULL, /* entity for __umoddi3 library call */
119 typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
122 * Used to create per-graph unique pseudo nodes.
124 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
125 create_const_node_func func,
126 const arch_register_t* reg)
128 ir_node *block, *res;
133 block = get_irg_start_block(irg);
134 res = func(NULL, block);
135 arch_set_irn_register(res, reg);
141 /* Creates the unique per irg GP NoReg node. */
142 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
144 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
145 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
146 &ia32_registers[REG_GP_NOREG]);
149 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
151 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
152 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
153 &ia32_registers[REG_VFP_NOREG]);
156 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
158 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
159 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
160 &ia32_registers[REG_XMM_NOREG]);
163 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
165 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
166 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
167 &ia32_registers[REG_FPCW]);
172 * Returns the admissible noreg register node for input register pos of node irn.
174 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
176 ir_graph *irg = get_irn_irg(irn);
177 const arch_register_req_t *req = arch_get_register_req(irn, pos);
179 assert(req != NULL && "Missing register requirements");
180 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
181 return ia32_new_NoReg_gp(irg);
183 if (ia32_cg_config.use_sse2) {
184 return ia32_new_NoReg_xmm(irg);
186 return ia32_new_NoReg_vfp(irg);
190 static arch_irn_class_t ia32_classify(const ir_node *irn)
192 arch_irn_class_t classification = arch_irn_class_none;
194 assert(is_ia32_irn(irn));
196 if (is_ia32_is_reload(irn))
197 classification |= arch_irn_class_reload;
199 if (is_ia32_is_spill(irn))
200 classification |= arch_irn_class_spill;
202 if (is_ia32_is_remat(irn))
203 classification |= arch_irn_class_remat;
205 return classification;
209 * The IA32 ABI callback object.
212 be_abi_call_flags_bits_t flags; /**< The call flags. */
213 ir_graph *irg; /**< The associated graph. */
216 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
218 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
221 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
223 if (is_be_node(node))
224 be_node_set_frame_entity(node, entity);
226 set_ia32_frame_ent(node, entity);
229 static void ia32_set_frame_offset(ir_node *irn, int bias)
231 if (get_ia32_frame_ent(irn) == NULL)
234 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
235 ir_graph *irg = get_irn_irg(irn);
236 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
237 if (layout->sp_relative) {
238 /* Pop nodes modify the stack pointer before calculating the
239 * destination address, so fix this here
244 add_ia32_am_offs_int(irn, bias);
247 static int ia32_get_sp_bias(const ir_node *node)
249 if (is_ia32_Call(node))
250 return -(int)get_ia32_call_attr_const(node)->pop;
252 if (is_ia32_Push(node))
255 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
258 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
259 return SP_BIAS_RESET;
266 * Build the between type and entities if not already build.
268 static void ia32_build_between_type(void)
270 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
271 if (! between_type) {
272 ir_type *old_bp_type = new_type_primitive(mode_Iu);
273 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
275 between_type = new_type_struct(IDENT("ia32_between_type"));
276 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
277 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
279 set_entity_offset(old_bp_ent, 0);
280 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
281 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
282 set_type_state(between_type, layout_fixed);
284 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
285 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
287 set_entity_offset(omit_fp_ret_addr_ent, 0);
288 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
289 set_type_state(omit_fp_between_type, layout_fixed);
295 * Produces the type which sits between the stack args and the locals on the stack.
296 * it will contain the return address and space to store the old base pointer.
297 * @return The Firm type modeling the ABI between type.
299 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
301 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
302 ia32_build_between_type();
303 return layout->sp_relative ? omit_fp_between_type : between_type;
307 * Return the stack entity that contains the return address.
309 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
311 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
312 ia32_build_between_type();
313 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
317 * Return the stack entity that contains the frame address.
319 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
321 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
322 ia32_build_between_type();
323 return layout->sp_relative ? NULL : old_bp_ent;
327 * Get the estimated cycle count for @p irn.
329 * @param self The this pointer.
330 * @param irn The node.
332 * @return The estimated cycle count for this operation
334 static int ia32_get_op_estimated_cost(const ir_node *irn)
337 ia32_op_type_t op_tp;
341 if (!is_ia32_irn(irn))
344 assert(is_ia32_irn(irn));
346 cost = get_ia32_latency(irn);
347 op_tp = get_ia32_op_type(irn);
349 if (is_ia32_CopyB(irn)) {
352 else if (is_ia32_CopyB_i(irn)) {
353 int size = get_ia32_copyb_size(irn);
354 cost = 20 + (int)ceil((4/3) * size);
356 /* in case of address mode operations add additional cycles */
357 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
359 In case of stack access and access to fixed addresses add 5 cycles
360 (we assume they are in cache), other memory operations cost 20
363 if (is_ia32_use_frame(irn) || (
364 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
365 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
377 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
379 * @param irn The original operation
380 * @param i Index of the argument we want the inverse operation to yield
381 * @param inverse struct to be filled with the resulting inverse op
382 * @param obstack The obstack to use for allocation of the returned nodes array
383 * @return The inverse operation or NULL if operation invertible
385 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
396 ir_node *block, *noreg, *nomem;
399 /* we cannot invert non-ia32 irns */
400 if (! is_ia32_irn(irn))
403 /* operand must always be a real operand (not base, index or mem) */
404 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
407 /* we don't invert address mode operations */
408 if (get_ia32_op_type(irn) != ia32_Normal)
411 /* TODO: adjust for new immediates... */
412 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
416 block = get_nodes_block(irn);
417 mode = get_irn_mode(irn);
418 irn_mode = get_irn_mode(irn);
419 noreg = get_irn_n(irn, 0);
420 nomem = get_irg_no_mem(irg);
421 dbgi = get_irn_dbg_info(irn);
423 /* initialize structure */
424 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
428 switch (get_ia32_irn_opcode(irn)) {
430 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
431 /* we have an add with a const here */
432 /* invers == add with negated const */
433 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
435 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
436 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
437 set_ia32_commutative(inverse->nodes[0]);
439 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
440 /* we have an add with a symconst here */
441 /* invers == sub with const */
442 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
444 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
447 /* normal add: inverse == sub */
448 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
453 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
454 /* we have a sub with a const/symconst here */
455 /* invers == add with this const */
456 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
457 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
458 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
462 if (i == n_ia32_binary_left) {
463 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
466 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
472 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
473 /* xor with const: inverse = xor */
474 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
475 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
476 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
480 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
485 inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
490 inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
495 /* inverse operation not supported */
503 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
505 if (mode_is_float(mode))
512 * Get the mode that should be used for spilling value node
514 static ir_mode *get_spill_mode(const ir_node *node)
516 ir_mode *mode = get_irn_mode(node);
517 return get_spill_mode_mode(mode);
521 * Checks whether an addressmode reload for a node with mode mode is compatible
522 * with a spillslot of mode spill_mode
524 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
526 return !mode_is_float(mode) || mode == spillmode;
530 * Check if irn can load its operand at position i from memory (source addressmode).
531 * @param irn The irn to be checked
532 * @param i The operands position
533 * @return Non-Zero if operand can be loaded
535 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
537 ir_node *op = get_irn_n(irn, i);
538 const ir_mode *mode = get_irn_mode(op);
539 const ir_mode *spillmode = get_spill_mode(op);
541 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
542 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
543 !ia32_is_spillmode_compatible(mode, spillmode) ||
544 is_ia32_use_frame(irn)) /* must not already use frame */
547 switch (get_ia32_am_support(irn)) {
552 if (i != n_ia32_unary_op)
558 case n_ia32_binary_left: {
559 const arch_register_req_t *req;
560 if (!is_ia32_commutative(irn))
563 /* we can't swap left/right for limited registers
564 * (As this (currently) breaks constraint handling copies)
566 req = arch_get_in_register_req(irn, n_ia32_binary_left);
567 if (req->type & arch_register_req_type_limited)
572 case n_ia32_binary_right:
581 panic("Unknown AM type");
584 /* HACK: must not already use "real" memory.
585 * This can happen for Call and Div */
586 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
592 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
596 ir_mode *dest_op_mode;
598 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
600 set_ia32_op_type(irn, ia32_AddrModeS);
602 load_mode = get_irn_mode(get_irn_n(irn, i));
603 dest_op_mode = get_ia32_ls_mode(irn);
604 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
605 set_ia32_ls_mode(irn, load_mode);
607 set_ia32_use_frame(irn);
608 set_ia32_need_stackent(irn);
610 if (i == n_ia32_binary_left &&
611 get_ia32_am_support(irn) == ia32_am_binary &&
612 /* immediates are only allowed on the right side */
613 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
614 ia32_swap_left_right(irn);
615 i = n_ia32_binary_right;
618 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
620 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
621 set_irn_n(irn, n_ia32_mem, spill);
622 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
623 set_ia32_is_reload(irn);
626 static const be_abi_callbacks_t ia32_abi_callbacks = {
627 ia32_abi_get_between_type,
630 /* register allocator interface */
631 static const arch_irn_ops_t ia32_irn_ops = {
633 ia32_get_frame_entity,
634 ia32_set_frame_offset,
637 ia32_get_op_estimated_cost,
638 ia32_possible_memory_operand,
639 ia32_perform_memory_operand,
642 static ir_entity *mcount = NULL;
643 static int gprof = 0;
645 static void ia32_before_abi(ir_graph *irg)
648 if (mcount == NULL) {
649 ir_type *tp = new_type_method(0, 0);
650 ident *id = new_id_from_str("mcount");
651 mcount = new_entity(get_glob_type(), id, tp);
652 /* FIXME: enter the right ld_ident here */
653 set_entity_ld_ident(mcount, get_entity_ident(mcount));
654 set_entity_visibility(mcount, ir_visibility_external);
656 instrument_initcall(irg, mcount);
661 * Transforms the standard firm graph into
664 static void ia32_prepare_graph(ir_graph *irg)
666 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
669 switch (be_transformer) {
670 case TRANSFORMER_DEFAULT:
671 /* transform remaining nodes into assembler instructions */
672 ia32_transform_graph(irg);
675 case TRANSFORMER_PBQP:
676 case TRANSFORMER_RAND:
677 /* transform nodes into assembler instructions by PBQP magic */
678 ia32_transform_graph_by_pbqp(irg);
682 panic("invalid transformer");
685 ia32_transform_graph(irg);
688 /* do local optimizations (mainly CSE) */
689 optimize_graph_df(irg);
692 dump_ir_graph(irg, "transformed");
694 /* optimize address mode */
695 ia32_optimize_graph(irg);
697 /* do code placement, to optimize the position of constants */
701 dump_ir_graph(irg, "place");
704 ir_node *ia32_turn_back_am(ir_node *node)
706 dbg_info *dbgi = get_irn_dbg_info(node);
707 ir_graph *irg = get_irn_irg(node);
708 ir_node *block = get_nodes_block(node);
709 ir_node *base = get_irn_n(node, n_ia32_base);
710 ir_node *idx = get_irn_n(node, n_ia32_index);
711 ir_node *mem = get_irn_n(node, n_ia32_mem);
714 ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
715 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
717 ia32_copy_am_attrs(load, node);
718 if (is_ia32_is_reload(node))
719 set_ia32_is_reload(load);
720 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
722 switch (get_ia32_am_support(node)) {
724 set_irn_n(node, n_ia32_unary_op, load_res);
728 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
729 set_irn_n(node, n_ia32_binary_left, load_res);
731 set_irn_n(node, n_ia32_binary_right, load_res);
736 panic("Unknown AM type");
738 noreg = ia32_new_NoReg_gp(current_ir_graph);
739 set_irn_n(node, n_ia32_base, noreg);
740 set_irn_n(node, n_ia32_index, noreg);
741 set_ia32_am_offs_int(node, 0);
742 set_ia32_am_sc(node, NULL);
743 set_ia32_am_scale(node, 0);
744 clear_ia32_am_sc_sign(node);
746 /* rewire mem-proj */
747 if (get_irn_mode(node) == mode_T) {
748 const ir_edge_t *edge;
749 foreach_out_edge(node, edge) {
750 ir_node *out = get_edge_src_irn(edge);
751 if (get_irn_mode(out) == mode_M) {
752 set_Proj_pred(out, load);
753 set_Proj_proj(out, pn_ia32_Load_M);
759 set_ia32_op_type(node, ia32_Normal);
760 if (sched_is_scheduled(node))
761 sched_add_before(node, load);
766 static ir_node *flags_remat(ir_node *node, ir_node *after)
768 /* we should turn back source address mode when rematerializing nodes */
773 if (is_Block(after)) {
776 block = get_nodes_block(after);
779 type = get_ia32_op_type(node);
782 ia32_turn_back_am(node);
786 /* TODO implement this later... */
787 panic("found DestAM with flag user %+F this should not happen", node);
789 default: assert(type == ia32_Normal); break;
792 copy = exact_copy(node);
793 set_nodes_block(copy, block);
794 sched_add_after(after, copy);
800 * Called before the register allocator.
802 static void ia32_before_ra(ir_graph *irg)
804 /* setup fpu rounding modes */
805 ia32_setup_fpu_mode(irg);
808 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
811 be_add_missing_keeps(irg);
816 * Transforms a be_Reload into a ia32 Load.
818 static void transform_to_Load(ir_node *node)
820 ir_graph *irg = get_irn_irg(node);
821 dbg_info *dbgi = get_irn_dbg_info(node);
822 ir_node *block = get_nodes_block(node);
823 ir_entity *ent = be_get_frame_entity(node);
824 ir_mode *mode = get_irn_mode(node);
825 ir_mode *spillmode = get_spill_mode(node);
826 ir_node *noreg = ia32_new_NoReg_gp(irg);
827 ir_node *sched_point = NULL;
828 ir_node *ptr = get_irg_frame(irg);
829 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
830 ir_node *new_op, *proj;
831 const arch_register_t *reg;
833 if (sched_is_scheduled(node)) {
834 sched_point = sched_prev(node);
837 if (mode_is_float(spillmode)) {
838 if (ia32_cg_config.use_sse2)
839 new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
841 new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
843 else if (get_mode_size_bits(spillmode) == 128) {
844 /* Reload 128 bit SSE registers */
845 new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
848 new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
850 set_ia32_op_type(new_op, ia32_AddrModeS);
851 set_ia32_ls_mode(new_op, spillmode);
852 set_ia32_frame_ent(new_op, ent);
853 set_ia32_use_frame(new_op);
854 set_ia32_is_reload(new_op);
856 DBG_OPT_RELOAD2LD(node, new_op);
858 proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
861 sched_add_after(sched_point, new_op);
865 /* copy the register from the old node to the new Load */
866 reg = arch_get_irn_register(node);
867 arch_set_irn_register(proj, reg);
869 SET_IA32_ORIG_NODE(new_op, node);
871 exchange(node, proj);
875 * Transforms a be_Spill node into a ia32 Store.
877 static void transform_to_Store(ir_node *node)
879 ir_graph *irg = get_irn_irg(node);
880 dbg_info *dbgi = get_irn_dbg_info(node);
881 ir_node *block = get_nodes_block(node);
882 ir_entity *ent = be_get_frame_entity(node);
883 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
884 ir_mode *mode = get_spill_mode(spillval);
885 ir_node *noreg = ia32_new_NoReg_gp(irg);
886 ir_node *nomem = get_irg_no_mem(irg);
887 ir_node *ptr = get_irg_frame(irg);
888 ir_node *val = get_irn_n(node, n_be_Spill_val);
891 ir_node *sched_point = NULL;
893 if (sched_is_scheduled(node)) {
894 sched_point = sched_prev(node);
897 if (mode_is_float(mode)) {
898 if (ia32_cg_config.use_sse2) {
899 store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
900 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
902 store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
903 res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
905 } else if (get_mode_size_bits(mode) == 128) {
906 /* Spill 128 bit SSE registers */
907 store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
908 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
909 } else if (get_mode_size_bits(mode) == 8) {
910 store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
911 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
913 store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
914 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
917 set_ia32_op_type(store, ia32_AddrModeD);
918 set_ia32_ls_mode(store, mode);
919 set_ia32_frame_ent(store, ent);
920 set_ia32_use_frame(store);
921 set_ia32_is_spill(store);
922 SET_IA32_ORIG_NODE(store, node);
923 DBG_OPT_SPILL2ST(node, store);
926 sched_add_after(sched_point, store);
933 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
935 dbg_info *dbgi = get_irn_dbg_info(node);
936 ir_node *block = get_nodes_block(node);
937 ir_graph *irg = get_irn_irg(node);
938 ir_node *noreg = ia32_new_NoReg_gp(irg);
939 ir_node *frame = get_irg_frame(irg);
941 ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
943 set_ia32_frame_ent(push, ent);
944 set_ia32_use_frame(push);
945 set_ia32_op_type(push, ia32_AddrModeS);
946 set_ia32_ls_mode(push, mode_Is);
947 set_ia32_is_spill(push);
949 sched_add_before(schedpoint, push);
953 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
955 dbg_info *dbgi = get_irn_dbg_info(node);
956 ir_node *block = get_nodes_block(node);
957 ir_graph *irg = get_irn_irg(node);
958 ir_node *noreg = ia32_new_NoReg_gp(irg);
959 ir_node *frame = get_irg_frame(irg);
961 ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
962 get_irg_no_mem(irg), sp);
964 set_ia32_frame_ent(pop, ent);
965 set_ia32_use_frame(pop);
966 set_ia32_op_type(pop, ia32_AddrModeD);
967 set_ia32_ls_mode(pop, mode_Is);
968 set_ia32_is_reload(pop);
970 sched_add_before(schedpoint, pop);
975 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
977 dbg_info *dbgi = get_irn_dbg_info(node);
978 ir_mode *spmode = mode_Iu;
979 const arch_register_t *spreg = &ia32_registers[REG_ESP];
982 sp = new_rd_Proj(dbgi, pred, spmode, pos);
983 arch_set_irn_register(sp, spreg);
989 * Transform MemPerm, currently we do this the ugly way and produce
990 * push/pop into/from memory cascades. This is possible without using
993 static void transform_MemPerm(ir_node *node)
995 ir_node *block = get_nodes_block(node);
996 ir_graph *irg = get_irn_irg(node);
997 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
998 int arity = be_get_MemPerm_entity_arity(node);
999 ir_node **pops = ALLOCAN(ir_node*, arity);
1003 const ir_edge_t *edge;
1004 const ir_edge_t *next;
1007 for (i = 0; i < arity; ++i) {
1008 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1009 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1010 ir_type *enttype = get_entity_type(inent);
1011 unsigned entsize = get_type_size_bytes(enttype);
1012 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1013 ir_node *mem = get_irn_n(node, i + 1);
1016 /* work around cases where entities have different sizes */
1017 if (entsize2 < entsize)
1019 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1021 push = create_push(node, node, sp, mem, inent);
1022 sp = create_spproj(node, push, pn_ia32_Push_stack);
1024 /* add another push after the first one */
1025 push = create_push(node, node, sp, mem, inent);
1026 add_ia32_am_offs_int(push, 4);
1027 sp = create_spproj(node, push, pn_ia32_Push_stack);
1030 set_irn_n(node, i, new_r_Bad(irg, mode_X));
1034 for (i = arity - 1; i >= 0; --i) {
1035 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1036 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1037 ir_type *enttype = get_entity_type(outent);
1038 unsigned entsize = get_type_size_bytes(enttype);
1039 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1042 /* work around cases where entities have different sizes */
1043 if (entsize2 < entsize)
1045 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1047 pop = create_pop(node, node, sp, outent);
1048 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1050 add_ia32_am_offs_int(pop, 4);
1052 /* add another pop after the first one */
1053 pop = create_pop(node, node, sp, outent);
1054 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1061 keep = be_new_Keep(block, 1, in);
1062 sched_add_before(node, keep);
1064 /* exchange memprojs */
1065 foreach_out_edge_safe(node, edge, next) {
1066 ir_node *proj = get_edge_src_irn(edge);
1067 int p = get_Proj_proj(proj);
1071 set_Proj_pred(proj, pops[p]);
1072 set_Proj_proj(proj, pn_ia32_Pop_M);
1075 /* remove memperm */
1081 * Block-Walker: Calls the transform functions Spill and Reload.
1083 static void ia32_after_ra_walker(ir_node *block, void *env)
1085 ir_node *node, *prev;
1088 /* beware: the schedule is changed here */
1089 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1090 prev = sched_prev(node);
1092 if (be_is_Reload(node)) {
1093 transform_to_Load(node);
1094 } else if (be_is_Spill(node)) {
1095 transform_to_Store(node);
1096 } else if (be_is_MemPerm(node)) {
1097 transform_MemPerm(node);
1103 * Collects nodes that need frame entities assigned.
1105 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1107 be_fec_env_t *env = (be_fec_env_t*)data;
1108 const ir_mode *mode;
1111 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1112 mode = get_spill_mode_mode(get_irn_mode(node));
1113 align = get_mode_size_bytes(mode);
1114 } else if (is_ia32_irn(node) &&
1115 get_ia32_frame_ent(node) == NULL &&
1116 is_ia32_use_frame(node)) {
1117 if (is_ia32_need_stackent(node))
1120 switch (get_ia32_irn_opcode(node)) {
1122 case iro_ia32_Load: {
1123 const ia32_attr_t *attr = get_ia32_attr_const(node);
1125 if (attr->data.need_32bit_stackent) {
1127 } else if (attr->data.need_64bit_stackent) {
1130 mode = get_ia32_ls_mode(node);
1131 if (is_ia32_is_reload(node))
1132 mode = get_spill_mode_mode(mode);
1134 align = get_mode_size_bytes(mode);
1138 case iro_ia32_vfild:
1140 case iro_ia32_xLoad: {
1141 mode = get_ia32_ls_mode(node);
1146 case iro_ia32_FldCW: {
1147 /* although 2 byte would be enough 4 byte performs best */
1155 panic("unexpected frame user while collection frame entity nodes");
1157 case iro_ia32_FnstCW:
1158 case iro_ia32_Store8Bit:
1159 case iro_ia32_Store:
1162 case iro_ia32_vfist:
1163 case iro_ia32_vfisttp:
1165 case iro_ia32_xStore:
1166 case iro_ia32_xStoreSimple:
1173 be_node_needs_frame_entity(env, node, mode, align);
1176 static int determine_ebp_input(ir_node *ret)
1178 const arch_register_t *bp = &ia32_registers[REG_EBP];
1179 int arity = get_irn_arity(ret);
1182 for (i = 0; i < arity; ++i) {
1183 ir_node *input = get_irn_n(ret, i);
1184 if (arch_get_irn_register(input) == bp)
1187 panic("no ebp input found at %+F", ret);
1190 static void introduce_epilog(ir_node *ret)
1192 const arch_register_t *sp = &ia32_registers[REG_ESP];
1193 const arch_register_t *bp = &ia32_registers[REG_EBP];
1194 ir_graph *irg = get_irn_irg(ret);
1195 ir_type *frame_type = get_irg_frame_type(irg);
1196 unsigned frame_size = get_type_size_bytes(frame_type);
1197 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1198 ir_node *block = get_nodes_block(ret);
1199 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1200 ir_node *curr_sp = first_sp;
1201 ir_mode *mode_gp = mode_Iu;
1203 if (!layout->sp_relative) {
1204 int n_ebp = determine_ebp_input(ret);
1205 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1206 if (ia32_cg_config.use_leave) {
1207 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1208 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1209 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1210 arch_set_irn_register(curr_bp, bp);
1211 arch_set_irn_register(curr_sp, sp);
1212 sched_add_before(ret, leave);
1215 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1216 /* copy ebp to esp */
1217 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1218 arch_set_irn_register(curr_sp, sp);
1219 sched_add_before(ret, curr_sp);
1222 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1223 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1224 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1225 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1226 arch_set_irn_register(curr_bp, bp);
1227 arch_set_irn_register(curr_sp, sp);
1228 sched_add_before(ret, pop);
1230 set_irn_n(ret, n_be_Return_mem, curr_mem);
1232 set_irn_n(ret, n_ebp, curr_bp);
1234 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1235 sched_add_before(ret, incsp);
1238 set_irn_n(ret, n_be_Return_sp, curr_sp);
1240 /* keep verifier happy... */
1241 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1242 kill_node(first_sp);
1247 * put the Prolog code at the beginning, epilog code before each return
1249 static void introduce_prolog_epilog(ir_graph *irg)
1251 const arch_register_t *sp = &ia32_registers[REG_ESP];
1252 const arch_register_t *bp = &ia32_registers[REG_EBP];
1253 ir_node *start = get_irg_start(irg);
1254 ir_node *block = get_nodes_block(start);
1255 ir_type *frame_type = get_irg_frame_type(irg);
1256 unsigned frame_size = get_type_size_bytes(frame_type);
1257 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1258 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1259 ir_node *curr_sp = initial_sp;
1260 ir_mode *mode_gp = mode_Iu;
1262 if (!layout->sp_relative) {
1264 ir_node *mem = get_irg_initial_mem(irg);
1265 ir_node *noreg = ia32_new_NoReg_gp(irg);
1266 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1267 ir_node *curr_bp = initial_bp;
1268 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
1271 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1272 mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
1273 arch_set_irn_register(curr_sp, sp);
1274 sched_add_after(start, push);
1276 /* move esp to ebp */
1277 curr_bp = be_new_Copy(bp->reg_class, block, curr_sp);
1278 sched_add_after(push, curr_bp);
1279 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1280 curr_sp = be_new_CopyKeep_single(sp->reg_class, block, curr_sp, curr_bp, mode_gp);
1281 sched_add_after(curr_bp, curr_sp);
1282 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1283 edges_reroute(initial_bp, curr_bp);
1284 set_irn_n(push, n_ia32_Push_val, initial_bp);
1286 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1287 edges_reroute(initial_sp, incsp);
1288 set_irn_n(push, n_ia32_Push_stack, initial_sp);
1289 sched_add_after(curr_sp, incsp);
1291 layout->initial_bias = -4;
1293 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1294 edges_reroute(initial_sp, incsp);
1295 be_set_IncSP_pred(incsp, curr_sp);
1296 sched_add_after(start, incsp);
1299 /* introduce epilog for every return node */
1301 ir_node *end_block = get_irg_end_block(irg);
1302 int arity = get_irn_arity(end_block);
1305 for (i = 0; i < arity; ++i) {
1306 ir_node *ret = get_irn_n(end_block, i);
1307 assert(be_is_Return(ret));
1308 introduce_epilog(ret);
1314 * We transform Spill and Reload here. This needs to be done before
1315 * stack biasing otherwise we would miss the corrected offset for these nodes.
1317 static void ia32_after_ra(ir_graph *irg)
1319 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1320 bool at_begin = stack_layout->sp_relative ? true : false;
1321 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1323 /* create and coalesce frame entities */
1324 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1325 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1326 be_free_frame_entity_coalescer(fec_env);
1328 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1330 introduce_prolog_epilog(irg);
1334 * Last touchups for the graph before emit: x87 simulation to replace the
1335 * virtual with real x87 instructions, creating a block schedule and peephole
1338 static void ia32_finish(ir_graph *irg)
1340 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1342 ia32_finish_irg(irg);
1344 /* we might have to rewrite x87 virtual registers */
1345 if (irg_data->do_x87_sim) {
1346 ia32_x87_simulate_graph(irg);
1349 /* do peephole optimisations */
1350 ia32_peephole_optimization(irg);
1352 /* create block schedule, this also removes empty blocks which might
1353 * produce critical edges */
1354 irg_data->blk_sched = be_create_block_schedule(irg);
1358 * Emits the code, closes the output file and frees
1359 * the code generator interface.
1361 static void ia32_emit(ir_graph *irg)
1363 if (ia32_cg_config.emit_machcode) {
1364 ia32_gen_binary_routine(irg);
1366 ia32_gen_routine(irg);
1371 * Returns the node representing the PIC base.
1373 static ir_node *ia32_get_pic_base(ir_graph *irg)
1375 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1377 ir_node *get_eip = irg_data->get_eip;
1378 if (get_eip != NULL)
1381 block = get_irg_start_block(irg);
1382 get_eip = new_bd_ia32_GetEIP(NULL, block);
1383 irg_data->get_eip = get_eip;
1389 * Initializes a IA32 code generator.
1391 static void ia32_init_graph(ir_graph *irg)
1393 struct obstack *obst = be_get_be_obst(irg);
1394 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1396 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1399 /* Linux gprof implementation needs base pointer */
1400 be_get_irg_options(irg)->omit_fp = 0;
1403 be_birg_from_irg(irg)->isa_link = irg_data;
1408 * Set output modes for GCC
1410 static const tarval_mode_info mo_integer = {
1417 * set the tarval output mode of all integer modes to decimal
1419 static void set_tarval_output_modes(void)
1423 for (i = get_irp_n_modes(); i > 0;) {
1424 ir_mode *mode = get_irp_mode(--i);
1426 if (mode_is_int(mode))
1427 set_tarval_mode_output_option(mode, &mo_integer);
1431 extern const arch_isa_if_t ia32_isa_if;
1434 * The template that generates a new ISA object.
1435 * Note that this template can be changed by command line
1438 static ia32_isa_t ia32_isa_template = {
1440 &ia32_isa_if, /* isa interface implementation */
1445 &ia32_registers[REG_ESP], /* stack pointer register */
1446 &ia32_registers[REG_EBP], /* base pointer register */
1447 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1448 2, /* power of two stack alignment, 2^2 == 4 */
1449 NULL, /* main environment */
1450 7, /* costs for a spill instruction */
1451 5, /* costs for a reload instruction */
1452 false, /* no custom abi handling */
1456 NULL, /* abstract machine */
1459 static void init_asm_constraints(void)
1461 be_init_default_asm_constraint_flags();
1463 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1464 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1465 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1466 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1467 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1468 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1469 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1470 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1471 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1472 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1473 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1474 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1475 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1476 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1477 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1478 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1479 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1480 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1481 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1482 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1484 /* no support for autodecrement/autoincrement */
1485 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1486 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1487 /* no float consts */
1488 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1489 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1490 /* makes no sense on x86 */
1491 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1492 /* no support for sse consts yet */
1493 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1494 /* no support for x87 consts yet */
1495 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1496 /* no support for mmx registers yet */
1497 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1498 /* not available in 32bit mode */
1499 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1500 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1502 /* no code yet to determine register class needed... */
1503 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1507 * Initializes the backend ISA.
1509 static arch_env_t *ia32_init(FILE *file_handle)
1511 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1513 set_tarval_output_modes();
1515 *isa = ia32_isa_template;
1517 if (ia32_mode_fpcw == NULL) {
1518 ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1521 ia32_register_init();
1522 ia32_create_opcodes(&ia32_irn_ops);
1524 be_emit_init(file_handle);
1525 isa->types = pmap_create();
1526 isa->tv_ent = pmap_create();
1527 isa->cpu = ia32_init_machine_description();
1529 /* enter the ISA object into the intrinsic environment */
1530 intrinsic_env.isa = isa;
1538 * Closes the output file and frees the ISA structure.
1540 static void ia32_done(void *self)
1542 ia32_isa_t *isa = (ia32_isa_t*)self;
1544 /* emit now all global declarations */
1545 be_gas_emit_decls(isa->base.main_env);
1547 pmap_destroy(isa->tv_ent);
1548 pmap_destroy(isa->types);
1557 * Get the register class which shall be used to store a value of a given mode.
1558 * @param self The this pointer.
1559 * @param mode The mode in question.
1560 * @return A register class which can hold values of the given mode.
1562 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1564 if (mode_is_float(mode)) {
1565 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1568 return &ia32_reg_classes[CLASS_ia32_gp];
1572 * Returns the register for parameter nr.
1574 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1575 const ir_mode *mode)
1577 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1578 &ia32_registers[REG_ECX],
1579 &ia32_registers[REG_EDX],
1582 static const unsigned MAXNUM_GPREG_ARGS = 3;
1584 static const arch_register_t *gpreg_param_reg_regparam[] = {
1585 &ia32_registers[REG_EAX],
1586 &ia32_registers[REG_EDX],
1587 &ia32_registers[REG_ECX]
1590 static const arch_register_t *gpreg_param_reg_this[] = {
1591 &ia32_registers[REG_ECX],
1596 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1597 &ia32_registers[REG_XMM0],
1598 &ia32_registers[REG_XMM1],
1599 &ia32_registers[REG_XMM2],
1600 &ia32_registers[REG_XMM3],
1601 &ia32_registers[REG_XMM4],
1602 &ia32_registers[REG_XMM5],
1603 &ia32_registers[REG_XMM6],
1604 &ia32_registers[REG_XMM7]
1607 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1608 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1610 static const unsigned MAXNUM_SSE_ARGS = 8;
1612 if ((cc & cc_this_call) && nr == 0)
1613 return gpreg_param_reg_this[0];
1615 if (! (cc & cc_reg_param))
1618 if (mode_is_float(mode)) {
1619 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1621 if (nr >= MAXNUM_SSE_ARGS)
1624 if (cc & cc_this_call) {
1625 return fpreg_sse_param_reg_this[nr];
1627 return fpreg_sse_param_reg_std[nr];
1628 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1629 unsigned num_regparam;
1631 if (get_mode_size_bits(mode) > 32)
1634 if (nr >= MAXNUM_GPREG_ARGS)
1637 if (cc & cc_this_call) {
1638 return gpreg_param_reg_this[nr];
1640 num_regparam = cc & ~cc_bits;
1641 if (num_regparam == 0) {
1642 /* default fastcall */
1643 return gpreg_param_reg_fastcall[nr];
1645 if (nr < num_regparam)
1646 return gpreg_param_reg_regparam[nr];
1650 panic("unknown argument mode");
1654 * Get the ABI restrictions for procedure calls.
1655 * @param self The this pointer.
1656 * @param method_type The type of the method (procedure) in question.
1657 * @param abi The abi object to be modified
1659 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1665 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1669 /* set abi flags for calls */
1670 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1671 call_flags.bits.store_args_sequential = 0;
1672 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1673 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1674 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1676 /* set parameter passing style */
1677 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1679 cc = get_method_calling_convention(method_type);
1680 if (get_method_variadicity(method_type) == variadicity_variadic) {
1681 /* pass all parameters of a variadic function on the stack */
1682 cc = cc_cdecl_set | (cc & cc_this_call);
1684 if (get_method_additional_properties(method_type) & mtp_property_private &&
1685 ia32_cg_config.optimize_cc) {
1686 /* set the fast calling conventions (allowing up to 3) */
1687 cc = SET_FASTCALL(cc) | 3;
1691 /* we have to pop the shadow parameter ourself for compound calls */
1692 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1693 && !(cc & cc_reg_param)) {
1694 pop_amount += get_mode_size_bytes(mode_P_data);
1697 n = get_method_n_params(method_type);
1698 for (i = regnum = 0; i < n; i++) {
1699 const arch_register_t *reg = NULL;
1700 ir_type *tp = get_method_param_type(method_type, i);
1701 ir_mode *mode = get_type_mode(tp);
1704 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1707 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1710 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1711 * movl has a shorter opcode than mov[sz][bw]l */
1712 ir_mode *load_mode = mode;
1715 unsigned size = get_mode_size_bytes(mode);
1717 if (cc & cc_callee_clear_stk) {
1718 pop_amount += (size + 3U) & ~3U;
1721 if (size < 4) load_mode = mode_Iu;
1724 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1728 be_abi_call_set_pop(abi, pop_amount);
1730 /* set return registers */
1731 n = get_method_n_ress(method_type);
1733 assert(n <= 2 && "more than two results not supported");
1735 /* In case of 64bit returns, we will have two 32bit values */
1737 ir_type *tp = get_method_res_type(method_type, 0);
1738 ir_mode *mode = get_type_mode(tp);
1740 assert(!mode_is_float(mode) && "two FP results not supported");
1742 tp = get_method_res_type(method_type, 1);
1743 mode = get_type_mode(tp);
1745 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1747 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1748 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1751 ir_type *tp = get_method_res_type(method_type, 0);
1752 ir_mode *mode = get_type_mode(tp);
1753 const arch_register_t *reg;
1754 assert(is_atomic_type(tp));
1756 reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
1758 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1763 * Returns the necessary byte alignment for storing a register of given class.
1765 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1767 ir_mode *mode = arch_register_class_mode(cls);
1768 int bytes = get_mode_size_bytes(mode);
1770 if (mode_is_float(mode) && bytes > 8)
1776 * Return irp irgs in the desired order.
1778 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1785 static void ia32_mark_remat(ir_node *node)
1787 if (is_ia32_irn(node)) {
1788 set_ia32_is_remat(node);
1793 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1795 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1800 ir_relation relation;
1805 cmp_l = get_Cmp_left(sel);
1806 cmp_r = get_Cmp_right(sel);
1807 if (!mode_is_float(get_irn_mode(cmp_l)))
1810 /* check for min/max. They're defined as (C-Semantik):
1811 * min(a, b) = a < b ? a : b
1812 * or min(a, b) = a <= b ? a : b
1813 * max(a, b) = a > b ? a : b
1814 * or max(a, b) = a >= b ? a : b
1815 * (Note we only handle float min/max here)
1817 relation = get_Cmp_relation(sel);
1819 case ir_relation_greater_equal:
1820 case ir_relation_greater:
1822 if (cmp_l == mux_true && cmp_r == mux_false)
1825 case ir_relation_less_equal:
1826 case ir_relation_less:
1828 if (cmp_l == mux_true && cmp_r == mux_false)
1831 case ir_relation_unordered_greater_equal:
1832 case ir_relation_unordered_greater:
1834 if (cmp_l == mux_false && cmp_r == mux_true)
1837 case ir_relation_unordered_less_equal:
1838 case ir_relation_unordered_less:
1840 if (cmp_l == mux_false && cmp_r == mux_true)
1851 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1853 ir_mode *mode = get_irn_mode(mux_true);
1856 if (!mode_is_int(mode) && !mode_is_reference(mode)
1860 if (is_Const(mux_true) && is_Const(mux_false)) {
1861 /* we can create a set plus up two 3 instructions for any combination
1869 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1874 if (!mode_is_float(get_irn_mode(mux_true)))
1877 return is_Const(mux_true) && is_Const(mux_false);
1880 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1887 ir_relation relation;
1892 mode = get_irn_mode(mux_true);
1893 if (mode_is_signed(mode) || mode_is_float(mode))
1896 relation = get_Cmp_relation(sel);
1897 cmp_left = get_Cmp_left(sel);
1898 cmp_right = get_Cmp_right(sel);
1900 /* "move" zero constant to false input */
1901 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1902 ir_node *tmp = mux_false;
1903 mux_false = mux_true;
1905 relation = get_negated_relation(relation);
1907 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1909 if (!is_Sub(mux_true))
1911 sub_left = get_Sub_left(mux_true);
1912 sub_right = get_Sub_right(mux_true);
1914 /* Mux(a >=u b, 0, a-b) */
1915 if ((relation & ir_relation_greater)
1916 && sub_left == cmp_left && sub_right == cmp_right)
1918 /* Mux(a <=u b, 0, b-a) */
1919 if ((relation & ir_relation_less)
1920 && sub_left == cmp_right && sub_right == cmp_left)
1926 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1931 /* we can handle Set for all modes and compares */
1932 if (mux_is_set(sel, mux_true, mux_false))
1934 /* SSE has own min/max operations */
1935 if (ia32_cg_config.use_sse2
1936 && mux_is_float_min_max(sel, mux_true, mux_false))
1938 /* we can handle Mux(?, Const[f], Const[f]) */
1939 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1940 #ifdef FIRM_GRGEN_BE
1941 /* well, some code selectors can't handle it */
1942 if (be_transformer != TRANSFORMER_PBQP
1943 || be_transformer != TRANSFORMER_RAND)
1950 /* no support for 64bit inputs to cmov */
1951 mode = get_irn_mode(mux_true);
1952 if (get_mode_size_bits(mode) > 32)
1954 /* we can handle Abs for all modes and compares (except 64bit) */
1955 if (ir_mux_is_abs(sel, mux_true, mux_false) != 0)
1957 /* we can't handle MuxF yet */
1958 if (mode_is_float(mode))
1961 if (mux_is_doz(sel, mux_true, mux_false))
1964 /* Check Cmp before the node */
1966 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1968 /* we can't handle 64bit compares */
1969 if (get_mode_size_bits(cmp_mode) > 32)
1972 /* we can't handle float compares */
1973 if (mode_is_float(cmp_mode))
1977 /* did we disable cmov generation? */
1978 if (!ia32_cg_config.use_cmov)
1981 /* we can use a cmov */
1985 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
1989 /* we already added all our simple flags to the flags modifier list in
1990 * init, so this flag we don't know. */
1991 return ASM_CONSTRAINT_FLAG_INVALID;
1994 static int ia32_is_valid_clobber(const char *clobber)
1996 return ia32_get_clobber_register(clobber) != NULL;
1999 static ir_node *ia32_create_set(ir_node *cond)
2001 /* ia32-set function produces 8-bit results which have to be converted */
2002 ir_node *set = ir_create_mux_set(cond, mode_Bu);
2003 ir_node *block = get_nodes_block(set);
2004 return new_r_Conv(block, set, mode_Iu);
2007 static void ia32_lower_for_target(void)
2009 size_t i, n_irgs = get_irp_n_irgs();
2010 lower_mode_b_config_t lower_mode_b_config = {
2011 mode_Iu, /* lowered mode */
2013 0, /* don't lower direct compares */
2015 lower_params_t params = {
2016 4, /* def_ptr_alignment */
2017 LF_COMPOUND_RETURN | LF_RETURN_HIDDEN, /* flags */
2018 ADD_HIDDEN_ALWAYS_IN_FRONT, /* hidden_params */
2019 NULL, /* find pointer type */
2020 NULL, /* ret_compound_in_regs */
2023 /* perform doubleword lowering */
2024 lwrdw_param_t lower_dw_params = {
2025 1, /* little endian */
2026 64, /* doubleword size */
2027 ia32_create_intrinsic_fkt,
2031 /* lower compound param handling */
2032 lower_calls_with_compounds(¶ms);
2034 ir_prepare_dw_lowering(&lower_dw_params);
2037 for (i = 0; i < n_irgs; ++i) {
2038 ir_graph *irg = get_irp_irg(i);
2039 /* lower for mode_b stuff */
2040 ir_lower_mode_b(irg, &lower_mode_b_config);
2041 /* break up switches with wide ranges */
2042 lower_switch(irg, 4, 256, false);
2047 * Create the trampoline code.
2049 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2051 ir_graph *irg = get_irn_irg(block);
2052 ir_node *p = trampoline;
2053 ir_mode *mode = get_irn_mode(p);
2057 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
2058 mem = new_r_Proj(st, mode_M, pn_Store_M);
2059 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2060 st = new_r_Store(block, mem, p, env, cons_none);
2061 mem = new_r_Proj(st, mode_M, pn_Store_M);
2062 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2064 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
2065 mem = new_r_Proj(st, mode_M, pn_Store_M);
2066 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2067 st = new_r_Store(block, mem, p, callee, cons_none);
2068 mem = new_r_Proj(st, mode_M, pn_Store_M);
2069 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2075 * Returns the libFirm configuration parameter for this backend.
2077 static const backend_params *ia32_get_libfirm_params(void)
2079 static const ir_settings_arch_dep_t ad = {
2080 1, /* also use subs */
2081 4, /* maximum shifts */
2082 63, /* maximum shift amount */
2083 ia32_evaluate_insn, /* evaluate the instruction sequence */
2085 1, /* allow Mulhs */
2086 1, /* allow Mulus */
2087 32, /* Mulh allowed up to 32 bit */
2089 static backend_params p = {
2090 1, /* support inline assembly */
2091 1, /* support Rotl nodes */
2092 0, /* little endian */
2093 NULL, /* will be set later */
2094 ia32_is_mux_allowed,
2095 32, /* machine_size */
2096 NULL, /* float arithmetic mode, will be set below */
2097 0, /* size of long double */
2098 12, /* size of trampoline code */
2099 4, /* alignment of trampoline code */
2100 ia32_create_trampoline_fkt,
2101 4 /* alignment of stack parameter */
2104 ia32_setup_cg_config();
2106 /* doesn't really belong here, but this is the earliest place the backend
2108 init_asm_constraints();
2111 if (! ia32_cg_config.use_sse2) {
2112 p.mode_float_arithmetic = mode_E;
2113 p.long_double_size = 96;
2115 p.mode_float_arithmetic = NULL;
2116 p.long_double_size = 64;
2122 * Check if the given register is callee or caller save.
2124 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
2127 /* check for callee saved */
2128 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2129 switch (reg->index) {
2140 /* check for caller saved */
2141 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2142 switch (reg->index) {
2150 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
2151 /* all XMM registers are caller save */
2152 return reg->index != REG_XMM_NOREG;
2153 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
2154 /* all VFP registers are caller save */
2155 return reg->index != REG_VFP_NOREG;
2161 static const lc_opt_enum_int_items_t gas_items[] = {
2162 { "elf", OBJECT_FILE_FORMAT_ELF },
2163 { "mingw", OBJECT_FILE_FORMAT_COFF },
2164 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2168 static lc_opt_enum_int_var_t gas_var = {
2169 (int*) &be_gas_object_file_format, gas_items
2172 #ifdef FIRM_GRGEN_BE
2173 static const lc_opt_enum_int_items_t transformer_items[] = {
2174 { "default", TRANSFORMER_DEFAULT },
2175 { "pbqp", TRANSFORMER_PBQP },
2176 { "random", TRANSFORMER_RAND },
2180 static lc_opt_enum_int_var_t transformer_var = {
2181 (int*)&be_transformer, transformer_items
2185 static const lc_opt_table_entry_t ia32_options[] = {
2186 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2187 #ifdef FIRM_GRGEN_BE
2188 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2190 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2191 &ia32_isa_template.base.stack_alignment),
2192 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2196 const arch_isa_if_t ia32_isa_if = {
2198 ia32_lower_for_target,
2200 ia32_handle_intrinsics,
2201 ia32_get_reg_class_for_mode,
2203 ia32_get_reg_class_alignment,
2204 ia32_get_libfirm_params,
2207 ia32_parse_asm_constraint,
2208 ia32_is_valid_clobber,
2211 ia32_get_pic_base, /* return node used as base in pic code addresses */
2212 ia32_before_abi, /* before abi introduce hook */
2214 ia32_before_ra, /* before register allocation hook */
2215 ia32_after_ra, /* after register allocation hook */
2216 ia32_finish, /* called before codegen */
2217 ia32_emit, /* emit && done */
2218 ia32_register_saved_by,
2221 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2222 void be_init_arch_ia32(void)
2224 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2225 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2227 lc_opt_add_table(ia32_grp, ia32_options);
2228 be_register_isa_if("ia32", &ia32_isa_if);
2230 ia32_init_emitter();
2232 ia32_init_optimize();
2233 ia32_init_transform();
2235 ia32_init_architecture();