2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
28 #include "lc_opts_enum.h"
36 #include "iredges_t.h"
49 #include "iroptimize.h"
50 #include "instrument.h"
53 #include "lower_calls.h"
54 #include "lower_mode_b.h"
55 #include "lower_softfloat.h"
65 #include "beblocksched.h"
66 #include "bespillutil.h"
67 #include "bespillslots.h"
72 #include "betranshlp.h"
73 #include "belistsched.h"
74 #include "beabihelper.h"
77 #include "bearch_ia32_t.h"
79 #include "ia32_new_nodes.h"
80 #include "gen_ia32_regalloc_if.h"
81 #include "ia32_common_transform.h"
82 #include "ia32_transform.h"
83 #include "ia32_emitter.h"
84 #include "ia32_optimize.h"
86 #include "ia32_dbg_stat.h"
87 #include "ia32_finish.h"
89 #include "ia32_architecture.h"
92 #include "ia32_pbqp_transform.h"
94 transformer_t be_transformer = TRANSFORMER_DEFAULT;
97 ir_mode *ia32_mode_fpcw;
101 /** The current omit-fp state */
102 static ir_type *omit_fp_between_type = NULL;
103 static ir_type *between_type = NULL;
104 static ir_entity *old_bp_ent = NULL;
105 static ir_entity *ret_addr_ent = NULL;
106 static ir_entity *omit_fp_ret_addr_ent = NULL;
109 * The environment for the intrinsic mapping.
111 static ia32_intrinsic_env_t intrinsic_env = {
113 NULL, /* the irg, these entities belong to */
114 NULL, /* entity for __divdi3 library call */
115 NULL, /* entity for __moddi3 library call */
116 NULL, /* entity for __udivdi3 library call */
117 NULL, /* entity for __umoddi3 library call */
121 typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
124 * Used to create per-graph unique pseudo nodes.
126 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
127 create_const_node_func func,
128 const arch_register_t* reg)
130 ir_node *block, *res;
135 block = get_irg_start_block(irg);
136 res = func(NULL, block);
137 arch_set_irn_register(res, reg);
143 /* Creates the unique per irg GP NoReg node. */
144 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
146 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
147 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
148 &ia32_registers[REG_GP_NOREG]);
151 ir_node *ia32_new_NoReg_fp(ir_graph *irg)
153 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
154 return create_const(irg, &irg_data->noreg_fp, new_bd_ia32_NoReg_FP,
155 &ia32_registers[REG_FP_NOREG]);
158 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
160 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
161 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
162 &ia32_registers[REG_XMM_NOREG]);
165 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
167 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
168 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
169 &ia32_registers[REG_FPCW]);
174 * Returns the admissible noreg register node for input register pos of node irn.
176 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
178 ir_graph *irg = get_irn_irg(irn);
179 const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
181 assert(req != NULL && "Missing register requirements");
182 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
183 return ia32_new_NoReg_gp(irg);
185 if (ia32_cg_config.use_sse2) {
186 return ia32_new_NoReg_xmm(irg);
188 return ia32_new_NoReg_fp(irg);
192 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
194 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
197 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
199 if (is_be_node(node))
200 be_node_set_frame_entity(node, entity);
202 set_ia32_frame_ent(node, entity);
205 static void ia32_set_frame_offset(ir_node *irn, int bias)
207 if (get_ia32_frame_ent(irn) == NULL)
210 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
211 ir_graph *irg = get_irn_irg(irn);
212 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
213 if (layout->sp_relative) {
214 /* Pop nodes modify the stack pointer before calculating the
215 * destination address, so fix this here
220 add_ia32_am_offs_int(irn, bias);
223 static int ia32_get_sp_bias(const ir_node *node)
225 if (is_ia32_Call(node))
226 return -(int)get_ia32_call_attr_const(node)->pop;
228 if (is_ia32_Push(node))
231 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
234 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
235 return SP_BIAS_RESET;
242 * Build the between type and entities if not already build.
244 static void ia32_build_between_type(void)
246 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
247 if (between_type == NULL) {
248 ir_type *old_bp_type = new_type_primitive(mode_Iu);
249 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
251 between_type = new_type_struct(IDENT("ia32_between_type"));
252 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
253 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
255 set_entity_offset(old_bp_ent, 0);
256 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
257 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
258 set_type_state(between_type, layout_fixed);
260 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
261 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
263 set_entity_offset(omit_fp_ret_addr_ent, 0);
264 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
265 set_type_state(omit_fp_between_type, layout_fixed);
271 * Produces the type which sits between the stack args and the locals on the stack.
272 * it will contain the return address and space to store the old base pointer.
273 * @return The Firm type modeling the ABI between type.
275 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
277 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
278 ia32_build_between_type();
279 return layout->sp_relative ? omit_fp_between_type : between_type;
283 * Return the stack entity that contains the return address.
285 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
287 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
288 ia32_build_between_type();
289 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
293 * Return the stack entity that contains the frame address.
295 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
297 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
298 ia32_build_between_type();
299 return layout->sp_relative ? NULL : old_bp_ent;
303 * Get the estimated cycle count for @p irn.
305 * @param self The this pointer.
306 * @param irn The node.
308 * @return The estimated cycle count for this operation
310 static int ia32_get_op_estimated_cost(const ir_node *irn)
313 ia32_op_type_t op_tp;
317 if (!is_ia32_irn(irn))
320 assert(is_ia32_irn(irn));
322 cost = get_ia32_latency(irn);
323 op_tp = get_ia32_op_type(irn);
325 if (is_ia32_CopyB(irn)) {
328 else if (is_ia32_CopyB_i(irn)) {
329 int size = get_ia32_copyb_size(irn);
330 cost = 20 + (int)ceil((4/3) * size);
332 /* in case of address mode operations add additional cycles */
333 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
335 In case of stack access and access to fixed addresses add 5 cycles
336 (we assume they are in cache), other memory operations cost 20
339 if (is_ia32_use_frame(irn) || (
340 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
341 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
353 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
355 * @param irn The original operation
356 * @param i Index of the argument we want the inverse operation to yield
357 * @param inverse struct to be filled with the resulting inverse op
358 * @param obstack The obstack to use for allocation of the returned nodes array
359 * @return The inverse operation or NULL if operation invertible
361 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
372 ir_node *block, *noreg, *nomem;
375 /* we cannot invert non-ia32 irns */
376 if (! is_ia32_irn(irn))
379 /* operand must always be a real operand (not base, index or mem) */
380 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
383 /* we don't invert address mode operations */
384 if (get_ia32_op_type(irn) != ia32_Normal)
387 /* TODO: adjust for new immediates... */
388 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
392 block = get_nodes_block(irn);
393 mode = get_irn_mode(irn);
394 irn_mode = get_irn_mode(irn);
395 noreg = get_irn_n(irn, 0);
396 nomem = get_irg_no_mem(irg);
397 dbgi = get_irn_dbg_info(irn);
399 /* initialize structure */
400 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
404 switch (get_ia32_irn_opcode(irn)) {
406 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
407 /* we have an add with a const here */
408 /* invers == add with negated const */
409 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
411 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
412 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
413 set_ia32_commutative(inverse->nodes[0]);
415 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
416 /* we have an add with a symconst here */
417 /* invers == sub with const */
418 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
420 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
423 /* normal add: inverse == sub */
424 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
429 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
430 /* we have a sub with a const/symconst here */
431 /* invers == add with this const */
432 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
433 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
434 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
438 if (i == n_ia32_binary_left) {
439 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
442 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
448 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
449 /* xor with const: inverse = xor */
450 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
451 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
452 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
456 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
461 inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
466 inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
471 /* inverse operation not supported */
479 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
481 if (mode_is_float(mode))
488 * Get the mode that should be used for spilling value node
490 static ir_mode *get_spill_mode(const ir_node *node)
492 ir_mode *mode = get_irn_mode(node);
493 return get_spill_mode_mode(mode);
497 * Checks whether an addressmode reload for a node with mode mode is compatible
498 * with a spillslot of mode spill_mode
500 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
502 return !mode_is_float(mode) || mode == spillmode;
506 * Check if irn can load its operand at position i from memory (source addressmode).
507 * @param irn The irn to be checked
508 * @param i The operands position
509 * @return Non-Zero if operand can be loaded
511 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
513 ir_node *op = get_irn_n(irn, i);
514 const ir_mode *mode = get_irn_mode(op);
515 const ir_mode *spillmode = get_spill_mode(op);
517 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
518 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
519 !ia32_is_spillmode_compatible(mode, spillmode) ||
520 is_ia32_use_frame(irn)) /* must not already use frame */
523 switch (get_ia32_am_support(irn)) {
528 if (i != n_ia32_unary_op)
534 case n_ia32_binary_left: {
535 const arch_register_req_t *req;
536 if (!is_ia32_commutative(irn))
539 /* we can't swap left/right for limited registers
540 * (As this (currently) breaks constraint handling copies)
542 req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
543 if (req->type & arch_register_req_type_limited)
548 case n_ia32_binary_right:
557 panic("Unknown AM type");
560 /* HACK: must not already use "real" memory.
561 * This can happen for Call and Div */
562 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
568 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
572 ir_mode *dest_op_mode;
574 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
576 set_ia32_op_type(irn, ia32_AddrModeS);
578 load_mode = get_irn_mode(get_irn_n(irn, i));
579 dest_op_mode = get_ia32_ls_mode(irn);
580 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
581 set_ia32_ls_mode(irn, load_mode);
583 set_ia32_use_frame(irn);
584 set_ia32_need_stackent(irn);
586 if (i == n_ia32_binary_left &&
587 get_ia32_am_support(irn) == ia32_am_binary &&
588 /* immediates are only allowed on the right side */
589 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
590 ia32_swap_left_right(irn);
591 i = n_ia32_binary_right;
594 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
596 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
597 set_irn_n(irn, n_ia32_mem, spill);
598 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
599 set_ia32_is_reload(irn);
602 static const be_abi_callbacks_t ia32_abi_callbacks = {
603 ia32_abi_get_between_type,
606 /* register allocator interface */
607 static const arch_irn_ops_t ia32_irn_ops = {
608 ia32_get_frame_entity,
609 ia32_set_frame_offset,
612 ia32_get_op_estimated_cost,
613 ia32_possible_memory_operand,
614 ia32_perform_memory_operand,
617 static ir_entity *mcount = NULL;
618 static int gprof = 0;
620 static void ia32_before_abi(ir_graph *irg)
623 if (mcount == NULL) {
624 ir_type *tp = new_type_method(0, 0);
625 ident *id = new_id_from_str("mcount");
626 mcount = new_entity(get_glob_type(), id, tp);
627 /* FIXME: enter the right ld_ident here */
628 set_entity_ld_ident(mcount, get_entity_ident(mcount));
629 set_entity_visibility(mcount, ir_visibility_external);
631 instrument_initcall(irg, mcount);
636 * Transforms the standard firm graph into
639 static void ia32_prepare_graph(ir_graph *irg)
641 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
644 switch (be_transformer) {
645 case TRANSFORMER_DEFAULT:
646 /* transform remaining nodes into assembler instructions */
647 ia32_transform_graph(irg);
650 case TRANSFORMER_PBQP:
651 case TRANSFORMER_RAND:
652 /* transform nodes into assembler instructions by PBQP magic */
653 ia32_transform_graph_by_pbqp(irg);
657 panic("invalid transformer");
660 ia32_transform_graph(irg);
663 /* do local optimizations (mainly CSE) */
664 optimize_graph_df(irg);
665 /* backend code expects that outedges are always enabled */
669 dump_ir_graph(irg, "transformed");
671 /* optimize address mode */
672 ia32_optimize_graph(irg);
674 /* do code placement, to optimize the position of constants */
676 /* backend code expects that outedges are always enabled */
680 dump_ir_graph(irg, "place");
683 ir_node *ia32_turn_back_am(ir_node *node)
685 dbg_info *dbgi = get_irn_dbg_info(node);
686 ir_graph *irg = get_irn_irg(node);
687 ir_node *block = get_nodes_block(node);
688 ir_node *base = get_irn_n(node, n_ia32_base);
689 ir_node *idx = get_irn_n(node, n_ia32_index);
690 ir_node *mem = get_irn_n(node, n_ia32_mem);
693 ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
694 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
696 ia32_copy_am_attrs(load, node);
697 if (is_ia32_is_reload(node))
698 set_ia32_is_reload(load);
699 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
701 switch (get_ia32_am_support(node)) {
703 set_irn_n(node, n_ia32_unary_op, load_res);
707 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
708 set_irn_n(node, n_ia32_binary_left, load_res);
710 set_irn_n(node, n_ia32_binary_right, load_res);
715 panic("Unknown AM type");
717 noreg = ia32_new_NoReg_gp(current_ir_graph);
718 set_irn_n(node, n_ia32_base, noreg);
719 set_irn_n(node, n_ia32_index, noreg);
720 set_ia32_am_offs_int(node, 0);
721 set_ia32_am_sc(node, NULL);
722 set_ia32_am_scale(node, 0);
723 clear_ia32_am_sc_sign(node);
725 /* rewire mem-proj */
726 if (get_irn_mode(node) == mode_T) {
727 foreach_out_edge(node, edge) {
728 ir_node *out = get_edge_src_irn(edge);
729 if (get_irn_mode(out) == mode_M) {
730 set_Proj_pred(out, load);
731 set_Proj_proj(out, pn_ia32_Load_M);
737 set_ia32_op_type(node, ia32_Normal);
738 if (sched_is_scheduled(node))
739 sched_add_before(node, load);
744 static ir_node *flags_remat(ir_node *node, ir_node *after)
746 /* we should turn back source address mode when rematerializing nodes */
751 if (is_Block(after)) {
754 block = get_nodes_block(after);
757 type = get_ia32_op_type(node);
760 ia32_turn_back_am(node);
764 /* TODO implement this later... */
765 panic("found DestAM with flag user %+F this should not happen", node);
767 default: assert(type == ia32_Normal); break;
770 copy = exact_copy(node);
771 set_nodes_block(copy, block);
772 sched_add_after(after, copy);
778 * Called before the register allocator.
780 static void ia32_before_ra(ir_graph *irg)
782 /* setup fpu rounding modes */
783 ia32_setup_fpu_mode(irg);
786 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
789 be_add_missing_keeps(irg);
794 * Transforms a be_Reload into a ia32 Load.
796 static void transform_to_Load(ir_node *node)
798 ir_graph *irg = get_irn_irg(node);
799 dbg_info *dbgi = get_irn_dbg_info(node);
800 ir_node *block = get_nodes_block(node);
801 ir_entity *ent = be_get_frame_entity(node);
802 ir_mode *mode = get_irn_mode(node);
803 ir_mode *spillmode = get_spill_mode(node);
804 ir_node *noreg = ia32_new_NoReg_gp(irg);
805 ir_node *sched_point = NULL;
806 ir_node *ptr = get_irg_frame(irg);
807 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
808 ir_node *new_op, *proj;
809 const arch_register_t *reg;
811 if (sched_is_scheduled(node)) {
812 sched_point = sched_prev(node);
815 if (mode_is_float(spillmode)) {
816 if (ia32_cg_config.use_sse2)
817 new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
819 new_op = new_bd_ia32_fld(dbgi, block, ptr, noreg, mem, spillmode);
821 else if (get_mode_size_bits(spillmode) == 128) {
822 /* Reload 128 bit SSE registers */
823 new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
826 new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
828 set_ia32_op_type(new_op, ia32_AddrModeS);
829 set_ia32_ls_mode(new_op, spillmode);
830 set_ia32_frame_ent(new_op, ent);
831 set_ia32_use_frame(new_op);
832 set_ia32_is_reload(new_op);
834 DBG_OPT_RELOAD2LD(node, new_op);
836 proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
839 sched_add_after(sched_point, new_op);
843 /* copy the register from the old node to the new Load */
844 reg = arch_get_irn_register(node);
845 arch_set_irn_register(proj, reg);
847 SET_IA32_ORIG_NODE(new_op, node);
849 exchange(node, proj);
853 * Transforms a be_Spill node into a ia32 Store.
855 static void transform_to_Store(ir_node *node)
857 ir_graph *irg = get_irn_irg(node);
858 dbg_info *dbgi = get_irn_dbg_info(node);
859 ir_node *block = get_nodes_block(node);
860 ir_entity *ent = be_get_frame_entity(node);
861 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
862 ir_mode *mode = get_spill_mode(spillval);
863 ir_node *noreg = ia32_new_NoReg_gp(irg);
864 ir_node *nomem = get_irg_no_mem(irg);
865 ir_node *ptr = get_irg_frame(irg);
866 ir_node *val = get_irn_n(node, n_be_Spill_val);
869 ir_node *sched_point = NULL;
871 if (sched_is_scheduled(node)) {
872 sched_point = sched_prev(node);
875 if (mode_is_float(mode)) {
876 if (ia32_cg_config.use_sse2) {
877 store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
878 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
880 store = new_bd_ia32_fst(dbgi, block, ptr, noreg, nomem, val, mode);
881 res = new_r_Proj(store, mode_M, pn_ia32_fst_M);
883 } else if (get_mode_size_bits(mode) == 128) {
884 /* Spill 128 bit SSE registers */
885 store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
886 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
887 } else if (get_mode_size_bits(mode) == 8) {
888 store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
889 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
891 store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
892 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
895 set_ia32_op_type(store, ia32_AddrModeD);
896 set_ia32_ls_mode(store, mode);
897 set_ia32_frame_ent(store, ent);
898 set_ia32_use_frame(store);
899 set_ia32_is_spill(store);
900 SET_IA32_ORIG_NODE(store, node);
901 DBG_OPT_SPILL2ST(node, store);
904 sched_add_after(sched_point, store);
911 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
913 dbg_info *dbgi = get_irn_dbg_info(node);
914 ir_node *block = get_nodes_block(node);
915 ir_graph *irg = get_irn_irg(node);
916 ir_node *noreg = ia32_new_NoReg_gp(irg);
917 ir_node *frame = get_irg_frame(irg);
919 ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
921 set_ia32_frame_ent(push, ent);
922 set_ia32_use_frame(push);
923 set_ia32_op_type(push, ia32_AddrModeS);
924 set_ia32_ls_mode(push, mode_Is);
925 set_ia32_is_spill(push);
927 sched_add_before(schedpoint, push);
931 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
933 dbg_info *dbgi = get_irn_dbg_info(node);
934 ir_node *block = get_nodes_block(node);
935 ir_graph *irg = get_irn_irg(node);
936 ir_node *noreg = ia32_new_NoReg_gp(irg);
937 ir_node *frame = get_irg_frame(irg);
939 ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
940 get_irg_no_mem(irg), sp);
942 set_ia32_frame_ent(pop, ent);
943 set_ia32_use_frame(pop);
944 set_ia32_op_type(pop, ia32_AddrModeD);
945 set_ia32_ls_mode(pop, mode_Is);
946 set_ia32_is_reload(pop);
948 sched_add_before(schedpoint, pop);
953 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
955 dbg_info *dbgi = get_irn_dbg_info(node);
956 ir_mode *spmode = mode_Iu;
957 const arch_register_t *spreg = &ia32_registers[REG_ESP];
960 sp = new_rd_Proj(dbgi, pred, spmode, pos);
961 arch_set_irn_register(sp, spreg);
967 * Transform MemPerm, currently we do this the ugly way and produce
968 * push/pop into/from memory cascades. This is possible without using
971 static void transform_MemPerm(ir_node *node)
973 ir_node *block = get_nodes_block(node);
974 ir_graph *irg = get_irn_irg(node);
975 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
976 int arity = be_get_MemPerm_entity_arity(node);
977 ir_node **pops = ALLOCAN(ir_node*, arity);
983 for (i = 0; i < arity; ++i) {
984 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
985 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
986 ir_type *enttype = get_entity_type(inent);
987 unsigned entsize = get_type_size_bytes(enttype);
988 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
989 ir_node *mem = get_irn_n(node, i + 1);
992 /* work around cases where entities have different sizes */
993 if (entsize2 < entsize)
995 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
997 push = create_push(node, node, sp, mem, inent);
998 sp = create_spproj(node, push, pn_ia32_Push_stack);
1000 /* add another push after the first one */
1001 push = create_push(node, node, sp, mem, inent);
1002 add_ia32_am_offs_int(push, 4);
1003 sp = create_spproj(node, push, pn_ia32_Push_stack);
1006 set_irn_n(node, i, new_r_Bad(irg, mode_X));
1010 for (i = arity - 1; i >= 0; --i) {
1011 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1012 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1013 ir_type *enttype = get_entity_type(outent);
1014 unsigned entsize = get_type_size_bytes(enttype);
1015 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1018 /* work around cases where entities have different sizes */
1019 if (entsize2 < entsize)
1021 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1023 pop = create_pop(node, node, sp, outent);
1024 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1026 add_ia32_am_offs_int(pop, 4);
1028 /* add another pop after the first one */
1029 pop = create_pop(node, node, sp, outent);
1030 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1037 keep = be_new_Keep(block, 1, in);
1038 sched_add_before(node, keep);
1040 /* exchange memprojs */
1041 foreach_out_edge_safe(node, edge) {
1042 ir_node *proj = get_edge_src_irn(edge);
1043 int p = get_Proj_proj(proj);
1047 set_Proj_pred(proj, pops[p]);
1048 set_Proj_proj(proj, pn_ia32_Pop_M);
1051 /* remove memperm */
1057 * Block-Walker: Calls the transform functions Spill and Reload.
1059 static void ia32_after_ra_walker(ir_node *block, void *env)
1061 ir_node *node, *prev;
1064 /* beware: the schedule is changed here */
1065 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1066 prev = sched_prev(node);
1068 if (be_is_Reload(node)) {
1069 transform_to_Load(node);
1070 } else if (be_is_Spill(node)) {
1071 transform_to_Store(node);
1072 } else if (be_is_MemPerm(node)) {
1073 transform_MemPerm(node);
1079 * Collects nodes that need frame entities assigned.
1081 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1083 be_fec_env_t *env = (be_fec_env_t*)data;
1084 const ir_mode *mode;
1087 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1088 mode = get_spill_mode_mode(get_irn_mode(node));
1089 align = get_mode_size_bytes(mode);
1090 } else if (is_ia32_irn(node) &&
1091 get_ia32_frame_ent(node) == NULL &&
1092 is_ia32_use_frame(node)) {
1093 if (is_ia32_need_stackent(node))
1096 switch (get_ia32_irn_opcode(node)) {
1098 case iro_ia32_Load: {
1099 const ia32_attr_t *attr = get_ia32_attr_const(node);
1101 if (attr->data.need_32bit_stackent) {
1103 } else if (attr->data.need_64bit_stackent) {
1106 mode = get_ia32_ls_mode(node);
1107 if (is_ia32_is_reload(node))
1108 mode = get_spill_mode_mode(mode);
1110 align = get_mode_size_bytes(mode);
1116 case iro_ia32_xLoad: {
1117 mode = get_ia32_ls_mode(node);
1122 case iro_ia32_FldCW: {
1123 /* although 2 byte would be enough 4 byte performs best */
1131 panic("unexpected frame user while collection frame entity nodes");
1133 case iro_ia32_FnstCW:
1134 case iro_ia32_Store8Bit:
1135 case iro_ia32_Store:
1138 case iro_ia32_fisttp:
1139 case iro_ia32_xStore:
1140 case iro_ia32_xStoreSimple:
1147 be_node_needs_frame_entity(env, node, mode, align);
1150 static int determine_ebp_input(ir_node *ret)
1152 const arch_register_t *bp = &ia32_registers[REG_EBP];
1153 int arity = get_irn_arity(ret);
1156 for (i = 0; i < arity; ++i) {
1157 ir_node *input = get_irn_n(ret, i);
1158 if (arch_get_irn_register(input) == bp)
1161 panic("no ebp input found at %+F", ret);
1164 static void introduce_epilog(ir_node *ret)
1166 const arch_register_t *sp = &ia32_registers[REG_ESP];
1167 const arch_register_t *bp = &ia32_registers[REG_EBP];
1168 ir_graph *irg = get_irn_irg(ret);
1169 ir_type *frame_type = get_irg_frame_type(irg);
1170 unsigned frame_size = get_type_size_bytes(frame_type);
1171 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1172 ir_node *block = get_nodes_block(ret);
1173 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1174 ir_node *curr_sp = first_sp;
1175 ir_mode *mode_gp = ia32_reg_classes[CLASS_ia32_gp].mode;
1177 if (!layout->sp_relative) {
1178 int n_ebp = determine_ebp_input(ret);
1179 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1180 if (ia32_cg_config.use_leave) {
1181 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1182 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1183 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1184 arch_set_irn_register(curr_bp, bp);
1185 arch_set_irn_register(curr_sp, sp);
1186 sched_add_before(ret, leave);
1189 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1190 /* copy ebp to esp */
1191 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1192 arch_set_irn_register(curr_sp, sp);
1193 sched_add_before(ret, curr_sp);
1196 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1197 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1198 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1199 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1200 arch_set_irn_register(curr_bp, bp);
1201 arch_set_irn_register(curr_sp, sp);
1202 sched_add_before(ret, pop);
1204 set_irn_n(ret, n_be_Return_mem, curr_mem);
1206 set_irn_n(ret, n_ebp, curr_bp);
1208 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1209 sched_add_before(ret, incsp);
1212 set_irn_n(ret, n_be_Return_sp, curr_sp);
1214 /* keep verifier happy... */
1215 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1216 kill_node(first_sp);
1221 * put the Prolog code at the beginning, epilog code before each return
1223 static void introduce_prolog_epilog(ir_graph *irg)
1225 const arch_register_t *sp = &ia32_registers[REG_ESP];
1226 const arch_register_t *bp = &ia32_registers[REG_EBP];
1227 ir_node *start = get_irg_start(irg);
1228 ir_node *block = get_nodes_block(start);
1229 ir_type *frame_type = get_irg_frame_type(irg);
1230 unsigned frame_size = get_type_size_bytes(frame_type);
1231 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1232 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1233 ir_node *curr_sp = initial_sp;
1234 ir_mode *mode_gp = mode_Iu;
1236 if (!layout->sp_relative) {
1238 ir_node *mem = get_irg_initial_mem(irg);
1239 ir_node *noreg = ia32_new_NoReg_gp(irg);
1240 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1241 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, initial_bp, initial_sp);
1244 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1245 arch_set_irn_register(curr_sp, sp);
1246 sched_add_after(start, push);
1248 /* move esp to ebp */
1249 ir_node *const curr_bp = be_new_Copy(block, curr_sp);
1250 sched_add_after(push, curr_bp);
1251 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1252 curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
1253 sched_add_after(curr_bp, curr_sp);
1254 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1255 edges_reroute_except(initial_bp, curr_bp, push);
1257 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1258 edges_reroute_except(initial_sp, incsp, push);
1259 sched_add_after(curr_sp, incsp);
1261 /* make sure the initial IncSP is really used by someone */
1262 if (get_irn_n_edges(incsp) <= 1) {
1263 ir_node *in[] = { incsp };
1264 ir_node *keep = be_new_Keep(block, 1, in);
1265 sched_add_after(incsp, keep);
1268 layout->initial_bias = -4;
1270 ir_node *const incsp = be_new_IncSP(sp, block, initial_sp, frame_size, 0);
1271 edges_reroute_except(initial_sp, incsp, incsp);
1272 sched_add_after(start, incsp);
1275 /* introduce epilog for every return node */
1277 ir_node *end_block = get_irg_end_block(irg);
1278 int arity = get_irn_arity(end_block);
1281 for (i = 0; i < arity; ++i) {
1282 ir_node *ret = get_irn_n(end_block, i);
1283 assert(be_is_Return(ret));
1284 introduce_epilog(ret);
1290 * Last touchups for the graph before emit: x87 simulation to replace the
1291 * virtual with real x87 instructions, creating a block schedule and peephole
1294 static void ia32_finish_graph(ir_graph *irg)
1296 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1297 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1298 bool at_begin = stack_layout->sp_relative ? true : false;
1299 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1301 /* create and coalesce frame entities */
1302 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1303 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1304 be_free_frame_entity_coalescer(fec_env);
1306 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1308 introduce_prolog_epilog(irg);
1310 /* fix stack entity offsets */
1311 be_abi_fix_stack_nodes(irg);
1312 be_abi_fix_stack_bias(irg);
1314 /* fix 2-address code constraints */
1315 ia32_finish_irg(irg);
1317 /* we might have to rewrite x87 virtual registers */
1318 if (irg_data->do_x87_sim) {
1319 ia32_x87_simulate_graph(irg);
1322 /* do peephole optimisations */
1323 ia32_peephole_optimization(irg);
1325 be_remove_dead_nodes_from_schedule(irg);
1327 /* create block schedule, this also removes empty blocks which might
1328 * produce critical edges */
1329 irg_data->blk_sched = be_create_block_schedule(irg);
1333 * Emits the code, closes the output file and frees
1334 * the code generator interface.
1336 static void ia32_emit(ir_graph *irg)
1338 if (ia32_cg_config.emit_machcode) {
1339 ia32_gen_binary_routine(irg);
1341 ia32_gen_routine(irg);
1346 * Returns the node representing the PIC base.
1348 static ir_node *ia32_get_pic_base(ir_graph *irg)
1350 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1352 ir_node *get_eip = irg_data->get_eip;
1353 if (get_eip != NULL)
1356 block = get_irg_start_block(irg);
1357 get_eip = new_bd_ia32_GetEIP(NULL, block);
1358 irg_data->get_eip = get_eip;
1364 * Initializes a IA32 code generator.
1366 static void ia32_init_graph(ir_graph *irg)
1368 struct obstack *obst = be_get_be_obst(irg);
1369 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1371 irg_data->dump = (be_options.dump_flags & DUMP_BE) ? 1 : 0;
1374 /* Linux gprof implementation needs base pointer */
1375 be_options.omit_fp = 0;
1378 be_birg_from_irg(irg)->isa_link = irg_data;
1381 static const tarval_mode_info mo_integer = {
1388 * set the tarval output mode of all integer modes to decimal
1390 static void set_tarval_output_modes(void)
1394 for (i = ir_get_n_modes(); i > 0;) {
1395 ir_mode *mode = ir_get_mode(--i);
1397 if (mode_is_int(mode))
1398 set_tarval_mode_output_option(mode, &mo_integer);
1402 extern const arch_isa_if_t ia32_isa_if;
1404 static void init_asm_constraints(void)
1406 be_init_default_asm_constraint_flags();
1408 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1409 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1410 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1411 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1412 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1413 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1414 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1415 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1416 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1417 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1418 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1419 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1420 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1421 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1422 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1423 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1424 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1425 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1426 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1427 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1429 /* no support for autodecrement/autoincrement */
1430 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1431 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1432 /* no float consts */
1433 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1434 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1435 /* makes no sense on x86 */
1436 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1437 /* no support for sse consts yet */
1438 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1439 /* no support for x87 consts yet */
1440 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1441 /* no support for mmx registers yet */
1442 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1443 /* not available in 32bit mode */
1444 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1445 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1447 /* no code yet to determine register class needed... */
1448 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1452 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1454 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1459 ir_relation relation;
1464 cmp_l = get_Cmp_left(sel);
1465 cmp_r = get_Cmp_right(sel);
1466 if (!mode_is_float(get_irn_mode(cmp_l)))
1469 /* check for min/max. They're defined as (C-Semantik):
1470 * min(a, b) = a < b ? a : b
1471 * or min(a, b) = a <= b ? a : b
1472 * max(a, b) = a > b ? a : b
1473 * or max(a, b) = a >= b ? a : b
1474 * (Note we only handle float min/max here)
1476 relation = get_Cmp_relation(sel);
1478 case ir_relation_greater_equal:
1479 case ir_relation_greater:
1481 if (cmp_l == mux_true && cmp_r == mux_false)
1484 case ir_relation_less_equal:
1485 case ir_relation_less:
1487 if (cmp_l == mux_true && cmp_r == mux_false)
1490 case ir_relation_unordered_greater_equal:
1491 case ir_relation_unordered_greater:
1493 if (cmp_l == mux_false && cmp_r == mux_true)
1496 case ir_relation_unordered_less_equal:
1497 case ir_relation_unordered_less:
1499 if (cmp_l == mux_false && cmp_r == mux_true)
1510 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1512 ir_mode *mode = get_irn_mode(mux_true);
1515 if (!mode_is_int(mode) && !mode_is_reference(mode)
1519 if (is_Const(mux_true) && is_Const(mux_false)) {
1520 /* we can create a set plus up two 3 instructions for any combination
1528 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1533 if (!mode_is_float(get_irn_mode(mux_true)))
1536 return is_Const(mux_true) && is_Const(mux_false);
1539 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1546 ir_relation relation;
1551 mode = get_irn_mode(mux_true);
1552 if (mode_is_signed(mode) || mode_is_float(mode))
1555 relation = get_Cmp_relation(sel);
1556 cmp_left = get_Cmp_left(sel);
1557 cmp_right = get_Cmp_right(sel);
1559 /* "move" zero constant to false input */
1560 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1561 ir_node *tmp = mux_false;
1562 mux_false = mux_true;
1564 relation = get_negated_relation(relation);
1566 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1568 if (!is_Sub(mux_true))
1570 sub_left = get_Sub_left(mux_true);
1571 sub_right = get_Sub_right(mux_true);
1573 /* Mux(a >=u b, 0, a-b) */
1574 if ((relation & ir_relation_greater)
1575 && sub_left == cmp_left && sub_right == cmp_right)
1577 /* Mux(a <=u b, 0, b-a) */
1578 if ((relation & ir_relation_less)
1579 && sub_left == cmp_right && sub_right == cmp_left)
1585 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1590 /* middleend can handle some things */
1591 if (ir_is_optimizable_mux(sel, mux_false, mux_true))
1593 /* we can handle Set for all modes and compares */
1594 if (mux_is_set(sel, mux_true, mux_false))
1596 /* SSE has own min/max operations */
1597 if (ia32_cg_config.use_sse2
1598 && mux_is_float_min_max(sel, mux_true, mux_false))
1600 /* we can handle Mux(?, Const[f], Const[f]) */
1601 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1602 #ifdef FIRM_GRGEN_BE
1603 /* well, some code selectors can't handle it */
1604 if (be_transformer != TRANSFORMER_PBQP
1605 || be_transformer != TRANSFORMER_RAND)
1612 /* no support for 64bit inputs to cmov */
1613 mode = get_irn_mode(mux_true);
1614 if (get_mode_size_bits(mode) > 32)
1616 /* we can handle Abs for all modes and compares (except 64bit) */
1617 if (ir_mux_is_abs(sel, mux_false, mux_true) != 0)
1619 /* we can't handle MuxF yet */
1620 if (mode_is_float(mode))
1623 if (mux_is_doz(sel, mux_true, mux_false))
1626 /* Check Cmp before the node */
1628 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1630 /* we can't handle 64bit compares */
1631 if (get_mode_size_bits(cmp_mode) > 32)
1634 /* we can't handle float compares */
1635 if (mode_is_float(cmp_mode))
1639 /* did we disable cmov generation? */
1640 if (!ia32_cg_config.use_cmov)
1643 /* we can use a cmov */
1648 * Create the trampoline code.
1650 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
1652 ir_graph *const irg = get_irn_irg(block);
1653 ir_node * p = trampoline;
1654 ir_mode *const mode = get_irn_mode(p);
1655 ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
1656 ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
1660 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
1661 mem = new_r_Proj(st, mode_M, pn_Store_M);
1662 p = new_r_Add(block, p, one, mode);
1663 st = new_r_Store(block, mem, p, env, cons_none);
1664 mem = new_r_Proj(st, mode_M, pn_Store_M);
1665 p = new_r_Add(block, p, four, mode);
1667 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
1668 mem = new_r_Proj(st, mode_M, pn_Store_M);
1669 p = new_r_Add(block, p, one, mode);
1670 st = new_r_Store(block, mem, p, callee, cons_none);
1671 mem = new_r_Proj(st, mode_M, pn_Store_M);
1676 static const ir_settings_arch_dep_t ia32_arch_dep = {
1677 1, /* also use subs */
1678 4, /* maximum shifts */
1679 63, /* maximum shift amount */
1680 ia32_evaluate_insn, /* evaluate the instruction sequence */
1682 1, /* allow Mulhs */
1683 1, /* allow Mulus */
1684 32, /* Mulh allowed up to 32 bit */
1686 static backend_params ia32_backend_params = {
1687 1, /* support inline assembly */
1688 1, /* support Rotl nodes */
1689 0, /* little endian */
1690 1, /* modulo shift efficient */
1691 0, /* non-modulo shift not efficient */
1692 &ia32_arch_dep, /* will be set later */
1693 ia32_is_mux_allowed,
1694 32, /* machine_size */
1695 NULL, /* float arithmetic mode, will be set below */
1696 NULL, /* long long type */
1697 NULL, /* unsigned long long type */
1698 NULL, /* long double type */
1699 12, /* size of trampoline code */
1700 4, /* alignment of trampoline code */
1701 ia32_create_trampoline_fkt,
1702 4 /* alignment of stack parameter */
1706 * Initializes the backend ISA.
1708 static void ia32_init(void)
1710 ir_mode *mode_long_long;
1711 ir_mode *mode_unsigned_long_long;
1712 ir_type *type_long_long;
1713 ir_type *type_unsigned_long_long;
1715 ia32_setup_cg_config();
1717 init_asm_constraints();
1719 ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0);
1721 /* note mantissa is 64bit but with explicitely encoded 1 so the really
1722 * usable part as counted by firm is only 63 bits */
1723 ia32_mode_E = new_float_mode("E", irma_x86_extended_float, 15, 63);
1724 ia32_type_E = new_type_primitive(ia32_mode_E);
1725 set_type_size_bytes(ia32_type_E, 12);
1726 set_type_alignment_bytes(ia32_type_E, 4);
1728 mode_long_long = new_int_mode("long long", irma_twos_complement, 64, 1, 64);
1729 type_long_long = new_type_primitive(mode_long_long);
1730 mode_unsigned_long_long
1731 = new_int_mode("unsigned long long", irma_twos_complement, 64, 0, 64);
1732 type_unsigned_long_long = new_type_primitive(mode_unsigned_long_long);
1734 ia32_backend_params.type_long_long = type_long_long;
1735 ia32_backend_params.type_unsigned_long_long = type_unsigned_long_long;
1737 if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
1738 ia32_backend_params.mode_float_arithmetic = NULL;
1739 ia32_backend_params.type_long_double = NULL;
1741 ia32_backend_params.mode_float_arithmetic = ia32_mode_E;
1742 ia32_backend_params.type_long_double = ia32_type_E;
1745 ia32_register_init();
1746 obstack_init(&opcodes_obst);
1747 ia32_create_opcodes(&ia32_irn_ops);
1750 static void ia32_finish(void)
1752 if (between_type != NULL) {
1753 free_type(between_type);
1754 between_type = NULL;
1756 ia32_free_opcodes();
1757 obstack_free(&opcodes_obst, NULL);
1761 * The template that generates a new ISA object.
1762 * Note that this template can be changed by command line
1765 static ia32_isa_t ia32_isa_template = {
1767 &ia32_isa_if, /* isa interface implementation */
1772 &ia32_registers[REG_ESP], /* stack pointer register */
1773 &ia32_registers[REG_EBP], /* base pointer register */
1774 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1775 2, /* power of two stack alignment, 2^2 == 4 */
1776 NULL, /* main environment */
1777 7, /* costs for a spill instruction */
1778 5, /* costs for a reload instruction */
1779 false, /* no custom abi handling */
1782 IA32_FPU_ARCH_X87, /* FPU architecture */
1785 static arch_env_t *ia32_begin_codegeneration(const be_main_env_t *env)
1787 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1789 set_tarval_output_modes();
1791 *isa = ia32_isa_template;
1792 isa->tv_ent = pmap_create();
1794 /* enter the ISA object into the intrinsic environment */
1795 intrinsic_env.isa = isa;
1797 be_emit_init(env->file_handle);
1798 be_gas_begin_compilation_unit(env);
1804 * Closes the output file and frees the ISA structure.
1806 static void ia32_end_codegeneration(void *self)
1808 ia32_isa_t *isa = (ia32_isa_t*)self;
1810 /* emit now all global declarations */
1811 be_gas_end_compilation_unit(isa->base.main_env);
1815 pmap_destroy(isa->tv_ent);
1820 * Returns the register for parameter nr.
1822 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1823 const ir_mode *mode)
1825 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1826 &ia32_registers[REG_ECX],
1827 &ia32_registers[REG_EDX],
1830 static const unsigned MAXNUM_GPREG_ARGS = 3;
1832 static const arch_register_t *gpreg_param_reg_regparam[] = {
1833 &ia32_registers[REG_EAX],
1834 &ia32_registers[REG_EDX],
1835 &ia32_registers[REG_ECX]
1838 static const arch_register_t *gpreg_param_reg_this[] = {
1839 &ia32_registers[REG_ECX],
1844 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1845 &ia32_registers[REG_XMM0],
1846 &ia32_registers[REG_XMM1],
1847 &ia32_registers[REG_XMM2],
1848 &ia32_registers[REG_XMM3],
1849 &ia32_registers[REG_XMM4],
1850 &ia32_registers[REG_XMM5],
1851 &ia32_registers[REG_XMM6],
1852 &ia32_registers[REG_XMM7]
1855 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1856 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1858 static const unsigned MAXNUM_SSE_ARGS = 8;
1860 if ((cc & cc_this_call) && nr == 0)
1861 return gpreg_param_reg_this[0];
1863 if (! (cc & cc_reg_param))
1866 if (mode_is_float(mode)) {
1867 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1869 if (nr >= MAXNUM_SSE_ARGS)
1872 if (cc & cc_this_call) {
1873 return fpreg_sse_param_reg_this[nr];
1875 return fpreg_sse_param_reg_std[nr];
1876 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1877 unsigned num_regparam;
1879 if (get_mode_size_bits(mode) > 32)
1882 if (nr >= MAXNUM_GPREG_ARGS)
1885 if (cc & cc_this_call) {
1886 return gpreg_param_reg_this[nr];
1888 num_regparam = cc & ~cc_bits;
1889 if (num_regparam == 0) {
1890 /* default fastcall */
1891 return gpreg_param_reg_fastcall[nr];
1893 if (nr < num_regparam)
1894 return gpreg_param_reg_regparam[nr];
1898 panic("unknown argument mode");
1902 * Get the ABI restrictions for procedure calls.
1904 static void ia32_get_call_abi(ir_type *method_type, be_abi_call_t *abi)
1909 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1911 /* set abi flags for calls */
1912 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1913 call_flags.bits.call_has_imm = false; /* No call immediate, we handle this by ourselves */
1915 /* set parameter passing style */
1916 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1918 cc = get_method_calling_convention(method_type);
1919 if (get_method_variadicity(method_type) == variadicity_variadic) {
1920 /* pass all parameters of a variadic function on the stack */
1921 cc = cc_cdecl_set | (cc & cc_this_call);
1923 if (get_method_additional_properties(method_type) & mtp_property_private &&
1924 ia32_cg_config.optimize_cc) {
1925 /* set the fast calling conventions (allowing up to 3) */
1926 cc = SET_FASTCALL(cc) | 3;
1930 /* we have to pop the shadow parameter ourself for compound calls */
1931 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1932 && !(cc & cc_reg_param)) {
1933 pop_amount += get_mode_size_bytes(mode_P_data);
1936 n = get_method_n_params(method_type);
1937 for (i = regnum = 0; i < n; i++) {
1938 const arch_register_t *reg = NULL;
1939 ir_type *tp = get_method_param_type(method_type, i);
1940 ir_mode *mode = get_type_mode(tp);
1943 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1946 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1949 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1950 * movl has a shorter opcode than mov[sz][bw]l */
1951 ir_mode *load_mode = mode;
1954 unsigned size = get_mode_size_bytes(mode);
1956 if (cc & cc_callee_clear_stk) {
1957 pop_amount += (size + 3U) & ~3U;
1960 if (size < 4) load_mode = mode_Iu;
1963 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1967 be_abi_call_set_pop(abi, pop_amount);
1969 /* set return registers */
1970 n = get_method_n_ress(method_type);
1972 assert(n <= 2 && "more than two results not supported");
1974 /* In case of 64bit returns, we will have two 32bit values */
1976 ir_type *tp = get_method_res_type(method_type, 0);
1977 ir_mode *mode = get_type_mode(tp);
1979 assert(!mode_is_float(mode) && "two FP results not supported");
1981 tp = get_method_res_type(method_type, 1);
1982 mode = get_type_mode(tp);
1984 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1986 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1987 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1990 ir_type *tp = get_method_res_type(method_type, 0);
1991 ir_mode *mode = get_type_mode(tp);
1992 const arch_register_t *reg;
1993 assert(is_atomic_type(tp));
1995 reg = mode_is_float(mode) ? &ia32_registers[REG_ST0] : &ia32_registers[REG_EAX];
1997 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
2001 static void ia32_mark_remat(ir_node *node)
2003 if (is_ia32_irn(node)) {
2004 set_ia32_is_remat(node);
2008 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2012 /* we already added all our simple flags to the flags modifier list in
2013 * init, so this flag we don't know. */
2014 return ASM_CONSTRAINT_FLAG_INVALID;
2017 static int ia32_is_valid_clobber(const char *clobber)
2019 return ia32_get_clobber_register(clobber) != NULL;
2022 static void ia32_lower_for_target(void)
2024 ir_mode *mode_gp = ia32_reg_classes[CLASS_ia32_gp].mode;
2025 size_t i, n_irgs = get_irp_n_irgs();
2027 /* perform doubleword lowering */
2028 lwrdw_param_t lower_dw_params = {
2029 1, /* little endian */
2030 64, /* doubleword size */
2031 ia32_create_intrinsic_fkt,
2035 /* lower compound param handling
2036 * Note: we lower compound arguments ourself, since on ia32 we don't
2037 * have hidden parameters but know where to find the structs on the stack.
2038 * (This also forces us to always allocate space for the compound arguments
2039 * on the callframe and we can't just use an arbitrary position on the
2042 lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS);
2044 /* replace floating point operations by function calls */
2045 if (ia32_cg_config.use_softfloat) {
2046 lower_floating_point();
2049 for (i = 0; i < n_irgs; ++i) {
2050 ir_graph *irg = get_irp_irg(i);
2051 /* break up switches with wide ranges */
2052 lower_switch(irg, 4, 256, mode_gp);
2055 ir_prepare_dw_lowering(&lower_dw_params);
2058 for (i = 0; i < n_irgs; ++i) {
2059 ir_graph *irg = get_irp_irg(i);
2060 /* lower for mode_b stuff */
2061 ir_lower_mode_b(irg, mode_Iu);
2064 for (i = 0; i < n_irgs; ++i) {
2065 ir_graph *irg = get_irp_irg(i);
2066 /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
2067 * so we can generate rep movs later, and turn all big CopyBs into
2069 lower_CopyB(irg, 64, 8193, true);
2074 * Returns the libFirm configuration parameter for this backend.
2076 static const backend_params *ia32_get_libfirm_params(void)
2078 return &ia32_backend_params;
2082 * Check if the given register is callee or caller save.
2084 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
2087 /* check for callee saved */
2088 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2089 switch (reg->index) {
2100 /* check for caller saved */
2101 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2102 switch (reg->index) {
2110 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
2111 /* all XMM registers are caller save */
2112 return reg->index != REG_XMM_NOREG;
2113 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_fp]) {
2114 /* all FP registers are caller save */
2115 return reg->index != REG_FP_NOREG;
2121 static const lc_opt_enum_int_items_t gas_items[] = {
2122 { "elf", OBJECT_FILE_FORMAT_ELF },
2123 { "mingw", OBJECT_FILE_FORMAT_COFF },
2124 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2128 static lc_opt_enum_int_var_t gas_var = {
2129 (int*) &be_gas_object_file_format, gas_items
2132 #ifdef FIRM_GRGEN_BE
2133 static const lc_opt_enum_int_items_t transformer_items[] = {
2134 { "default", TRANSFORMER_DEFAULT },
2135 { "pbqp", TRANSFORMER_PBQP },
2136 { "random", TRANSFORMER_RAND },
2140 static lc_opt_enum_int_var_t transformer_var = {
2141 (int*)&be_transformer, transformer_items
2145 static const lc_opt_table_entry_t ia32_options[] = {
2146 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2147 #ifdef FIRM_GRGEN_BE
2148 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2150 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2151 &ia32_isa_template.base.stack_alignment),
2152 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2156 const arch_isa_if_t ia32_isa_if = {
2159 ia32_get_libfirm_params,
2160 ia32_lower_for_target,
2161 ia32_parse_asm_constraint,
2162 ia32_is_valid_clobber,
2164 ia32_begin_codegeneration,
2165 ia32_end_codegeneration,
2169 ia32_get_pic_base, /* return node used as base in pic code addresses */
2172 ia32_register_saved_by,
2174 ia32_handle_intrinsics,
2175 ia32_before_abi, /* before abi introduce hook */
2177 ia32_before_ra, /* before register allocation hook */
2178 ia32_finish_graph, /* called before codegen */
2179 ia32_emit, /* emit && done */
2182 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2183 void be_init_arch_ia32(void)
2185 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2186 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2188 lc_opt_add_table(ia32_grp, ia32_options);
2189 be_register_isa_if("ia32", &ia32_isa_if);
2191 ia32_init_emitter();
2193 ia32_init_optimize();
2194 ia32_init_transform();
2196 ia32_init_architecture();