2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
57 #include "../benode.h"
58 #include "../belower.h"
59 #include "../besched.h"
62 #include "../beirgmod.h"
63 #include "../be_dbgout.h"
64 #include "../beblocksched.h"
65 #include "../bemachine.h"
66 #include "../beilpsched.h"
67 #include "../bespillslots.h"
68 #include "../bemodule.h"
69 #include "../begnuas.h"
70 #include "../bestate.h"
71 #include "../beflags.h"
72 #include "../betranshlp.h"
73 #include "../belistsched.h"
74 #include "../beabihelper.h"
76 #include "bearch_ia32_t.h"
78 #include "ia32_new_nodes.h"
79 #include "gen_ia32_regalloc_if.h"
80 #include "gen_ia32_machine.h"
81 #include "ia32_common_transform.h"
82 #include "ia32_transform.h"
83 #include "ia32_emitter.h"
84 #include "ia32_map_regs.h"
85 #include "ia32_optimize.h"
87 #include "ia32_dbg_stat.h"
88 #include "ia32_finish.h"
89 #include "ia32_util.h"
91 #include "ia32_architecture.h"
94 #include "ia32_pbqp_transform.h"
96 transformer_t be_transformer = TRANSFORMER_DEFAULT;
99 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
101 ir_mode *mode_fpcw = NULL;
102 ia32_code_gen_t *ia32_current_cg = NULL;
104 /** The current omit-fp state */
105 static unsigned ia32_curr_fp_ommitted = 0;
106 static ir_type *omit_fp_between_type = NULL;
107 static ir_type *between_type = NULL;
108 static ir_entity *old_bp_ent = NULL;
109 static ir_entity *ret_addr_ent = NULL;
110 static ir_entity *omit_fp_ret_addr_ent = NULL;
113 * The environment for the intrinsic mapping.
115 static ia32_intrinsic_env_t intrinsic_env = {
117 NULL, /* the irg, these entities belong to */
118 NULL, /* entity for __divdi3 library call */
119 NULL, /* entity for __moddi3 library call */
120 NULL, /* entity for __udivdi3 library call */
121 NULL, /* entity for __umoddi3 library call */
125 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
128 * Used to create per-graph unique pseudo nodes.
130 static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
131 create_const_node_func func,
132 const arch_register_t* reg)
134 ir_node *block, *res;
139 block = get_irg_start_block(cg->irg);
140 res = func(NULL, block);
141 arch_set_irn_register(res, reg);
147 /* Creates the unique per irg GP NoReg node. */
148 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg)
150 return create_const(cg, &cg->noreg_gp, new_bd_ia32_NoReg_GP,
151 &ia32_gp_regs[REG_GP_NOREG]);
154 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg)
156 return create_const(cg, &cg->noreg_vfp, new_bd_ia32_NoReg_VFP,
157 &ia32_vfp_regs[REG_VFP_NOREG]);
160 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg)
162 return create_const(cg, &cg->noreg_xmm, new_bd_ia32_NoReg_XMM,
163 &ia32_xmm_regs[REG_XMM_NOREG]);
166 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg)
168 return create_const(cg, &cg->fpu_trunc_mode, new_bd_ia32_ChangeCW,
169 &ia32_fp_cw_regs[REG_FPCW]);
174 * Returns the admissible noreg register node for input register pos of node irn.
176 static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
178 const arch_register_req_t *req = arch_get_register_req(irn, pos);
180 assert(req != NULL && "Missing register requirements");
181 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
182 return ia32_new_NoReg_gp(cg);
184 if (ia32_cg_config.use_sse2) {
185 return ia32_new_NoReg_xmm(cg);
187 return ia32_new_NoReg_vfp(cg);
192 static const arch_register_req_t *get_ia32_SwitchJmp_out_req(
193 const ir_node *node, int pos)
197 return arch_no_register_req;
200 static arch_irn_class_t ia32_classify(const ir_node *irn)
202 arch_irn_class_t classification = 0;
204 assert(is_ia32_irn(irn));
206 if (is_ia32_is_reload(irn))
207 classification |= arch_irn_class_reload;
209 if (is_ia32_is_spill(irn))
210 classification |= arch_irn_class_spill;
212 if (is_ia32_is_remat(irn))
213 classification |= arch_irn_class_remat;
215 return classification;
219 * The IA32 ABI callback object.
222 be_abi_call_flags_bits_t flags; /**< The call flags. */
223 ir_graph *irg; /**< The associated graph. */
226 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
228 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
231 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
233 if (is_be_node(node))
234 be_node_set_frame_entity(node, entity);
236 set_ia32_frame_ent(node, entity);
239 static void ia32_set_frame_offset(ir_node *irn, int bias)
241 if (get_ia32_frame_ent(irn) == NULL)
244 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
245 ir_graph *irg = get_irn_irg(irn);
246 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
247 if (layout->sp_relative) {
248 /* Pop nodes modify the stack pointer before calculating the
249 * destination address, so fix this here
254 add_ia32_am_offs_int(irn, bias);
257 static int ia32_get_sp_bias(const ir_node *node)
259 if (is_ia32_Call(node))
260 return -(int)get_ia32_call_attr_const(node)->pop;
262 if (is_ia32_Push(node))
265 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
272 * Generate the routine prologue.
274 * @param self The callback object.
275 * @param mem A pointer to the mem node. Update this if you define new memory.
276 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
277 * @param stack_bias Points to the current stack bias, can be modified if needed.
279 * @return The register which shall be used as a stack frame base.
281 * All nodes which define registers in @p reg_map must keep @p reg_map current.
283 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
285 ia32_abi_env_t *env = self;
286 ia32_code_gen_t *cg = ia32_current_cg;
287 const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
289 ia32_curr_fp_ommitted = env->flags.try_omit_fp;
290 if (! env->flags.try_omit_fp) {
291 ir_node *bl = get_irg_start_block(env->irg);
292 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
293 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
294 ir_node *noreg = ia32_new_NoReg_gp(cg);
297 /* mark bp register as ignore */
298 be_set_constr_single_reg_out(get_Proj_pred(curr_bp),
299 get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
302 push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
303 curr_sp = new_r_Proj(push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
304 *mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
306 /* the push must have SP out register */
307 arch_set_irn_register(curr_sp, arch_env->sp);
309 /* this modifies the stack bias, because we pushed 32bit */
312 /* move esp to ebp */
313 curr_bp = be_new_Copy(arch_env->bp->reg_class, bl, curr_sp);
314 be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
315 arch_register_req_type_ignore);
317 /* beware: the copy must be done before any other sp use */
318 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
319 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
320 arch_register_req_type_produces_sp);
322 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
323 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
332 * Generate the routine epilogue.
333 * @param self The callback object.
334 * @param bl The block for the epilog
335 * @param mem A pointer to the mem node. Update this if you define new memory.
336 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
337 * @return The register which shall be used as a stack frame base.
339 * All nodes which define registers in @p reg_map must keep @p reg_map current.
341 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
343 ia32_abi_env_t *env = self;
344 const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
345 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
346 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
348 if (env->flags.try_omit_fp) {
349 /* simply remove the stack frame here */
350 curr_sp = be_new_IncSP(arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
352 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
354 if (ia32_cg_config.use_leave) {
358 leave = new_bd_ia32_Leave(NULL, bl, curr_bp);
359 curr_bp = new_r_Proj(leave, mode_bp, pn_ia32_Leave_frame);
360 curr_sp = new_r_Proj(leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
364 /* the old SP is not needed anymore (kill the proj) */
365 assert(is_Proj(curr_sp));
368 /* copy ebp to esp */
369 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], bl, curr_bp);
370 arch_set_irn_register(curr_sp, arch_env->sp);
371 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
372 arch_register_req_type_ignore);
375 pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
376 curr_bp = new_r_Proj(pop, mode_bp, pn_ia32_Pop_res);
377 curr_sp = new_r_Proj(pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
379 *mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
381 arch_set_irn_register(curr_sp, arch_env->sp);
382 arch_set_irn_register(curr_bp, arch_env->bp);
385 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
386 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
390 * Initialize the callback object.
391 * @param call The call object.
392 * @param irg The graph with the method.
393 * @return Some pointer. This pointer is passed to all other callback functions as self object.
395 static void *ia32_abi_init(const be_abi_call_t *call, ir_graph *irg)
397 ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
398 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
399 env->flags = fl.bits;
405 * Destroy the callback object.
406 * @param self The callback object.
408 static void ia32_abi_done(void *self)
414 * Build the between type and entities if not already build.
416 static void ia32_build_between_type(void)
418 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
419 if (! between_type) {
420 ir_type *old_bp_type = new_type_primitive(mode_Iu);
421 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
423 between_type = new_type_struct(IDENT("ia32_between_type"));
424 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
425 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
427 set_entity_offset(old_bp_ent, 0);
428 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
429 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
430 set_type_state(between_type, layout_fixed);
432 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
433 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
435 set_entity_offset(omit_fp_ret_addr_ent, 0);
436 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
437 set_type_state(omit_fp_between_type, layout_fixed);
443 * Produces the type which sits between the stack args and the locals on the stack.
444 * it will contain the return address and space to store the old base pointer.
445 * @return The Firm type modeling the ABI between type.
447 static ir_type *ia32_abi_get_between_type(void *self)
449 ia32_abi_env_t *env = self;
451 ia32_build_between_type();
452 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
456 * Return the stack entity that contains the return address.
458 ir_entity *ia32_get_return_address_entity(void)
460 ia32_build_between_type();
461 return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent;
465 * Return the stack entity that contains the frame address.
467 ir_entity *ia32_get_frame_address_entity(void)
469 ia32_build_between_type();
470 return ia32_curr_fp_ommitted ? NULL : old_bp_ent;
474 * Get the estimated cycle count for @p irn.
476 * @param self The this pointer.
477 * @param irn The node.
479 * @return The estimated cycle count for this operation
481 static int ia32_get_op_estimated_cost(const ir_node *irn)
484 ia32_op_type_t op_tp;
488 if (!is_ia32_irn(irn))
491 assert(is_ia32_irn(irn));
493 cost = get_ia32_latency(irn);
494 op_tp = get_ia32_op_type(irn);
496 if (is_ia32_CopyB(irn)) {
499 else if (is_ia32_CopyB_i(irn)) {
500 int size = get_ia32_copyb_size(irn);
501 cost = 20 + (int)ceil((4/3) * size);
503 /* in case of address mode operations add additional cycles */
504 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
506 In case of stack access and access to fixed addresses add 5 cycles
507 (we assume they are in cache), other memory operations cost 20
510 if (is_ia32_use_frame(irn) || (
511 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
512 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
524 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
526 * @param irn The original operation
527 * @param i Index of the argument we want the inverse operation to yield
528 * @param inverse struct to be filled with the resulting inverse op
529 * @param obstack The obstack to use for allocation of the returned nodes array
530 * @return The inverse operation or NULL if operation invertible
532 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
543 ir_node *block, *noreg, *nomem;
546 /* we cannot invert non-ia32 irns */
547 if (! is_ia32_irn(irn))
550 /* operand must always be a real operand (not base, index or mem) */
551 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
554 /* we don't invert address mode operations */
555 if (get_ia32_op_type(irn) != ia32_Normal)
558 /* TODO: adjust for new immediates... */
559 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
563 block = get_nodes_block(irn);
564 mode = get_irn_mode(irn);
565 irn_mode = get_irn_mode(irn);
566 noreg = get_irn_n(irn, 0);
568 dbg = get_irn_dbg_info(irn);
570 /* initialize structure */
571 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
575 switch (get_ia32_irn_opcode(irn)) {
578 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
579 /* we have an add with a const here */
580 /* invers == add with negated const */
581 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
583 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
584 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
585 set_ia32_commutative(inverse->nodes[0]);
587 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
588 /* we have an add with a symconst here */
589 /* invers == sub with const */
590 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
592 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
595 /* normal add: inverse == sub */
596 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
603 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
604 /* we have a sub with a const/symconst here */
605 /* invers == add with this const */
606 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
607 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
608 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
612 if (i == n_ia32_binary_left) {
613 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
616 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
624 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
625 /* xor with const: inverse = xor */
626 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
627 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
628 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
632 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
638 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
643 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
648 /* inverse operation not supported */
656 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
658 if (mode_is_float(mode))
665 * Get the mode that should be used for spilling value node
667 static ir_mode *get_spill_mode(const ir_node *node)
669 ir_mode *mode = get_irn_mode(node);
670 return get_spill_mode_mode(mode);
674 * Checks whether an addressmode reload for a node with mode mode is compatible
675 * with a spillslot of mode spill_mode
677 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
679 return !mode_is_float(mode) || mode == spillmode;
683 * Check if irn can load its operand at position i from memory (source addressmode).
684 * @param irn The irn to be checked
685 * @param i The operands position
686 * @return Non-Zero if operand can be loaded
688 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
690 ir_node *op = get_irn_n(irn, i);
691 const ir_mode *mode = get_irn_mode(op);
692 const ir_mode *spillmode = get_spill_mode(op);
694 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
695 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
696 !ia32_is_spillmode_compatible(mode, spillmode) ||
697 is_ia32_use_frame(irn)) /* must not already use frame */
700 switch (get_ia32_am_support(irn)) {
705 if (i != n_ia32_unary_op)
711 case n_ia32_binary_left: {
712 const arch_register_req_t *req;
713 if (!is_ia32_commutative(irn))
716 /* we can't swap left/right for limited registers
717 * (As this (currently) breaks constraint handling copies)
719 req = get_ia32_in_req(irn, n_ia32_binary_left);
720 if (req->type & arch_register_req_type_limited)
725 case n_ia32_binary_right:
734 panic("Unknown AM type");
737 /* HACK: must not already use "real" memory.
738 * This can happen for Call and Div */
739 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
745 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
749 ir_mode *dest_op_mode;
751 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
753 set_ia32_op_type(irn, ia32_AddrModeS);
755 load_mode = get_irn_mode(get_irn_n(irn, i));
756 dest_op_mode = get_ia32_ls_mode(irn);
757 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
758 set_ia32_ls_mode(irn, load_mode);
760 set_ia32_use_frame(irn);
761 set_ia32_need_stackent(irn);
763 if (i == n_ia32_binary_left &&
764 get_ia32_am_support(irn) == ia32_am_binary &&
765 /* immediates are only allowed on the right side */
766 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
767 ia32_swap_left_right(irn);
768 i = n_ia32_binary_right;
771 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
773 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
774 set_irn_n(irn, n_ia32_mem, spill);
775 set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i));
776 set_ia32_is_reload(irn);
779 static const be_abi_callbacks_t ia32_abi_callbacks = {
782 ia32_abi_get_between_type,
787 /* register allocator interface */
788 static const arch_irn_ops_t ia32_irn_ops = {
791 ia32_get_frame_entity,
792 ia32_set_frame_offset,
795 ia32_get_op_estimated_cost,
796 ia32_possible_memory_operand,
797 ia32_perform_memory_operand,
800 /* special register allocator interface for SwitchJmp
801 as it possibly has a WIDE range of Proj numbers.
802 We don't want to allocate output for register constraints for
804 static const arch_irn_ops_t ia32_SwitchJmp_irn_ops = {
805 /* Note: we also use SwitchJmp_out_req for the inputs too:
806 This is because the bearch API has a conceptual problem at the moment.
807 Querying for negative proj numbers which can happen for switchs
808 isn't possible and will result in inputs getting queried */
809 get_ia32_SwitchJmp_out_req,
811 ia32_get_frame_entity,
812 ia32_set_frame_offset,
815 ia32_get_op_estimated_cost,
816 ia32_possible_memory_operand,
817 ia32_perform_memory_operand,
821 static ir_entity *mcount = NULL;
823 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
825 static void ia32_before_abi(void *self)
827 lower_mode_b_config_t lower_mode_b_config = {
828 mode_Iu, /* lowered mode */
829 mode_Bu, /* preferred mode for set */
830 0, /* don't lower direct compares */
832 ia32_code_gen_t *cg = self;
834 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
836 dump_ir_graph(cg->irg, "lower_modeb");
839 if (mcount == NULL) {
840 ir_type *tp = new_type_method(0, 0);
841 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
842 /* FIXME: enter the right ld_ident here */
843 set_entity_ld_ident(mcount, get_entity_ident(mcount));
844 set_entity_visibility(mcount, ir_visibility_external);
846 instrument_initcall(cg->irg, mcount);
851 * Transforms the standard firm graph into
854 static void ia32_prepare_graph(void *self)
856 ia32_code_gen_t *cg = self;
859 switch (be_transformer) {
860 case TRANSFORMER_DEFAULT:
861 /* transform remaining nodes into assembler instructions */
862 ia32_transform_graph(cg);
865 case TRANSFORMER_PBQP:
866 case TRANSFORMER_RAND:
867 /* transform nodes into assembler instructions by PBQP magic */
868 ia32_transform_graph_by_pbqp(cg);
872 panic("invalid transformer");
875 ia32_transform_graph(cg);
878 /* do local optimizations (mainly CSE) */
879 optimize_graph_df(cg->irg);
882 dump_ir_graph(cg->irg, "transformed");
884 /* optimize address mode */
885 ia32_optimize_graph(cg);
887 /* do code placement, to optimize the position of constants */
891 dump_ir_graph(cg->irg, "place");
894 ir_node *turn_back_am(ir_node *node)
896 dbg_info *dbgi = get_irn_dbg_info(node);
897 ir_node *block = get_nodes_block(node);
898 ir_node *base = get_irn_n(node, n_ia32_base);
899 ir_node *index = get_irn_n(node, n_ia32_index);
900 ir_node *mem = get_irn_n(node, n_ia32_mem);
903 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
904 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
906 ia32_copy_am_attrs(load, node);
907 if (is_ia32_is_reload(node))
908 set_ia32_is_reload(load);
909 set_irn_n(node, n_ia32_mem, new_NoMem());
911 switch (get_ia32_am_support(node)) {
913 set_irn_n(node, n_ia32_unary_op, load_res);
917 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
918 set_irn_n(node, n_ia32_binary_left, load_res);
920 set_irn_n(node, n_ia32_binary_right, load_res);
925 panic("Unknown AM type");
927 noreg = ia32_new_NoReg_gp(ia32_current_cg);
928 set_irn_n(node, n_ia32_base, noreg);
929 set_irn_n(node, n_ia32_index, noreg);
930 set_ia32_am_offs_int(node, 0);
931 set_ia32_am_sc(node, NULL);
932 set_ia32_am_scale(node, 0);
933 clear_ia32_am_sc_sign(node);
935 /* rewire mem-proj */
936 if (get_irn_mode(node) == mode_T) {
937 const ir_edge_t *edge;
938 foreach_out_edge(node, edge) {
939 ir_node *out = get_edge_src_irn(edge);
940 if (get_irn_mode(out) == mode_M) {
941 set_Proj_pred(out, load);
942 set_Proj_proj(out, pn_ia32_Load_M);
948 set_ia32_op_type(node, ia32_Normal);
949 if (sched_is_scheduled(node))
950 sched_add_before(node, load);
955 static ir_node *flags_remat(ir_node *node, ir_node *after)
957 /* we should turn back source address mode when rematerializing nodes */
962 if (is_Block(after)) {
965 block = get_nodes_block(after);
968 type = get_ia32_op_type(node);
975 /* TODO implement this later... */
976 panic("found DestAM with flag user %+F this should not happen", node);
979 default: assert(type == ia32_Normal); break;
982 copy = exact_copy(node);
983 set_nodes_block(copy, block);
984 sched_add_after(after, copy);
990 * Called before the register allocator.
992 static void ia32_before_ra(void *self)
994 ia32_code_gen_t *cg = self;
996 /* setup fpu rounding modes */
997 ia32_setup_fpu_mode(cg);
1000 be_sched_fix_flags(cg->irg, &ia32_reg_classes[CLASS_ia32_flags],
1001 &flags_remat, NULL);
1003 be_add_missing_keeps(cg->irg);
1008 * Transforms a be_Reload into a ia32 Load.
1010 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node)
1012 ir_graph *irg = get_irn_irg(node);
1013 dbg_info *dbg = get_irn_dbg_info(node);
1014 ir_node *block = get_nodes_block(node);
1015 ir_entity *ent = be_get_frame_entity(node);
1016 ir_mode *mode = get_irn_mode(node);
1017 ir_mode *spillmode = get_spill_mode(node);
1018 ir_node *noreg = ia32_new_NoReg_gp(cg);
1019 ir_node *sched_point = NULL;
1020 ir_node *ptr = get_irg_frame(irg);
1021 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1022 ir_node *new_op, *proj;
1023 const arch_register_t *reg;
1025 if (sched_is_scheduled(node)) {
1026 sched_point = sched_prev(node);
1029 if (mode_is_float(spillmode)) {
1030 if (ia32_cg_config.use_sse2)
1031 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
1033 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
1035 else if (get_mode_size_bits(spillmode) == 128) {
1036 /* Reload 128 bit SSE registers */
1037 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
1040 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
1042 set_ia32_op_type(new_op, ia32_AddrModeS);
1043 set_ia32_ls_mode(new_op, spillmode);
1044 set_ia32_frame_ent(new_op, ent);
1045 set_ia32_use_frame(new_op);
1046 set_ia32_is_reload(new_op);
1048 DBG_OPT_RELOAD2LD(node, new_op);
1050 proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
1053 sched_add_after(sched_point, new_op);
1057 /* copy the register from the old node to the new Load */
1058 reg = arch_get_irn_register(node);
1059 arch_set_irn_register(proj, reg);
1061 SET_IA32_ORIG_NODE(new_op, node);
1063 exchange(node, proj);
1067 * Transforms a be_Spill node into a ia32 Store.
1069 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node)
1071 ir_graph *irg = get_irn_irg(node);
1072 dbg_info *dbg = get_irn_dbg_info(node);
1073 ir_node *block = get_nodes_block(node);
1074 ir_entity *ent = be_get_frame_entity(node);
1075 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1076 ir_mode *mode = get_spill_mode(spillval);
1077 ir_node *noreg = ia32_new_NoReg_gp(cg);
1078 ir_node *nomem = new_NoMem();
1079 ir_node *ptr = get_irg_frame(irg);
1080 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1082 ir_node *sched_point = NULL;
1084 if (sched_is_scheduled(node)) {
1085 sched_point = sched_prev(node);
1088 if (mode_is_float(mode)) {
1089 if (ia32_cg_config.use_sse2)
1090 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
1092 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
1093 } else if (get_mode_size_bits(mode) == 128) {
1094 /* Spill 128 bit SSE registers */
1095 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
1096 } else if (get_mode_size_bits(mode) == 8) {
1097 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
1099 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
1102 set_ia32_op_type(store, ia32_AddrModeD);
1103 set_ia32_ls_mode(store, mode);
1104 set_ia32_frame_ent(store, ent);
1105 set_ia32_use_frame(store);
1106 set_ia32_is_spill(store);
1107 SET_IA32_ORIG_NODE(store, node);
1108 DBG_OPT_SPILL2ST(node, store);
1111 sched_add_after(sched_point, store);
1115 exchange(node, store);
1118 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
1120 dbg_info *dbg = get_irn_dbg_info(node);
1121 ir_node *block = get_nodes_block(node);
1122 ir_node *noreg = ia32_new_NoReg_gp(cg);
1123 ir_graph *irg = get_irn_irg(node);
1124 ir_node *frame = get_irg_frame(irg);
1126 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
1128 set_ia32_frame_ent(push, ent);
1129 set_ia32_use_frame(push);
1130 set_ia32_op_type(push, ia32_AddrModeS);
1131 set_ia32_ls_mode(push, mode_Is);
1132 set_ia32_is_spill(push);
1134 sched_add_before(schedpoint, push);
1138 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
1140 dbg_info *dbg = get_irn_dbg_info(node);
1141 ir_node *block = get_nodes_block(node);
1142 ir_node *noreg = ia32_new_NoReg_gp(cg);
1143 ir_graph *irg = get_irn_irg(node);
1144 ir_node *frame = get_irg_frame(irg);
1146 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
1148 set_ia32_frame_ent(pop, ent);
1149 set_ia32_use_frame(pop);
1150 set_ia32_op_type(pop, ia32_AddrModeD);
1151 set_ia32_ls_mode(pop, mode_Is);
1152 set_ia32_is_reload(pop);
1154 sched_add_before(schedpoint, pop);
1159 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1161 dbg_info *dbg = get_irn_dbg_info(node);
1162 ir_mode *spmode = mode_Iu;
1163 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1166 sp = new_rd_Proj(dbg, pred, spmode, pos);
1167 arch_set_irn_register(sp, spreg);
1173 * Transform MemPerm, currently we do this the ugly way and produce
1174 * push/pop into/from memory cascades. This is possible without using
1177 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
1179 ir_node *block = get_nodes_block(node);
1180 ir_node *sp = be_abi_get_ignore_irn(be_get_irg_abi(cg->irg), &ia32_gp_regs[REG_ESP]);
1181 int arity = be_get_MemPerm_entity_arity(node);
1182 ir_node **pops = ALLOCAN(ir_node*, arity);
1186 const ir_edge_t *edge;
1187 const ir_edge_t *next;
1190 for (i = 0; i < arity; ++i) {
1191 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1192 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1193 ir_type *enttype = get_entity_type(inent);
1194 unsigned entsize = get_type_size_bytes(enttype);
1195 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1196 ir_node *mem = get_irn_n(node, i + 1);
1199 /* work around cases where entities have different sizes */
1200 if (entsize2 < entsize)
1202 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1204 push = create_push(cg, node, node, sp, mem, inent);
1205 sp = create_spproj(node, push, pn_ia32_Push_stack);
1207 /* add another push after the first one */
1208 push = create_push(cg, node, node, sp, mem, inent);
1209 add_ia32_am_offs_int(push, 4);
1210 sp = create_spproj(node, push, pn_ia32_Push_stack);
1213 set_irn_n(node, i, new_Bad());
1217 for (i = arity - 1; i >= 0; --i) {
1218 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1219 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1220 ir_type *enttype = get_entity_type(outent);
1221 unsigned entsize = get_type_size_bytes(enttype);
1222 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1225 /* work around cases where entities have different sizes */
1226 if (entsize2 < entsize)
1228 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1230 pop = create_pop(cg, node, node, sp, outent);
1231 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1233 add_ia32_am_offs_int(pop, 4);
1235 /* add another pop after the first one */
1236 pop = create_pop(cg, node, node, sp, outent);
1237 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1244 keep = be_new_Keep(block, 1, in);
1245 sched_add_before(node, keep);
1247 /* exchange memprojs */
1248 foreach_out_edge_safe(node, edge, next) {
1249 ir_node *proj = get_edge_src_irn(edge);
1250 int p = get_Proj_proj(proj);
1254 set_Proj_pred(proj, pops[p]);
1255 set_Proj_proj(proj, pn_ia32_Pop_M);
1258 /* remove memperm */
1259 arity = get_irn_arity(node);
1260 for (i = 0; i < arity; ++i) {
1261 set_irn_n(node, i, new_Bad());
1267 * Block-Walker: Calls the transform functions Spill and Reload.
1269 static void ia32_after_ra_walker(ir_node *block, void *env)
1271 ir_node *node, *prev;
1272 ia32_code_gen_t *cg = env;
1274 /* beware: the schedule is changed here */
1275 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1276 prev = sched_prev(node);
1278 if (be_is_Reload(node)) {
1279 transform_to_Load(cg, node);
1280 } else if (be_is_Spill(node)) {
1281 transform_to_Store(cg, node);
1282 } else if (be_is_MemPerm(node)) {
1283 transform_MemPerm(cg, node);
1289 * Collects nodes that need frame entities assigned.
1291 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1293 be_fec_env_t *env = data;
1294 const ir_mode *mode;
1297 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1298 mode = get_spill_mode_mode(get_irn_mode(node));
1299 align = get_mode_size_bytes(mode);
1300 } else if (is_ia32_irn(node) &&
1301 get_ia32_frame_ent(node) == NULL &&
1302 is_ia32_use_frame(node)) {
1303 if (is_ia32_need_stackent(node))
1306 switch (get_ia32_irn_opcode(node)) {
1308 case iro_ia32_Load: {
1309 const ia32_attr_t *attr = get_ia32_attr_const(node);
1311 if (attr->data.need_32bit_stackent) {
1313 } else if (attr->data.need_64bit_stackent) {
1316 mode = get_ia32_ls_mode(node);
1317 if (is_ia32_is_reload(node))
1318 mode = get_spill_mode_mode(mode);
1320 align = get_mode_size_bytes(mode);
1324 case iro_ia32_vfild:
1326 case iro_ia32_xLoad: {
1327 mode = get_ia32_ls_mode(node);
1332 case iro_ia32_FldCW: {
1333 /* although 2 byte would be enough 4 byte performs best */
1341 panic("unexpected frame user while collection frame entity nodes");
1343 case iro_ia32_FnstCW:
1344 case iro_ia32_Store8Bit:
1345 case iro_ia32_Store:
1348 case iro_ia32_vfist:
1349 case iro_ia32_vfisttp:
1351 case iro_ia32_xStore:
1352 case iro_ia32_xStoreSimple:
1359 be_node_needs_frame_entity(env, node, mode, align);
1363 * We transform Spill and Reload here. This needs to be done before
1364 * stack biasing otherwise we would miss the corrected offset for these nodes.
1366 static void ia32_after_ra(void *self)
1368 ia32_code_gen_t *cg = self;
1369 ir_graph *irg = cg->irg;
1370 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->irg);
1372 /* create and coalesce frame entities */
1373 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1374 be_assign_entities(fec_env, ia32_set_frame_entity);
1375 be_free_frame_entity_coalescer(fec_env);
1377 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1381 * Last touchups for the graph before emit: x87 simulation to replace the
1382 * virtual with real x87 instructions, creating a block schedule and peephole
1385 static void ia32_finish(void *self)
1387 ia32_code_gen_t *cg = self;
1388 ir_graph *irg = cg->irg;
1390 ia32_finish_irg(irg, cg);
1392 /* we might have to rewrite x87 virtual registers */
1393 if (cg->do_x87_sim) {
1394 x87_simulate_graph(cg->irg);
1397 /* do peephole optimisations */
1398 ia32_peephole_optimization(cg);
1400 /* create block schedule, this also removes empty blocks which might
1401 * produce critical edges */
1402 cg->blk_sched = be_create_block_schedule(irg);
1406 * Emits the code, closes the output file and frees
1407 * the code generator interface.
1409 static void ia32_codegen(void *self)
1411 ia32_code_gen_t *cg = self;
1412 ir_graph *irg = cg->irg;
1414 if (ia32_cg_config.emit_machcode) {
1415 ia32_gen_binary_routine(cg, irg);
1417 ia32_gen_routine(cg, irg);
1420 /* remove it from the isa */
1423 assert(ia32_current_cg == cg);
1424 ia32_current_cg = NULL;
1426 /* de-allocate code generator */
1431 * Returns the node representing the PIC base.
1433 static ir_node *ia32_get_pic_base(void *self)
1436 ia32_code_gen_t *cg = self;
1437 ir_node *get_eip = cg->get_eip;
1438 if (get_eip != NULL)
1441 block = get_irg_start_block(cg->irg);
1442 get_eip = new_bd_ia32_GetEIP(NULL, block);
1443 cg->get_eip = get_eip;
1445 be_dep_on_frame(get_eip);
1449 static void *ia32_cg_init(ir_graph *irg);
1451 static const arch_code_generator_if_t ia32_code_gen_if = {
1453 ia32_get_pic_base, /* return node used as base in pic code addresses */
1454 ia32_before_abi, /* before abi introduce hook */
1457 ia32_before_ra, /* before register allocation hook */
1458 ia32_after_ra, /* after register allocation hook */
1459 ia32_finish, /* called before codegen */
1460 ia32_codegen /* emit && done */
1464 * Initializes a IA32 code generator.
1466 static void *ia32_cg_init(ir_graph *irg)
1468 ia32_isa_t *isa = (ia32_isa_t *)be_get_irg_arch_env(irg);
1469 ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t);
1471 cg->impl = &ia32_code_gen_if;
1474 cg->blk_sched = NULL;
1475 cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1476 cg->gprof = (be_get_irg_options(irg)->gprof) ? 1 : 0;
1479 /* Linux gprof implementation needs base pointer */
1480 be_get_irg_options(irg)->omit_fp = 0;
1487 if (isa->name_obst) {
1488 obstack_free(isa->name_obst, NULL);
1489 obstack_init(isa->name_obst);
1493 assert(ia32_current_cg == NULL);
1494 ia32_current_cg = cg;
1496 return (arch_code_generator_t *)cg;
1501 * Set output modes for GCC
1503 static const tarval_mode_info mo_integer = {
1510 * set the tarval output mode of all integer modes to decimal
1512 static void set_tarval_output_modes(void)
1516 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1517 ir_mode *mode = get_irp_mode(i);
1519 if (mode_is_int(mode))
1520 set_tarval_mode_output_option(mode, &mo_integer);
1524 const arch_isa_if_t ia32_isa_if;
1527 * The template that generates a new ISA object.
1528 * Note that this template can be changed by command line
1531 static ia32_isa_t ia32_isa_template = {
1533 &ia32_isa_if, /* isa interface implementation */
1534 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1535 &ia32_gp_regs[REG_EBP], /* base pointer register */
1536 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1537 -1, /* stack direction */
1538 2, /* power of two stack alignment, 2^2 == 4 */
1539 NULL, /* main environment */
1540 7, /* costs for a spill instruction */
1541 5, /* costs for a reload instruction */
1542 false, /* no custom abi handling */
1544 NULL, /* 16bit register names */
1545 NULL, /* 8bit register names */
1546 NULL, /* 8bit register names high */
1549 NULL, /* current code generator */
1550 NULL, /* abstract machine */
1552 NULL, /* name obstack */
1556 static void init_asm_constraints(void)
1558 be_init_default_asm_constraint_flags();
1560 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1561 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1562 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1563 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1564 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1565 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1566 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1567 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1568 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1569 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1570 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1571 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1572 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1573 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1574 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1575 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1576 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1577 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1578 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1579 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1581 /* no support for autodecrement/autoincrement */
1582 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1583 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1584 /* no float consts */
1585 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1586 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1587 /* makes no sense on x86 */
1588 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1589 /* no support for sse consts yet */
1590 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1591 /* no support for x87 consts yet */
1592 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1593 /* no support for mmx registers yet */
1594 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1595 /* not available in 32bit mode */
1596 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1597 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1599 /* no code yet to determine register class needed... */
1600 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1604 * Initializes the backend ISA.
1606 static arch_env_t *ia32_init(FILE *file_handle)
1608 static int inited = 0;
1616 set_tarval_output_modes();
1618 isa = XMALLOC(ia32_isa_t);
1619 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1621 if (mode_fpcw == NULL) {
1622 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1625 ia32_register_init();
1626 ia32_create_opcodes(&ia32_irn_ops);
1627 /* special handling for SwitchJmp */
1628 op_ia32_SwitchJmp->ops.be_ops = &ia32_SwitchJmp_irn_ops;
1630 be_emit_init(file_handle);
1631 isa->regs_16bit = pmap_create();
1632 isa->regs_8bit = pmap_create();
1633 isa->regs_8bit_high = pmap_create();
1634 isa->types = pmap_create();
1635 isa->tv_ent = pmap_create();
1636 isa->cpu = ia32_init_machine_description();
1638 ia32_build_16bit_reg_map(isa->regs_16bit);
1639 ia32_build_8bit_reg_map(isa->regs_8bit);
1640 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1643 isa->name_obst = XMALLOC(struct obstack);
1644 obstack_init(isa->name_obst);
1647 /* enter the ISA object into the intrinsic environment */
1648 intrinsic_env.isa = isa;
1650 /* emit asm includes */
1651 n = get_irp_n_asms();
1652 for (i = 0; i < n; ++i) {
1653 be_emit_cstring("#APP\n");
1654 be_emit_ident(get_irp_asm(i));
1655 be_emit_cstring("\n#NO_APP\n");
1658 /* needed for the debug support */
1659 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1660 be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
1661 be_emit_write_line();
1669 * Closes the output file and frees the ISA structure.
1671 static void ia32_done(void *self)
1673 ia32_isa_t *isa = self;
1675 /* emit now all global declarations */
1676 be_gas_emit_decls(isa->base.main_env);
1678 pmap_destroy(isa->regs_16bit);
1679 pmap_destroy(isa->regs_8bit);
1680 pmap_destroy(isa->regs_8bit_high);
1681 pmap_destroy(isa->tv_ent);
1682 pmap_destroy(isa->types);
1685 obstack_free(isa->name_obst, NULL);
1695 * Return the number of register classes for this architecture.
1696 * We report always these:
1697 * - the general purpose registers
1698 * - the SSE floating point register set
1699 * - the virtual floating point registers
1700 * - the SSE vector register set
1702 static unsigned ia32_get_n_reg_class(void)
1708 * Return the register class for index i.
1710 static const arch_register_class_t *ia32_get_reg_class(unsigned i)
1712 assert(i < N_CLASSES);
1713 return &ia32_reg_classes[i];
1717 * Get the register class which shall be used to store a value of a given mode.
1718 * @param self The this pointer.
1719 * @param mode The mode in question.
1720 * @return A register class which can hold values of the given mode.
1722 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1724 if (mode_is_float(mode)) {
1725 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1728 return &ia32_reg_classes[CLASS_ia32_gp];
1732 * Returns the register for parameter nr.
1734 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1735 const ir_mode *mode)
1737 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1738 &ia32_gp_regs[REG_ECX],
1739 &ia32_gp_regs[REG_EDX],
1742 static const unsigned MAXNUM_GPREG_ARGS = 3;
1744 static const arch_register_t *gpreg_param_reg_regparam[] = {
1745 &ia32_gp_regs[REG_EAX],
1746 &ia32_gp_regs[REG_EDX],
1747 &ia32_gp_regs[REG_ECX]
1750 static const arch_register_t *gpreg_param_reg_this[] = {
1751 &ia32_gp_regs[REG_ECX],
1756 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1757 &ia32_xmm_regs[REG_XMM0],
1758 &ia32_xmm_regs[REG_XMM1],
1759 &ia32_xmm_regs[REG_XMM2],
1760 &ia32_xmm_regs[REG_XMM3],
1761 &ia32_xmm_regs[REG_XMM4],
1762 &ia32_xmm_regs[REG_XMM5],
1763 &ia32_xmm_regs[REG_XMM6],
1764 &ia32_xmm_regs[REG_XMM7]
1767 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1768 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1770 static const unsigned MAXNUM_SSE_ARGS = 8;
1772 if ((cc & cc_this_call) && nr == 0)
1773 return gpreg_param_reg_this[0];
1775 if (! (cc & cc_reg_param))
1778 if (mode_is_float(mode)) {
1779 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1781 if (nr >= MAXNUM_SSE_ARGS)
1784 if (cc & cc_this_call) {
1785 return fpreg_sse_param_reg_this[nr];
1787 return fpreg_sse_param_reg_std[nr];
1788 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1789 unsigned num_regparam;
1791 if (get_mode_size_bits(mode) > 32)
1794 if (nr >= MAXNUM_GPREG_ARGS)
1797 if (cc & cc_this_call) {
1798 return gpreg_param_reg_this[nr];
1800 num_regparam = cc & ~cc_bits;
1801 if (num_regparam == 0) {
1802 /* default fastcall */
1803 return gpreg_param_reg_fastcall[nr];
1805 if (nr < num_regparam)
1806 return gpreg_param_reg_regparam[nr];
1810 panic("unknown argument mode");
1814 * Get the ABI restrictions for procedure calls.
1815 * @param self The this pointer.
1816 * @param method_type The type of the method (procedure) in question.
1817 * @param abi The abi object to be modified
1819 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1827 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1831 /* set abi flags for calls */
1832 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1833 call_flags.bits.store_args_sequential = 0;
1834 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1835 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1836 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1838 /* set parameter passing style */
1839 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1841 cc = get_method_calling_convention(method_type);
1842 if (get_method_variadicity(method_type) == variadicity_variadic) {
1843 /* pass all parameters of a variadic function on the stack */
1844 cc = cc_cdecl_set | (cc & cc_this_call);
1846 if (get_method_additional_properties(method_type) & mtp_property_private &&
1847 ia32_cg_config.optimize_cc) {
1848 /* set the fast calling conventions (allowing up to 3) */
1849 cc = SET_FASTCALL(cc) | 3;
1853 /* we have to pop the shadow parameter ourself for compound calls */
1854 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1855 && !(cc & cc_reg_param)) {
1856 pop_amount += get_mode_size_bytes(mode_P_data);
1859 n = get_method_n_params(method_type);
1860 for (i = regnum = 0; i < n; i++) {
1862 const arch_register_t *reg = NULL;
1864 tp = get_method_param_type(method_type, i);
1865 mode = get_type_mode(tp);
1867 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1870 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1873 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1874 * movl has a shorter opcode than mov[sz][bw]l */
1875 ir_mode *load_mode = mode;
1878 unsigned size = get_mode_size_bytes(mode);
1880 if (cc & cc_callee_clear_stk) {
1881 pop_amount += (size + 3U) & ~3U;
1884 if (size < 4) load_mode = mode_Iu;
1887 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1891 be_abi_call_set_pop(abi, pop_amount);
1893 /* set return registers */
1894 n = get_method_n_ress(method_type);
1896 assert(n <= 2 && "more than two results not supported");
1898 /* In case of 64bit returns, we will have two 32bit values */
1900 tp = get_method_res_type(method_type, 0);
1901 mode = get_type_mode(tp);
1903 assert(!mode_is_float(mode) && "two FP results not supported");
1905 tp = get_method_res_type(method_type, 1);
1906 mode = get_type_mode(tp);
1908 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1910 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX], ABI_CONTEXT_BOTH);
1911 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX], ABI_CONTEXT_BOTH);
1914 const arch_register_t *reg;
1916 tp = get_method_res_type(method_type, 0);
1917 assert(is_atomic_type(tp));
1918 mode = get_type_mode(tp);
1920 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1922 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1926 static int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1930 if (!is_ia32_irn(irn)) {
1934 if (is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1935 || is_ia32_ChangeCW(irn) || is_ia32_Immediate(irn))
1942 * Initializes the code generator interface.
1944 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1947 return &ia32_code_gen_if;
1951 * Returns the estimated execution time of an ia32 irn.
1953 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn)
1956 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
1959 list_sched_selector_t ia32_sched_selector;
1962 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1964 static const list_sched_selector_t *ia32_get_list_sched_selector(
1965 const void *self, list_sched_selector_t *selector)
1968 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1969 ia32_sched_selector.exectime = ia32_sched_exectime;
1970 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1971 return &ia32_sched_selector;
1974 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1981 * Returns the necessary byte alignment for storing a register of given class.
1983 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1985 ir_mode *mode = arch_register_class_mode(cls);
1986 int bytes = get_mode_size_bytes(mode);
1988 if (mode_is_float(mode) && bytes > 8)
1993 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1996 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1997 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1998 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
2001 static const be_execution_unit_t *_allowed_units_GP[] = {
2002 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
2003 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
2004 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
2005 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
2006 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
2007 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
2008 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2011 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2012 &be_machine_execution_units_DUMMY[0],
2015 static const be_execution_unit_t **_units_callret[] = {
2016 _allowed_units_BRANCH,
2019 static const be_execution_unit_t **_units_other[] = {
2023 static const be_execution_unit_t **_units_dummy[] = {
2024 _allowed_units_DUMMY,
2027 const be_execution_unit_t ***ret;
2029 if (is_ia32_irn(irn)) {
2030 ret = get_ia32_exec_units(irn);
2031 } else if (is_be_node(irn)) {
2032 if (be_is_Return(irn)) {
2033 ret = _units_callret;
2034 } else if (be_is_Barrier(irn)) {
2048 * Return the abstract ia32 machine.
2050 static const be_machine_t *ia32_get_machine(const void *self)
2052 const ia32_isa_t *isa = self;
2057 * Return irp irgs in the desired order.
2059 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2066 static void ia32_mark_remat(ir_node *node)
2068 if (is_ia32_irn(node)) {
2069 set_ia32_is_remat(node);
2074 * Check if Mux(sel, t, f) would represent an Abs (or -Abs).
2076 static bool mux_is_abs(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
2085 cmp = get_Proj_pred(sel);
2089 /* must be <, <=, >=, > */
2090 pnc = get_Proj_proj(sel);
2105 if (!is_negated_value(mux_true, mux_false))
2108 /* must be x cmp 0 */
2109 cmp_right = get_Cmp_right(cmp);
2110 if (!is_Const(cmp_right) || !is_Const_null(cmp_right))
2113 cmp_left = get_Cmp_left(cmp);
2114 if (cmp_left != mux_true && cmp_left != mux_false)
2121 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
2123 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
2133 cmp = get_Proj_pred(sel);
2137 cmp_l = get_Cmp_left(cmp);
2138 cmp_r = get_Cmp_right(cmp);
2139 if (!mode_is_float(get_irn_mode(cmp_l)))
2142 /* check for min/max. They're defined as (C-Semantik):
2143 * min(a, b) = a < b ? a : b
2144 * or min(a, b) = a <= b ? a : b
2145 * max(a, b) = a > b ? a : b
2146 * or max(a, b) = a >= b ? a : b
2147 * (Note we only handle float min/max here)
2149 pnc = get_Proj_proj(sel);
2154 if (cmp_l == mux_true && cmp_r == mux_false)
2160 if (cmp_l == mux_true && cmp_r == mux_false)
2166 if (cmp_l == mux_false && cmp_r == mux_true)
2172 if (cmp_l == mux_false && cmp_r == mux_true)
2183 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
2185 ir_mode *mode = get_irn_mode(mux_true);
2188 if (!mode_is_int(mode) && !mode_is_reference(mode)
2192 if (is_Const(mux_true) && is_Const(mux_false)) {
2193 /* we can create a set plus up two 3 instructions for any combination of constants */
2200 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
2205 if (!mode_is_float(get_irn_mode(mux_true)))
2208 return is_Const(mux_true) && is_Const(mux_false);
2211 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
2224 cmp = get_Proj_pred(sel);
2228 mode = get_irn_mode(mux_true);
2229 if (mode_is_signed(mode) || mode_is_float(mode))
2232 pn = get_Proj_proj(sel);
2233 cmp_left = get_Cmp_left(cmp);
2234 cmp_right = get_Cmp_right(cmp);
2236 /* "move" zero constant to false input */
2237 if (is_Const(mux_true) && is_Const_null(mux_true)) {
2238 ir_node *tmp = mux_false;
2239 mux_false = mux_true;
2241 pn = get_negated_pnc(pn, mode);
2243 if (!is_Const(mux_false) || !is_Const_null(mux_false))
2245 if (!is_Sub(mux_true))
2247 sub_left = get_Sub_left(mux_true);
2248 sub_right = get_Sub_right(mux_true);
2250 /* Mux(a >=u b, 0, a-b) */
2251 if ((pn == pn_Cmp_Gt || pn == pn_Cmp_Ge)
2252 && sub_left == cmp_left && sub_right == cmp_right)
2254 /* Mux(a <=u b, 0, b-a) */
2255 if ((pn == pn_Cmp_Lt || pn == pn_Cmp_Le)
2256 && sub_left == cmp_right && sub_right == cmp_left)
2262 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
2267 /* we can handle Abs for all modes and compares */
2268 if (mux_is_abs(sel, mux_true, mux_false))
2270 /* we can handle Set for all modes and compares */
2271 if (mux_is_set(sel, mux_true, mux_false))
2273 /* SSE has own min/max operations */
2274 if (ia32_cg_config.use_sse2
2275 && mux_is_float_min_max(sel, mux_true, mux_false))
2277 /* we can handle Mux(?, Const[f], Const[f]) */
2278 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
2279 #ifdef FIRM_GRGEN_BE
2280 /* well, some code selectors can't handle it */
2281 if (be_transformer != TRANSFORMER_PBQP
2282 || be_transformer != TRANSFORMER_RAND)
2289 /* no support for 64bit inputs to cmov */
2290 mode = get_irn_mode(mux_true);
2291 if (get_mode_size_bits(mode) > 32)
2293 /* we can't handle MuxF yet */
2294 if (mode_is_float(mode))
2297 if (mux_is_doz(sel, mux_true, mux_false))
2300 /* Check Cmp before the node */
2302 ir_node *cmp = get_Proj_pred(sel);
2304 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(cmp));
2306 /* we can't handle 64bit compares */
2307 if (get_mode_size_bits(cmp_mode) > 32)
2310 /* we can't handle float compares */
2311 if (mode_is_float(cmp_mode))
2316 /* did we disable cmov generation? */
2317 if (!ia32_cg_config.use_cmov)
2320 /* we can use a cmov */
2324 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2328 /* we already added all our simple flags to the flags modifier list in
2329 * init, so this flag we don't know. */
2330 return ASM_CONSTRAINT_FLAG_INVALID;
2333 static int ia32_is_valid_clobber(const char *clobber)
2335 return ia32_get_clobber_register(clobber) != NULL;
2339 * Create the trampoline code.
2341 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2343 ir_node *st, *p = trampoline;
2344 ir_mode *mode = get_irn_mode(p);
2347 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xb9), 0);
2348 mem = new_r_Proj(st, mode_M, pn_Store_M);
2349 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2350 st = new_r_Store(block, mem, p, env, 0);
2351 mem = new_r_Proj(st, mode_M, pn_Store_M);
2352 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2354 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xe9), 0);
2355 mem = new_r_Proj(st, mode_M, pn_Store_M);
2356 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2357 st = new_r_Store(block, mem, p, callee, 0);
2358 mem = new_r_Proj(st, mode_M, pn_Store_M);
2359 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2365 * Returns the libFirm configuration parameter for this backend.
2367 static const backend_params *ia32_get_libfirm_params(void)
2369 static const ir_settings_arch_dep_t ad = {
2370 1, /* also use subs */
2371 4, /* maximum shifts */
2372 31, /* maximum shift amount */
2373 ia32_evaluate_insn, /* evaluate the instruction sequence */
2375 1, /* allow Mulhs */
2376 1, /* allow Mulus */
2377 32, /* Mulh allowed up to 32 bit */
2379 static backend_params p = {
2380 1, /* need dword lowering */
2381 1, /* support inline assembly */
2382 NULL, /* will be set later */
2383 ia32_create_intrinsic_fkt,
2384 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2385 ia32_is_mux_allowed, /* ifconv info will be set below */
2386 NULL, /* float arithmetic mode, will be set below */
2387 12, /* size of trampoline code */
2388 4, /* alignment of trampoline code */
2389 ia32_create_trampoline_fkt,
2390 4 /* alignment of stack parameter */
2393 ia32_setup_cg_config();
2395 /* doesn't really belong here, but this is the earliest place the backend
2397 init_asm_constraints();
2400 if (! ia32_cg_config.use_sse2)
2401 p.mode_float_arithmetic = mode_E;
2405 static const lc_opt_enum_int_items_t gas_items[] = {
2406 { "elf", OBJECT_FILE_FORMAT_ELF },
2407 { "mingw", OBJECT_FILE_FORMAT_COFF },
2408 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2412 static lc_opt_enum_int_var_t gas_var = {
2413 (int*) &be_gas_object_file_format, gas_items
2416 #ifdef FIRM_GRGEN_BE
2417 static const lc_opt_enum_int_items_t transformer_items[] = {
2418 { "default", TRANSFORMER_DEFAULT },
2419 { "pbqp", TRANSFORMER_PBQP },
2420 { "random", TRANSFORMER_RAND },
2424 static lc_opt_enum_int_var_t transformer_var = {
2425 (int*)&be_transformer, transformer_items
2429 static const lc_opt_table_entry_t ia32_options[] = {
2430 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2431 #ifdef FIRM_GRGEN_BE
2432 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2434 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2435 &ia32_isa_template.base.stack_alignment),
2439 const arch_isa_if_t ia32_isa_if = {
2442 ia32_handle_intrinsics,
2443 ia32_get_n_reg_class,
2445 ia32_get_reg_class_for_mode,
2447 ia32_get_code_generator_if,
2448 ia32_get_list_sched_selector,
2449 ia32_get_ilp_sched_selector,
2450 ia32_get_reg_class_alignment,
2451 ia32_get_libfirm_params,
2452 ia32_get_allowed_execution_units,
2456 ia32_parse_asm_constraint,
2457 ia32_is_valid_clobber
2460 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
2461 void be_init_arch_ia32(void)
2463 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2464 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2466 lc_opt_add_table(ia32_grp, ia32_options);
2467 be_register_isa_if("ia32", &ia32_isa_if);
2469 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2471 ia32_init_emitter();
2473 ia32_init_optimize();
2474 ia32_init_transform();
2476 ia32_init_architecture();