2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
55 #include "lower_calls.h"
56 #include "lower_mode_b.h"
57 #include "lower_softfloat.h"
67 #include "be_dbgout.h"
68 #include "beblocksched.h"
69 #include "bemachine.h"
70 #include "bespillutil.h"
71 #include "bespillslots.h"
76 #include "betranshlp.h"
77 #include "belistsched.h"
78 #include "beabihelper.h"
81 #include "bearch_ia32_t.h"
83 #include "ia32_new_nodes.h"
84 #include "gen_ia32_regalloc_if.h"
85 #include "gen_ia32_machine.h"
86 #include "ia32_common_transform.h"
87 #include "ia32_transform.h"
88 #include "ia32_emitter.h"
89 #include "ia32_optimize.h"
91 #include "ia32_dbg_stat.h"
92 #include "ia32_finish.h"
94 #include "ia32_architecture.h"
97 #include "ia32_pbqp_transform.h"
99 transformer_t be_transformer = TRANSFORMER_DEFAULT;
102 ir_mode *ia32_mode_fpcw;
103 ir_mode *ia32_mode_E;
104 ir_type *ia32_type_E;
106 /** The current omit-fp state */
107 static ir_type *omit_fp_between_type = NULL;
108 static ir_type *between_type = NULL;
109 static ir_entity *old_bp_ent = NULL;
110 static ir_entity *ret_addr_ent = NULL;
111 static ir_entity *omit_fp_ret_addr_ent = NULL;
114 * The environment for the intrinsic mapping.
116 static ia32_intrinsic_env_t intrinsic_env = {
118 NULL, /* the irg, these entities belong to */
119 NULL, /* entity for __divdi3 library call */
120 NULL, /* entity for __moddi3 library call */
121 NULL, /* entity for __udivdi3 library call */
122 NULL, /* entity for __umoddi3 library call */
126 typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
129 * Used to create per-graph unique pseudo nodes.
131 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
132 create_const_node_func func,
133 const arch_register_t* reg)
135 ir_node *block, *res;
140 block = get_irg_start_block(irg);
141 res = func(NULL, block);
142 arch_set_irn_register(res, reg);
148 /* Creates the unique per irg GP NoReg node. */
149 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
151 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
152 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
153 &ia32_registers[REG_GP_NOREG]);
156 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
158 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
159 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
160 &ia32_registers[REG_VFP_NOREG]);
163 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
165 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
166 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
167 &ia32_registers[REG_XMM_NOREG]);
170 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
172 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
173 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
174 &ia32_registers[REG_FPCW]);
179 * Returns the admissible noreg register node for input register pos of node irn.
181 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
183 ir_graph *irg = get_irn_irg(irn);
184 const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
186 assert(req != NULL && "Missing register requirements");
187 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
188 return ia32_new_NoReg_gp(irg);
190 if (ia32_cg_config.use_sse2) {
191 return ia32_new_NoReg_xmm(irg);
193 return ia32_new_NoReg_vfp(irg);
197 static arch_irn_class_t ia32_classify(const ir_node *irn)
199 arch_irn_class_t classification = arch_irn_class_none;
201 assert(is_ia32_irn(irn));
203 if (is_ia32_is_reload(irn))
204 classification |= arch_irn_class_reload;
206 if (is_ia32_is_spill(irn))
207 classification |= arch_irn_class_spill;
209 if (is_ia32_is_remat(irn))
210 classification |= arch_irn_class_remat;
212 return classification;
216 * The IA32 ABI callback object.
219 be_abi_call_flags_bits_t flags; /**< The call flags. */
220 ir_graph *irg; /**< The associated graph. */
223 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
225 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
228 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
230 if (is_be_node(node))
231 be_node_set_frame_entity(node, entity);
233 set_ia32_frame_ent(node, entity);
236 static void ia32_set_frame_offset(ir_node *irn, int bias)
238 if (get_ia32_frame_ent(irn) == NULL)
241 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
242 ir_graph *irg = get_irn_irg(irn);
243 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
244 if (layout->sp_relative) {
245 /* Pop nodes modify the stack pointer before calculating the
246 * destination address, so fix this here
251 add_ia32_am_offs_int(irn, bias);
254 static int ia32_get_sp_bias(const ir_node *node)
256 if (is_ia32_Call(node))
257 return -(int)get_ia32_call_attr_const(node)->pop;
259 if (is_ia32_Push(node))
262 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
265 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
266 return SP_BIAS_RESET;
273 * Build the between type and entities if not already build.
275 static void ia32_build_between_type(void)
277 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
278 if (! between_type) {
279 ir_type *old_bp_type = new_type_primitive(mode_Iu);
280 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
282 between_type = new_type_struct(IDENT("ia32_between_type"));
283 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
284 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
286 set_entity_offset(old_bp_ent, 0);
287 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
288 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
289 set_type_state(between_type, layout_fixed);
291 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
292 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
294 set_entity_offset(omit_fp_ret_addr_ent, 0);
295 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
296 set_type_state(omit_fp_between_type, layout_fixed);
302 * Produces the type which sits between the stack args and the locals on the stack.
303 * it will contain the return address and space to store the old base pointer.
304 * @return The Firm type modeling the ABI between type.
306 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
308 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
309 ia32_build_between_type();
310 return layout->sp_relative ? omit_fp_between_type : between_type;
314 * Return the stack entity that contains the return address.
316 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
318 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
319 ia32_build_between_type();
320 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
324 * Return the stack entity that contains the frame address.
326 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
328 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
329 ia32_build_between_type();
330 return layout->sp_relative ? NULL : old_bp_ent;
334 * Get the estimated cycle count for @p irn.
336 * @param self The this pointer.
337 * @param irn The node.
339 * @return The estimated cycle count for this operation
341 static int ia32_get_op_estimated_cost(const ir_node *irn)
344 ia32_op_type_t op_tp;
348 if (!is_ia32_irn(irn))
351 assert(is_ia32_irn(irn));
353 cost = get_ia32_latency(irn);
354 op_tp = get_ia32_op_type(irn);
356 if (is_ia32_CopyB(irn)) {
359 else if (is_ia32_CopyB_i(irn)) {
360 int size = get_ia32_copyb_size(irn);
361 cost = 20 + (int)ceil((4/3) * size);
363 /* in case of address mode operations add additional cycles */
364 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
366 In case of stack access and access to fixed addresses add 5 cycles
367 (we assume they are in cache), other memory operations cost 20
370 if (is_ia32_use_frame(irn) || (
371 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
372 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
384 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
386 * @param irn The original operation
387 * @param i Index of the argument we want the inverse operation to yield
388 * @param inverse struct to be filled with the resulting inverse op
389 * @param obstack The obstack to use for allocation of the returned nodes array
390 * @return The inverse operation or NULL if operation invertible
392 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
403 ir_node *block, *noreg, *nomem;
406 /* we cannot invert non-ia32 irns */
407 if (! is_ia32_irn(irn))
410 /* operand must always be a real operand (not base, index or mem) */
411 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
414 /* we don't invert address mode operations */
415 if (get_ia32_op_type(irn) != ia32_Normal)
418 /* TODO: adjust for new immediates... */
419 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
423 block = get_nodes_block(irn);
424 mode = get_irn_mode(irn);
425 irn_mode = get_irn_mode(irn);
426 noreg = get_irn_n(irn, 0);
427 nomem = get_irg_no_mem(irg);
428 dbgi = get_irn_dbg_info(irn);
430 /* initialize structure */
431 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
435 switch (get_ia32_irn_opcode(irn)) {
437 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
438 /* we have an add with a const here */
439 /* invers == add with negated const */
440 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
442 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
443 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
444 set_ia32_commutative(inverse->nodes[0]);
446 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
447 /* we have an add with a symconst here */
448 /* invers == sub with const */
449 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
451 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
454 /* normal add: inverse == sub */
455 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
460 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
461 /* we have a sub with a const/symconst here */
462 /* invers == add with this const */
463 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
464 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
465 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
469 if (i == n_ia32_binary_left) {
470 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
473 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
479 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
480 /* xor with const: inverse = xor */
481 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
482 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
483 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
487 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
492 inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
497 inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
502 /* inverse operation not supported */
510 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
512 if (mode_is_float(mode))
519 * Get the mode that should be used for spilling value node
521 static ir_mode *get_spill_mode(const ir_node *node)
523 ir_mode *mode = get_irn_mode(node);
524 return get_spill_mode_mode(mode);
528 * Checks whether an addressmode reload for a node with mode mode is compatible
529 * with a spillslot of mode spill_mode
531 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
533 return !mode_is_float(mode) || mode == spillmode;
537 * Check if irn can load its operand at position i from memory (source addressmode).
538 * @param irn The irn to be checked
539 * @param i The operands position
540 * @return Non-Zero if operand can be loaded
542 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
544 ir_node *op = get_irn_n(irn, i);
545 const ir_mode *mode = get_irn_mode(op);
546 const ir_mode *spillmode = get_spill_mode(op);
548 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
549 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
550 !ia32_is_spillmode_compatible(mode, spillmode) ||
551 is_ia32_use_frame(irn)) /* must not already use frame */
554 switch (get_ia32_am_support(irn)) {
559 if (i != n_ia32_unary_op)
565 case n_ia32_binary_left: {
566 const arch_register_req_t *req;
567 if (!is_ia32_commutative(irn))
570 /* we can't swap left/right for limited registers
571 * (As this (currently) breaks constraint handling copies)
573 req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
574 if (req->type & arch_register_req_type_limited)
579 case n_ia32_binary_right:
588 panic("Unknown AM type");
591 /* HACK: must not already use "real" memory.
592 * This can happen for Call and Div */
593 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
599 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
603 ir_mode *dest_op_mode;
605 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
607 set_ia32_op_type(irn, ia32_AddrModeS);
609 load_mode = get_irn_mode(get_irn_n(irn, i));
610 dest_op_mode = get_ia32_ls_mode(irn);
611 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
612 set_ia32_ls_mode(irn, load_mode);
614 set_ia32_use_frame(irn);
615 set_ia32_need_stackent(irn);
617 if (i == n_ia32_binary_left &&
618 get_ia32_am_support(irn) == ia32_am_binary &&
619 /* immediates are only allowed on the right side */
620 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
621 ia32_swap_left_right(irn);
622 i = n_ia32_binary_right;
625 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
627 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
628 set_irn_n(irn, n_ia32_mem, spill);
629 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
630 set_ia32_is_reload(irn);
633 static const be_abi_callbacks_t ia32_abi_callbacks = {
634 ia32_abi_get_between_type,
637 /* register allocator interface */
638 static const arch_irn_ops_t ia32_irn_ops = {
640 ia32_get_frame_entity,
641 ia32_set_frame_offset,
644 ia32_get_op_estimated_cost,
645 ia32_possible_memory_operand,
646 ia32_perform_memory_operand,
649 static ir_entity *mcount = NULL;
650 static int gprof = 0;
652 static void ia32_before_abi(ir_graph *irg)
655 if (mcount == NULL) {
656 ir_type *tp = new_type_method(0, 0);
657 ident *id = new_id_from_str("mcount");
658 mcount = new_entity(get_glob_type(), id, tp);
659 /* FIXME: enter the right ld_ident here */
660 set_entity_ld_ident(mcount, get_entity_ident(mcount));
661 set_entity_visibility(mcount, ir_visibility_external);
663 instrument_initcall(irg, mcount);
668 * Transforms the standard firm graph into
671 static void ia32_prepare_graph(ir_graph *irg)
673 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
676 switch (be_transformer) {
677 case TRANSFORMER_DEFAULT:
678 /* transform remaining nodes into assembler instructions */
679 ia32_transform_graph(irg);
682 case TRANSFORMER_PBQP:
683 case TRANSFORMER_RAND:
684 /* transform nodes into assembler instructions by PBQP magic */
685 ia32_transform_graph_by_pbqp(irg);
689 panic("invalid transformer");
692 ia32_transform_graph(irg);
695 /* do local optimizations (mainly CSE) */
696 optimize_graph_df(irg);
697 /* backend code expects that outedges are always enabled */
701 dump_ir_graph(irg, "transformed");
703 /* optimize address mode */
704 ia32_optimize_graph(irg);
706 /* do code placement, to optimize the position of constants */
708 /* backend code expects that outedges are always enabled */
712 dump_ir_graph(irg, "place");
715 ir_node *ia32_turn_back_am(ir_node *node)
717 dbg_info *dbgi = get_irn_dbg_info(node);
718 ir_graph *irg = get_irn_irg(node);
719 ir_node *block = get_nodes_block(node);
720 ir_node *base = get_irn_n(node, n_ia32_base);
721 ir_node *idx = get_irn_n(node, n_ia32_index);
722 ir_node *mem = get_irn_n(node, n_ia32_mem);
725 ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
726 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
728 ia32_copy_am_attrs(load, node);
729 if (is_ia32_is_reload(node))
730 set_ia32_is_reload(load);
731 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
733 switch (get_ia32_am_support(node)) {
735 set_irn_n(node, n_ia32_unary_op, load_res);
739 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
740 set_irn_n(node, n_ia32_binary_left, load_res);
742 set_irn_n(node, n_ia32_binary_right, load_res);
747 panic("Unknown AM type");
749 noreg = ia32_new_NoReg_gp(current_ir_graph);
750 set_irn_n(node, n_ia32_base, noreg);
751 set_irn_n(node, n_ia32_index, noreg);
752 set_ia32_am_offs_int(node, 0);
753 set_ia32_am_sc(node, NULL);
754 set_ia32_am_scale(node, 0);
755 clear_ia32_am_sc_sign(node);
757 /* rewire mem-proj */
758 if (get_irn_mode(node) == mode_T) {
759 const ir_edge_t *edge;
760 foreach_out_edge(node, edge) {
761 ir_node *out = get_edge_src_irn(edge);
762 if (get_irn_mode(out) == mode_M) {
763 set_Proj_pred(out, load);
764 set_Proj_proj(out, pn_ia32_Load_M);
770 set_ia32_op_type(node, ia32_Normal);
771 if (sched_is_scheduled(node))
772 sched_add_before(node, load);
777 static ir_node *flags_remat(ir_node *node, ir_node *after)
779 /* we should turn back source address mode when rematerializing nodes */
784 if (is_Block(after)) {
787 block = get_nodes_block(after);
790 type = get_ia32_op_type(node);
793 ia32_turn_back_am(node);
797 /* TODO implement this later... */
798 panic("found DestAM with flag user %+F this should not happen", node);
800 default: assert(type == ia32_Normal); break;
803 copy = exact_copy(node);
804 set_nodes_block(copy, block);
805 sched_add_after(after, copy);
811 * Called before the register allocator.
813 static void ia32_before_ra(ir_graph *irg)
815 /* setup fpu rounding modes */
816 ia32_setup_fpu_mode(irg);
819 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
822 be_add_missing_keeps(irg);
827 * Transforms a be_Reload into a ia32 Load.
829 static void transform_to_Load(ir_node *node)
831 ir_graph *irg = get_irn_irg(node);
832 dbg_info *dbgi = get_irn_dbg_info(node);
833 ir_node *block = get_nodes_block(node);
834 ir_entity *ent = be_get_frame_entity(node);
835 ir_mode *mode = get_irn_mode(node);
836 ir_mode *spillmode = get_spill_mode(node);
837 ir_node *noreg = ia32_new_NoReg_gp(irg);
838 ir_node *sched_point = NULL;
839 ir_node *ptr = get_irg_frame(irg);
840 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
841 ir_node *new_op, *proj;
842 const arch_register_t *reg;
844 if (sched_is_scheduled(node)) {
845 sched_point = sched_prev(node);
848 if (mode_is_float(spillmode)) {
849 if (ia32_cg_config.use_sse2)
850 new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
852 new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
854 else if (get_mode_size_bits(spillmode) == 128) {
855 /* Reload 128 bit SSE registers */
856 new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
859 new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
861 set_ia32_op_type(new_op, ia32_AddrModeS);
862 set_ia32_ls_mode(new_op, spillmode);
863 set_ia32_frame_ent(new_op, ent);
864 set_ia32_use_frame(new_op);
865 set_ia32_is_reload(new_op);
867 DBG_OPT_RELOAD2LD(node, new_op);
869 proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
872 sched_add_after(sched_point, new_op);
876 /* copy the register from the old node to the new Load */
877 reg = arch_get_irn_register(node);
878 arch_set_irn_register(proj, reg);
880 SET_IA32_ORIG_NODE(new_op, node);
882 exchange(node, proj);
886 * Transforms a be_Spill node into a ia32 Store.
888 static void transform_to_Store(ir_node *node)
890 ir_graph *irg = get_irn_irg(node);
891 dbg_info *dbgi = get_irn_dbg_info(node);
892 ir_node *block = get_nodes_block(node);
893 ir_entity *ent = be_get_frame_entity(node);
894 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
895 ir_mode *mode = get_spill_mode(spillval);
896 ir_node *noreg = ia32_new_NoReg_gp(irg);
897 ir_node *nomem = get_irg_no_mem(irg);
898 ir_node *ptr = get_irg_frame(irg);
899 ir_node *val = get_irn_n(node, n_be_Spill_val);
902 ir_node *sched_point = NULL;
904 if (sched_is_scheduled(node)) {
905 sched_point = sched_prev(node);
908 if (mode_is_float(mode)) {
909 if (ia32_cg_config.use_sse2) {
910 store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
911 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
913 store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
914 res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
916 } else if (get_mode_size_bits(mode) == 128) {
917 /* Spill 128 bit SSE registers */
918 store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
919 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
920 } else if (get_mode_size_bits(mode) == 8) {
921 store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
922 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
924 store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
925 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
928 set_ia32_op_type(store, ia32_AddrModeD);
929 set_ia32_ls_mode(store, mode);
930 set_ia32_frame_ent(store, ent);
931 set_ia32_use_frame(store);
932 set_ia32_is_spill(store);
933 SET_IA32_ORIG_NODE(store, node);
934 DBG_OPT_SPILL2ST(node, store);
937 sched_add_after(sched_point, store);
944 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
946 dbg_info *dbgi = get_irn_dbg_info(node);
947 ir_node *block = get_nodes_block(node);
948 ir_graph *irg = get_irn_irg(node);
949 ir_node *noreg = ia32_new_NoReg_gp(irg);
950 ir_node *frame = get_irg_frame(irg);
952 ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
954 set_ia32_frame_ent(push, ent);
955 set_ia32_use_frame(push);
956 set_ia32_op_type(push, ia32_AddrModeS);
957 set_ia32_ls_mode(push, mode_Is);
958 set_ia32_is_spill(push);
960 sched_add_before(schedpoint, push);
964 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
966 dbg_info *dbgi = get_irn_dbg_info(node);
967 ir_node *block = get_nodes_block(node);
968 ir_graph *irg = get_irn_irg(node);
969 ir_node *noreg = ia32_new_NoReg_gp(irg);
970 ir_node *frame = get_irg_frame(irg);
972 ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
973 get_irg_no_mem(irg), sp);
975 set_ia32_frame_ent(pop, ent);
976 set_ia32_use_frame(pop);
977 set_ia32_op_type(pop, ia32_AddrModeD);
978 set_ia32_ls_mode(pop, mode_Is);
979 set_ia32_is_reload(pop);
981 sched_add_before(schedpoint, pop);
986 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
988 dbg_info *dbgi = get_irn_dbg_info(node);
989 ir_mode *spmode = mode_Iu;
990 const arch_register_t *spreg = &ia32_registers[REG_ESP];
993 sp = new_rd_Proj(dbgi, pred, spmode, pos);
994 arch_set_irn_register(sp, spreg);
1000 * Transform MemPerm, currently we do this the ugly way and produce
1001 * push/pop into/from memory cascades. This is possible without using
1004 static void transform_MemPerm(ir_node *node)
1006 ir_node *block = get_nodes_block(node);
1007 ir_graph *irg = get_irn_irg(node);
1008 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
1009 int arity = be_get_MemPerm_entity_arity(node);
1010 ir_node **pops = ALLOCAN(ir_node*, arity);
1014 const ir_edge_t *edge;
1015 const ir_edge_t *next;
1018 for (i = 0; i < arity; ++i) {
1019 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1020 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1021 ir_type *enttype = get_entity_type(inent);
1022 unsigned entsize = get_type_size_bytes(enttype);
1023 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1024 ir_node *mem = get_irn_n(node, i + 1);
1027 /* work around cases where entities have different sizes */
1028 if (entsize2 < entsize)
1030 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1032 push = create_push(node, node, sp, mem, inent);
1033 sp = create_spproj(node, push, pn_ia32_Push_stack);
1035 /* add another push after the first one */
1036 push = create_push(node, node, sp, mem, inent);
1037 add_ia32_am_offs_int(push, 4);
1038 sp = create_spproj(node, push, pn_ia32_Push_stack);
1041 set_irn_n(node, i, new_r_Bad(irg, mode_X));
1045 for (i = arity - 1; i >= 0; --i) {
1046 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1047 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1048 ir_type *enttype = get_entity_type(outent);
1049 unsigned entsize = get_type_size_bytes(enttype);
1050 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1053 /* work around cases where entities have different sizes */
1054 if (entsize2 < entsize)
1056 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1058 pop = create_pop(node, node, sp, outent);
1059 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1061 add_ia32_am_offs_int(pop, 4);
1063 /* add another pop after the first one */
1064 pop = create_pop(node, node, sp, outent);
1065 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1072 keep = be_new_Keep(block, 1, in);
1073 sched_add_before(node, keep);
1075 /* exchange memprojs */
1076 foreach_out_edge_safe(node, edge, next) {
1077 ir_node *proj = get_edge_src_irn(edge);
1078 int p = get_Proj_proj(proj);
1082 set_Proj_pred(proj, pops[p]);
1083 set_Proj_proj(proj, pn_ia32_Pop_M);
1086 /* remove memperm */
1092 * Block-Walker: Calls the transform functions Spill and Reload.
1094 static void ia32_after_ra_walker(ir_node *block, void *env)
1096 ir_node *node, *prev;
1099 /* beware: the schedule is changed here */
1100 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1101 prev = sched_prev(node);
1103 if (be_is_Reload(node)) {
1104 transform_to_Load(node);
1105 } else if (be_is_Spill(node)) {
1106 transform_to_Store(node);
1107 } else if (be_is_MemPerm(node)) {
1108 transform_MemPerm(node);
1114 * Collects nodes that need frame entities assigned.
1116 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1118 be_fec_env_t *env = (be_fec_env_t*)data;
1119 const ir_mode *mode;
1122 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1123 mode = get_spill_mode_mode(get_irn_mode(node));
1124 align = get_mode_size_bytes(mode);
1125 } else if (is_ia32_irn(node) &&
1126 get_ia32_frame_ent(node) == NULL &&
1127 is_ia32_use_frame(node)) {
1128 if (is_ia32_need_stackent(node))
1131 switch (get_ia32_irn_opcode(node)) {
1133 case iro_ia32_Load: {
1134 const ia32_attr_t *attr = get_ia32_attr_const(node);
1136 if (attr->data.need_32bit_stackent) {
1138 } else if (attr->data.need_64bit_stackent) {
1141 mode = get_ia32_ls_mode(node);
1142 if (is_ia32_is_reload(node))
1143 mode = get_spill_mode_mode(mode);
1145 align = get_mode_size_bytes(mode);
1149 case iro_ia32_vfild:
1151 case iro_ia32_xLoad: {
1152 mode = get_ia32_ls_mode(node);
1157 case iro_ia32_FldCW: {
1158 /* although 2 byte would be enough 4 byte performs best */
1166 panic("unexpected frame user while collection frame entity nodes");
1168 case iro_ia32_FnstCW:
1169 case iro_ia32_Store8Bit:
1170 case iro_ia32_Store:
1173 case iro_ia32_vfist:
1174 case iro_ia32_vfisttp:
1176 case iro_ia32_xStore:
1177 case iro_ia32_xStoreSimple:
1184 be_node_needs_frame_entity(env, node, mode, align);
1187 static int determine_ebp_input(ir_node *ret)
1189 const arch_register_t *bp = &ia32_registers[REG_EBP];
1190 int arity = get_irn_arity(ret);
1193 for (i = 0; i < arity; ++i) {
1194 ir_node *input = get_irn_n(ret, i);
1195 if (arch_get_irn_register(input) == bp)
1198 panic("no ebp input found at %+F", ret);
1201 static void introduce_epilog(ir_node *ret)
1203 const arch_register_t *sp = &ia32_registers[REG_ESP];
1204 const arch_register_t *bp = &ia32_registers[REG_EBP];
1205 ir_graph *irg = get_irn_irg(ret);
1206 ir_type *frame_type = get_irg_frame_type(irg);
1207 unsigned frame_size = get_type_size_bytes(frame_type);
1208 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1209 ir_node *block = get_nodes_block(ret);
1210 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1211 ir_node *curr_sp = first_sp;
1212 ir_mode *mode_gp = mode_Iu;
1214 if (!layout->sp_relative) {
1215 int n_ebp = determine_ebp_input(ret);
1216 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1217 if (ia32_cg_config.use_leave) {
1218 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1219 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1220 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1221 arch_set_irn_register(curr_bp, bp);
1222 arch_set_irn_register(curr_sp, sp);
1223 sched_add_before(ret, leave);
1226 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1227 /* copy ebp to esp */
1228 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1229 arch_set_irn_register(curr_sp, sp);
1230 sched_add_before(ret, curr_sp);
1233 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1234 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1235 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1236 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1237 arch_set_irn_register(curr_bp, bp);
1238 arch_set_irn_register(curr_sp, sp);
1239 sched_add_before(ret, pop);
1241 set_irn_n(ret, n_be_Return_mem, curr_mem);
1243 set_irn_n(ret, n_ebp, curr_bp);
1245 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1246 sched_add_before(ret, incsp);
1249 set_irn_n(ret, n_be_Return_sp, curr_sp);
1251 /* keep verifier happy... */
1252 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1253 kill_node(first_sp);
1258 * put the Prolog code at the beginning, epilog code before each return
1260 static void introduce_prolog_epilog(ir_graph *irg)
1262 const arch_register_t *sp = &ia32_registers[REG_ESP];
1263 const arch_register_t *bp = &ia32_registers[REG_EBP];
1264 ir_node *start = get_irg_start(irg);
1265 ir_node *block = get_nodes_block(start);
1266 ir_type *frame_type = get_irg_frame_type(irg);
1267 unsigned frame_size = get_type_size_bytes(frame_type);
1268 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1269 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1270 ir_node *curr_sp = initial_sp;
1271 ir_mode *mode_gp = mode_Iu;
1273 if (!layout->sp_relative) {
1275 ir_node *mem = get_irg_initial_mem(irg);
1276 ir_node *noreg = ia32_new_NoReg_gp(irg);
1277 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1278 ir_node *curr_bp = initial_bp;
1279 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
1282 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1283 mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
1284 arch_set_irn_register(curr_sp, sp);
1285 sched_add_after(start, push);
1287 /* move esp to ebp */
1288 curr_bp = be_new_Copy(block, curr_sp);
1289 sched_add_after(push, curr_bp);
1290 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1291 curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
1292 sched_add_after(curr_bp, curr_sp);
1293 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1294 edges_reroute(initial_bp, curr_bp);
1295 set_irn_n(push, n_ia32_Push_val, initial_bp);
1297 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1298 edges_reroute(initial_sp, incsp);
1299 set_irn_n(push, n_ia32_Push_stack, initial_sp);
1300 sched_add_after(curr_sp, incsp);
1302 /* make sure the initial IncSP is really used by someone */
1303 if (get_irn_n_edges(incsp) <= 1) {
1304 ir_node *in[] = { incsp };
1305 ir_node *keep = be_new_Keep(block, 1, in);
1306 sched_add_after(incsp, keep);
1309 layout->initial_bias = -4;
1311 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1312 edges_reroute(initial_sp, incsp);
1313 be_set_IncSP_pred(incsp, curr_sp);
1314 sched_add_after(start, incsp);
1317 /* introduce epilog for every return node */
1319 ir_node *end_block = get_irg_end_block(irg);
1320 int arity = get_irn_arity(end_block);
1323 for (i = 0; i < arity; ++i) {
1324 ir_node *ret = get_irn_n(end_block, i);
1325 assert(be_is_Return(ret));
1326 introduce_epilog(ret);
1332 * Last touchups for the graph before emit: x87 simulation to replace the
1333 * virtual with real x87 instructions, creating a block schedule and peephole
1336 static void ia32_finish(ir_graph *irg)
1338 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1339 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1340 bool at_begin = stack_layout->sp_relative ? true : false;
1341 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1343 /* create and coalesce frame entities */
1344 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1345 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1346 be_free_frame_entity_coalescer(fec_env);
1348 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1350 introduce_prolog_epilog(irg);
1352 /* fix stack entity offsets */
1353 be_abi_fix_stack_nodes(irg);
1354 be_abi_fix_stack_bias(irg);
1356 /* fix 2-address code constraints */
1357 ia32_finish_irg(irg);
1359 /* we might have to rewrite x87 virtual registers */
1360 if (irg_data->do_x87_sim) {
1361 ia32_x87_simulate_graph(irg);
1364 /* do peephole optimisations */
1365 ia32_peephole_optimization(irg);
1367 be_remove_dead_nodes_from_schedule(irg);
1369 /* create block schedule, this also removes empty blocks which might
1370 * produce critical edges */
1371 irg_data->blk_sched = be_create_block_schedule(irg);
1375 * Emits the code, closes the output file and frees
1376 * the code generator interface.
1378 static void ia32_emit(ir_graph *irg)
1380 if (ia32_cg_config.emit_machcode) {
1381 ia32_gen_binary_routine(irg);
1383 ia32_gen_routine(irg);
1388 * Returns the node representing the PIC base.
1390 static ir_node *ia32_get_pic_base(ir_graph *irg)
1392 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1394 ir_node *get_eip = irg_data->get_eip;
1395 if (get_eip != NULL)
1398 block = get_irg_start_block(irg);
1399 get_eip = new_bd_ia32_GetEIP(NULL, block);
1400 irg_data->get_eip = get_eip;
1406 * Initializes a IA32 code generator.
1408 static void ia32_init_graph(ir_graph *irg)
1410 struct obstack *obst = be_get_be_obst(irg);
1411 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1413 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1416 /* Linux gprof implementation needs base pointer */
1417 be_get_irg_options(irg)->omit_fp = 0;
1420 be_birg_from_irg(irg)->isa_link = irg_data;
1425 * Set output modes for GCC
1427 static const tarval_mode_info mo_integer = {
1434 * set the tarval output mode of all integer modes to decimal
1436 static void set_tarval_output_modes(void)
1440 for (i = get_irp_n_modes(); i > 0;) {
1441 ir_mode *mode = get_irp_mode(--i);
1443 if (mode_is_int(mode))
1444 set_tarval_mode_output_option(mode, &mo_integer);
1448 extern const arch_isa_if_t ia32_isa_if;
1451 * The template that generates a new ISA object.
1452 * Note that this template can be changed by command line
1455 static ia32_isa_t ia32_isa_template = {
1457 &ia32_isa_if, /* isa interface implementation */
1462 &ia32_registers[REG_ESP], /* stack pointer register */
1463 &ia32_registers[REG_EBP], /* base pointer register */
1464 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1465 2, /* power of two stack alignment, 2^2 == 4 */
1466 NULL, /* main environment */
1467 7, /* costs for a spill instruction */
1468 5, /* costs for a reload instruction */
1469 false, /* no custom abi handling */
1472 NULL, /* abstract machine */
1473 IA32_FPU_ARCH_X87, /* FPU architecture */
1476 static void init_asm_constraints(void)
1478 be_init_default_asm_constraint_flags();
1480 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1481 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1482 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1483 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1484 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1485 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1486 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1487 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1488 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1489 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1490 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1491 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1492 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1493 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1494 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1495 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1496 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1497 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1498 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1499 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1501 /* no support for autodecrement/autoincrement */
1502 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1503 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1504 /* no float consts */
1505 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1506 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1507 /* makes no sense on x86 */
1508 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1509 /* no support for sse consts yet */
1510 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1511 /* no support for x87 consts yet */
1512 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1513 /* no support for mmx registers yet */
1514 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1515 /* not available in 32bit mode */
1516 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1517 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1519 /* no code yet to determine register class needed... */
1520 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1524 * Initializes the backend ISA.
1526 static arch_env_t *ia32_init(const be_main_env_t *env)
1528 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1530 set_tarval_output_modes();
1532 *isa = ia32_isa_template;
1534 if (ia32_mode_fpcw == NULL) {
1535 ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0);
1538 ia32_register_init();
1539 ia32_create_opcodes(&ia32_irn_ops);
1541 isa->tv_ent = pmap_create();
1542 isa->cpu = ia32_init_machine_description();
1544 /* enter the ISA object into the intrinsic environment */
1545 intrinsic_env.isa = isa;
1547 be_emit_init(env->file_handle);
1548 be_gas_begin_compilation_unit(env);
1554 * Closes the output file and frees the ISA structure.
1556 static void ia32_done(void *self)
1558 ia32_isa_t *isa = (ia32_isa_t*)self;
1560 /* emit now all global declarations */
1561 be_gas_end_compilation_unit(isa->base.main_env);
1565 pmap_destroy(isa->tv_ent);
1571 * Get the register class which shall be used to store a value of a given mode.
1572 * @param self The this pointer.
1573 * @param mode The mode in question.
1574 * @return A register class which can hold values of the given mode.
1576 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1578 if (mode_is_float(mode)) {
1579 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1582 return &ia32_reg_classes[CLASS_ia32_gp];
1586 * Returns the register for parameter nr.
1588 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1589 const ir_mode *mode)
1591 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1592 &ia32_registers[REG_ECX],
1593 &ia32_registers[REG_EDX],
1596 static const unsigned MAXNUM_GPREG_ARGS = 3;
1598 static const arch_register_t *gpreg_param_reg_regparam[] = {
1599 &ia32_registers[REG_EAX],
1600 &ia32_registers[REG_EDX],
1601 &ia32_registers[REG_ECX]
1604 static const arch_register_t *gpreg_param_reg_this[] = {
1605 &ia32_registers[REG_ECX],
1610 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1611 &ia32_registers[REG_XMM0],
1612 &ia32_registers[REG_XMM1],
1613 &ia32_registers[REG_XMM2],
1614 &ia32_registers[REG_XMM3],
1615 &ia32_registers[REG_XMM4],
1616 &ia32_registers[REG_XMM5],
1617 &ia32_registers[REG_XMM6],
1618 &ia32_registers[REG_XMM7]
1621 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1622 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1624 static const unsigned MAXNUM_SSE_ARGS = 8;
1626 if ((cc & cc_this_call) && nr == 0)
1627 return gpreg_param_reg_this[0];
1629 if (! (cc & cc_reg_param))
1632 if (mode_is_float(mode)) {
1633 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1635 if (nr >= MAXNUM_SSE_ARGS)
1638 if (cc & cc_this_call) {
1639 return fpreg_sse_param_reg_this[nr];
1641 return fpreg_sse_param_reg_std[nr];
1642 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1643 unsigned num_regparam;
1645 if (get_mode_size_bits(mode) > 32)
1648 if (nr >= MAXNUM_GPREG_ARGS)
1651 if (cc & cc_this_call) {
1652 return gpreg_param_reg_this[nr];
1654 num_regparam = cc & ~cc_bits;
1655 if (num_regparam == 0) {
1656 /* default fastcall */
1657 return gpreg_param_reg_fastcall[nr];
1659 if (nr < num_regparam)
1660 return gpreg_param_reg_regparam[nr];
1664 panic("unknown argument mode");
1668 * Get the ABI restrictions for procedure calls.
1669 * @param self The this pointer.
1670 * @param method_type The type of the method (procedure) in question.
1671 * @param abi The abi object to be modified
1673 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1679 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1683 /* set abi flags for calls */
1684 call_flags.bits.store_args_sequential = 0;
1685 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1686 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1687 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1689 /* set parameter passing style */
1690 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1692 cc = get_method_calling_convention(method_type);
1693 if (get_method_variadicity(method_type) == variadicity_variadic) {
1694 /* pass all parameters of a variadic function on the stack */
1695 cc = cc_cdecl_set | (cc & cc_this_call);
1697 if (get_method_additional_properties(method_type) & mtp_property_private &&
1698 ia32_cg_config.optimize_cc) {
1699 /* set the fast calling conventions (allowing up to 3) */
1700 cc = SET_FASTCALL(cc) | 3;
1704 /* we have to pop the shadow parameter ourself for compound calls */
1705 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1706 && !(cc & cc_reg_param)) {
1707 pop_amount += get_mode_size_bytes(mode_P_data);
1710 n = get_method_n_params(method_type);
1711 for (i = regnum = 0; i < n; i++) {
1712 const arch_register_t *reg = NULL;
1713 ir_type *tp = get_method_param_type(method_type, i);
1714 ir_mode *mode = get_type_mode(tp);
1717 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1720 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1723 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1724 * movl has a shorter opcode than mov[sz][bw]l */
1725 ir_mode *load_mode = mode;
1728 unsigned size = get_mode_size_bytes(mode);
1730 if (cc & cc_callee_clear_stk) {
1731 pop_amount += (size + 3U) & ~3U;
1734 if (size < 4) load_mode = mode_Iu;
1737 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1741 be_abi_call_set_pop(abi, pop_amount);
1743 /* set return registers */
1744 n = get_method_n_ress(method_type);
1746 assert(n <= 2 && "more than two results not supported");
1748 /* In case of 64bit returns, we will have two 32bit values */
1750 ir_type *tp = get_method_res_type(method_type, 0);
1751 ir_mode *mode = get_type_mode(tp);
1753 assert(!mode_is_float(mode) && "two FP results not supported");
1755 tp = get_method_res_type(method_type, 1);
1756 mode = get_type_mode(tp);
1758 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1760 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1761 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1764 ir_type *tp = get_method_res_type(method_type, 0);
1765 ir_mode *mode = get_type_mode(tp);
1766 const arch_register_t *reg;
1767 assert(is_atomic_type(tp));
1769 reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
1771 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1776 * Returns the necessary byte alignment for storing a register of given class.
1778 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1780 ir_mode *mode = arch_register_class_mode(cls);
1781 int bytes = get_mode_size_bytes(mode);
1783 if (mode_is_float(mode) && bytes > 8)
1789 * Return irp irgs in the desired order.
1791 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1798 static void ia32_mark_remat(ir_node *node)
1800 if (is_ia32_irn(node)) {
1801 set_ia32_is_remat(node);
1806 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1808 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1813 ir_relation relation;
1818 cmp_l = get_Cmp_left(sel);
1819 cmp_r = get_Cmp_right(sel);
1820 if (!mode_is_float(get_irn_mode(cmp_l)))
1823 /* check for min/max. They're defined as (C-Semantik):
1824 * min(a, b) = a < b ? a : b
1825 * or min(a, b) = a <= b ? a : b
1826 * max(a, b) = a > b ? a : b
1827 * or max(a, b) = a >= b ? a : b
1828 * (Note we only handle float min/max here)
1830 relation = get_Cmp_relation(sel);
1832 case ir_relation_greater_equal:
1833 case ir_relation_greater:
1835 if (cmp_l == mux_true && cmp_r == mux_false)
1838 case ir_relation_less_equal:
1839 case ir_relation_less:
1841 if (cmp_l == mux_true && cmp_r == mux_false)
1844 case ir_relation_unordered_greater_equal:
1845 case ir_relation_unordered_greater:
1847 if (cmp_l == mux_false && cmp_r == mux_true)
1850 case ir_relation_unordered_less_equal:
1851 case ir_relation_unordered_less:
1853 if (cmp_l == mux_false && cmp_r == mux_true)
1864 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1866 ir_mode *mode = get_irn_mode(mux_true);
1869 if (!mode_is_int(mode) && !mode_is_reference(mode)
1873 if (is_Const(mux_true) && is_Const(mux_false)) {
1874 /* we can create a set plus up two 3 instructions for any combination
1882 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1887 if (!mode_is_float(get_irn_mode(mux_true)))
1890 return is_Const(mux_true) && is_Const(mux_false);
1893 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1900 ir_relation relation;
1905 mode = get_irn_mode(mux_true);
1906 if (mode_is_signed(mode) || mode_is_float(mode))
1909 relation = get_Cmp_relation(sel);
1910 cmp_left = get_Cmp_left(sel);
1911 cmp_right = get_Cmp_right(sel);
1913 /* "move" zero constant to false input */
1914 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1915 ir_node *tmp = mux_false;
1916 mux_false = mux_true;
1918 relation = get_negated_relation(relation);
1920 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1922 if (!is_Sub(mux_true))
1924 sub_left = get_Sub_left(mux_true);
1925 sub_right = get_Sub_right(mux_true);
1927 /* Mux(a >=u b, 0, a-b) */
1928 if ((relation & ir_relation_greater)
1929 && sub_left == cmp_left && sub_right == cmp_right)
1931 /* Mux(a <=u b, 0, b-a) */
1932 if ((relation & ir_relation_less)
1933 && sub_left == cmp_right && sub_right == cmp_left)
1939 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1944 /* middleend can handle some things */
1945 if (ir_is_optimizable_mux(sel, mux_false, mux_true))
1947 /* we can handle Set for all modes and compares */
1948 if (mux_is_set(sel, mux_true, mux_false))
1950 /* SSE has own min/max operations */
1951 if (ia32_cg_config.use_sse2
1952 && mux_is_float_min_max(sel, mux_true, mux_false))
1954 /* we can handle Mux(?, Const[f], Const[f]) */
1955 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1956 #ifdef FIRM_GRGEN_BE
1957 /* well, some code selectors can't handle it */
1958 if (be_transformer != TRANSFORMER_PBQP
1959 || be_transformer != TRANSFORMER_RAND)
1966 /* no support for 64bit inputs to cmov */
1967 mode = get_irn_mode(mux_true);
1968 if (get_mode_size_bits(mode) > 32)
1970 /* we can handle Abs for all modes and compares (except 64bit) */
1971 if (ir_mux_is_abs(sel, mux_false, mux_true) != 0)
1973 /* we can't handle MuxF yet */
1974 if (mode_is_float(mode))
1977 if (mux_is_doz(sel, mux_true, mux_false))
1980 /* Check Cmp before the node */
1982 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1984 /* we can't handle 64bit compares */
1985 if (get_mode_size_bits(cmp_mode) > 32)
1988 /* we can't handle float compares */
1989 if (mode_is_float(cmp_mode))
1993 /* did we disable cmov generation? */
1994 if (!ia32_cg_config.use_cmov)
1997 /* we can use a cmov */
2001 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2005 /* we already added all our simple flags to the flags modifier list in
2006 * init, so this flag we don't know. */
2007 return ASM_CONSTRAINT_FLAG_INVALID;
2010 static int ia32_is_valid_clobber(const char *clobber)
2012 return ia32_get_clobber_register(clobber) != NULL;
2015 static void ia32_lower_for_target(void)
2017 size_t i, n_irgs = get_irp_n_irgs();
2019 /* perform doubleword lowering */
2020 lwrdw_param_t lower_dw_params = {
2021 1, /* little endian */
2022 64, /* doubleword size */
2023 ia32_create_intrinsic_fkt,
2027 ia32_create_opcodes(&ia32_irn_ops);
2029 /* lower compound param handling
2030 * Note: we lower compound arguments ourself, since on ia32 we don't
2031 * have hidden parameters but know where to find the structs on the stack.
2032 * (This also forces us to always allocate space for the compound arguments
2033 * on the callframe and we can't just use an arbitrary position on the
2036 lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS);
2038 /* replace floating point operations by function calls */
2039 if (ia32_cg_config.use_softfloat) {
2040 lower_floating_point();
2043 ir_prepare_dw_lowering(&lower_dw_params);
2046 for (i = 0; i < n_irgs; ++i) {
2047 ir_graph *irg = get_irp_irg(i);
2048 /* lower for mode_b stuff */
2049 ir_lower_mode_b(irg, mode_Iu);
2050 /* break up switches with wide ranges */
2051 lower_switch(irg, 4, 256, false);
2054 for (i = 0; i < n_irgs; ++i) {
2055 ir_graph *irg = get_irp_irg(i);
2056 /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
2057 * so we can generate rep movs later, and turn all big CopyBs into
2059 lower_CopyB(irg, 64, 8193, true);
2064 * Create the trampoline code.
2066 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2068 ir_graph *const irg = get_irn_irg(block);
2069 ir_node * p = trampoline;
2070 ir_mode *const mode = get_irn_mode(p);
2071 ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
2072 ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
2076 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
2077 mem = new_r_Proj(st, mode_M, pn_Store_M);
2078 p = new_r_Add(block, p, one, mode);
2079 st = new_r_Store(block, mem, p, env, cons_none);
2080 mem = new_r_Proj(st, mode_M, pn_Store_M);
2081 p = new_r_Add(block, p, four, mode);
2083 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
2084 mem = new_r_Proj(st, mode_M, pn_Store_M);
2085 p = new_r_Add(block, p, one, mode);
2086 st = new_r_Store(block, mem, p, callee, cons_none);
2087 mem = new_r_Proj(st, mode_M, pn_Store_M);
2088 p = new_r_Add(block, p, four, mode);
2094 * Returns the libFirm configuration parameter for this backend.
2096 static const backend_params *ia32_get_libfirm_params(void)
2098 static const ir_settings_arch_dep_t ad = {
2099 1, /* also use subs */
2100 4, /* maximum shifts */
2101 63, /* maximum shift amount */
2102 ia32_evaluate_insn, /* evaluate the instruction sequence */
2104 1, /* allow Mulhs */
2105 1, /* allow Mulus */
2106 32, /* Mulh allowed up to 32 bit */
2108 static backend_params p = {
2109 1, /* support inline assembly */
2110 1, /* support Rotl nodes */
2111 0, /* little endian */
2112 1, /* modulo shift efficient */
2113 0, /* non-modulo shift not efficient */
2114 &ad, /* will be set later */
2115 ia32_is_mux_allowed,
2116 32, /* machine_size */
2117 NULL, /* float arithmetic mode, will be set below */
2118 NULL, /* long long type */
2119 NULL, /* unsigned long long type */
2120 NULL, /* long double type */
2121 12, /* size of trampoline code */
2122 4, /* alignment of trampoline code */
2123 ia32_create_trampoline_fkt,
2124 4 /* alignment of stack parameter */
2127 if (ia32_mode_E == NULL) {
2128 /* note mantissa is 64bit but with explicitely encoded 1 so the really
2129 * usable part as counted by firm is only 63 bits */
2130 ia32_mode_E = new_float_mode("E", irma_x86_extended_float, 15, 63);
2131 ia32_type_E = new_type_primitive(ia32_mode_E);
2132 set_type_size_bytes(ia32_type_E, 12);
2133 set_type_alignment_bytes(ia32_type_E, 16);
2136 ir_mode *mode_long_long
2137 = new_int_mode("long long", irma_twos_complement, 64, 1, 64);
2138 ir_type *type_long_long = new_type_primitive(mode_long_long);
2139 ir_mode *mode_unsigned_long_long
2140 = new_int_mode("unsigned long long", irma_twos_complement, 64, 0, 64);
2141 ir_type *type_unsigned_long_long
2142 = new_type_primitive(mode_unsigned_long_long);
2144 ia32_setup_cg_config();
2146 /* doesn't really belong here, but this is the earliest place the backend
2148 init_asm_constraints();
2150 p.type_long_long = type_long_long;
2151 p.type_unsigned_long_long = type_unsigned_long_long;
2153 if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
2154 p.mode_float_arithmetic = NULL;
2155 p.type_long_double = NULL;
2157 p.mode_float_arithmetic = ia32_mode_E;
2158 p.type_long_double = ia32_type_E;
2164 * Check if the given register is callee or caller save.
2166 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
2169 /* check for callee saved */
2170 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2171 switch (reg->index) {
2182 /* check for caller saved */
2183 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2184 switch (reg->index) {
2192 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
2193 /* all XMM registers are caller save */
2194 return reg->index != REG_XMM_NOREG;
2195 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
2196 /* all VFP registers are caller save */
2197 return reg->index != REG_VFP_NOREG;
2203 static const lc_opt_enum_int_items_t gas_items[] = {
2204 { "elf", OBJECT_FILE_FORMAT_ELF },
2205 { "mingw", OBJECT_FILE_FORMAT_COFF },
2206 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2210 static lc_opt_enum_int_var_t gas_var = {
2211 (int*) &be_gas_object_file_format, gas_items
2214 #ifdef FIRM_GRGEN_BE
2215 static const lc_opt_enum_int_items_t transformer_items[] = {
2216 { "default", TRANSFORMER_DEFAULT },
2217 { "pbqp", TRANSFORMER_PBQP },
2218 { "random", TRANSFORMER_RAND },
2222 static lc_opt_enum_int_var_t transformer_var = {
2223 (int*)&be_transformer, transformer_items
2227 static const lc_opt_table_entry_t ia32_options[] = {
2228 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2229 #ifdef FIRM_GRGEN_BE
2230 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2232 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2233 &ia32_isa_template.base.stack_alignment),
2234 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2238 const arch_isa_if_t ia32_isa_if = {
2240 ia32_lower_for_target,
2242 ia32_handle_intrinsics,
2243 ia32_get_reg_class_for_mode,
2245 ia32_get_reg_class_alignment,
2246 ia32_get_libfirm_params,
2249 ia32_parse_asm_constraint,
2250 ia32_is_valid_clobber,
2253 ia32_get_pic_base, /* return node used as base in pic code addresses */
2254 ia32_before_abi, /* before abi introduce hook */
2256 ia32_before_ra, /* before register allocation hook */
2257 ia32_finish, /* called before codegen */
2258 ia32_emit, /* emit && done */
2259 ia32_register_saved_by,
2264 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2265 void be_init_arch_ia32(void)
2267 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2268 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2270 lc_opt_add_table(ia32_grp, ia32_options);
2271 be_register_isa_if("ia32", &ia32_isa_if);
2273 ia32_init_emitter();
2275 ia32_init_optimize();
2276 ia32_init_transform();
2278 ia32_init_architecture();