2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
55 #include "lower_calls.h"
56 #include "lower_mode_b.h"
57 #include "lower_softfloat.h"
61 #include "../benode.h"
62 #include "../belower.h"
63 #include "../besched.h"
66 #include "../beirgmod.h"
67 #include "../be_dbgout.h"
68 #include "../beblocksched.h"
69 #include "../bemachine.h"
70 #include "../bespillutil.h"
71 #include "../bespillslots.h"
72 #include "../bemodule.h"
73 #include "../begnuas.h"
74 #include "../bestate.h"
75 #include "../beflags.h"
76 #include "../betranshlp.h"
77 #include "../belistsched.h"
78 #include "../beabihelper.h"
79 #include "../bestack.h"
81 #include "bearch_ia32_t.h"
83 #include "ia32_new_nodes.h"
84 #include "gen_ia32_regalloc_if.h"
85 #include "gen_ia32_machine.h"
86 #include "ia32_common_transform.h"
87 #include "ia32_transform.h"
88 #include "ia32_emitter.h"
89 #include "ia32_optimize.h"
91 #include "ia32_dbg_stat.h"
92 #include "ia32_finish.h"
94 #include "ia32_architecture.h"
97 #include "ia32_pbqp_transform.h"
99 transformer_t be_transformer = TRANSFORMER_DEFAULT;
102 ir_mode *ia32_mode_fpcw = NULL;
104 /** The current omit-fp state */
105 static ir_type *omit_fp_between_type = NULL;
106 static ir_type *between_type = NULL;
107 static ir_entity *old_bp_ent = NULL;
108 static ir_entity *ret_addr_ent = NULL;
109 static ir_entity *omit_fp_ret_addr_ent = NULL;
112 * The environment for the intrinsic mapping.
114 static ia32_intrinsic_env_t intrinsic_env = {
116 NULL, /* the irg, these entities belong to */
117 NULL, /* entity for __divdi3 library call */
118 NULL, /* entity for __moddi3 library call */
119 NULL, /* entity for __udivdi3 library call */
120 NULL, /* entity for __umoddi3 library call */
124 typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
127 * Used to create per-graph unique pseudo nodes.
129 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
130 create_const_node_func func,
131 const arch_register_t* reg)
133 ir_node *block, *res;
138 block = get_irg_start_block(irg);
139 res = func(NULL, block);
140 arch_set_irn_register(res, reg);
146 /* Creates the unique per irg GP NoReg node. */
147 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
149 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
150 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
151 &ia32_registers[REG_GP_NOREG]);
154 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
156 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
157 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
158 &ia32_registers[REG_VFP_NOREG]);
161 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
163 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
164 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
165 &ia32_registers[REG_XMM_NOREG]);
168 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
170 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
171 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
172 &ia32_registers[REG_FPCW]);
177 * Returns the admissible noreg register node for input register pos of node irn.
179 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
181 ir_graph *irg = get_irn_irg(irn);
182 const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
184 assert(req != NULL && "Missing register requirements");
185 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
186 return ia32_new_NoReg_gp(irg);
188 if (ia32_cg_config.use_sse2) {
189 return ia32_new_NoReg_xmm(irg);
191 return ia32_new_NoReg_vfp(irg);
195 static arch_irn_class_t ia32_classify(const ir_node *irn)
197 arch_irn_class_t classification = arch_irn_class_none;
199 assert(is_ia32_irn(irn));
201 if (is_ia32_is_reload(irn))
202 classification |= arch_irn_class_reload;
204 if (is_ia32_is_spill(irn))
205 classification |= arch_irn_class_spill;
207 if (is_ia32_is_remat(irn))
208 classification |= arch_irn_class_remat;
210 return classification;
214 * The IA32 ABI callback object.
217 be_abi_call_flags_bits_t flags; /**< The call flags. */
218 ir_graph *irg; /**< The associated graph. */
221 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
223 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
226 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
228 if (is_be_node(node))
229 be_node_set_frame_entity(node, entity);
231 set_ia32_frame_ent(node, entity);
234 static void ia32_set_frame_offset(ir_node *irn, int bias)
236 if (get_ia32_frame_ent(irn) == NULL)
239 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
240 ir_graph *irg = get_irn_irg(irn);
241 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
242 if (layout->sp_relative) {
243 /* Pop nodes modify the stack pointer before calculating the
244 * destination address, so fix this here
249 add_ia32_am_offs_int(irn, bias);
252 static int ia32_get_sp_bias(const ir_node *node)
254 if (is_ia32_Call(node))
255 return -(int)get_ia32_call_attr_const(node)->pop;
257 if (is_ia32_Push(node))
260 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
263 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
264 return SP_BIAS_RESET;
271 * Build the between type and entities if not already build.
273 static void ia32_build_between_type(void)
275 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
276 if (! between_type) {
277 ir_type *old_bp_type = new_type_primitive(mode_Iu);
278 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
280 between_type = new_type_struct(IDENT("ia32_between_type"));
281 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
282 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
284 set_entity_offset(old_bp_ent, 0);
285 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
286 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
287 set_type_state(between_type, layout_fixed);
289 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
290 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
292 set_entity_offset(omit_fp_ret_addr_ent, 0);
293 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
294 set_type_state(omit_fp_between_type, layout_fixed);
300 * Produces the type which sits between the stack args and the locals on the stack.
301 * it will contain the return address and space to store the old base pointer.
302 * @return The Firm type modeling the ABI between type.
304 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
306 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
307 ia32_build_between_type();
308 return layout->sp_relative ? omit_fp_between_type : between_type;
312 * Return the stack entity that contains the return address.
314 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
316 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
317 ia32_build_between_type();
318 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
322 * Return the stack entity that contains the frame address.
324 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
326 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
327 ia32_build_between_type();
328 return layout->sp_relative ? NULL : old_bp_ent;
332 * Get the estimated cycle count for @p irn.
334 * @param self The this pointer.
335 * @param irn The node.
337 * @return The estimated cycle count for this operation
339 static int ia32_get_op_estimated_cost(const ir_node *irn)
342 ia32_op_type_t op_tp;
346 if (!is_ia32_irn(irn))
349 assert(is_ia32_irn(irn));
351 cost = get_ia32_latency(irn);
352 op_tp = get_ia32_op_type(irn);
354 if (is_ia32_CopyB(irn)) {
357 else if (is_ia32_CopyB_i(irn)) {
358 int size = get_ia32_copyb_size(irn);
359 cost = 20 + (int)ceil((4/3) * size);
361 /* in case of address mode operations add additional cycles */
362 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
364 In case of stack access and access to fixed addresses add 5 cycles
365 (we assume they are in cache), other memory operations cost 20
368 if (is_ia32_use_frame(irn) || (
369 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
370 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
382 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
384 * @param irn The original operation
385 * @param i Index of the argument we want the inverse operation to yield
386 * @param inverse struct to be filled with the resulting inverse op
387 * @param obstack The obstack to use for allocation of the returned nodes array
388 * @return The inverse operation or NULL if operation invertible
390 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
401 ir_node *block, *noreg, *nomem;
404 /* we cannot invert non-ia32 irns */
405 if (! is_ia32_irn(irn))
408 /* operand must always be a real operand (not base, index or mem) */
409 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
412 /* we don't invert address mode operations */
413 if (get_ia32_op_type(irn) != ia32_Normal)
416 /* TODO: adjust for new immediates... */
417 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
421 block = get_nodes_block(irn);
422 mode = get_irn_mode(irn);
423 irn_mode = get_irn_mode(irn);
424 noreg = get_irn_n(irn, 0);
425 nomem = get_irg_no_mem(irg);
426 dbgi = get_irn_dbg_info(irn);
428 /* initialize structure */
429 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
433 switch (get_ia32_irn_opcode(irn)) {
435 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
436 /* we have an add with a const here */
437 /* invers == add with negated const */
438 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
440 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
441 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
442 set_ia32_commutative(inverse->nodes[0]);
444 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
445 /* we have an add with a symconst here */
446 /* invers == sub with const */
447 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
449 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
452 /* normal add: inverse == sub */
453 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
458 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
459 /* we have a sub with a const/symconst here */
460 /* invers == add with this const */
461 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
462 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
463 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
467 if (i == n_ia32_binary_left) {
468 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
471 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
477 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
478 /* xor with const: inverse = xor */
479 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
480 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
481 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
485 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
490 inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
495 inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
500 /* inverse operation not supported */
508 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
510 if (mode_is_float(mode))
517 * Get the mode that should be used for spilling value node
519 static ir_mode *get_spill_mode(const ir_node *node)
521 ir_mode *mode = get_irn_mode(node);
522 return get_spill_mode_mode(mode);
526 * Checks whether an addressmode reload for a node with mode mode is compatible
527 * with a spillslot of mode spill_mode
529 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
531 return !mode_is_float(mode) || mode == spillmode;
535 * Check if irn can load its operand at position i from memory (source addressmode).
536 * @param irn The irn to be checked
537 * @param i The operands position
538 * @return Non-Zero if operand can be loaded
540 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
542 ir_node *op = get_irn_n(irn, i);
543 const ir_mode *mode = get_irn_mode(op);
544 const ir_mode *spillmode = get_spill_mode(op);
546 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
547 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
548 !ia32_is_spillmode_compatible(mode, spillmode) ||
549 is_ia32_use_frame(irn)) /* must not already use frame */
552 switch (get_ia32_am_support(irn)) {
557 if (i != n_ia32_unary_op)
563 case n_ia32_binary_left: {
564 const arch_register_req_t *req;
565 if (!is_ia32_commutative(irn))
568 /* we can't swap left/right for limited registers
569 * (As this (currently) breaks constraint handling copies)
571 req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
572 if (req->type & arch_register_req_type_limited)
577 case n_ia32_binary_right:
586 panic("Unknown AM type");
589 /* HACK: must not already use "real" memory.
590 * This can happen for Call and Div */
591 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
597 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
601 ir_mode *dest_op_mode;
603 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
605 set_ia32_op_type(irn, ia32_AddrModeS);
607 load_mode = get_irn_mode(get_irn_n(irn, i));
608 dest_op_mode = get_ia32_ls_mode(irn);
609 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
610 set_ia32_ls_mode(irn, load_mode);
612 set_ia32_use_frame(irn);
613 set_ia32_need_stackent(irn);
615 if (i == n_ia32_binary_left &&
616 get_ia32_am_support(irn) == ia32_am_binary &&
617 /* immediates are only allowed on the right side */
618 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
619 ia32_swap_left_right(irn);
620 i = n_ia32_binary_right;
623 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
625 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
626 set_irn_n(irn, n_ia32_mem, spill);
627 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
628 set_ia32_is_reload(irn);
631 static const be_abi_callbacks_t ia32_abi_callbacks = {
632 ia32_abi_get_between_type,
635 /* register allocator interface */
636 static const arch_irn_ops_t ia32_irn_ops = {
638 ia32_get_frame_entity,
639 ia32_set_frame_offset,
642 ia32_get_op_estimated_cost,
643 ia32_possible_memory_operand,
644 ia32_perform_memory_operand,
647 static ir_entity *mcount = NULL;
648 static int gprof = 0;
650 static void ia32_before_abi(ir_graph *irg)
653 if (mcount == NULL) {
654 ir_type *tp = new_type_method(0, 0);
655 ident *id = new_id_from_str("mcount");
656 mcount = new_entity(get_glob_type(), id, tp);
657 /* FIXME: enter the right ld_ident here */
658 set_entity_ld_ident(mcount, get_entity_ident(mcount));
659 set_entity_visibility(mcount, ir_visibility_external);
661 instrument_initcall(irg, mcount);
666 * Transforms the standard firm graph into
669 static void ia32_prepare_graph(ir_graph *irg)
671 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
674 switch (be_transformer) {
675 case TRANSFORMER_DEFAULT:
676 /* transform remaining nodes into assembler instructions */
677 ia32_transform_graph(irg);
680 case TRANSFORMER_PBQP:
681 case TRANSFORMER_RAND:
682 /* transform nodes into assembler instructions by PBQP magic */
683 ia32_transform_graph_by_pbqp(irg);
687 panic("invalid transformer");
690 ia32_transform_graph(irg);
693 /* do local optimizations (mainly CSE) */
694 optimize_graph_df(irg);
695 /* backend code expects that outedges are always enabled */
699 dump_ir_graph(irg, "transformed");
701 /* optimize address mode */
702 ia32_optimize_graph(irg);
704 /* do code placement, to optimize the position of constants */
706 /* backend code expects that outedges are always enabled */
710 dump_ir_graph(irg, "place");
713 ir_node *ia32_turn_back_am(ir_node *node)
715 dbg_info *dbgi = get_irn_dbg_info(node);
716 ir_graph *irg = get_irn_irg(node);
717 ir_node *block = get_nodes_block(node);
718 ir_node *base = get_irn_n(node, n_ia32_base);
719 ir_node *idx = get_irn_n(node, n_ia32_index);
720 ir_node *mem = get_irn_n(node, n_ia32_mem);
723 ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
724 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
726 ia32_copy_am_attrs(load, node);
727 if (is_ia32_is_reload(node))
728 set_ia32_is_reload(load);
729 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
731 switch (get_ia32_am_support(node)) {
733 set_irn_n(node, n_ia32_unary_op, load_res);
737 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
738 set_irn_n(node, n_ia32_binary_left, load_res);
740 set_irn_n(node, n_ia32_binary_right, load_res);
745 panic("Unknown AM type");
747 noreg = ia32_new_NoReg_gp(current_ir_graph);
748 set_irn_n(node, n_ia32_base, noreg);
749 set_irn_n(node, n_ia32_index, noreg);
750 set_ia32_am_offs_int(node, 0);
751 set_ia32_am_sc(node, NULL);
752 set_ia32_am_scale(node, 0);
753 clear_ia32_am_sc_sign(node);
755 /* rewire mem-proj */
756 if (get_irn_mode(node) == mode_T) {
757 const ir_edge_t *edge;
758 foreach_out_edge(node, edge) {
759 ir_node *out = get_edge_src_irn(edge);
760 if (get_irn_mode(out) == mode_M) {
761 set_Proj_pred(out, load);
762 set_Proj_proj(out, pn_ia32_Load_M);
768 set_ia32_op_type(node, ia32_Normal);
769 if (sched_is_scheduled(node))
770 sched_add_before(node, load);
775 static ir_node *flags_remat(ir_node *node, ir_node *after)
777 /* we should turn back source address mode when rematerializing nodes */
782 if (is_Block(after)) {
785 block = get_nodes_block(after);
788 type = get_ia32_op_type(node);
791 ia32_turn_back_am(node);
795 /* TODO implement this later... */
796 panic("found DestAM with flag user %+F this should not happen", node);
798 default: assert(type == ia32_Normal); break;
801 copy = exact_copy(node);
802 set_nodes_block(copy, block);
803 sched_add_after(after, copy);
809 * Called before the register allocator.
811 static void ia32_before_ra(ir_graph *irg)
813 /* setup fpu rounding modes */
814 ia32_setup_fpu_mode(irg);
817 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
820 be_add_missing_keeps(irg);
825 * Transforms a be_Reload into a ia32 Load.
827 static void transform_to_Load(ir_node *node)
829 ir_graph *irg = get_irn_irg(node);
830 dbg_info *dbgi = get_irn_dbg_info(node);
831 ir_node *block = get_nodes_block(node);
832 ir_entity *ent = be_get_frame_entity(node);
833 ir_mode *mode = get_irn_mode(node);
834 ir_mode *spillmode = get_spill_mode(node);
835 ir_node *noreg = ia32_new_NoReg_gp(irg);
836 ir_node *sched_point = NULL;
837 ir_node *ptr = get_irg_frame(irg);
838 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
839 ir_node *new_op, *proj;
840 const arch_register_t *reg;
842 if (sched_is_scheduled(node)) {
843 sched_point = sched_prev(node);
846 if (mode_is_float(spillmode)) {
847 if (ia32_cg_config.use_sse2)
848 new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
850 new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
852 else if (get_mode_size_bits(spillmode) == 128) {
853 /* Reload 128 bit SSE registers */
854 new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
857 new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
859 set_ia32_op_type(new_op, ia32_AddrModeS);
860 set_ia32_ls_mode(new_op, spillmode);
861 set_ia32_frame_ent(new_op, ent);
862 set_ia32_use_frame(new_op);
863 set_ia32_is_reload(new_op);
865 DBG_OPT_RELOAD2LD(node, new_op);
867 proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
870 sched_add_after(sched_point, new_op);
874 /* copy the register from the old node to the new Load */
875 reg = arch_get_irn_register(node);
876 arch_set_irn_register(proj, reg);
878 SET_IA32_ORIG_NODE(new_op, node);
880 exchange(node, proj);
884 * Transforms a be_Spill node into a ia32 Store.
886 static void transform_to_Store(ir_node *node)
888 ir_graph *irg = get_irn_irg(node);
889 dbg_info *dbgi = get_irn_dbg_info(node);
890 ir_node *block = get_nodes_block(node);
891 ir_entity *ent = be_get_frame_entity(node);
892 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
893 ir_mode *mode = get_spill_mode(spillval);
894 ir_node *noreg = ia32_new_NoReg_gp(irg);
895 ir_node *nomem = get_irg_no_mem(irg);
896 ir_node *ptr = get_irg_frame(irg);
897 ir_node *val = get_irn_n(node, n_be_Spill_val);
900 ir_node *sched_point = NULL;
902 if (sched_is_scheduled(node)) {
903 sched_point = sched_prev(node);
906 if (mode_is_float(mode)) {
907 if (ia32_cg_config.use_sse2) {
908 store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
909 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
911 store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
912 res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
914 } else if (get_mode_size_bits(mode) == 128) {
915 /* Spill 128 bit SSE registers */
916 store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
917 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
918 } else if (get_mode_size_bits(mode) == 8) {
919 store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
920 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
922 store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
923 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
926 set_ia32_op_type(store, ia32_AddrModeD);
927 set_ia32_ls_mode(store, mode);
928 set_ia32_frame_ent(store, ent);
929 set_ia32_use_frame(store);
930 set_ia32_is_spill(store);
931 SET_IA32_ORIG_NODE(store, node);
932 DBG_OPT_SPILL2ST(node, store);
935 sched_add_after(sched_point, store);
942 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
944 dbg_info *dbgi = get_irn_dbg_info(node);
945 ir_node *block = get_nodes_block(node);
946 ir_graph *irg = get_irn_irg(node);
947 ir_node *noreg = ia32_new_NoReg_gp(irg);
948 ir_node *frame = get_irg_frame(irg);
950 ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
952 set_ia32_frame_ent(push, ent);
953 set_ia32_use_frame(push);
954 set_ia32_op_type(push, ia32_AddrModeS);
955 set_ia32_ls_mode(push, mode_Is);
956 set_ia32_is_spill(push);
958 sched_add_before(schedpoint, push);
962 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
964 dbg_info *dbgi = get_irn_dbg_info(node);
965 ir_node *block = get_nodes_block(node);
966 ir_graph *irg = get_irn_irg(node);
967 ir_node *noreg = ia32_new_NoReg_gp(irg);
968 ir_node *frame = get_irg_frame(irg);
970 ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
971 get_irg_no_mem(irg), sp);
973 set_ia32_frame_ent(pop, ent);
974 set_ia32_use_frame(pop);
975 set_ia32_op_type(pop, ia32_AddrModeD);
976 set_ia32_ls_mode(pop, mode_Is);
977 set_ia32_is_reload(pop);
979 sched_add_before(schedpoint, pop);
984 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
986 dbg_info *dbgi = get_irn_dbg_info(node);
987 ir_mode *spmode = mode_Iu;
988 const arch_register_t *spreg = &ia32_registers[REG_ESP];
991 sp = new_rd_Proj(dbgi, pred, spmode, pos);
992 arch_set_irn_register(sp, spreg);
998 * Transform MemPerm, currently we do this the ugly way and produce
999 * push/pop into/from memory cascades. This is possible without using
1002 static void transform_MemPerm(ir_node *node)
1004 ir_node *block = get_nodes_block(node);
1005 ir_graph *irg = get_irn_irg(node);
1006 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
1007 int arity = be_get_MemPerm_entity_arity(node);
1008 ir_node **pops = ALLOCAN(ir_node*, arity);
1012 const ir_edge_t *edge;
1013 const ir_edge_t *next;
1016 for (i = 0; i < arity; ++i) {
1017 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1018 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1019 ir_type *enttype = get_entity_type(inent);
1020 unsigned entsize = get_type_size_bytes(enttype);
1021 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1022 ir_node *mem = get_irn_n(node, i + 1);
1025 /* work around cases where entities have different sizes */
1026 if (entsize2 < entsize)
1028 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1030 push = create_push(node, node, sp, mem, inent);
1031 sp = create_spproj(node, push, pn_ia32_Push_stack);
1033 /* add another push after the first one */
1034 push = create_push(node, node, sp, mem, inent);
1035 add_ia32_am_offs_int(push, 4);
1036 sp = create_spproj(node, push, pn_ia32_Push_stack);
1039 set_irn_n(node, i, new_r_Bad(irg, mode_X));
1043 for (i = arity - 1; i >= 0; --i) {
1044 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1045 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1046 ir_type *enttype = get_entity_type(outent);
1047 unsigned entsize = get_type_size_bytes(enttype);
1048 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1051 /* work around cases where entities have different sizes */
1052 if (entsize2 < entsize)
1054 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1056 pop = create_pop(node, node, sp, outent);
1057 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1059 add_ia32_am_offs_int(pop, 4);
1061 /* add another pop after the first one */
1062 pop = create_pop(node, node, sp, outent);
1063 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1070 keep = be_new_Keep(block, 1, in);
1071 sched_add_before(node, keep);
1073 /* exchange memprojs */
1074 foreach_out_edge_safe(node, edge, next) {
1075 ir_node *proj = get_edge_src_irn(edge);
1076 int p = get_Proj_proj(proj);
1080 set_Proj_pred(proj, pops[p]);
1081 set_Proj_proj(proj, pn_ia32_Pop_M);
1084 /* remove memperm */
1090 * Block-Walker: Calls the transform functions Spill and Reload.
1092 static void ia32_after_ra_walker(ir_node *block, void *env)
1094 ir_node *node, *prev;
1097 /* beware: the schedule is changed here */
1098 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1099 prev = sched_prev(node);
1101 if (be_is_Reload(node)) {
1102 transform_to_Load(node);
1103 } else if (be_is_Spill(node)) {
1104 transform_to_Store(node);
1105 } else if (be_is_MemPerm(node)) {
1106 transform_MemPerm(node);
1112 * Collects nodes that need frame entities assigned.
1114 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1116 be_fec_env_t *env = (be_fec_env_t*)data;
1117 const ir_mode *mode;
1120 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1121 mode = get_spill_mode_mode(get_irn_mode(node));
1122 align = get_mode_size_bytes(mode);
1123 } else if (is_ia32_irn(node) &&
1124 get_ia32_frame_ent(node) == NULL &&
1125 is_ia32_use_frame(node)) {
1126 if (is_ia32_need_stackent(node))
1129 switch (get_ia32_irn_opcode(node)) {
1131 case iro_ia32_Load: {
1132 const ia32_attr_t *attr = get_ia32_attr_const(node);
1134 if (attr->data.need_32bit_stackent) {
1136 } else if (attr->data.need_64bit_stackent) {
1139 mode = get_ia32_ls_mode(node);
1140 if (is_ia32_is_reload(node))
1141 mode = get_spill_mode_mode(mode);
1143 align = get_mode_size_bytes(mode);
1147 case iro_ia32_vfild:
1149 case iro_ia32_xLoad: {
1150 mode = get_ia32_ls_mode(node);
1155 case iro_ia32_FldCW: {
1156 /* although 2 byte would be enough 4 byte performs best */
1164 panic("unexpected frame user while collection frame entity nodes");
1166 case iro_ia32_FnstCW:
1167 case iro_ia32_Store8Bit:
1168 case iro_ia32_Store:
1171 case iro_ia32_vfist:
1172 case iro_ia32_vfisttp:
1174 case iro_ia32_xStore:
1175 case iro_ia32_xStoreSimple:
1182 be_node_needs_frame_entity(env, node, mode, align);
1185 static int determine_ebp_input(ir_node *ret)
1187 const arch_register_t *bp = &ia32_registers[REG_EBP];
1188 int arity = get_irn_arity(ret);
1191 for (i = 0; i < arity; ++i) {
1192 ir_node *input = get_irn_n(ret, i);
1193 if (arch_get_irn_register(input) == bp)
1196 panic("no ebp input found at %+F", ret);
1199 static void introduce_epilog(ir_node *ret)
1201 const arch_register_t *sp = &ia32_registers[REG_ESP];
1202 const arch_register_t *bp = &ia32_registers[REG_EBP];
1203 ir_graph *irg = get_irn_irg(ret);
1204 ir_type *frame_type = get_irg_frame_type(irg);
1205 unsigned frame_size = get_type_size_bytes(frame_type);
1206 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1207 ir_node *block = get_nodes_block(ret);
1208 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1209 ir_node *curr_sp = first_sp;
1210 ir_mode *mode_gp = mode_Iu;
1212 if (!layout->sp_relative) {
1213 int n_ebp = determine_ebp_input(ret);
1214 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1215 if (ia32_cg_config.use_leave) {
1216 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1217 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1218 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1219 arch_set_irn_register(curr_bp, bp);
1220 arch_set_irn_register(curr_sp, sp);
1221 sched_add_before(ret, leave);
1224 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1225 /* copy ebp to esp */
1226 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1227 arch_set_irn_register(curr_sp, sp);
1228 sched_add_before(ret, curr_sp);
1231 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1232 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1233 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1234 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1235 arch_set_irn_register(curr_bp, bp);
1236 arch_set_irn_register(curr_sp, sp);
1237 sched_add_before(ret, pop);
1239 set_irn_n(ret, n_be_Return_mem, curr_mem);
1241 set_irn_n(ret, n_ebp, curr_bp);
1243 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1244 sched_add_before(ret, incsp);
1247 set_irn_n(ret, n_be_Return_sp, curr_sp);
1249 /* keep verifier happy... */
1250 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1251 kill_node(first_sp);
1256 * put the Prolog code at the beginning, epilog code before each return
1258 static void introduce_prolog_epilog(ir_graph *irg)
1260 const arch_register_t *sp = &ia32_registers[REG_ESP];
1261 const arch_register_t *bp = &ia32_registers[REG_EBP];
1262 ir_node *start = get_irg_start(irg);
1263 ir_node *block = get_nodes_block(start);
1264 ir_type *frame_type = get_irg_frame_type(irg);
1265 unsigned frame_size = get_type_size_bytes(frame_type);
1266 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1267 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1268 ir_node *curr_sp = initial_sp;
1269 ir_mode *mode_gp = mode_Iu;
1271 if (!layout->sp_relative) {
1273 ir_node *mem = get_irg_initial_mem(irg);
1274 ir_node *noreg = ia32_new_NoReg_gp(irg);
1275 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1276 ir_node *curr_bp = initial_bp;
1277 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
1280 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1281 mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
1282 arch_set_irn_register(curr_sp, sp);
1283 sched_add_after(start, push);
1285 /* move esp to ebp */
1286 curr_bp = be_new_Copy(block, curr_sp);
1287 sched_add_after(push, curr_bp);
1288 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1289 curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
1290 sched_add_after(curr_bp, curr_sp);
1291 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1292 edges_reroute(initial_bp, curr_bp);
1293 set_irn_n(push, n_ia32_Push_val, initial_bp);
1295 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1296 edges_reroute(initial_sp, incsp);
1297 set_irn_n(push, n_ia32_Push_stack, initial_sp);
1298 sched_add_after(curr_sp, incsp);
1300 /* make sure the initial IncSP is really used by someone */
1301 if (get_irn_n_edges(incsp) <= 1) {
1302 ir_node *in[] = { incsp };
1303 ir_node *keep = be_new_Keep(block, 1, in);
1304 sched_add_after(incsp, keep);
1307 layout->initial_bias = -4;
1309 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1310 edges_reroute(initial_sp, incsp);
1311 be_set_IncSP_pred(incsp, curr_sp);
1312 sched_add_after(start, incsp);
1315 /* introduce epilog for every return node */
1317 ir_node *end_block = get_irg_end_block(irg);
1318 int arity = get_irn_arity(end_block);
1321 for (i = 0; i < arity; ++i) {
1322 ir_node *ret = get_irn_n(end_block, i);
1323 assert(be_is_Return(ret));
1324 introduce_epilog(ret);
1330 * Last touchups for the graph before emit: x87 simulation to replace the
1331 * virtual with real x87 instructions, creating a block schedule and peephole
1334 static void ia32_finish(ir_graph *irg)
1336 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1337 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1338 bool at_begin = stack_layout->sp_relative ? true : false;
1339 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1341 /* create and coalesce frame entities */
1342 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1343 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1344 be_free_frame_entity_coalescer(fec_env);
1346 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1348 introduce_prolog_epilog(irg);
1350 /* fix stack entity offsets */
1351 be_abi_fix_stack_nodes(irg);
1352 be_abi_fix_stack_bias(irg);
1354 /* fix 2-address code constraints */
1355 ia32_finish_irg(irg);
1357 /* we might have to rewrite x87 virtual registers */
1358 if (irg_data->do_x87_sim) {
1359 ia32_x87_simulate_graph(irg);
1362 /* do peephole optimisations */
1363 ia32_peephole_optimization(irg);
1365 be_remove_dead_nodes_from_schedule(irg);
1367 /* create block schedule, this also removes empty blocks which might
1368 * produce critical edges */
1369 irg_data->blk_sched = be_create_block_schedule(irg);
1373 * Emits the code, closes the output file and frees
1374 * the code generator interface.
1376 static void ia32_emit(ir_graph *irg)
1378 if (ia32_cg_config.emit_machcode) {
1379 ia32_gen_binary_routine(irg);
1381 ia32_gen_routine(irg);
1386 * Returns the node representing the PIC base.
1388 static ir_node *ia32_get_pic_base(ir_graph *irg)
1390 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1392 ir_node *get_eip = irg_data->get_eip;
1393 if (get_eip != NULL)
1396 block = get_irg_start_block(irg);
1397 get_eip = new_bd_ia32_GetEIP(NULL, block);
1398 irg_data->get_eip = get_eip;
1404 * Initializes a IA32 code generator.
1406 static void ia32_init_graph(ir_graph *irg)
1408 struct obstack *obst = be_get_be_obst(irg);
1409 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1411 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1414 /* Linux gprof implementation needs base pointer */
1415 be_get_irg_options(irg)->omit_fp = 0;
1418 be_birg_from_irg(irg)->isa_link = irg_data;
1423 * Set output modes for GCC
1425 static const tarval_mode_info mo_integer = {
1432 * set the tarval output mode of all integer modes to decimal
1434 static void set_tarval_output_modes(void)
1438 for (i = get_irp_n_modes(); i > 0;) {
1439 ir_mode *mode = get_irp_mode(--i);
1441 if (mode_is_int(mode))
1442 set_tarval_mode_output_option(mode, &mo_integer);
1446 extern const arch_isa_if_t ia32_isa_if;
1449 * The template that generates a new ISA object.
1450 * Note that this template can be changed by command line
1453 static ia32_isa_t ia32_isa_template = {
1455 &ia32_isa_if, /* isa interface implementation */
1460 &ia32_registers[REG_ESP], /* stack pointer register */
1461 &ia32_registers[REG_EBP], /* base pointer register */
1462 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1463 2, /* power of two stack alignment, 2^2 == 4 */
1464 NULL, /* main environment */
1465 7, /* costs for a spill instruction */
1466 5, /* costs for a reload instruction */
1467 false, /* no custom abi handling */
1471 NULL, /* abstract machine */
1472 IA32_FPU_ARCH_X87, /* FPU architecture */
1475 static void init_asm_constraints(void)
1477 be_init_default_asm_constraint_flags();
1479 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1480 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1481 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1482 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1483 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1484 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1485 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1486 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1487 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1488 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1489 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1490 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1491 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1492 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1493 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1494 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1495 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1496 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1497 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1498 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1500 /* no support for autodecrement/autoincrement */
1501 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1502 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1503 /* no float consts */
1504 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1505 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1506 /* makes no sense on x86 */
1507 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1508 /* no support for sse consts yet */
1509 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1510 /* no support for x87 consts yet */
1511 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1512 /* no support for mmx registers yet */
1513 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1514 /* not available in 32bit mode */
1515 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1516 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1518 /* no code yet to determine register class needed... */
1519 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1523 * Initializes the backend ISA.
1525 static arch_env_t *ia32_init(FILE *file_handle)
1527 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1529 set_tarval_output_modes();
1531 *isa = ia32_isa_template;
1533 if (ia32_mode_fpcw == NULL) {
1534 ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1537 ia32_register_init();
1538 ia32_create_opcodes(&ia32_irn_ops);
1540 be_emit_init(file_handle);
1541 isa->types = pmap_create();
1542 isa->tv_ent = pmap_create();
1543 isa->cpu = ia32_init_machine_description();
1545 /* enter the ISA object into the intrinsic environment */
1546 intrinsic_env.isa = isa;
1554 * Closes the output file and frees the ISA structure.
1556 static void ia32_done(void *self)
1558 ia32_isa_t *isa = (ia32_isa_t*)self;
1560 /* emit now all global declarations */
1561 be_gas_emit_decls(isa->base.main_env);
1563 pmap_destroy(isa->tv_ent);
1564 pmap_destroy(isa->types);
1573 * Get the register class which shall be used to store a value of a given mode.
1574 * @param self The this pointer.
1575 * @param mode The mode in question.
1576 * @return A register class which can hold values of the given mode.
1578 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1580 if (mode_is_float(mode)) {
1581 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1584 return &ia32_reg_classes[CLASS_ia32_gp];
1588 * Returns the register for parameter nr.
1590 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1591 const ir_mode *mode)
1593 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1594 &ia32_registers[REG_ECX],
1595 &ia32_registers[REG_EDX],
1598 static const unsigned MAXNUM_GPREG_ARGS = 3;
1600 static const arch_register_t *gpreg_param_reg_regparam[] = {
1601 &ia32_registers[REG_EAX],
1602 &ia32_registers[REG_EDX],
1603 &ia32_registers[REG_ECX]
1606 static const arch_register_t *gpreg_param_reg_this[] = {
1607 &ia32_registers[REG_ECX],
1612 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1613 &ia32_registers[REG_XMM0],
1614 &ia32_registers[REG_XMM1],
1615 &ia32_registers[REG_XMM2],
1616 &ia32_registers[REG_XMM3],
1617 &ia32_registers[REG_XMM4],
1618 &ia32_registers[REG_XMM5],
1619 &ia32_registers[REG_XMM6],
1620 &ia32_registers[REG_XMM7]
1623 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1624 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1626 static const unsigned MAXNUM_SSE_ARGS = 8;
1628 if ((cc & cc_this_call) && nr == 0)
1629 return gpreg_param_reg_this[0];
1631 if (! (cc & cc_reg_param))
1634 if (mode_is_float(mode)) {
1635 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1637 if (nr >= MAXNUM_SSE_ARGS)
1640 if (cc & cc_this_call) {
1641 return fpreg_sse_param_reg_this[nr];
1643 return fpreg_sse_param_reg_std[nr];
1644 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1645 unsigned num_regparam;
1647 if (get_mode_size_bits(mode) > 32)
1650 if (nr >= MAXNUM_GPREG_ARGS)
1653 if (cc & cc_this_call) {
1654 return gpreg_param_reg_this[nr];
1656 num_regparam = cc & ~cc_bits;
1657 if (num_regparam == 0) {
1658 /* default fastcall */
1659 return gpreg_param_reg_fastcall[nr];
1661 if (nr < num_regparam)
1662 return gpreg_param_reg_regparam[nr];
1666 panic("unknown argument mode");
1670 * Get the ABI restrictions for procedure calls.
1671 * @param self The this pointer.
1672 * @param method_type The type of the method (procedure) in question.
1673 * @param abi The abi object to be modified
1675 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1681 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1685 /* set abi flags for calls */
1686 call_flags.bits.store_args_sequential = 0;
1687 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1688 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1689 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1691 /* set parameter passing style */
1692 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1694 cc = get_method_calling_convention(method_type);
1695 if (get_method_variadicity(method_type) == variadicity_variadic) {
1696 /* pass all parameters of a variadic function on the stack */
1697 cc = cc_cdecl_set | (cc & cc_this_call);
1699 if (get_method_additional_properties(method_type) & mtp_property_private &&
1700 ia32_cg_config.optimize_cc) {
1701 /* set the fast calling conventions (allowing up to 3) */
1702 cc = SET_FASTCALL(cc) | 3;
1706 /* we have to pop the shadow parameter ourself for compound calls */
1707 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1708 && !(cc & cc_reg_param)) {
1709 pop_amount += get_mode_size_bytes(mode_P_data);
1712 n = get_method_n_params(method_type);
1713 for (i = regnum = 0; i < n; i++) {
1714 const arch_register_t *reg = NULL;
1715 ir_type *tp = get_method_param_type(method_type, i);
1716 ir_mode *mode = get_type_mode(tp);
1719 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1722 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1725 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1726 * movl has a shorter opcode than mov[sz][bw]l */
1727 ir_mode *load_mode = mode;
1730 unsigned size = get_mode_size_bytes(mode);
1732 if (cc & cc_callee_clear_stk) {
1733 pop_amount += (size + 3U) & ~3U;
1736 if (size < 4) load_mode = mode_Iu;
1739 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1743 be_abi_call_set_pop(abi, pop_amount);
1745 /* set return registers */
1746 n = get_method_n_ress(method_type);
1748 assert(n <= 2 && "more than two results not supported");
1750 /* In case of 64bit returns, we will have two 32bit values */
1752 ir_type *tp = get_method_res_type(method_type, 0);
1753 ir_mode *mode = get_type_mode(tp);
1755 assert(!mode_is_float(mode) && "two FP results not supported");
1757 tp = get_method_res_type(method_type, 1);
1758 mode = get_type_mode(tp);
1760 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1762 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1763 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1766 ir_type *tp = get_method_res_type(method_type, 0);
1767 ir_mode *mode = get_type_mode(tp);
1768 const arch_register_t *reg;
1769 assert(is_atomic_type(tp));
1771 reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
1773 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1778 * Returns the necessary byte alignment for storing a register of given class.
1780 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1782 ir_mode *mode = arch_register_class_mode(cls);
1783 int bytes = get_mode_size_bytes(mode);
1785 if (mode_is_float(mode) && bytes > 8)
1791 * Return irp irgs in the desired order.
1793 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1800 static void ia32_mark_remat(ir_node *node)
1802 if (is_ia32_irn(node)) {
1803 set_ia32_is_remat(node);
1808 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1810 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1815 ir_relation relation;
1820 cmp_l = get_Cmp_left(sel);
1821 cmp_r = get_Cmp_right(sel);
1822 if (!mode_is_float(get_irn_mode(cmp_l)))
1825 /* check for min/max. They're defined as (C-Semantik):
1826 * min(a, b) = a < b ? a : b
1827 * or min(a, b) = a <= b ? a : b
1828 * max(a, b) = a > b ? a : b
1829 * or max(a, b) = a >= b ? a : b
1830 * (Note we only handle float min/max here)
1832 relation = get_Cmp_relation(sel);
1834 case ir_relation_greater_equal:
1835 case ir_relation_greater:
1837 if (cmp_l == mux_true && cmp_r == mux_false)
1840 case ir_relation_less_equal:
1841 case ir_relation_less:
1843 if (cmp_l == mux_true && cmp_r == mux_false)
1846 case ir_relation_unordered_greater_equal:
1847 case ir_relation_unordered_greater:
1849 if (cmp_l == mux_false && cmp_r == mux_true)
1852 case ir_relation_unordered_less_equal:
1853 case ir_relation_unordered_less:
1855 if (cmp_l == mux_false && cmp_r == mux_true)
1866 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1868 ir_mode *mode = get_irn_mode(mux_true);
1871 if (!mode_is_int(mode) && !mode_is_reference(mode)
1875 if (is_Const(mux_true) && is_Const(mux_false)) {
1876 /* we can create a set plus up two 3 instructions for any combination
1884 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1889 if (!mode_is_float(get_irn_mode(mux_true)))
1892 return is_Const(mux_true) && is_Const(mux_false);
1895 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1902 ir_relation relation;
1907 mode = get_irn_mode(mux_true);
1908 if (mode_is_signed(mode) || mode_is_float(mode))
1911 relation = get_Cmp_relation(sel);
1912 cmp_left = get_Cmp_left(sel);
1913 cmp_right = get_Cmp_right(sel);
1915 /* "move" zero constant to false input */
1916 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1917 ir_node *tmp = mux_false;
1918 mux_false = mux_true;
1920 relation = get_negated_relation(relation);
1922 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1924 if (!is_Sub(mux_true))
1926 sub_left = get_Sub_left(mux_true);
1927 sub_right = get_Sub_right(mux_true);
1929 /* Mux(a >=u b, 0, a-b) */
1930 if ((relation & ir_relation_greater)
1931 && sub_left == cmp_left && sub_right == cmp_right)
1933 /* Mux(a <=u b, 0, b-a) */
1934 if ((relation & ir_relation_less)
1935 && sub_left == cmp_right && sub_right == cmp_left)
1941 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1946 /* middleend can handle some things */
1947 if (ir_is_optimizable_mux(sel, mux_false, mux_true))
1949 /* we can handle Set for all modes and compares */
1950 if (mux_is_set(sel, mux_true, mux_false))
1952 /* SSE has own min/max operations */
1953 if (ia32_cg_config.use_sse2
1954 && mux_is_float_min_max(sel, mux_true, mux_false))
1956 /* we can handle Mux(?, Const[f], Const[f]) */
1957 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1958 #ifdef FIRM_GRGEN_BE
1959 /* well, some code selectors can't handle it */
1960 if (be_transformer != TRANSFORMER_PBQP
1961 || be_transformer != TRANSFORMER_RAND)
1968 /* no support for 64bit inputs to cmov */
1969 mode = get_irn_mode(mux_true);
1970 if (get_mode_size_bits(mode) > 32)
1972 /* we can handle Abs for all modes and compares (except 64bit) */
1973 if (ir_mux_is_abs(sel, mux_false, mux_true) != 0)
1975 /* we can't handle MuxF yet */
1976 if (mode_is_float(mode))
1979 if (mux_is_doz(sel, mux_true, mux_false))
1982 /* Check Cmp before the node */
1984 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1986 /* we can't handle 64bit compares */
1987 if (get_mode_size_bits(cmp_mode) > 32)
1990 /* we can't handle float compares */
1991 if (mode_is_float(cmp_mode))
1995 /* did we disable cmov generation? */
1996 if (!ia32_cg_config.use_cmov)
1999 /* we can use a cmov */
2003 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2007 /* we already added all our simple flags to the flags modifier list in
2008 * init, so this flag we don't know. */
2009 return ASM_CONSTRAINT_FLAG_INVALID;
2012 static int ia32_is_valid_clobber(const char *clobber)
2014 return ia32_get_clobber_register(clobber) != NULL;
2017 static ir_node *ia32_create_set(ir_node *cond)
2019 ir_node *block = get_nodes_block(cond);
2020 ir_node *set = new_bd_ia32_l_Setcc(NULL, block, cond);
2021 ir_node *conv = new_r_Conv(block, set, mode_Iu);
2025 static void ia32_lower_for_target(void)
2027 size_t i, n_irgs = get_irp_n_irgs();
2028 lower_mode_b_config_t lower_mode_b_config = {
2029 mode_Iu, /* lowered mode */
2033 /* perform doubleword lowering */
2034 lwrdw_param_t lower_dw_params = {
2035 1, /* little endian */
2036 64, /* doubleword size */
2037 ia32_create_intrinsic_fkt,
2041 ia32_create_opcodes(&ia32_irn_ops);
2043 /* lower compound param handling
2044 * Note: we lower compound arguments ourself, since on ia32 we don't
2045 * have hidden parameters but know where to find the structs on the stack.
2046 * (This also forces us to always allocate space for the compound arguments
2047 * on the callframe and we can't just use an arbitrary position on the
2050 lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS);
2052 /* replace floating point operations by function calls */
2053 if (ia32_cg_config.use_softfloat) {
2054 lower_floating_point();
2057 ir_prepare_dw_lowering(&lower_dw_params);
2060 for (i = 0; i < n_irgs; ++i) {
2061 ir_graph *irg = get_irp_irg(i);
2062 /* lower for mode_b stuff */
2063 ir_lower_mode_b(irg, &lower_mode_b_config);
2064 /* break up switches with wide ranges */
2065 lower_switch(irg, 4, 256, false);
2068 for (i = 0; i < n_irgs; ++i) {
2069 ir_graph *irg = get_irp_irg(i);
2070 /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
2071 * so we can generate rep movs later, and turn all big CopyBs into
2073 lower_CopyB(irg, 64, 8193, true);
2078 * Create the trampoline code.
2080 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2082 ir_graph *const irg = get_irn_irg(block);
2083 ir_node * p = trampoline;
2084 ir_mode *const mode = get_irn_mode(p);
2085 ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
2086 ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
2090 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
2091 mem = new_r_Proj(st, mode_M, pn_Store_M);
2092 p = new_r_Add(block, p, one, mode);
2093 st = new_r_Store(block, mem, p, env, cons_none);
2094 mem = new_r_Proj(st, mode_M, pn_Store_M);
2095 p = new_r_Add(block, p, four, mode);
2097 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
2098 mem = new_r_Proj(st, mode_M, pn_Store_M);
2099 p = new_r_Add(block, p, one, mode);
2100 st = new_r_Store(block, mem, p, callee, cons_none);
2101 mem = new_r_Proj(st, mode_M, pn_Store_M);
2102 p = new_r_Add(block, p, four, mode);
2108 * Returns the libFirm configuration parameter for this backend.
2110 static const backend_params *ia32_get_libfirm_params(void)
2112 static const ir_settings_arch_dep_t ad = {
2113 1, /* also use subs */
2114 4, /* maximum shifts */
2115 63, /* maximum shift amount */
2116 ia32_evaluate_insn, /* evaluate the instruction sequence */
2118 1, /* allow Mulhs */
2119 1, /* allow Mulus */
2120 32, /* Mulh allowed up to 32 bit */
2122 static backend_params p = {
2123 1, /* support inline assembly */
2124 1, /* support Rotl nodes */
2125 0, /* little endian */
2126 1, /* modulo shift efficient */
2127 0, /* non-modulo shift not efficient */
2128 &ad, /* will be set later */
2129 ia32_is_mux_allowed,
2130 32, /* machine_size */
2131 NULL, /* float arithmetic mode, will be set below */
2132 NULL, /* long long type */
2133 NULL, /* unsigned long long type */
2134 NULL, /* long double type */
2135 12, /* size of trampoline code */
2136 4, /* alignment of trampoline code */
2137 ia32_create_trampoline_fkt,
2138 4 /* alignment of stack parameter */
2140 ir_mode *mode_long_long
2141 = new_ir_mode("long long", irms_int_number, 64, 1, irma_twos_complement,
2143 ir_type *type_long_long = new_type_primitive(mode_long_long);
2144 ir_mode *mode_unsigned_long_long
2145 = new_ir_mode("unsigned long long", irms_int_number, 64, 0,
2146 irma_twos_complement, 64);
2147 ir_type *type_unsigned_long_long
2148 = new_type_primitive(mode_unsigned_long_long);
2150 ia32_setup_cg_config();
2152 /* doesn't really belong here, but this is the earliest place the backend
2154 init_asm_constraints();
2156 p.type_long_long = type_long_long;
2157 p.type_unsigned_long_long = type_unsigned_long_long;
2159 if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
2160 p.mode_float_arithmetic = NULL;
2161 p.type_long_double = NULL;
2163 p.mode_float_arithmetic = mode_E;
2164 ir_mode *mode = new_ir_mode("long double", irms_float_number, 80, 1,
2166 ir_type *type = new_type_primitive(mode);
2167 set_type_size_bytes(type, 12);
2168 set_type_alignment_bytes(type, 4);
2169 p.type_long_double = type;
2175 * Check if the given register is callee or caller save.
2177 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
2180 /* check for callee saved */
2181 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2182 switch (reg->index) {
2193 /* check for caller saved */
2194 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2195 switch (reg->index) {
2203 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
2204 /* all XMM registers are caller save */
2205 return reg->index != REG_XMM_NOREG;
2206 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
2207 /* all VFP registers are caller save */
2208 return reg->index != REG_VFP_NOREG;
2214 static const lc_opt_enum_int_items_t gas_items[] = {
2215 { "elf", OBJECT_FILE_FORMAT_ELF },
2216 { "mingw", OBJECT_FILE_FORMAT_COFF },
2217 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2221 static lc_opt_enum_int_var_t gas_var = {
2222 (int*) &be_gas_object_file_format, gas_items
2225 #ifdef FIRM_GRGEN_BE
2226 static const lc_opt_enum_int_items_t transformer_items[] = {
2227 { "default", TRANSFORMER_DEFAULT },
2228 { "pbqp", TRANSFORMER_PBQP },
2229 { "random", TRANSFORMER_RAND },
2233 static lc_opt_enum_int_var_t transformer_var = {
2234 (int*)&be_transformer, transformer_items
2238 static const lc_opt_table_entry_t ia32_options[] = {
2239 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2240 #ifdef FIRM_GRGEN_BE
2241 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2243 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2244 &ia32_isa_template.base.stack_alignment),
2245 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2249 const arch_isa_if_t ia32_isa_if = {
2251 ia32_lower_for_target,
2253 ia32_handle_intrinsics,
2254 ia32_get_reg_class_for_mode,
2256 ia32_get_reg_class_alignment,
2257 ia32_get_libfirm_params,
2260 ia32_parse_asm_constraint,
2261 ia32_is_valid_clobber,
2264 ia32_get_pic_base, /* return node used as base in pic code addresses */
2265 ia32_before_abi, /* before abi introduce hook */
2267 ia32_before_ra, /* before register allocation hook */
2268 ia32_finish, /* called before codegen */
2269 ia32_emit, /* emit && done */
2270 ia32_register_saved_by,
2275 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2276 void be_init_arch_ia32(void)
2278 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2279 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2281 lc_opt_add_table(ia32_grp, ia32_options);
2282 be_register_isa_if("ia32", &ia32_isa_if);
2284 ia32_init_emitter();
2286 ia32_init_optimize();
2287 ia32_init_transform();
2289 ia32_init_architecture();