2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
28 #include "lc_opts_enum.h"
36 #include "iredges_t.h"
50 #include "iroptimize.h"
51 #include "instrument.h"
54 #include "lower_calls.h"
55 #include "lower_mode_b.h"
56 #include "lower_softfloat.h"
66 #include "be_dbgout.h"
67 #include "beblocksched.h"
68 #include "bemachine.h"
69 #include "bespillutil.h"
70 #include "bespillslots.h"
75 #include "betranshlp.h"
76 #include "belistsched.h"
77 #include "beabihelper.h"
80 #include "bearch_ia32_t.h"
82 #include "ia32_new_nodes.h"
83 #include "gen_ia32_regalloc_if.h"
84 #include "gen_ia32_machine.h"
85 #include "ia32_common_transform.h"
86 #include "ia32_transform.h"
87 #include "ia32_emitter.h"
88 #include "ia32_optimize.h"
90 #include "ia32_dbg_stat.h"
91 #include "ia32_finish.h"
93 #include "ia32_architecture.h"
96 #include "ia32_pbqp_transform.h"
98 transformer_t be_transformer = TRANSFORMER_DEFAULT;
101 ir_mode *ia32_mode_fpcw;
102 ir_mode *ia32_mode_E;
103 ir_type *ia32_type_E;
105 /** The current omit-fp state */
106 static ir_type *omit_fp_between_type = NULL;
107 static ir_type *between_type = NULL;
108 static ir_entity *old_bp_ent = NULL;
109 static ir_entity *ret_addr_ent = NULL;
110 static ir_entity *omit_fp_ret_addr_ent = NULL;
113 * The environment for the intrinsic mapping.
115 static ia32_intrinsic_env_t intrinsic_env = {
117 NULL, /* the irg, these entities belong to */
118 NULL, /* entity for __divdi3 library call */
119 NULL, /* entity for __moddi3 library call */
120 NULL, /* entity for __udivdi3 library call */
121 NULL, /* entity for __umoddi3 library call */
125 typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
128 * Used to create per-graph unique pseudo nodes.
130 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
131 create_const_node_func func,
132 const arch_register_t* reg)
134 ir_node *block, *res;
139 block = get_irg_start_block(irg);
140 res = func(NULL, block);
141 arch_set_irn_register(res, reg);
147 /* Creates the unique per irg GP NoReg node. */
148 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
150 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
151 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
152 &ia32_registers[REG_GP_NOREG]);
155 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
157 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
158 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
159 &ia32_registers[REG_VFP_NOREG]);
162 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
164 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
165 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
166 &ia32_registers[REG_XMM_NOREG]);
169 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
171 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
172 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
173 &ia32_registers[REG_FPCW]);
178 * Returns the admissible noreg register node for input register pos of node irn.
180 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
182 ir_graph *irg = get_irn_irg(irn);
183 const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
185 assert(req != NULL && "Missing register requirements");
186 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
187 return ia32_new_NoReg_gp(irg);
189 if (ia32_cg_config.use_sse2) {
190 return ia32_new_NoReg_xmm(irg);
192 return ia32_new_NoReg_vfp(irg);
196 static arch_irn_class_t ia32_classify(const ir_node *irn)
198 arch_irn_class_t classification = arch_irn_class_none;
200 assert(is_ia32_irn(irn));
202 if (is_ia32_is_reload(irn))
203 classification |= arch_irn_class_reload;
205 if (is_ia32_is_spill(irn))
206 classification |= arch_irn_class_spill;
208 if (is_ia32_is_remat(irn))
209 classification |= arch_irn_class_remat;
211 return classification;
215 * The IA32 ABI callback object.
218 be_abi_call_flags_bits_t flags; /**< The call flags. */
219 ir_graph *irg; /**< The associated graph. */
222 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
224 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
227 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
229 if (is_be_node(node))
230 be_node_set_frame_entity(node, entity);
232 set_ia32_frame_ent(node, entity);
235 static void ia32_set_frame_offset(ir_node *irn, int bias)
237 if (get_ia32_frame_ent(irn) == NULL)
240 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
241 ir_graph *irg = get_irn_irg(irn);
242 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
243 if (layout->sp_relative) {
244 /* Pop nodes modify the stack pointer before calculating the
245 * destination address, so fix this here
250 add_ia32_am_offs_int(irn, bias);
253 static int ia32_get_sp_bias(const ir_node *node)
255 if (is_ia32_Call(node))
256 return -(int)get_ia32_call_attr_const(node)->pop;
258 if (is_ia32_Push(node))
261 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
264 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
265 return SP_BIAS_RESET;
272 * Build the between type and entities if not already build.
274 static void ia32_build_between_type(void)
276 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
277 if (! between_type) {
278 ir_type *old_bp_type = new_type_primitive(mode_Iu);
279 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
281 between_type = new_type_struct(IDENT("ia32_between_type"));
282 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
283 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
285 set_entity_offset(old_bp_ent, 0);
286 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
287 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
288 set_type_state(between_type, layout_fixed);
290 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
291 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
293 set_entity_offset(omit_fp_ret_addr_ent, 0);
294 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
295 set_type_state(omit_fp_between_type, layout_fixed);
301 * Produces the type which sits between the stack args and the locals on the stack.
302 * it will contain the return address and space to store the old base pointer.
303 * @return The Firm type modeling the ABI between type.
305 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
307 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
308 ia32_build_between_type();
309 return layout->sp_relative ? omit_fp_between_type : between_type;
313 * Return the stack entity that contains the return address.
315 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
317 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
318 ia32_build_between_type();
319 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
323 * Return the stack entity that contains the frame address.
325 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
327 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
328 ia32_build_between_type();
329 return layout->sp_relative ? NULL : old_bp_ent;
333 * Get the estimated cycle count for @p irn.
335 * @param self The this pointer.
336 * @param irn The node.
338 * @return The estimated cycle count for this operation
340 static int ia32_get_op_estimated_cost(const ir_node *irn)
343 ia32_op_type_t op_tp;
347 if (!is_ia32_irn(irn))
350 assert(is_ia32_irn(irn));
352 cost = get_ia32_latency(irn);
353 op_tp = get_ia32_op_type(irn);
355 if (is_ia32_CopyB(irn)) {
358 else if (is_ia32_CopyB_i(irn)) {
359 int size = get_ia32_copyb_size(irn);
360 cost = 20 + (int)ceil((4/3) * size);
362 /* in case of address mode operations add additional cycles */
363 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
365 In case of stack access and access to fixed addresses add 5 cycles
366 (we assume they are in cache), other memory operations cost 20
369 if (is_ia32_use_frame(irn) || (
370 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
371 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
383 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
385 * @param irn The original operation
386 * @param i Index of the argument we want the inverse operation to yield
387 * @param inverse struct to be filled with the resulting inverse op
388 * @param obstack The obstack to use for allocation of the returned nodes array
389 * @return The inverse operation or NULL if operation invertible
391 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
402 ir_node *block, *noreg, *nomem;
405 /* we cannot invert non-ia32 irns */
406 if (! is_ia32_irn(irn))
409 /* operand must always be a real operand (not base, index or mem) */
410 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
413 /* we don't invert address mode operations */
414 if (get_ia32_op_type(irn) != ia32_Normal)
417 /* TODO: adjust for new immediates... */
418 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
422 block = get_nodes_block(irn);
423 mode = get_irn_mode(irn);
424 irn_mode = get_irn_mode(irn);
425 noreg = get_irn_n(irn, 0);
426 nomem = get_irg_no_mem(irg);
427 dbgi = get_irn_dbg_info(irn);
429 /* initialize structure */
430 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
434 switch (get_ia32_irn_opcode(irn)) {
436 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
437 /* we have an add with a const here */
438 /* invers == add with negated const */
439 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
441 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
442 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
443 set_ia32_commutative(inverse->nodes[0]);
445 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
446 /* we have an add with a symconst here */
447 /* invers == sub with const */
448 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
450 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
453 /* normal add: inverse == sub */
454 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
459 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
460 /* we have a sub with a const/symconst here */
461 /* invers == add with this const */
462 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
463 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
464 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
468 if (i == n_ia32_binary_left) {
469 inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
472 inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
478 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
479 /* xor with const: inverse = xor */
480 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
481 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
482 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
486 inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
491 inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
496 inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
501 /* inverse operation not supported */
509 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
511 if (mode_is_float(mode))
518 * Get the mode that should be used for spilling value node
520 static ir_mode *get_spill_mode(const ir_node *node)
522 ir_mode *mode = get_irn_mode(node);
523 return get_spill_mode_mode(mode);
527 * Checks whether an addressmode reload for a node with mode mode is compatible
528 * with a spillslot of mode spill_mode
530 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
532 return !mode_is_float(mode) || mode == spillmode;
536 * Check if irn can load its operand at position i from memory (source addressmode).
537 * @param irn The irn to be checked
538 * @param i The operands position
539 * @return Non-Zero if operand can be loaded
541 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
543 ir_node *op = get_irn_n(irn, i);
544 const ir_mode *mode = get_irn_mode(op);
545 const ir_mode *spillmode = get_spill_mode(op);
547 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
548 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
549 !ia32_is_spillmode_compatible(mode, spillmode) ||
550 is_ia32_use_frame(irn)) /* must not already use frame */
553 switch (get_ia32_am_support(irn)) {
558 if (i != n_ia32_unary_op)
564 case n_ia32_binary_left: {
565 const arch_register_req_t *req;
566 if (!is_ia32_commutative(irn))
569 /* we can't swap left/right for limited registers
570 * (As this (currently) breaks constraint handling copies)
572 req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
573 if (req->type & arch_register_req_type_limited)
578 case n_ia32_binary_right:
587 panic("Unknown AM type");
590 /* HACK: must not already use "real" memory.
591 * This can happen for Call and Div */
592 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
598 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
602 ir_mode *dest_op_mode;
604 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
606 set_ia32_op_type(irn, ia32_AddrModeS);
608 load_mode = get_irn_mode(get_irn_n(irn, i));
609 dest_op_mode = get_ia32_ls_mode(irn);
610 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
611 set_ia32_ls_mode(irn, load_mode);
613 set_ia32_use_frame(irn);
614 set_ia32_need_stackent(irn);
616 if (i == n_ia32_binary_left &&
617 get_ia32_am_support(irn) == ia32_am_binary &&
618 /* immediates are only allowed on the right side */
619 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
620 ia32_swap_left_right(irn);
621 i = n_ia32_binary_right;
624 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
626 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
627 set_irn_n(irn, n_ia32_mem, spill);
628 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
629 set_ia32_is_reload(irn);
632 static const be_abi_callbacks_t ia32_abi_callbacks = {
633 ia32_abi_get_between_type,
636 /* register allocator interface */
637 static const arch_irn_ops_t ia32_irn_ops = {
639 ia32_get_frame_entity,
640 ia32_set_frame_offset,
643 ia32_get_op_estimated_cost,
644 ia32_possible_memory_operand,
645 ia32_perform_memory_operand,
648 static ir_entity *mcount = NULL;
649 static int gprof = 0;
651 static void ia32_before_abi(ir_graph *irg)
654 if (mcount == NULL) {
655 ir_type *tp = new_type_method(0, 0);
656 ident *id = new_id_from_str("mcount");
657 mcount = new_entity(get_glob_type(), id, tp);
658 /* FIXME: enter the right ld_ident here */
659 set_entity_ld_ident(mcount, get_entity_ident(mcount));
660 set_entity_visibility(mcount, ir_visibility_external);
662 instrument_initcall(irg, mcount);
667 * Transforms the standard firm graph into
670 static void ia32_prepare_graph(ir_graph *irg)
672 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
675 switch (be_transformer) {
676 case TRANSFORMER_DEFAULT:
677 /* transform remaining nodes into assembler instructions */
678 ia32_transform_graph(irg);
681 case TRANSFORMER_PBQP:
682 case TRANSFORMER_RAND:
683 /* transform nodes into assembler instructions by PBQP magic */
684 ia32_transform_graph_by_pbqp(irg);
688 panic("invalid transformer");
691 ia32_transform_graph(irg);
694 /* do local optimizations (mainly CSE) */
695 optimize_graph_df(irg);
696 /* backend code expects that outedges are always enabled */
700 dump_ir_graph(irg, "transformed");
702 /* optimize address mode */
703 ia32_optimize_graph(irg);
705 /* do code placement, to optimize the position of constants */
707 /* backend code expects that outedges are always enabled */
711 dump_ir_graph(irg, "place");
714 ir_node *ia32_turn_back_am(ir_node *node)
716 dbg_info *dbgi = get_irn_dbg_info(node);
717 ir_graph *irg = get_irn_irg(node);
718 ir_node *block = get_nodes_block(node);
719 ir_node *base = get_irn_n(node, n_ia32_base);
720 ir_node *idx = get_irn_n(node, n_ia32_index);
721 ir_node *mem = get_irn_n(node, n_ia32_mem);
724 ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
725 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
727 ia32_copy_am_attrs(load, node);
728 if (is_ia32_is_reload(node))
729 set_ia32_is_reload(load);
730 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
732 switch (get_ia32_am_support(node)) {
734 set_irn_n(node, n_ia32_unary_op, load_res);
738 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
739 set_irn_n(node, n_ia32_binary_left, load_res);
741 set_irn_n(node, n_ia32_binary_right, load_res);
746 panic("Unknown AM type");
748 noreg = ia32_new_NoReg_gp(current_ir_graph);
749 set_irn_n(node, n_ia32_base, noreg);
750 set_irn_n(node, n_ia32_index, noreg);
751 set_ia32_am_offs_int(node, 0);
752 set_ia32_am_sc(node, NULL);
753 set_ia32_am_scale(node, 0);
754 clear_ia32_am_sc_sign(node);
756 /* rewire mem-proj */
757 if (get_irn_mode(node) == mode_T) {
758 const ir_edge_t *edge;
759 foreach_out_edge(node, edge) {
760 ir_node *out = get_edge_src_irn(edge);
761 if (get_irn_mode(out) == mode_M) {
762 set_Proj_pred(out, load);
763 set_Proj_proj(out, pn_ia32_Load_M);
769 set_ia32_op_type(node, ia32_Normal);
770 if (sched_is_scheduled(node))
771 sched_add_before(node, load);
776 static ir_node *flags_remat(ir_node *node, ir_node *after)
778 /* we should turn back source address mode when rematerializing nodes */
783 if (is_Block(after)) {
786 block = get_nodes_block(after);
789 type = get_ia32_op_type(node);
792 ia32_turn_back_am(node);
796 /* TODO implement this later... */
797 panic("found DestAM with flag user %+F this should not happen", node);
799 default: assert(type == ia32_Normal); break;
802 copy = exact_copy(node);
803 set_nodes_block(copy, block);
804 sched_add_after(after, copy);
810 * Called before the register allocator.
812 static void ia32_before_ra(ir_graph *irg)
814 /* setup fpu rounding modes */
815 ia32_setup_fpu_mode(irg);
818 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
821 be_add_missing_keeps(irg);
826 * Transforms a be_Reload into a ia32 Load.
828 static void transform_to_Load(ir_node *node)
830 ir_graph *irg = get_irn_irg(node);
831 dbg_info *dbgi = get_irn_dbg_info(node);
832 ir_node *block = get_nodes_block(node);
833 ir_entity *ent = be_get_frame_entity(node);
834 ir_mode *mode = get_irn_mode(node);
835 ir_mode *spillmode = get_spill_mode(node);
836 ir_node *noreg = ia32_new_NoReg_gp(irg);
837 ir_node *sched_point = NULL;
838 ir_node *ptr = get_irg_frame(irg);
839 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
840 ir_node *new_op, *proj;
841 const arch_register_t *reg;
843 if (sched_is_scheduled(node)) {
844 sched_point = sched_prev(node);
847 if (mode_is_float(spillmode)) {
848 if (ia32_cg_config.use_sse2)
849 new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
851 new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
853 else if (get_mode_size_bits(spillmode) == 128) {
854 /* Reload 128 bit SSE registers */
855 new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
858 new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
860 set_ia32_op_type(new_op, ia32_AddrModeS);
861 set_ia32_ls_mode(new_op, spillmode);
862 set_ia32_frame_ent(new_op, ent);
863 set_ia32_use_frame(new_op);
864 set_ia32_is_reload(new_op);
866 DBG_OPT_RELOAD2LD(node, new_op);
868 proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
871 sched_add_after(sched_point, new_op);
875 /* copy the register from the old node to the new Load */
876 reg = arch_get_irn_register(node);
877 arch_set_irn_register(proj, reg);
879 SET_IA32_ORIG_NODE(new_op, node);
881 exchange(node, proj);
885 * Transforms a be_Spill node into a ia32 Store.
887 static void transform_to_Store(ir_node *node)
889 ir_graph *irg = get_irn_irg(node);
890 dbg_info *dbgi = get_irn_dbg_info(node);
891 ir_node *block = get_nodes_block(node);
892 ir_entity *ent = be_get_frame_entity(node);
893 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
894 ir_mode *mode = get_spill_mode(spillval);
895 ir_node *noreg = ia32_new_NoReg_gp(irg);
896 ir_node *nomem = get_irg_no_mem(irg);
897 ir_node *ptr = get_irg_frame(irg);
898 ir_node *val = get_irn_n(node, n_be_Spill_val);
901 ir_node *sched_point = NULL;
903 if (sched_is_scheduled(node)) {
904 sched_point = sched_prev(node);
907 if (mode_is_float(mode)) {
908 if (ia32_cg_config.use_sse2) {
909 store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
910 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
912 store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
913 res = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
915 } else if (get_mode_size_bits(mode) == 128) {
916 /* Spill 128 bit SSE registers */
917 store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
918 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
919 } else if (get_mode_size_bits(mode) == 8) {
920 store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
921 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
923 store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
924 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
927 set_ia32_op_type(store, ia32_AddrModeD);
928 set_ia32_ls_mode(store, mode);
929 set_ia32_frame_ent(store, ent);
930 set_ia32_use_frame(store);
931 set_ia32_is_spill(store);
932 SET_IA32_ORIG_NODE(store, node);
933 DBG_OPT_SPILL2ST(node, store);
936 sched_add_after(sched_point, store);
943 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
945 dbg_info *dbgi = get_irn_dbg_info(node);
946 ir_node *block = get_nodes_block(node);
947 ir_graph *irg = get_irn_irg(node);
948 ir_node *noreg = ia32_new_NoReg_gp(irg);
949 ir_node *frame = get_irg_frame(irg);
951 ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
953 set_ia32_frame_ent(push, ent);
954 set_ia32_use_frame(push);
955 set_ia32_op_type(push, ia32_AddrModeS);
956 set_ia32_ls_mode(push, mode_Is);
957 set_ia32_is_spill(push);
959 sched_add_before(schedpoint, push);
963 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
965 dbg_info *dbgi = get_irn_dbg_info(node);
966 ir_node *block = get_nodes_block(node);
967 ir_graph *irg = get_irn_irg(node);
968 ir_node *noreg = ia32_new_NoReg_gp(irg);
969 ir_node *frame = get_irg_frame(irg);
971 ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
972 get_irg_no_mem(irg), sp);
974 set_ia32_frame_ent(pop, ent);
975 set_ia32_use_frame(pop);
976 set_ia32_op_type(pop, ia32_AddrModeD);
977 set_ia32_ls_mode(pop, mode_Is);
978 set_ia32_is_reload(pop);
980 sched_add_before(schedpoint, pop);
985 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
987 dbg_info *dbgi = get_irn_dbg_info(node);
988 ir_mode *spmode = mode_Iu;
989 const arch_register_t *spreg = &ia32_registers[REG_ESP];
992 sp = new_rd_Proj(dbgi, pred, spmode, pos);
993 arch_set_irn_register(sp, spreg);
999 * Transform MemPerm, currently we do this the ugly way and produce
1000 * push/pop into/from memory cascades. This is possible without using
1003 static void transform_MemPerm(ir_node *node)
1005 ir_node *block = get_nodes_block(node);
1006 ir_graph *irg = get_irn_irg(node);
1007 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
1008 int arity = be_get_MemPerm_entity_arity(node);
1009 ir_node **pops = ALLOCAN(ir_node*, arity);
1013 const ir_edge_t *edge;
1014 const ir_edge_t *next;
1017 for (i = 0; i < arity; ++i) {
1018 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1019 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1020 ir_type *enttype = get_entity_type(inent);
1021 unsigned entsize = get_type_size_bytes(enttype);
1022 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1023 ir_node *mem = get_irn_n(node, i + 1);
1026 /* work around cases where entities have different sizes */
1027 if (entsize2 < entsize)
1029 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1031 push = create_push(node, node, sp, mem, inent);
1032 sp = create_spproj(node, push, pn_ia32_Push_stack);
1034 /* add another push after the first one */
1035 push = create_push(node, node, sp, mem, inent);
1036 add_ia32_am_offs_int(push, 4);
1037 sp = create_spproj(node, push, pn_ia32_Push_stack);
1040 set_irn_n(node, i, new_r_Bad(irg, mode_X));
1044 for (i = arity - 1; i >= 0; --i) {
1045 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1046 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1047 ir_type *enttype = get_entity_type(outent);
1048 unsigned entsize = get_type_size_bytes(enttype);
1049 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1052 /* work around cases where entities have different sizes */
1053 if (entsize2 < entsize)
1055 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1057 pop = create_pop(node, node, sp, outent);
1058 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1060 add_ia32_am_offs_int(pop, 4);
1062 /* add another pop after the first one */
1063 pop = create_pop(node, node, sp, outent);
1064 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1071 keep = be_new_Keep(block, 1, in);
1072 sched_add_before(node, keep);
1074 /* exchange memprojs */
1075 foreach_out_edge_safe(node, edge, next) {
1076 ir_node *proj = get_edge_src_irn(edge);
1077 int p = get_Proj_proj(proj);
1081 set_Proj_pred(proj, pops[p]);
1082 set_Proj_proj(proj, pn_ia32_Pop_M);
1085 /* remove memperm */
1091 * Block-Walker: Calls the transform functions Spill and Reload.
1093 static void ia32_after_ra_walker(ir_node *block, void *env)
1095 ir_node *node, *prev;
1098 /* beware: the schedule is changed here */
1099 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1100 prev = sched_prev(node);
1102 if (be_is_Reload(node)) {
1103 transform_to_Load(node);
1104 } else if (be_is_Spill(node)) {
1105 transform_to_Store(node);
1106 } else if (be_is_MemPerm(node)) {
1107 transform_MemPerm(node);
1113 * Collects nodes that need frame entities assigned.
1115 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1117 be_fec_env_t *env = (be_fec_env_t*)data;
1118 const ir_mode *mode;
1121 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1122 mode = get_spill_mode_mode(get_irn_mode(node));
1123 align = get_mode_size_bytes(mode);
1124 } else if (is_ia32_irn(node) &&
1125 get_ia32_frame_ent(node) == NULL &&
1126 is_ia32_use_frame(node)) {
1127 if (is_ia32_need_stackent(node))
1130 switch (get_ia32_irn_opcode(node)) {
1132 case iro_ia32_Load: {
1133 const ia32_attr_t *attr = get_ia32_attr_const(node);
1135 if (attr->data.need_32bit_stackent) {
1137 } else if (attr->data.need_64bit_stackent) {
1140 mode = get_ia32_ls_mode(node);
1141 if (is_ia32_is_reload(node))
1142 mode = get_spill_mode_mode(mode);
1144 align = get_mode_size_bytes(mode);
1148 case iro_ia32_vfild:
1150 case iro_ia32_xLoad: {
1151 mode = get_ia32_ls_mode(node);
1156 case iro_ia32_FldCW: {
1157 /* although 2 byte would be enough 4 byte performs best */
1165 panic("unexpected frame user while collection frame entity nodes");
1167 case iro_ia32_FnstCW:
1168 case iro_ia32_Store8Bit:
1169 case iro_ia32_Store:
1172 case iro_ia32_vfist:
1173 case iro_ia32_vfisttp:
1175 case iro_ia32_xStore:
1176 case iro_ia32_xStoreSimple:
1183 be_node_needs_frame_entity(env, node, mode, align);
1186 static int determine_ebp_input(ir_node *ret)
1188 const arch_register_t *bp = &ia32_registers[REG_EBP];
1189 int arity = get_irn_arity(ret);
1192 for (i = 0; i < arity; ++i) {
1193 ir_node *input = get_irn_n(ret, i);
1194 if (arch_get_irn_register(input) == bp)
1197 panic("no ebp input found at %+F", ret);
1200 static void introduce_epilog(ir_node *ret)
1202 const arch_register_t *sp = &ia32_registers[REG_ESP];
1203 const arch_register_t *bp = &ia32_registers[REG_EBP];
1204 ir_graph *irg = get_irn_irg(ret);
1205 ir_type *frame_type = get_irg_frame_type(irg);
1206 unsigned frame_size = get_type_size_bytes(frame_type);
1207 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1208 ir_node *block = get_nodes_block(ret);
1209 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1210 ir_node *curr_sp = first_sp;
1211 ir_mode *mode_gp = mode_Iu;
1213 if (!layout->sp_relative) {
1214 int n_ebp = determine_ebp_input(ret);
1215 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1216 if (ia32_cg_config.use_leave) {
1217 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1218 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1219 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1220 arch_set_irn_register(curr_bp, bp);
1221 arch_set_irn_register(curr_sp, sp);
1222 sched_add_before(ret, leave);
1225 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1226 /* copy ebp to esp */
1227 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1228 arch_set_irn_register(curr_sp, sp);
1229 sched_add_before(ret, curr_sp);
1232 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1233 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1234 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1235 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1236 arch_set_irn_register(curr_bp, bp);
1237 arch_set_irn_register(curr_sp, sp);
1238 sched_add_before(ret, pop);
1240 set_irn_n(ret, n_be_Return_mem, curr_mem);
1242 set_irn_n(ret, n_ebp, curr_bp);
1244 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1245 sched_add_before(ret, incsp);
1248 set_irn_n(ret, n_be_Return_sp, curr_sp);
1250 /* keep verifier happy... */
1251 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1252 kill_node(first_sp);
1257 * put the Prolog code at the beginning, epilog code before each return
1259 static void introduce_prolog_epilog(ir_graph *irg)
1261 const arch_register_t *sp = &ia32_registers[REG_ESP];
1262 const arch_register_t *bp = &ia32_registers[REG_EBP];
1263 ir_node *start = get_irg_start(irg);
1264 ir_node *block = get_nodes_block(start);
1265 ir_type *frame_type = get_irg_frame_type(irg);
1266 unsigned frame_size = get_type_size_bytes(frame_type);
1267 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1268 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1269 ir_node *curr_sp = initial_sp;
1270 ir_mode *mode_gp = mode_Iu;
1272 if (!layout->sp_relative) {
1274 ir_node *mem = get_irg_initial_mem(irg);
1275 ir_node *noreg = ia32_new_NoReg_gp(irg);
1276 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1277 ir_node *curr_bp = initial_bp;
1278 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
1281 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1282 mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
1283 arch_set_irn_register(curr_sp, sp);
1284 sched_add_after(start, push);
1286 /* move esp to ebp */
1287 curr_bp = be_new_Copy(block, curr_sp);
1288 sched_add_after(push, curr_bp);
1289 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1290 curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
1291 sched_add_after(curr_bp, curr_sp);
1292 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1293 edges_reroute(initial_bp, curr_bp);
1294 set_irn_n(push, n_ia32_Push_val, initial_bp);
1296 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1297 edges_reroute(initial_sp, incsp);
1298 set_irn_n(push, n_ia32_Push_stack, initial_sp);
1299 sched_add_after(curr_sp, incsp);
1301 /* make sure the initial IncSP is really used by someone */
1302 if (get_irn_n_edges(incsp) <= 1) {
1303 ir_node *in[] = { incsp };
1304 ir_node *keep = be_new_Keep(block, 1, in);
1305 sched_add_after(incsp, keep);
1308 layout->initial_bias = -4;
1310 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1311 edges_reroute(initial_sp, incsp);
1312 be_set_IncSP_pred(incsp, curr_sp);
1313 sched_add_after(start, incsp);
1316 /* introduce epilog for every return node */
1318 ir_node *end_block = get_irg_end_block(irg);
1319 int arity = get_irn_arity(end_block);
1322 for (i = 0; i < arity; ++i) {
1323 ir_node *ret = get_irn_n(end_block, i);
1324 assert(be_is_Return(ret));
1325 introduce_epilog(ret);
1331 * Last touchups for the graph before emit: x87 simulation to replace the
1332 * virtual with real x87 instructions, creating a block schedule and peephole
1335 static void ia32_finish(ir_graph *irg)
1337 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1338 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1339 bool at_begin = stack_layout->sp_relative ? true : false;
1340 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1342 /* create and coalesce frame entities */
1343 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1344 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1345 be_free_frame_entity_coalescer(fec_env);
1347 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1349 introduce_prolog_epilog(irg);
1351 /* fix stack entity offsets */
1352 be_abi_fix_stack_nodes(irg);
1353 be_abi_fix_stack_bias(irg);
1355 /* fix 2-address code constraints */
1356 ia32_finish_irg(irg);
1358 /* we might have to rewrite x87 virtual registers */
1359 if (irg_data->do_x87_sim) {
1360 ia32_x87_simulate_graph(irg);
1363 /* do peephole optimisations */
1364 ia32_peephole_optimization(irg);
1366 be_remove_dead_nodes_from_schedule(irg);
1368 /* create block schedule, this also removes empty blocks which might
1369 * produce critical edges */
1370 irg_data->blk_sched = be_create_block_schedule(irg);
1374 * Emits the code, closes the output file and frees
1375 * the code generator interface.
1377 static void ia32_emit(ir_graph *irg)
1379 if (ia32_cg_config.emit_machcode) {
1380 ia32_gen_binary_routine(irg);
1382 ia32_gen_routine(irg);
1387 * Returns the node representing the PIC base.
1389 static ir_node *ia32_get_pic_base(ir_graph *irg)
1391 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1393 ir_node *get_eip = irg_data->get_eip;
1394 if (get_eip != NULL)
1397 block = get_irg_start_block(irg);
1398 get_eip = new_bd_ia32_GetEIP(NULL, block);
1399 irg_data->get_eip = get_eip;
1405 * Initializes a IA32 code generator.
1407 static void ia32_init_graph(ir_graph *irg)
1409 struct obstack *obst = be_get_be_obst(irg);
1410 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1412 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1415 /* Linux gprof implementation needs base pointer */
1416 be_get_irg_options(irg)->omit_fp = 0;
1419 be_birg_from_irg(irg)->isa_link = irg_data;
1424 * Set output modes for GCC
1426 static const tarval_mode_info mo_integer = {
1433 * set the tarval output mode of all integer modes to decimal
1435 static void set_tarval_output_modes(void)
1439 for (i = get_irp_n_modes(); i > 0;) {
1440 ir_mode *mode = get_irp_mode(--i);
1442 if (mode_is_int(mode))
1443 set_tarval_mode_output_option(mode, &mo_integer);
1447 extern const arch_isa_if_t ia32_isa_if;
1450 * The template that generates a new ISA object.
1451 * Note that this template can be changed by command line
1454 static ia32_isa_t ia32_isa_template = {
1456 &ia32_isa_if, /* isa interface implementation */
1461 &ia32_registers[REG_ESP], /* stack pointer register */
1462 &ia32_registers[REG_EBP], /* base pointer register */
1463 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1464 2, /* power of two stack alignment, 2^2 == 4 */
1465 NULL, /* main environment */
1466 7, /* costs for a spill instruction */
1467 5, /* costs for a reload instruction */
1468 false, /* no custom abi handling */
1471 NULL, /* abstract machine */
1472 IA32_FPU_ARCH_X87, /* FPU architecture */
1475 static void init_asm_constraints(void)
1477 be_init_default_asm_constraint_flags();
1479 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1480 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1481 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1482 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1483 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1484 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1485 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1486 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1487 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1488 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1489 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1490 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1491 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1492 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1493 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1494 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1495 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1496 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1497 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1498 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1500 /* no support for autodecrement/autoincrement */
1501 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1502 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1503 /* no float consts */
1504 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1505 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1506 /* makes no sense on x86 */
1507 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1508 /* no support for sse consts yet */
1509 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1510 /* no support for x87 consts yet */
1511 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1512 /* no support for mmx registers yet */
1513 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1514 /* not available in 32bit mode */
1515 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1516 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1518 /* no code yet to determine register class needed... */
1519 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1523 * Initializes the backend ISA.
1525 static arch_env_t *ia32_init(const be_main_env_t *env)
1527 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1529 set_tarval_output_modes();
1531 *isa = ia32_isa_template;
1533 if (ia32_mode_fpcw == NULL) {
1534 ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0);
1537 ia32_register_init();
1538 ia32_create_opcodes(&ia32_irn_ops);
1540 isa->tv_ent = pmap_create();
1541 isa->cpu = ia32_init_machine_description();
1543 /* enter the ISA object into the intrinsic environment */
1544 intrinsic_env.isa = isa;
1546 be_emit_init(env->file_handle);
1547 be_gas_begin_compilation_unit(env);
1553 * Closes the output file and frees the ISA structure.
1555 static void ia32_done(void *self)
1557 ia32_isa_t *isa = (ia32_isa_t*)self;
1559 /* emit now all global declarations */
1560 be_gas_end_compilation_unit(isa->base.main_env);
1564 pmap_destroy(isa->tv_ent);
1570 * Get the register class which shall be used to store a value of a given mode.
1571 * @param self The this pointer.
1572 * @param mode The mode in question.
1573 * @return A register class which can hold values of the given mode.
1575 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1577 if (mode_is_float(mode)) {
1578 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1581 return &ia32_reg_classes[CLASS_ia32_gp];
1585 * Returns the register for parameter nr.
1587 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1588 const ir_mode *mode)
1590 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1591 &ia32_registers[REG_ECX],
1592 &ia32_registers[REG_EDX],
1595 static const unsigned MAXNUM_GPREG_ARGS = 3;
1597 static const arch_register_t *gpreg_param_reg_regparam[] = {
1598 &ia32_registers[REG_EAX],
1599 &ia32_registers[REG_EDX],
1600 &ia32_registers[REG_ECX]
1603 static const arch_register_t *gpreg_param_reg_this[] = {
1604 &ia32_registers[REG_ECX],
1609 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1610 &ia32_registers[REG_XMM0],
1611 &ia32_registers[REG_XMM1],
1612 &ia32_registers[REG_XMM2],
1613 &ia32_registers[REG_XMM3],
1614 &ia32_registers[REG_XMM4],
1615 &ia32_registers[REG_XMM5],
1616 &ia32_registers[REG_XMM6],
1617 &ia32_registers[REG_XMM7]
1620 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1621 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1623 static const unsigned MAXNUM_SSE_ARGS = 8;
1625 if ((cc & cc_this_call) && nr == 0)
1626 return gpreg_param_reg_this[0];
1628 if (! (cc & cc_reg_param))
1631 if (mode_is_float(mode)) {
1632 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1634 if (nr >= MAXNUM_SSE_ARGS)
1637 if (cc & cc_this_call) {
1638 return fpreg_sse_param_reg_this[nr];
1640 return fpreg_sse_param_reg_std[nr];
1641 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1642 unsigned num_regparam;
1644 if (get_mode_size_bits(mode) > 32)
1647 if (nr >= MAXNUM_GPREG_ARGS)
1650 if (cc & cc_this_call) {
1651 return gpreg_param_reg_this[nr];
1653 num_regparam = cc & ~cc_bits;
1654 if (num_regparam == 0) {
1655 /* default fastcall */
1656 return gpreg_param_reg_fastcall[nr];
1658 if (nr < num_regparam)
1659 return gpreg_param_reg_regparam[nr];
1663 panic("unknown argument mode");
1667 * Get the ABI restrictions for procedure calls.
1668 * @param self The this pointer.
1669 * @param method_type The type of the method (procedure) in question.
1670 * @param abi The abi object to be modified
1672 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1678 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1682 /* set abi flags for calls */
1683 call_flags.bits.store_args_sequential = 0;
1684 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1685 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1686 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1688 /* set parameter passing style */
1689 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1691 cc = get_method_calling_convention(method_type);
1692 if (get_method_variadicity(method_type) == variadicity_variadic) {
1693 /* pass all parameters of a variadic function on the stack */
1694 cc = cc_cdecl_set | (cc & cc_this_call);
1696 if (get_method_additional_properties(method_type) & mtp_property_private &&
1697 ia32_cg_config.optimize_cc) {
1698 /* set the fast calling conventions (allowing up to 3) */
1699 cc = SET_FASTCALL(cc) | 3;
1703 /* we have to pop the shadow parameter ourself for compound calls */
1704 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1705 && !(cc & cc_reg_param)) {
1706 pop_amount += get_mode_size_bytes(mode_P_data);
1709 n = get_method_n_params(method_type);
1710 for (i = regnum = 0; i < n; i++) {
1711 const arch_register_t *reg = NULL;
1712 ir_type *tp = get_method_param_type(method_type, i);
1713 ir_mode *mode = get_type_mode(tp);
1716 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1719 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1722 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1723 * movl has a shorter opcode than mov[sz][bw]l */
1724 ir_mode *load_mode = mode;
1727 unsigned size = get_mode_size_bytes(mode);
1729 if (cc & cc_callee_clear_stk) {
1730 pop_amount += (size + 3U) & ~3U;
1733 if (size < 4) load_mode = mode_Iu;
1736 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1740 be_abi_call_set_pop(abi, pop_amount);
1742 /* set return registers */
1743 n = get_method_n_ress(method_type);
1745 assert(n <= 2 && "more than two results not supported");
1747 /* In case of 64bit returns, we will have two 32bit values */
1749 ir_type *tp = get_method_res_type(method_type, 0);
1750 ir_mode *mode = get_type_mode(tp);
1752 assert(!mode_is_float(mode) && "two FP results not supported");
1754 tp = get_method_res_type(method_type, 1);
1755 mode = get_type_mode(tp);
1757 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1759 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1760 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1763 ir_type *tp = get_method_res_type(method_type, 0);
1764 ir_mode *mode = get_type_mode(tp);
1765 const arch_register_t *reg;
1766 assert(is_atomic_type(tp));
1768 reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
1770 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1775 * Returns the necessary byte alignment for storing a register of given class.
1777 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1779 ir_mode *mode = arch_register_class_mode(cls);
1780 int bytes = get_mode_size_bytes(mode);
1782 if (mode_is_float(mode) && bytes > 8)
1788 * Return irp irgs in the desired order.
1790 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1797 static void ia32_mark_remat(ir_node *node)
1799 if (is_ia32_irn(node)) {
1800 set_ia32_is_remat(node);
1805 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1807 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1812 ir_relation relation;
1817 cmp_l = get_Cmp_left(sel);
1818 cmp_r = get_Cmp_right(sel);
1819 if (!mode_is_float(get_irn_mode(cmp_l)))
1822 /* check for min/max. They're defined as (C-Semantik):
1823 * min(a, b) = a < b ? a : b
1824 * or min(a, b) = a <= b ? a : b
1825 * max(a, b) = a > b ? a : b
1826 * or max(a, b) = a >= b ? a : b
1827 * (Note we only handle float min/max here)
1829 relation = get_Cmp_relation(sel);
1831 case ir_relation_greater_equal:
1832 case ir_relation_greater:
1834 if (cmp_l == mux_true && cmp_r == mux_false)
1837 case ir_relation_less_equal:
1838 case ir_relation_less:
1840 if (cmp_l == mux_true && cmp_r == mux_false)
1843 case ir_relation_unordered_greater_equal:
1844 case ir_relation_unordered_greater:
1846 if (cmp_l == mux_false && cmp_r == mux_true)
1849 case ir_relation_unordered_less_equal:
1850 case ir_relation_unordered_less:
1852 if (cmp_l == mux_false && cmp_r == mux_true)
1863 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1865 ir_mode *mode = get_irn_mode(mux_true);
1868 if (!mode_is_int(mode) && !mode_is_reference(mode)
1872 if (is_Const(mux_true) && is_Const(mux_false)) {
1873 /* we can create a set plus up two 3 instructions for any combination
1881 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1886 if (!mode_is_float(get_irn_mode(mux_true)))
1889 return is_Const(mux_true) && is_Const(mux_false);
1892 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1899 ir_relation relation;
1904 mode = get_irn_mode(mux_true);
1905 if (mode_is_signed(mode) || mode_is_float(mode))
1908 relation = get_Cmp_relation(sel);
1909 cmp_left = get_Cmp_left(sel);
1910 cmp_right = get_Cmp_right(sel);
1912 /* "move" zero constant to false input */
1913 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1914 ir_node *tmp = mux_false;
1915 mux_false = mux_true;
1917 relation = get_negated_relation(relation);
1919 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1921 if (!is_Sub(mux_true))
1923 sub_left = get_Sub_left(mux_true);
1924 sub_right = get_Sub_right(mux_true);
1926 /* Mux(a >=u b, 0, a-b) */
1927 if ((relation & ir_relation_greater)
1928 && sub_left == cmp_left && sub_right == cmp_right)
1930 /* Mux(a <=u b, 0, b-a) */
1931 if ((relation & ir_relation_less)
1932 && sub_left == cmp_right && sub_right == cmp_left)
1938 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1943 /* middleend can handle some things */
1944 if (ir_is_optimizable_mux(sel, mux_false, mux_true))
1946 /* we can handle Set for all modes and compares */
1947 if (mux_is_set(sel, mux_true, mux_false))
1949 /* SSE has own min/max operations */
1950 if (ia32_cg_config.use_sse2
1951 && mux_is_float_min_max(sel, mux_true, mux_false))
1953 /* we can handle Mux(?, Const[f], Const[f]) */
1954 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1955 #ifdef FIRM_GRGEN_BE
1956 /* well, some code selectors can't handle it */
1957 if (be_transformer != TRANSFORMER_PBQP
1958 || be_transformer != TRANSFORMER_RAND)
1965 /* no support for 64bit inputs to cmov */
1966 mode = get_irn_mode(mux_true);
1967 if (get_mode_size_bits(mode) > 32)
1969 /* we can handle Abs for all modes and compares (except 64bit) */
1970 if (ir_mux_is_abs(sel, mux_false, mux_true) != 0)
1972 /* we can't handle MuxF yet */
1973 if (mode_is_float(mode))
1976 if (mux_is_doz(sel, mux_true, mux_false))
1979 /* Check Cmp before the node */
1981 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1983 /* we can't handle 64bit compares */
1984 if (get_mode_size_bits(cmp_mode) > 32)
1987 /* we can't handle float compares */
1988 if (mode_is_float(cmp_mode))
1992 /* did we disable cmov generation? */
1993 if (!ia32_cg_config.use_cmov)
1996 /* we can use a cmov */
2000 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2004 /* we already added all our simple flags to the flags modifier list in
2005 * init, so this flag we don't know. */
2006 return ASM_CONSTRAINT_FLAG_INVALID;
2009 static int ia32_is_valid_clobber(const char *clobber)
2011 return ia32_get_clobber_register(clobber) != NULL;
2014 static void ia32_lower_for_target(void)
2016 size_t i, n_irgs = get_irp_n_irgs();
2018 /* perform doubleword lowering */
2019 lwrdw_param_t lower_dw_params = {
2020 1, /* little endian */
2021 64, /* doubleword size */
2022 ia32_create_intrinsic_fkt,
2026 ia32_create_opcodes(&ia32_irn_ops);
2028 /* lower compound param handling
2029 * Note: we lower compound arguments ourself, since on ia32 we don't
2030 * have hidden parameters but know where to find the structs on the stack.
2031 * (This also forces us to always allocate space for the compound arguments
2032 * on the callframe and we can't just use an arbitrary position on the
2035 lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS);
2037 /* replace floating point operations by function calls */
2038 if (ia32_cg_config.use_softfloat) {
2039 lower_floating_point();
2042 ir_prepare_dw_lowering(&lower_dw_params);
2045 for (i = 0; i < n_irgs; ++i) {
2046 ir_graph *irg = get_irp_irg(i);
2047 /* lower for mode_b stuff */
2048 ir_lower_mode_b(irg, mode_Iu);
2049 /* break up switches with wide ranges */
2050 lower_switch(irg, 4, 256, false);
2053 for (i = 0; i < n_irgs; ++i) {
2054 ir_graph *irg = get_irp_irg(i);
2055 /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
2056 * so we can generate rep movs later, and turn all big CopyBs into
2058 lower_CopyB(irg, 64, 8193, true);
2063 * Create the trampoline code.
2065 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2067 ir_graph *const irg = get_irn_irg(block);
2068 ir_node * p = trampoline;
2069 ir_mode *const mode = get_irn_mode(p);
2070 ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
2071 ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
2075 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
2076 mem = new_r_Proj(st, mode_M, pn_Store_M);
2077 p = new_r_Add(block, p, one, mode);
2078 st = new_r_Store(block, mem, p, env, cons_none);
2079 mem = new_r_Proj(st, mode_M, pn_Store_M);
2080 p = new_r_Add(block, p, four, mode);
2082 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
2083 mem = new_r_Proj(st, mode_M, pn_Store_M);
2084 p = new_r_Add(block, p, one, mode);
2085 st = new_r_Store(block, mem, p, callee, cons_none);
2086 mem = new_r_Proj(st, mode_M, pn_Store_M);
2087 p = new_r_Add(block, p, four, mode);
2093 * Returns the libFirm configuration parameter for this backend.
2095 static const backend_params *ia32_get_libfirm_params(void)
2097 static const ir_settings_arch_dep_t ad = {
2098 1, /* also use subs */
2099 4, /* maximum shifts */
2100 63, /* maximum shift amount */
2101 ia32_evaluate_insn, /* evaluate the instruction sequence */
2103 1, /* allow Mulhs */
2104 1, /* allow Mulus */
2105 32, /* Mulh allowed up to 32 bit */
2107 static backend_params p = {
2108 1, /* support inline assembly */
2109 1, /* support Rotl nodes */
2110 0, /* little endian */
2111 1, /* modulo shift efficient */
2112 0, /* non-modulo shift not efficient */
2113 &ad, /* will be set later */
2114 ia32_is_mux_allowed,
2115 32, /* machine_size */
2116 NULL, /* float arithmetic mode, will be set below */
2117 NULL, /* long long type */
2118 NULL, /* unsigned long long type */
2119 NULL, /* long double type */
2120 12, /* size of trampoline code */
2121 4, /* alignment of trampoline code */
2122 ia32_create_trampoline_fkt,
2123 4 /* alignment of stack parameter */
2126 if (ia32_mode_E == NULL) {
2127 /* note mantissa is 64bit but with explicitely encoded 1 so the really
2128 * usable part as counted by firm is only 63 bits */
2129 ia32_mode_E = new_float_mode("E", irma_x86_extended_float, 15, 63);
2130 ia32_type_E = new_type_primitive(ia32_mode_E);
2131 set_type_size_bytes(ia32_type_E, 12);
2132 set_type_alignment_bytes(ia32_type_E, 16);
2135 ir_mode *mode_long_long
2136 = new_int_mode("long long", irma_twos_complement, 64, 1, 64);
2137 ir_type *type_long_long = new_type_primitive(mode_long_long);
2138 ir_mode *mode_unsigned_long_long
2139 = new_int_mode("unsigned long long", irma_twos_complement, 64, 0, 64);
2140 ir_type *type_unsigned_long_long
2141 = new_type_primitive(mode_unsigned_long_long);
2143 ia32_setup_cg_config();
2145 /* doesn't really belong here, but this is the earliest place the backend
2147 init_asm_constraints();
2149 p.type_long_long = type_long_long;
2150 p.type_unsigned_long_long = type_unsigned_long_long;
2152 if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
2153 p.mode_float_arithmetic = NULL;
2154 p.type_long_double = NULL;
2156 p.mode_float_arithmetic = ia32_mode_E;
2157 p.type_long_double = ia32_type_E;
2163 * Check if the given register is callee or caller save.
2165 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
2168 /* check for callee saved */
2169 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2170 switch (reg->index) {
2181 /* check for caller saved */
2182 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
2183 switch (reg->index) {
2191 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
2192 /* all XMM registers are caller save */
2193 return reg->index != REG_XMM_NOREG;
2194 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
2195 /* all VFP registers are caller save */
2196 return reg->index != REG_VFP_NOREG;
2202 static const lc_opt_enum_int_items_t gas_items[] = {
2203 { "elf", OBJECT_FILE_FORMAT_ELF },
2204 { "mingw", OBJECT_FILE_FORMAT_COFF },
2205 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2209 static lc_opt_enum_int_var_t gas_var = {
2210 (int*) &be_gas_object_file_format, gas_items
2213 #ifdef FIRM_GRGEN_BE
2214 static const lc_opt_enum_int_items_t transformer_items[] = {
2215 { "default", TRANSFORMER_DEFAULT },
2216 { "pbqp", TRANSFORMER_PBQP },
2217 { "random", TRANSFORMER_RAND },
2221 static lc_opt_enum_int_var_t transformer_var = {
2222 (int*)&be_transformer, transformer_items
2226 static const lc_opt_table_entry_t ia32_options[] = {
2227 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2228 #ifdef FIRM_GRGEN_BE
2229 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2231 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2232 &ia32_isa_template.base.stack_alignment),
2233 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2237 const arch_isa_if_t ia32_isa_if = {
2239 ia32_lower_for_target,
2241 ia32_handle_intrinsics,
2242 ia32_get_reg_class_for_mode,
2244 ia32_get_reg_class_alignment,
2245 ia32_get_libfirm_params,
2248 ia32_parse_asm_constraint,
2249 ia32_is_valid_clobber,
2252 ia32_get_pic_base, /* return node used as base in pic code addresses */
2253 ia32_before_abi, /* before abi introduce hook */
2255 ia32_before_ra, /* before register allocation hook */
2256 ia32_finish, /* called before codegen */
2257 ia32_emit, /* emit && done */
2258 ia32_register_saved_by,
2263 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2264 void be_init_arch_ia32(void)
2266 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2267 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2269 lc_opt_add_table(ia32_grp, ia32_options);
2270 be_register_isa_if("ia32", &ia32_isa_if);
2272 ia32_init_emitter();
2274 ia32_init_optimize();
2275 ia32_init_transform();
2277 ia32_init_architecture();