2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
57 #include "../benode.h"
58 #include "../belower.h"
59 #include "../besched.h"
62 #include "../beirgmod.h"
63 #include "../be_dbgout.h"
64 #include "../beblocksched.h"
65 #include "../bemachine.h"
66 #include "../bespillslots.h"
67 #include "../bemodule.h"
68 #include "../begnuas.h"
69 #include "../bestate.h"
70 #include "../beflags.h"
71 #include "../betranshlp.h"
72 #include "../belistsched.h"
73 #include "../beabihelper.h"
75 #include "bearch_ia32_t.h"
77 #include "ia32_new_nodes.h"
78 #include "gen_ia32_regalloc_if.h"
79 #include "gen_ia32_machine.h"
80 #include "ia32_common_transform.h"
81 #include "ia32_transform.h"
82 #include "ia32_emitter.h"
83 #include "ia32_optimize.h"
85 #include "ia32_dbg_stat.h"
86 #include "ia32_finish.h"
88 #include "ia32_architecture.h"
91 #include "ia32_pbqp_transform.h"
93 transformer_t be_transformer = TRANSFORMER_DEFAULT;
96 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
98 ir_mode *ia32_mode_fpcw = NULL;
100 /** The current omit-fp state */
101 static ir_type *omit_fp_between_type = NULL;
102 static ir_type *between_type = NULL;
103 static ir_entity *old_bp_ent = NULL;
104 static ir_entity *ret_addr_ent = NULL;
105 static ir_entity *omit_fp_ret_addr_ent = NULL;
108 * The environment for the intrinsic mapping.
110 static ia32_intrinsic_env_t intrinsic_env = {
112 NULL, /* the irg, these entities belong to */
113 NULL, /* entity for __divdi3 library call */
114 NULL, /* entity for __moddi3 library call */
115 NULL, /* entity for __udivdi3 library call */
116 NULL, /* entity for __umoddi3 library call */
120 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
123 * Used to create per-graph unique pseudo nodes.
125 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
126 create_const_node_func func,
127 const arch_register_t* reg)
129 ir_node *block, *res;
134 block = get_irg_start_block(irg);
135 res = func(NULL, block);
136 arch_set_irn_register(res, reg);
142 /* Creates the unique per irg GP NoReg node. */
143 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
145 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
146 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
147 &ia32_registers[REG_GP_NOREG]);
150 ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
152 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
153 return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
154 &ia32_registers[REG_VFP_NOREG]);
157 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
159 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
160 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
161 &ia32_registers[REG_XMM_NOREG]);
164 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
166 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
167 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
168 &ia32_registers[REG_FPCW]);
173 * Returns the admissible noreg register node for input register pos of node irn.
175 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
177 ir_graph *irg = get_irn_irg(irn);
178 const arch_register_req_t *req = arch_get_register_req(irn, pos);
180 assert(req != NULL && "Missing register requirements");
181 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
182 return ia32_new_NoReg_gp(irg);
184 if (ia32_cg_config.use_sse2) {
185 return ia32_new_NoReg_xmm(irg);
187 return ia32_new_NoReg_vfp(irg);
191 static arch_irn_class_t ia32_classify(const ir_node *irn)
193 arch_irn_class_t classification = arch_irn_class_none;
195 assert(is_ia32_irn(irn));
197 if (is_ia32_is_reload(irn))
198 classification |= arch_irn_class_reload;
200 if (is_ia32_is_spill(irn))
201 classification |= arch_irn_class_spill;
203 if (is_ia32_is_remat(irn))
204 classification |= arch_irn_class_remat;
206 return classification;
210 * The IA32 ABI callback object.
213 be_abi_call_flags_bits_t flags; /**< The call flags. */
214 ir_graph *irg; /**< The associated graph. */
217 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
219 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
222 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
224 if (is_be_node(node))
225 be_node_set_frame_entity(node, entity);
227 set_ia32_frame_ent(node, entity);
230 static void ia32_set_frame_offset(ir_node *irn, int bias)
232 if (get_ia32_frame_ent(irn) == NULL)
235 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
236 ir_graph *irg = get_irn_irg(irn);
237 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
238 if (layout->sp_relative) {
239 /* Pop nodes modify the stack pointer before calculating the
240 * destination address, so fix this here
245 add_ia32_am_offs_int(irn, bias);
248 static int ia32_get_sp_bias(const ir_node *node)
250 if (is_ia32_Call(node))
251 return -(int)get_ia32_call_attr_const(node)->pop;
253 if (is_ia32_Push(node))
256 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
259 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
260 return SP_BIAS_RESET;
266 static int get_start_reg_index(ir_graph *irg, const arch_register_t *reg)
268 ir_node *start = get_irg_start(irg);
269 unsigned n_outs = arch_irn_get_n_outs(start);
272 /* do a naive linear search... */
273 for (i = 0; i < (int)n_outs; ++i) {
274 const arch_register_req_t *out_req
275 = arch_get_out_register_req(start, i);
276 if (! (out_req->type & arch_register_req_type_limited))
278 if (out_req->cls != arch_register_get_class(reg))
280 if (!rbitset_is_set(out_req->limited, reg->index))
284 panic("Tried querying undefined register '%s' at Start", reg->name);
287 ir_node *ia32_get_initial_reg_value(ir_graph *irg, const arch_register_t *reg)
289 int i = get_start_reg_index(irg, reg);
290 ir_node *start = get_irg_start(irg);
291 ir_mode *mode = arch_register_class_mode(arch_register_get_class(reg));
292 const ir_edge_t *edge;
294 foreach_out_edge(start, edge) {
295 ir_node *proj = get_edge_src_irn(edge);
296 if (!is_Proj(proj)) // maybe End/Anchor
298 if (get_Proj_proj(proj) == i) {
302 ir_node *res = new_r_Proj(start, mode, i);
307 * Build the between type and entities if not already build.
309 static void ia32_build_between_type(void)
311 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
312 if (! between_type) {
313 ir_type *old_bp_type = new_type_primitive(mode_Iu);
314 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
316 between_type = new_type_struct(IDENT("ia32_between_type"));
317 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
318 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
320 set_entity_offset(old_bp_ent, 0);
321 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
322 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
323 set_type_state(between_type, layout_fixed);
325 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
326 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
328 set_entity_offset(omit_fp_ret_addr_ent, 0);
329 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
330 set_type_state(omit_fp_between_type, layout_fixed);
336 * Produces the type which sits between the stack args and the locals on the stack.
337 * it will contain the return address and space to store the old base pointer.
338 * @return The Firm type modeling the ABI between type.
340 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
342 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
343 ia32_build_between_type();
344 return layout->sp_relative ? omit_fp_between_type : between_type;
348 * Return the stack entity that contains the return address.
350 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
352 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
353 ia32_build_between_type();
354 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
358 * Return the stack entity that contains the frame address.
360 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
362 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
363 ia32_build_between_type();
364 return layout->sp_relative ? NULL : old_bp_ent;
368 * Get the estimated cycle count for @p irn.
370 * @param self The this pointer.
371 * @param irn The node.
373 * @return The estimated cycle count for this operation
375 static int ia32_get_op_estimated_cost(const ir_node *irn)
378 ia32_op_type_t op_tp;
382 if (!is_ia32_irn(irn))
385 assert(is_ia32_irn(irn));
387 cost = get_ia32_latency(irn);
388 op_tp = get_ia32_op_type(irn);
390 if (is_ia32_CopyB(irn)) {
393 else if (is_ia32_CopyB_i(irn)) {
394 int size = get_ia32_copyb_size(irn);
395 cost = 20 + (int)ceil((4/3) * size);
397 /* in case of address mode operations add additional cycles */
398 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
400 In case of stack access and access to fixed addresses add 5 cycles
401 (we assume they are in cache), other memory operations cost 20
404 if (is_ia32_use_frame(irn) || (
405 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
406 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
418 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
420 * @param irn The original operation
421 * @param i Index of the argument we want the inverse operation to yield
422 * @param inverse struct to be filled with the resulting inverse op
423 * @param obstack The obstack to use for allocation of the returned nodes array
424 * @return The inverse operation or NULL if operation invertible
426 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
437 ir_node *block, *noreg, *nomem;
440 /* we cannot invert non-ia32 irns */
441 if (! is_ia32_irn(irn))
444 /* operand must always be a real operand (not base, index or mem) */
445 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
448 /* we don't invert address mode operations */
449 if (get_ia32_op_type(irn) != ia32_Normal)
452 /* TODO: adjust for new immediates... */
453 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
457 block = get_nodes_block(irn);
458 mode = get_irn_mode(irn);
459 irn_mode = get_irn_mode(irn);
460 noreg = get_irn_n(irn, 0);
461 nomem = get_irg_no_mem(irg);
462 dbg = get_irn_dbg_info(irn);
464 /* initialize structure */
465 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
469 switch (get_ia32_irn_opcode(irn)) {
471 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
472 /* we have an add with a const here */
473 /* invers == add with negated const */
474 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
476 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
477 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
478 set_ia32_commutative(inverse->nodes[0]);
480 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
481 /* we have an add with a symconst here */
482 /* invers == sub with const */
483 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
485 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
488 /* normal add: inverse == sub */
489 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
494 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
495 /* we have a sub with a const/symconst here */
496 /* invers == add with this const */
497 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
498 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
499 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
503 if (i == n_ia32_binary_left) {
504 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
507 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
513 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
514 /* xor with const: inverse = xor */
515 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
516 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
517 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
521 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
526 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
531 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
536 /* inverse operation not supported */
544 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
546 if (mode_is_float(mode))
553 * Get the mode that should be used for spilling value node
555 static ir_mode *get_spill_mode(const ir_node *node)
557 ir_mode *mode = get_irn_mode(node);
558 return get_spill_mode_mode(mode);
562 * Checks whether an addressmode reload for a node with mode mode is compatible
563 * with a spillslot of mode spill_mode
565 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
567 return !mode_is_float(mode) || mode == spillmode;
571 * Check if irn can load its operand at position i from memory (source addressmode).
572 * @param irn The irn to be checked
573 * @param i The operands position
574 * @return Non-Zero if operand can be loaded
576 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
578 ir_node *op = get_irn_n(irn, i);
579 const ir_mode *mode = get_irn_mode(op);
580 const ir_mode *spillmode = get_spill_mode(op);
582 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
583 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
584 !ia32_is_spillmode_compatible(mode, spillmode) ||
585 is_ia32_use_frame(irn)) /* must not already use frame */
588 switch (get_ia32_am_support(irn)) {
593 if (i != n_ia32_unary_op)
599 case n_ia32_binary_left: {
600 const arch_register_req_t *req;
601 if (!is_ia32_commutative(irn))
604 /* we can't swap left/right for limited registers
605 * (As this (currently) breaks constraint handling copies)
607 req = arch_get_in_register_req(irn, n_ia32_binary_left);
608 if (req->type & arch_register_req_type_limited)
613 case n_ia32_binary_right:
622 panic("Unknown AM type");
625 /* HACK: must not already use "real" memory.
626 * This can happen for Call and Div */
627 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
633 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
637 ir_mode *dest_op_mode;
639 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
641 set_ia32_op_type(irn, ia32_AddrModeS);
643 load_mode = get_irn_mode(get_irn_n(irn, i));
644 dest_op_mode = get_ia32_ls_mode(irn);
645 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
646 set_ia32_ls_mode(irn, load_mode);
648 set_ia32_use_frame(irn);
649 set_ia32_need_stackent(irn);
651 if (i == n_ia32_binary_left &&
652 get_ia32_am_support(irn) == ia32_am_binary &&
653 /* immediates are only allowed on the right side */
654 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
655 ia32_swap_left_right(irn);
656 i = n_ia32_binary_right;
659 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
661 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
662 set_irn_n(irn, n_ia32_mem, spill);
663 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
664 set_ia32_is_reload(irn);
667 static const be_abi_callbacks_t ia32_abi_callbacks = {
668 ia32_abi_get_between_type,
671 /* register allocator interface */
672 static const arch_irn_ops_t ia32_irn_ops = {
674 ia32_get_frame_entity,
675 ia32_set_frame_offset,
678 ia32_get_op_estimated_cost,
679 ia32_possible_memory_operand,
680 ia32_perform_memory_operand,
683 static ir_entity *mcount = NULL;
684 static int gprof = 0;
686 static void ia32_before_abi(ir_graph *irg)
689 if (mcount == NULL) {
690 ir_type *tp = new_type_method(0, 0);
691 ident *id = new_id_from_str("mcount");
692 mcount = new_entity(get_glob_type(), id, tp);
693 /* FIXME: enter the right ld_ident here */
694 set_entity_ld_ident(mcount, get_entity_ident(mcount));
695 set_entity_visibility(mcount, ir_visibility_external);
697 instrument_initcall(irg, mcount);
702 * Transforms the standard firm graph into
705 static void ia32_prepare_graph(ir_graph *irg)
707 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
710 switch (be_transformer) {
711 case TRANSFORMER_DEFAULT:
712 /* transform remaining nodes into assembler instructions */
713 ia32_transform_graph(irg);
716 case TRANSFORMER_PBQP:
717 case TRANSFORMER_RAND:
718 /* transform nodes into assembler instructions by PBQP magic */
719 ia32_transform_graph_by_pbqp(irg);
723 panic("invalid transformer");
726 ia32_transform_graph(irg);
729 /* do local optimizations (mainly CSE) */
730 optimize_graph_df(irg);
733 dump_ir_graph(irg, "transformed");
735 /* optimize address mode */
736 ia32_optimize_graph(irg);
738 /* do code placement, to optimize the position of constants */
742 dump_ir_graph(irg, "place");
745 ir_node *ia32_turn_back_am(ir_node *node)
747 dbg_info *dbgi = get_irn_dbg_info(node);
748 ir_graph *irg = get_irn_irg(node);
749 ir_node *block = get_nodes_block(node);
750 ir_node *base = get_irn_n(node, n_ia32_base);
751 ir_node *index = get_irn_n(node, n_ia32_index);
752 ir_node *mem = get_irn_n(node, n_ia32_mem);
755 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
756 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
758 ia32_copy_am_attrs(load, node);
759 if (is_ia32_is_reload(node))
760 set_ia32_is_reload(load);
761 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
763 switch (get_ia32_am_support(node)) {
765 set_irn_n(node, n_ia32_unary_op, load_res);
769 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
770 set_irn_n(node, n_ia32_binary_left, load_res);
772 set_irn_n(node, n_ia32_binary_right, load_res);
777 panic("Unknown AM type");
779 noreg = ia32_new_NoReg_gp(current_ir_graph);
780 set_irn_n(node, n_ia32_base, noreg);
781 set_irn_n(node, n_ia32_index, noreg);
782 set_ia32_am_offs_int(node, 0);
783 set_ia32_am_sc(node, NULL);
784 set_ia32_am_scale(node, 0);
785 clear_ia32_am_sc_sign(node);
787 /* rewire mem-proj */
788 if (get_irn_mode(node) == mode_T) {
789 const ir_edge_t *edge;
790 foreach_out_edge(node, edge) {
791 ir_node *out = get_edge_src_irn(edge);
792 if (get_irn_mode(out) == mode_M) {
793 set_Proj_pred(out, load);
794 set_Proj_proj(out, pn_ia32_Load_M);
800 set_ia32_op_type(node, ia32_Normal);
801 if (sched_is_scheduled(node))
802 sched_add_before(node, load);
807 static ir_node *flags_remat(ir_node *node, ir_node *after)
809 /* we should turn back source address mode when rematerializing nodes */
814 if (is_Block(after)) {
817 block = get_nodes_block(after);
820 type = get_ia32_op_type(node);
823 ia32_turn_back_am(node);
827 /* TODO implement this later... */
828 panic("found DestAM with flag user %+F this should not happen", node);
831 default: assert(type == ia32_Normal); break;
834 copy = exact_copy(node);
835 set_nodes_block(copy, block);
836 sched_add_after(after, copy);
842 * Called before the register allocator.
844 static void ia32_before_ra(ir_graph *irg)
846 /* setup fpu rounding modes */
847 ia32_setup_fpu_mode(irg);
850 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
853 be_add_missing_keeps(irg);
858 * Transforms a be_Reload into a ia32 Load.
860 static void transform_to_Load(ir_node *node)
862 ir_graph *irg = get_irn_irg(node);
863 dbg_info *dbg = get_irn_dbg_info(node);
864 ir_node *block = get_nodes_block(node);
865 ir_entity *ent = be_get_frame_entity(node);
866 ir_mode *mode = get_irn_mode(node);
867 ir_mode *spillmode = get_spill_mode(node);
868 ir_node *noreg = ia32_new_NoReg_gp(irg);
869 ir_node *sched_point = NULL;
870 ir_node *ptr = get_irg_frame(irg);
871 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
872 ir_node *new_op, *proj;
873 const arch_register_t *reg;
875 if (sched_is_scheduled(node)) {
876 sched_point = sched_prev(node);
879 if (mode_is_float(spillmode)) {
880 if (ia32_cg_config.use_sse2)
881 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
883 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
885 else if (get_mode_size_bits(spillmode) == 128) {
886 /* Reload 128 bit SSE registers */
887 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
890 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
892 set_ia32_op_type(new_op, ia32_AddrModeS);
893 set_ia32_ls_mode(new_op, spillmode);
894 set_ia32_frame_ent(new_op, ent);
895 set_ia32_use_frame(new_op);
896 set_ia32_is_reload(new_op);
898 DBG_OPT_RELOAD2LD(node, new_op);
900 proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
903 sched_add_after(sched_point, new_op);
907 /* copy the register from the old node to the new Load */
908 reg = arch_get_irn_register(node);
909 arch_set_irn_register(proj, reg);
911 SET_IA32_ORIG_NODE(new_op, node);
913 exchange(node, proj);
917 * Transforms a be_Spill node into a ia32 Store.
919 static void transform_to_Store(ir_node *node)
921 ir_graph *irg = get_irn_irg(node);
922 dbg_info *dbg = get_irn_dbg_info(node);
923 ir_node *block = get_nodes_block(node);
924 ir_entity *ent = be_get_frame_entity(node);
925 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
926 ir_mode *mode = get_spill_mode(spillval);
927 ir_node *noreg = ia32_new_NoReg_gp(irg);
928 ir_node *nomem = get_irg_no_mem(irg);
929 ir_node *ptr = get_irg_frame(irg);
930 ir_node *val = get_irn_n(node, n_be_Spill_val);
932 ir_node *sched_point = NULL;
934 if (sched_is_scheduled(node)) {
935 sched_point = sched_prev(node);
938 if (mode_is_float(mode)) {
939 if (ia32_cg_config.use_sse2)
940 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
942 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
943 } else if (get_mode_size_bits(mode) == 128) {
944 /* Spill 128 bit SSE registers */
945 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
946 } else if (get_mode_size_bits(mode) == 8) {
947 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
949 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
952 set_ia32_op_type(store, ia32_AddrModeD);
953 set_ia32_ls_mode(store, mode);
954 set_ia32_frame_ent(store, ent);
955 set_ia32_use_frame(store);
956 set_ia32_is_spill(store);
957 SET_IA32_ORIG_NODE(store, node);
958 DBG_OPT_SPILL2ST(node, store);
961 sched_add_after(sched_point, store);
965 exchange(node, store);
968 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
970 dbg_info *dbg = get_irn_dbg_info(node);
971 ir_node *block = get_nodes_block(node);
972 ir_graph *irg = get_irn_irg(node);
973 ir_node *noreg = ia32_new_NoReg_gp(irg);
974 ir_node *frame = get_irg_frame(irg);
976 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
978 set_ia32_frame_ent(push, ent);
979 set_ia32_use_frame(push);
980 set_ia32_op_type(push, ia32_AddrModeS);
981 set_ia32_ls_mode(push, mode_Is);
982 set_ia32_is_spill(push);
984 sched_add_before(schedpoint, push);
988 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
990 dbg_info *dbg = get_irn_dbg_info(node);
991 ir_node *block = get_nodes_block(node);
992 ir_graph *irg = get_irn_irg(node);
993 ir_node *noreg = ia32_new_NoReg_gp(irg);
994 ir_node *frame = get_irg_frame(irg);
996 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg,
997 get_irg_no_mem(irg), sp);
999 set_ia32_frame_ent(pop, ent);
1000 set_ia32_use_frame(pop);
1001 set_ia32_op_type(pop, ia32_AddrModeD);
1002 set_ia32_ls_mode(pop, mode_Is);
1003 set_ia32_is_reload(pop);
1005 sched_add_before(schedpoint, pop);
1010 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1012 dbg_info *dbg = get_irn_dbg_info(node);
1013 ir_mode *spmode = mode_Iu;
1014 const arch_register_t *spreg = &ia32_registers[REG_ESP];
1017 sp = new_rd_Proj(dbg, pred, spmode, pos);
1018 arch_set_irn_register(sp, spreg);
1024 * Transform MemPerm, currently we do this the ugly way and produce
1025 * push/pop into/from memory cascades. This is possible without using
1028 static void transform_MemPerm(ir_node *node)
1030 ir_node *block = get_nodes_block(node);
1031 ir_graph *irg = get_irn_irg(node);
1032 ir_node *sp = ia32_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
1033 int arity = be_get_MemPerm_entity_arity(node);
1034 ir_node **pops = ALLOCAN(ir_node*, arity);
1038 const ir_edge_t *edge;
1039 const ir_edge_t *next;
1042 for (i = 0; i < arity; ++i) {
1043 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1044 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1045 ir_type *enttype = get_entity_type(inent);
1046 unsigned entsize = get_type_size_bytes(enttype);
1047 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1048 ir_node *mem = get_irn_n(node, i + 1);
1051 /* work around cases where entities have different sizes */
1052 if (entsize2 < entsize)
1054 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1056 push = create_push(node, node, sp, mem, inent);
1057 sp = create_spproj(node, push, pn_ia32_Push_stack);
1059 /* add another push after the first one */
1060 push = create_push(node, node, sp, mem, inent);
1061 add_ia32_am_offs_int(push, 4);
1062 sp = create_spproj(node, push, pn_ia32_Push_stack);
1065 set_irn_n(node, i, new_r_Bad(irg));
1069 for (i = arity - 1; i >= 0; --i) {
1070 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1071 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1072 ir_type *enttype = get_entity_type(outent);
1073 unsigned entsize = get_type_size_bytes(enttype);
1074 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1077 /* work around cases where entities have different sizes */
1078 if (entsize2 < entsize)
1080 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1082 pop = create_pop(node, node, sp, outent);
1083 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1085 add_ia32_am_offs_int(pop, 4);
1087 /* add another pop after the first one */
1088 pop = create_pop(node, node, sp, outent);
1089 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1096 keep = be_new_Keep(block, 1, in);
1097 sched_add_before(node, keep);
1099 /* exchange memprojs */
1100 foreach_out_edge_safe(node, edge, next) {
1101 ir_node *proj = get_edge_src_irn(edge);
1102 int p = get_Proj_proj(proj);
1106 set_Proj_pred(proj, pops[p]);
1107 set_Proj_proj(proj, pn_ia32_Pop_M);
1110 /* remove memperm */
1111 arity = get_irn_arity(node);
1112 for (i = 0; i < arity; ++i) {
1113 set_irn_n(node, i, new_r_Bad(irg));
1119 * Block-Walker: Calls the transform functions Spill and Reload.
1121 static void ia32_after_ra_walker(ir_node *block, void *env)
1123 ir_node *node, *prev;
1126 /* beware: the schedule is changed here */
1127 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1128 prev = sched_prev(node);
1130 if (be_is_Reload(node)) {
1131 transform_to_Load(node);
1132 } else if (be_is_Spill(node)) {
1133 transform_to_Store(node);
1134 } else if (be_is_MemPerm(node)) {
1135 transform_MemPerm(node);
1141 * Collects nodes that need frame entities assigned.
1143 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1145 be_fec_env_t *env = (be_fec_env_t*)data;
1146 const ir_mode *mode;
1149 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1150 mode = get_spill_mode_mode(get_irn_mode(node));
1151 align = get_mode_size_bytes(mode);
1152 } else if (is_ia32_irn(node) &&
1153 get_ia32_frame_ent(node) == NULL &&
1154 is_ia32_use_frame(node)) {
1155 if (is_ia32_need_stackent(node))
1158 switch (get_ia32_irn_opcode(node)) {
1160 case iro_ia32_Load: {
1161 const ia32_attr_t *attr = get_ia32_attr_const(node);
1163 if (attr->data.need_32bit_stackent) {
1165 } else if (attr->data.need_64bit_stackent) {
1168 mode = get_ia32_ls_mode(node);
1169 if (is_ia32_is_reload(node))
1170 mode = get_spill_mode_mode(mode);
1172 align = get_mode_size_bytes(mode);
1176 case iro_ia32_vfild:
1178 case iro_ia32_xLoad: {
1179 mode = get_ia32_ls_mode(node);
1184 case iro_ia32_FldCW: {
1185 /* although 2 byte would be enough 4 byte performs best */
1193 panic("unexpected frame user while collection frame entity nodes");
1195 case iro_ia32_FnstCW:
1196 case iro_ia32_Store8Bit:
1197 case iro_ia32_Store:
1200 case iro_ia32_vfist:
1201 case iro_ia32_vfisttp:
1203 case iro_ia32_xStore:
1204 case iro_ia32_xStoreSimple:
1211 be_node_needs_frame_entity(env, node, mode, align);
1214 static int determine_ebp_input(ir_node *ret)
1216 const arch_register_t *bp = &ia32_registers[REG_EBP];
1217 int arity = get_irn_arity(ret);
1220 for (i = 0; i < arity; ++i) {
1221 ir_node *input = get_irn_n(ret, i);
1222 if (arch_get_irn_register(input) == bp)
1225 panic("no ebp input found at %+F", ret);
1228 static void introduce_epilog(ir_node *ret)
1230 const arch_register_t *sp = &ia32_registers[REG_ESP];
1231 const arch_register_t *bp = &ia32_registers[REG_EBP];
1232 ir_graph *irg = get_irn_irg(ret);
1233 ir_type *frame_type = get_irg_frame_type(irg);
1234 unsigned frame_size = get_type_size_bytes(frame_type);
1235 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1236 ir_node *block = get_nodes_block(ret);
1237 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1238 ir_node *curr_sp = first_sp;
1239 ir_mode *mode_gp = mode_Iu;
1241 if (!layout->sp_relative) {
1242 int n_ebp = determine_ebp_input(ret);
1243 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1244 if (ia32_cg_config.use_leave) {
1245 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1246 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1247 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1248 arch_set_irn_register(curr_bp, bp);
1249 arch_set_irn_register(curr_sp, sp);
1250 sched_add_before(ret, leave);
1253 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1254 /* copy ebp to esp */
1255 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1256 arch_set_irn_register(curr_sp, sp);
1257 sched_add_before(ret, curr_sp);
1260 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1261 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1262 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1263 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1264 arch_set_irn_register(curr_bp, bp);
1265 arch_set_irn_register(curr_sp, sp);
1266 sched_add_before(ret, pop);
1268 set_irn_n(ret, n_be_Return_mem, curr_mem);
1270 set_irn_n(ret, n_ebp, curr_bp);
1272 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1273 sched_add_before(ret, incsp);
1276 set_irn_n(ret, n_be_Return_sp, curr_sp);
1278 /* keep verifier happy... */
1279 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1280 kill_node(first_sp);
1285 * put the Prolog code at the beginning, epilog code before each return
1287 static void introduce_prolog_epilog(ir_graph *irg)
1289 const arch_register_t *sp = &ia32_registers[REG_ESP];
1290 const arch_register_t *bp = &ia32_registers[REG_EBP];
1291 ir_node *start = get_irg_start(irg);
1292 ir_node *block = get_nodes_block(start);
1293 ir_type *frame_type = get_irg_frame_type(irg);
1294 unsigned frame_size = get_type_size_bytes(frame_type);
1295 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1296 ir_node *initial_sp = ia32_get_initial_reg_value(irg, sp);
1297 ir_node *curr_sp = initial_sp;
1298 ir_mode *mode_gp = mode_Iu;
1300 if (!layout->sp_relative) {
1302 ir_node *mem = get_irg_initial_mem(irg);
1303 ir_node *noreg = ia32_new_NoReg_gp(irg);
1304 ir_node *initial_bp = ia32_get_initial_reg_value(irg, bp);
1305 ir_node *curr_bp = initial_bp;
1306 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
1309 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1310 mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
1311 arch_set_irn_register(curr_sp, sp);
1312 sched_add_after(start, push);
1314 /* move esp to ebp */
1315 curr_bp = be_new_Copy(bp->reg_class, block, curr_sp);
1316 sched_add_after(push, curr_bp);
1317 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1318 curr_sp = be_new_CopyKeep_single(sp->reg_class, block, curr_sp, curr_bp, mode_gp);
1319 sched_add_after(curr_bp, curr_sp);
1320 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1321 edges_reroute(initial_bp, curr_bp);
1322 set_irn_n(push, n_ia32_Push_val, initial_bp);
1324 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1325 edges_reroute(initial_sp, incsp);
1326 set_irn_n(push, n_ia32_Push_stack, initial_sp);
1327 sched_add_after(curr_sp, incsp);
1329 layout->initial_bias = -4;
1331 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1332 edges_reroute(initial_sp, incsp);
1333 be_set_IncSP_pred(incsp, curr_sp);
1334 sched_add_after(start, incsp);
1337 /* introduce epilog for every return node */
1339 ir_node *end_block = get_irg_end_block(irg);
1340 int arity = get_irn_arity(end_block);
1343 for (i = 0; i < arity; ++i) {
1344 ir_node *ret = get_irn_n(end_block, i);
1345 assert(be_is_Return(ret));
1346 introduce_epilog(ret);
1352 * We transform Spill and Reload here. This needs to be done before
1353 * stack biasing otherwise we would miss the corrected offset for these nodes.
1355 static void ia32_after_ra(ir_graph *irg)
1357 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1358 bool at_begin = stack_layout->sp_relative ? true : false;
1359 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1361 /* create and coalesce frame entities */
1362 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1363 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1364 be_free_frame_entity_coalescer(fec_env);
1366 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1368 introduce_prolog_epilog(irg);
1372 * Last touchups for the graph before emit: x87 simulation to replace the
1373 * virtual with real x87 instructions, creating a block schedule and peephole
1376 static void ia32_finish(ir_graph *irg)
1378 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1380 ia32_finish_irg(irg);
1382 /* we might have to rewrite x87 virtual registers */
1383 if (irg_data->do_x87_sim) {
1384 ia32_x87_simulate_graph(irg);
1387 /* do peephole optimisations */
1388 ia32_peephole_optimization(irg);
1390 /* create block schedule, this also removes empty blocks which might
1391 * produce critical edges */
1392 irg_data->blk_sched = be_create_block_schedule(irg);
1396 * Emits the code, closes the output file and frees
1397 * the code generator interface.
1399 static void ia32_emit(ir_graph *irg)
1401 if (ia32_cg_config.emit_machcode) {
1402 ia32_gen_binary_routine(irg);
1404 ia32_gen_routine(irg);
1409 * Returns the node representing the PIC base.
1411 static ir_node *ia32_get_pic_base(ir_graph *irg)
1413 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1415 ir_node *get_eip = irg_data->get_eip;
1416 if (get_eip != NULL)
1419 block = get_irg_start_block(irg);
1420 get_eip = new_bd_ia32_GetEIP(NULL, block);
1421 irg_data->get_eip = get_eip;
1427 * Initializes a IA32 code generator.
1429 static void ia32_init_graph(ir_graph *irg)
1431 struct obstack *obst = be_get_be_obst(irg);
1432 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1434 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1437 /* Linux gprof implementation needs base pointer */
1438 be_get_irg_options(irg)->omit_fp = 0;
1441 be_birg_from_irg(irg)->isa_link = irg_data;
1446 * Set output modes for GCC
1448 static const tarval_mode_info mo_integer = {
1455 * set the tarval output mode of all integer modes to decimal
1457 static void set_tarval_output_modes(void)
1461 for (i = get_irp_n_modes(); i > 0;) {
1462 ir_mode *mode = get_irp_mode(--i);
1464 if (mode_is_int(mode))
1465 set_tarval_mode_output_option(mode, &mo_integer);
1469 extern const arch_isa_if_t ia32_isa_if;
1472 * The template that generates a new ISA object.
1473 * Note that this template can be changed by command line
1476 static ia32_isa_t ia32_isa_template = {
1478 &ia32_isa_if, /* isa interface implementation */
1483 &ia32_registers[REG_ESP], /* stack pointer register */
1484 &ia32_registers[REG_EBP], /* base pointer register */
1485 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1486 2, /* power of two stack alignment, 2^2 == 4 */
1487 NULL, /* main environment */
1488 7, /* costs for a spill instruction */
1489 5, /* costs for a reload instruction */
1490 false, /* no custom abi handling */
1494 NULL, /* abstract machine */
1497 static void init_asm_constraints(void)
1499 be_init_default_asm_constraint_flags();
1501 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1502 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1503 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1504 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1505 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1506 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1507 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1508 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1509 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1510 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1511 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1512 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1513 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1514 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1515 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1516 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1517 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1518 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1519 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1520 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1522 /* no support for autodecrement/autoincrement */
1523 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1524 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1525 /* no float consts */
1526 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1527 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1528 /* makes no sense on x86 */
1529 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1530 /* no support for sse consts yet */
1531 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1532 /* no support for x87 consts yet */
1533 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1534 /* no support for mmx registers yet */
1535 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1536 /* not available in 32bit mode */
1537 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1538 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1540 /* no code yet to determine register class needed... */
1541 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1545 * Initializes the backend ISA.
1547 static arch_env_t *ia32_init(FILE *file_handle)
1549 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1551 set_tarval_output_modes();
1553 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1555 if (ia32_mode_fpcw == NULL) {
1556 ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1559 ia32_register_init();
1560 ia32_create_opcodes(&ia32_irn_ops);
1562 be_emit_init(file_handle);
1563 isa->types = pmap_create();
1564 isa->tv_ent = pmap_create();
1565 isa->cpu = ia32_init_machine_description();
1567 /* enter the ISA object into the intrinsic environment */
1568 intrinsic_env.isa = isa;
1576 * Closes the output file and frees the ISA structure.
1578 static void ia32_done(void *self)
1580 ia32_isa_t *isa = (ia32_isa_t*)self;
1582 /* emit now all global declarations */
1583 be_gas_emit_decls(isa->base.main_env);
1585 pmap_destroy(isa->tv_ent);
1586 pmap_destroy(isa->types);
1595 * Get the register class which shall be used to store a value of a given mode.
1596 * @param self The this pointer.
1597 * @param mode The mode in question.
1598 * @return A register class which can hold values of the given mode.
1600 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1602 if (mode_is_float(mode)) {
1603 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1606 return &ia32_reg_classes[CLASS_ia32_gp];
1610 * Returns the register for parameter nr.
1612 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1613 const ir_mode *mode)
1615 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1616 &ia32_registers[REG_ECX],
1617 &ia32_registers[REG_EDX],
1620 static const unsigned MAXNUM_GPREG_ARGS = 3;
1622 static const arch_register_t *gpreg_param_reg_regparam[] = {
1623 &ia32_registers[REG_EAX],
1624 &ia32_registers[REG_EDX],
1625 &ia32_registers[REG_ECX]
1628 static const arch_register_t *gpreg_param_reg_this[] = {
1629 &ia32_registers[REG_ECX],
1634 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1635 &ia32_registers[REG_XMM0],
1636 &ia32_registers[REG_XMM1],
1637 &ia32_registers[REG_XMM2],
1638 &ia32_registers[REG_XMM3],
1639 &ia32_registers[REG_XMM4],
1640 &ia32_registers[REG_XMM5],
1641 &ia32_registers[REG_XMM6],
1642 &ia32_registers[REG_XMM7]
1645 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1646 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1648 static const unsigned MAXNUM_SSE_ARGS = 8;
1650 if ((cc & cc_this_call) && nr == 0)
1651 return gpreg_param_reg_this[0];
1653 if (! (cc & cc_reg_param))
1656 if (mode_is_float(mode)) {
1657 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1659 if (nr >= MAXNUM_SSE_ARGS)
1662 if (cc & cc_this_call) {
1663 return fpreg_sse_param_reg_this[nr];
1665 return fpreg_sse_param_reg_std[nr];
1666 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1667 unsigned num_regparam;
1669 if (get_mode_size_bits(mode) > 32)
1672 if (nr >= MAXNUM_GPREG_ARGS)
1675 if (cc & cc_this_call) {
1676 return gpreg_param_reg_this[nr];
1678 num_regparam = cc & ~cc_bits;
1679 if (num_regparam == 0) {
1680 /* default fastcall */
1681 return gpreg_param_reg_fastcall[nr];
1683 if (nr < num_regparam)
1684 return gpreg_param_reg_regparam[nr];
1688 panic("unknown argument mode");
1692 * Get the ABI restrictions for procedure calls.
1693 * @param self The this pointer.
1694 * @param method_type The type of the method (procedure) in question.
1695 * @param abi The abi object to be modified
1697 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1705 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1709 /* set abi flags for calls */
1710 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1711 call_flags.bits.store_args_sequential = 0;
1712 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1713 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1714 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1716 /* set parameter passing style */
1717 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1719 cc = get_method_calling_convention(method_type);
1720 if (get_method_variadicity(method_type) == variadicity_variadic) {
1721 /* pass all parameters of a variadic function on the stack */
1722 cc = cc_cdecl_set | (cc & cc_this_call);
1724 if (get_method_additional_properties(method_type) & mtp_property_private &&
1725 ia32_cg_config.optimize_cc) {
1726 /* set the fast calling conventions (allowing up to 3) */
1727 cc = SET_FASTCALL(cc) | 3;
1731 /* we have to pop the shadow parameter ourself for compound calls */
1732 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1733 && !(cc & cc_reg_param)) {
1734 pop_amount += get_mode_size_bytes(mode_P_data);
1737 n = get_method_n_params(method_type);
1738 for (i = regnum = 0; i < n; i++) {
1740 const arch_register_t *reg = NULL;
1742 tp = get_method_param_type(method_type, i);
1743 mode = get_type_mode(tp);
1745 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1748 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1751 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1752 * movl has a shorter opcode than mov[sz][bw]l */
1753 ir_mode *load_mode = mode;
1756 unsigned size = get_mode_size_bytes(mode);
1758 if (cc & cc_callee_clear_stk) {
1759 pop_amount += (size + 3U) & ~3U;
1762 if (size < 4) load_mode = mode_Iu;
1765 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1769 be_abi_call_set_pop(abi, pop_amount);
1771 /* set return registers */
1772 n = get_method_n_ress(method_type);
1774 assert(n <= 2 && "more than two results not supported");
1776 /* In case of 64bit returns, we will have two 32bit values */
1778 tp = get_method_res_type(method_type, 0);
1779 mode = get_type_mode(tp);
1781 assert(!mode_is_float(mode) && "two FP results not supported");
1783 tp = get_method_res_type(method_type, 1);
1784 mode = get_type_mode(tp);
1786 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1788 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1789 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1792 const arch_register_t *reg;
1794 tp = get_method_res_type(method_type, 0);
1795 assert(is_atomic_type(tp));
1796 mode = get_type_mode(tp);
1798 reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
1800 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1805 * Returns the necessary byte alignment for storing a register of given class.
1807 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1809 ir_mode *mode = arch_register_class_mode(cls);
1810 int bytes = get_mode_size_bytes(mode);
1812 if (mode_is_float(mode) && bytes > 8)
1818 * Return irp irgs in the desired order.
1820 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1827 static void ia32_mark_remat(ir_node *node)
1829 if (is_ia32_irn(node)) {
1830 set_ia32_is_remat(node);
1835 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1837 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1842 ir_relation relation;
1847 cmp_l = get_Cmp_left(sel);
1848 cmp_r = get_Cmp_right(sel);
1849 if (!mode_is_float(get_irn_mode(cmp_l)))
1852 /* check for min/max. They're defined as (C-Semantik):
1853 * min(a, b) = a < b ? a : b
1854 * or min(a, b) = a <= b ? a : b
1855 * max(a, b) = a > b ? a : b
1856 * or max(a, b) = a >= b ? a : b
1857 * (Note we only handle float min/max here)
1859 relation = get_Cmp_relation(sel);
1861 case ir_relation_greater_equal:
1862 case ir_relation_greater:
1864 if (cmp_l == mux_true && cmp_r == mux_false)
1867 case ir_relation_less_equal:
1868 case ir_relation_less:
1870 if (cmp_l == mux_true && cmp_r == mux_false)
1873 case ir_relation_unordered_greater_equal:
1874 case ir_relation_unordered_greater:
1876 if (cmp_l == mux_false && cmp_r == mux_true)
1879 case ir_relation_unordered_less_equal:
1880 case ir_relation_unordered_less:
1882 if (cmp_l == mux_false && cmp_r == mux_true)
1893 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1895 ir_mode *mode = get_irn_mode(mux_true);
1898 if (!mode_is_int(mode) && !mode_is_reference(mode)
1902 if (is_Const(mux_true) && is_Const(mux_false)) {
1903 /* we can create a set plus up two 3 instructions for any combination
1911 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1916 if (!mode_is_float(get_irn_mode(mux_true)))
1919 return is_Const(mux_true) && is_Const(mux_false);
1922 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1929 ir_relation relation;
1934 mode = get_irn_mode(mux_true);
1935 if (mode_is_signed(mode) || mode_is_float(mode))
1938 relation = get_Cmp_relation(sel);
1939 cmp_left = get_Cmp_left(sel);
1940 cmp_right = get_Cmp_right(sel);
1942 /* "move" zero constant to false input */
1943 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1944 ir_node *tmp = mux_false;
1945 mux_false = mux_true;
1947 relation = get_negated_relation(relation);
1949 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1951 if (!is_Sub(mux_true))
1953 sub_left = get_Sub_left(mux_true);
1954 sub_right = get_Sub_right(mux_true);
1956 /* Mux(a >=u b, 0, a-b) */
1957 if ((relation & ir_relation_greater)
1958 && sub_left == cmp_left && sub_right == cmp_right)
1960 /* Mux(a <=u b, 0, b-a) */
1961 if ((relation & ir_relation_less)
1962 && sub_left == cmp_right && sub_right == cmp_left)
1968 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1973 /* we can handle Set for all modes and compares */
1974 if (mux_is_set(sel, mux_true, mux_false))
1976 /* SSE has own min/max operations */
1977 if (ia32_cg_config.use_sse2
1978 && mux_is_float_min_max(sel, mux_true, mux_false))
1980 /* we can handle Mux(?, Const[f], Const[f]) */
1981 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1982 #ifdef FIRM_GRGEN_BE
1983 /* well, some code selectors can't handle it */
1984 if (be_transformer != TRANSFORMER_PBQP
1985 || be_transformer != TRANSFORMER_RAND)
1992 /* no support for 64bit inputs to cmov */
1993 mode = get_irn_mode(mux_true);
1994 if (get_mode_size_bits(mode) > 32)
1996 /* we can handle Abs for all modes and compares (except 64bit) */
1997 if (be_mux_is_abs(sel, mux_true, mux_false) != 0)
1999 /* we can't handle MuxF yet */
2000 if (mode_is_float(mode))
2003 if (mux_is_doz(sel, mux_true, mux_false))
2006 /* Check Cmp before the node */
2008 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
2010 /* we can't handle 64bit compares */
2011 if (get_mode_size_bits(cmp_mode) > 32)
2014 /* we can't handle float compares */
2015 if (mode_is_float(cmp_mode))
2019 /* did we disable cmov generation? */
2020 if (!ia32_cg_config.use_cmov)
2023 /* we can use a cmov */
2027 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2031 /* we already added all our simple flags to the flags modifier list in
2032 * init, so this flag we don't know. */
2033 return ASM_CONSTRAINT_FLAG_INVALID;
2036 static int ia32_is_valid_clobber(const char *clobber)
2038 return ia32_get_clobber_register(clobber) != NULL;
2041 static ir_node *ia32_create_set(ir_node *cond)
2043 /* ia32-set function produces 8-bit results which have to be converted */
2044 ir_node *set = ir_create_mux_set(cond, mode_Bu);
2045 ir_node *block = get_nodes_block(set);
2046 return new_r_Conv(block, set, mode_Iu);
2049 static void ia32_lower_for_target(void)
2051 size_t i, n_irgs = get_irp_n_irgs();
2052 lower_mode_b_config_t lower_mode_b_config = {
2053 mode_Iu, /* lowered mode */
2055 0, /* don't lower direct compares */
2057 lower_params_t params = {
2058 4, /* def_ptr_alignment */
2059 LF_COMPOUND_RETURN | LF_RETURN_HIDDEN, /* flags */
2060 ADD_HIDDEN_ALWAYS_IN_FRONT, /* hidden_params */
2061 NULL, /* find pointer type */
2062 NULL, /* ret_compound_in_regs */
2065 /* perform doubleword lowering */
2066 lwrdw_param_t lower_dw_params = {
2067 1, /* little endian */
2068 64, /* doubleword size */
2069 ia32_create_intrinsic_fkt,
2073 /* lower compound param handling */
2074 lower_calls_with_compounds(¶ms);
2076 lower_dw_ops(&lower_dw_params);
2078 for (i = 0; i < n_irgs; ++i) {
2079 ir_graph *irg = get_irp_irg(i);
2080 /* lower for mode_b stuff */
2081 ir_lower_mode_b(irg, &lower_mode_b_config);
2082 /* break up switches with wide ranges */
2083 lower_switch(irg, 256, true);
2088 * Create the trampoline code.
2090 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2092 ir_graph *irg = get_irn_irg(block);
2093 ir_node *p = trampoline;
2094 ir_mode *mode = get_irn_mode(p);
2098 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
2099 mem = new_r_Proj(st, mode_M, pn_Store_M);
2100 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2101 st = new_r_Store(block, mem, p, env, cons_none);
2102 mem = new_r_Proj(st, mode_M, pn_Store_M);
2103 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2105 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
2106 mem = new_r_Proj(st, mode_M, pn_Store_M);
2107 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
2108 st = new_r_Store(block, mem, p, callee, cons_none);
2109 mem = new_r_Proj(st, mode_M, pn_Store_M);
2110 p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
2116 * Returns the libFirm configuration parameter for this backend.
2118 static const backend_params *ia32_get_libfirm_params(void)
2120 static const ir_settings_arch_dep_t ad = {
2121 1, /* also use subs */
2122 4, /* maximum shifts */
2123 63, /* maximum shift amount */
2124 ia32_evaluate_insn, /* evaluate the instruction sequence */
2126 1, /* allow Mulhs */
2127 1, /* allow Mulus */
2128 32, /* Mulh allowed up to 32 bit */
2130 static backend_params p = {
2131 1, /* support inline assembly */
2132 1, /* support Rotl nodes */
2133 0, /* little endian */
2134 NULL, /* will be set later */
2135 ia32_is_mux_allowed,
2136 NULL, /* float arithmetic mode, will be set below */
2137 12, /* size of trampoline code */
2138 4, /* alignment of trampoline code */
2139 ia32_create_trampoline_fkt,
2140 4 /* alignment of stack parameter */
2143 ia32_setup_cg_config();
2145 /* doesn't really belong here, but this is the earliest place the backend
2147 init_asm_constraints();
2150 if (! ia32_cg_config.use_sse2)
2151 p.mode_float_arithmetic = mode_E;
2155 static const lc_opt_enum_int_items_t gas_items[] = {
2156 { "elf", OBJECT_FILE_FORMAT_ELF },
2157 { "mingw", OBJECT_FILE_FORMAT_COFF },
2158 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2162 static lc_opt_enum_int_var_t gas_var = {
2163 (int*) &be_gas_object_file_format, gas_items
2166 #ifdef FIRM_GRGEN_BE
2167 static const lc_opt_enum_int_items_t transformer_items[] = {
2168 { "default", TRANSFORMER_DEFAULT },
2169 { "pbqp", TRANSFORMER_PBQP },
2170 { "random", TRANSFORMER_RAND },
2174 static lc_opt_enum_int_var_t transformer_var = {
2175 (int*)&be_transformer, transformer_items
2179 static const lc_opt_table_entry_t ia32_options[] = {
2180 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2181 #ifdef FIRM_GRGEN_BE
2182 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2184 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2185 &ia32_isa_template.base.stack_alignment),
2186 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2190 const arch_isa_if_t ia32_isa_if = {
2192 ia32_lower_for_target,
2194 ia32_handle_intrinsics,
2195 ia32_get_reg_class_for_mode,
2197 ia32_get_reg_class_alignment,
2198 ia32_get_libfirm_params,
2201 ia32_parse_asm_constraint,
2202 ia32_is_valid_clobber,
2205 ia32_get_pic_base, /* return node used as base in pic code addresses */
2206 ia32_before_abi, /* before abi introduce hook */
2208 ia32_before_ra, /* before register allocation hook */
2209 ia32_after_ra, /* after register allocation hook */
2210 ia32_finish, /* called before codegen */
2211 ia32_emit, /* emit && done */
2214 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
2215 void be_init_arch_ia32(void)
2217 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2218 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2220 lc_opt_add_table(ia32_grp, ia32_options);
2221 be_register_isa_if("ia32", &ia32_isa_if);
2223 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2225 ia32_init_emitter();
2227 ia32_init_optimize();
2228 ia32_init_transform();
2230 ia32_init_architecture();