1 #include "pseudo_irg.h"
5 #include "bearch_ia32.h"
12 #ifdef obstack_chunk_alloc
13 # undef obstack_chunk_alloc
14 # define obstack_chunk_alloc malloc
16 # define obstack_chunk_alloc malloc
17 # define obstack_chunk_free free
20 #include "../bearch.h" /* the general register allocator interface */
22 #include "ia32_new_nodes.h" /* ia32 nodes interface */
23 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
24 #include "ia32_gen_decls.h" /* interface declaration emitter */
25 #include "ia32_transform.h"
26 #include "ia32_emitter.h"
27 #include "ia32_map_regs.h"
29 #define DEBUG_MODULE "be.isa.ia32"
32 static set *cur_reg_set = NULL;
35 * Stuff needed for dummy register requirements to keep register allocator
36 * happy during development.
38 static arch_register_t ia32_dummy_regs[500];
39 static arch_register_class_t ia32_dummy_reg_class = {
45 static arch_register_req_t ia32_dummy_register_req = {
46 arch_register_req_type_normal,
47 &ia32_dummy_reg_class,
53 /**************************************************
56 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
57 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
58 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
59 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
62 **************************************************/
64 static ir_node *my_skip_proj(const ir_node *n) {
71 * Return register requirements for an ia32 node.
72 * If the node returns a tuple (mode_T) then the proj's
73 * will be asked for this information.
75 static const arch_register_req_t *ia32_get_irn_reg_req(const arch_irn_ops_t *self, arch_register_req_t *req, const ir_node *irn, int pos) {
76 const arch_register_req_t **irn_req;
77 long node_pos = pos == -1 ? 0 : pos;
78 ir_mode *mode = get_irn_mode(irn);
79 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
81 if (mode == mode_T || mode == mode_M) {
82 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
86 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
90 node_pos = translate_proj_pos(irn);
94 irn = my_skip_proj(irn);
96 DBG((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
99 if (is_ia32_irn(irn)) {
101 irn_req = get_ia32_in_req(irn);
104 irn_req = get_ia32_out_req(irn);
108 DBG((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
110 memcpy(req, irn_req[pos], sizeof(*req));
114 /* treat Phi like Const with default requirements */
116 DBG((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
117 if (mode_is_float(mode))
118 memcpy(req, &ia32_default_req_ia32_floating_point, sizeof(*req));
119 else if (mode_is_int(mode) || mode_is_reference(mode))
120 memcpy(req, &ia32_default_req_ia32_general_purpose, sizeof(*req));
121 else if (mode == mode_T || mode == mode_M) {
122 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
126 assert(0 && "unsupported Phi-Mode");
128 else if (get_irn_op(irn) == op_Start) {
129 DBG((mod, LEVEL_1, "returning reqs none for ProjX -> Start (%+F )\n", irn));
131 case pn_Start_X_initial_exec:
132 case pn_Start_P_value_arg_base:
133 case pn_Start_P_globals:
134 case pn_Start_P_frame_base:
135 memcpy(req, &ia32_default_req_none, sizeof(*req));
137 // memcpy(req, &ia32_default_req_ia32_general_purpose, sizeof(*req));
139 case pn_Start_T_args:
140 assert(0 && "ProjT(pn_Start_T_args) should not be asked");
143 else if (get_irn_op(irn) == op_Return && pos >= 0) {
144 DBG((mod, LEVEL_1, "returning reqs EAX for %+F\n", irn));
145 memcpy(req, &ia32_default_req_ia32_general_purpose_eax, sizeof(*req));
148 DBG((mod, LEVEL_1, "returning standard reqs for %+F (not ia32)\n", irn));
149 memcpy(req, &ia32_dummy_register_req, sizeof(*req));
156 static void ia32_set_irn_reg(const arch_irn_ops_t *self, ir_node *irn, const arch_register_t *reg) {
160 pos = translate_proj_pos(irn);
161 irn = my_skip_proj(irn);
164 if (is_ia32_irn(irn)) {
165 const arch_register_t **slots;
167 slots = get_ia32_slots(irn);
171 ia32_set_firm_reg(self, irn, reg, cur_reg_set);
175 static const arch_register_t *ia32_get_irn_reg(const arch_irn_ops_t *self, const ir_node *irn) {
177 const arch_register_t *reg = NULL;
180 pos = translate_proj_pos(irn);
181 irn = my_skip_proj(irn);
184 if (is_ia32_irn(irn)) {
185 const arch_register_t **slots;
186 slots = get_ia32_slots(irn);
190 reg = ia32_get_firm_reg(self, irn, cur_reg_set);
196 static arch_irn_class_t ia32_classify(const arch_irn_ops_t *self, const ir_node *irn) {
197 irn = my_skip_proj(irn);
199 return arch_irn_class_branch;
201 return arch_irn_class_normal;
204 static arch_irn_flags_t ia32_get_flags(const arch_irn_ops_t *self, const ir_node *irn) {
205 irn = my_skip_proj(irn);
206 if (is_ia32_irn(irn))
207 return get_ia32_flags(irn);
209 ir_printf("don't know flags of %+F\n", irn);
214 /* fill register allocator interface */
216 static const arch_irn_ops_t ia32_irn_ops = {
217 ia32_get_irn_reg_req,
226 /**************************************************
229 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
230 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
231 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
232 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
235 **************************************************/
237 typedef struct _ia32_code_gen_t {
238 const arch_code_generator_if_t *impl; /* implementation */
239 ir_graph *irg; /* current irg */
240 FILE *out; /* output file */
241 set *reg_set; /* set to memorize registers for non-ia32 nodes (e.g. phi nodes) */
242 firm_dbg_module_t *mod; /* debugging module */
249 * Transforms the standard firm graph into
252 static void ia32_prepare_graph(void *self) {
253 ia32_code_gen_t *cg = self;
255 if (! is_pseudo_ir_graph(cg->irg))
256 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg->mod);
262 * Dummy functions for hooks we don't need but which must be filled.
264 static void ia32_before_sched(void *self) {
267 static void ia32_before_ra(void *self) {
273 * Emits the code, closes the output file and frees
274 * the code generator interface.
276 static void ia32_codegen(void *self) {
277 ia32_code_gen_t *cg = self;
278 ir_graph *irg = cg->irg;
281 if (cg->emit_decls) {
282 ia32_gen_decls(cg->out);
286 // ia32_finish_irg(irg);
287 ia32_gen_routine(out, irg, cur_reg_set);
291 /* de-allocate code generator */
292 del_set(cg->reg_set);
296 static const arch_code_generator_if_t ia32_code_gen_if = {
298 ia32_before_sched, /* before scheduling hook */
299 ia32_before_ra, /* before register allocation hook */
300 ia32_codegen /* emit && done */
305 /*****************************************************************
306 * ____ _ _ _____ _____
307 * | _ \ | | | | |_ _|/ ____| /\
308 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
309 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
310 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
311 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
313 *****************************************************************/
315 typedef struct _ia32_isa_t {
316 const arch_isa_if_t *impl;
322 * Initializes the backend ISA and opens the output file.
324 static void *ia32_init(FILE *out) {
326 static struct obstack obst;
327 static int inited = 0;
328 ia32_isa_t *isa = malloc(sizeof(*isa));
330 isa->impl = &ia32_isa_if;
337 isa->output_file = out;
338 isa->num_codegens = 0;
340 /* init dummy register requirements */
343 for (i = 0; i < 500; i++) {
347 arch_register_t *reg = &ia32_dummy_regs[i];
349 n = snprintf(buf, sizeof(buf), "d%d", i);
350 name = obstack_copy0(&obst, buf, n);
353 reg->reg_class = &ia32_dummy_reg_class;
355 reg->type = arch_register_type_none;
358 obstack_free(&obst, NULL);
360 ia32_register_init();
361 ia32_create_opcodes();
369 * Closes the output file and frees the ISA structure.
371 static void ia32_done(void *self) {
377 static int ia32_get_n_reg_class(const void *self) {
381 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
382 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
383 return &ia32_reg_classes[i];
386 static const arch_irn_ops_t *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
387 return &ia32_irn_ops;
390 const arch_irn_handler_t ia32_irn_handler = {
394 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
395 return &ia32_irn_handler;
401 * Initializes the code generator interface.
403 static arch_code_generator_t *ia32_make_code_generator(void *self, ir_graph *irg) {
404 ia32_isa_t *isa = self;
405 ia32_code_gen_t *cg = malloc(sizeof(*cg));
407 cg->impl = &ia32_code_gen_if;
409 cg->reg_set = new_set(cmp_irn_reg_assoc, 1024);
410 cg->mod = firm_dbg_register("be.transform.ia32");
411 cg->out = isa->output_file;
415 if (isa->num_codegens > 1)
420 cur_reg_set = cg->reg_set;
422 return (arch_code_generator_t *)cg;
426 * Returns the default scheduler
428 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
429 return trivial_selector;
433 static void ia32_register_options(lc_opt_entry_t *ent)
436 #endif /* WITH_LIBCORE */
438 const arch_isa_if_t ia32_isa_if = {
440 ia32_register_options,
444 ia32_get_n_reg_class,
446 ia32_get_irn_handler,
447 ia32_make_code_generator,
448 ia32_get_list_sched_selector