2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
33 #include "pseudo_irg.h"
38 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
56 #include "../benode.h"
57 #include "../belower.h"
58 #include "../besched.h"
61 #include "../beirgmod.h"
62 #include "../be_dbgout.h"
63 #include "../beblocksched.h"
64 #include "../bemachine.h"
65 #include "../beilpsched.h"
66 #include "../bespillslots.h"
67 #include "../bemodule.h"
68 #include "../begnuas.h"
69 #include "../bestate.h"
70 #include "../beflags.h"
71 #include "../betranshlp.h"
72 #include "../belistsched.h"
74 #include "bearch_ia32_t.h"
76 #include "ia32_new_nodes.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "gen_ia32_machine.h"
79 #include "ia32_common_transform.h"
80 #include "ia32_transform.h"
81 #include "ia32_emitter.h"
82 #include "ia32_map_regs.h"
83 #include "ia32_optimize.h"
85 #include "ia32_dbg_stat.h"
86 #include "ia32_finish.h"
87 #include "ia32_util.h"
89 #include "ia32_architecture.h"
92 #include "ia32_pbqp_transform.h"
94 transformer_t be_transformer = TRANSFORMER_DEFAULT;
97 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
99 ir_mode *mode_fpcw = NULL;
100 ia32_code_gen_t *ia32_current_cg = NULL;
102 /** The current omit-fp state */
103 static unsigned ia32_curr_fp_ommitted = 0;
104 static ir_type *omit_fp_between_type = NULL;
105 static ir_type *between_type = NULL;
106 static ir_entity *old_bp_ent = NULL;
107 static ir_entity *ret_addr_ent = NULL;
108 static ir_entity *omit_fp_ret_addr_ent = NULL;
111 * The environment for the intrinsic mapping.
113 static ia32_intrinsic_env_t intrinsic_env = {
115 NULL, /* the irg, these entities belong to */
116 NULL, /* entity for __divdi3 library call */
117 NULL, /* entity for __moddi3 library call */
118 NULL, /* entity for __udivdi3 library call */
119 NULL, /* entity for __umoddi3 library call */
123 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
126 * Used to create per-graph unique pseudo nodes.
128 static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
129 create_const_node_func func,
130 const arch_register_t* reg)
132 ir_node *block, *res;
137 block = get_irg_start_block(cg->irg);
138 res = func(NULL, block);
139 arch_set_irn_register(res, reg);
145 /* Creates the unique per irg GP NoReg node. */
146 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg)
148 return create_const(cg, &cg->noreg_gp, new_bd_ia32_NoReg_GP,
149 &ia32_gp_regs[REG_GP_NOREG]);
152 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg)
154 return create_const(cg, &cg->noreg_vfp, new_bd_ia32_NoReg_VFP,
155 &ia32_vfp_regs[REG_VFP_NOREG]);
158 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg)
160 return create_const(cg, &cg->noreg_xmm, new_bd_ia32_NoReg_XMM,
161 &ia32_xmm_regs[REG_XMM_NOREG]);
164 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg)
166 return create_const(cg, &cg->unknown_gp, new_bd_ia32_Unknown_GP,
167 &ia32_gp_regs[REG_GP_UKNWN]);
170 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg)
172 return create_const(cg, &cg->unknown_vfp, new_bd_ia32_Unknown_VFP,
173 &ia32_vfp_regs[REG_VFP_UKNWN]);
176 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg)
178 return create_const(cg, &cg->unknown_xmm, new_bd_ia32_Unknown_XMM,
179 &ia32_xmm_regs[REG_XMM_UKNWN]);
182 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg)
184 return create_const(cg, &cg->fpu_trunc_mode, new_bd_ia32_ChangeCW,
185 &ia32_fp_cw_regs[REG_FPCW]);
190 * Returns the admissible noreg register node for input register pos of node irn.
192 static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
194 const arch_register_req_t *req = arch_get_register_req(irn, pos);
196 assert(req != NULL && "Missing register requirements");
197 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
198 return ia32_new_NoReg_gp(cg);
200 if (ia32_cg_config.use_sse2) {
201 return ia32_new_NoReg_xmm(cg);
203 return ia32_new_NoReg_vfp(cg);
207 /**************************************************
210 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
211 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
212 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
213 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
216 **************************************************/
218 static const arch_register_req_t *get_ia32_SwitchJmp_out_req(
219 const ir_node *node, int pos)
223 return arch_no_register_req;
226 static arch_irn_class_t ia32_classify(const ir_node *irn)
228 arch_irn_class_t classification = 0;
230 assert(is_ia32_irn(irn));
232 if (is_ia32_is_reload(irn))
233 classification |= arch_irn_class_reload;
235 if (is_ia32_is_spill(irn))
236 classification |= arch_irn_class_spill;
238 if (is_ia32_is_remat(irn))
239 classification |= arch_irn_class_remat;
241 return classification;
245 * The IA32 ABI callback object.
248 be_abi_call_flags_bits_t flags; /**< The call flags. */
249 const arch_env_t *aenv; /**< The architecture environment. */
250 ir_graph *irg; /**< The associated graph. */
253 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
255 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
258 static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent)
260 set_ia32_frame_ent(irn, ent);
263 static void ia32_set_frame_offset(ir_node *irn, int bias)
265 if (get_ia32_frame_ent(irn) == NULL)
268 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
269 ia32_code_gen_t *cg = ia32_current_cg;
270 int omit_fp = be_abi_omit_fp(cg->birg->abi);
272 /* Pop nodes modify the stack pointer before calculating the
273 * destination address, so fix this here
278 add_ia32_am_offs_int(irn, bias);
281 static int ia32_get_sp_bias(const ir_node *node)
283 if (is_ia32_Call(node))
284 return -(int)get_ia32_call_attr_const(node)->pop;
286 if (is_ia32_Push(node))
289 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
296 * Generate the routine prologue.
298 * @param self The callback object.
299 * @param mem A pointer to the mem node. Update this if you define new memory.
300 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
301 * @param stack_bias Points to the current stack bias, can be modified if needed.
303 * @return The register which shall be used as a stack frame base.
305 * All nodes which define registers in @p reg_map must keep @p reg_map current.
307 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
309 ia32_abi_env_t *env = self;
310 ia32_code_gen_t *cg = ia32_current_cg;
311 const arch_env_t *arch_env = env->aenv;
313 ia32_curr_fp_ommitted = env->flags.try_omit_fp;
314 if (! env->flags.try_omit_fp) {
315 ir_node *bl = get_irg_start_block(env->irg);
316 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
317 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
318 ir_node *noreg = ia32_new_NoReg_gp(cg);
321 /* mark bp register as ignore */
322 be_set_constr_single_reg_out(get_Proj_pred(curr_bp),
323 get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
326 push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
327 curr_sp = new_r_Proj(bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
328 *mem = new_r_Proj(bl, push, mode_M, pn_ia32_Push_M);
330 /* the push must have SP out register */
331 arch_set_irn_register(curr_sp, arch_env->sp);
333 /* this modifies the stack bias, because we pushed 32bit */
336 /* move esp to ebp */
337 curr_bp = be_new_Copy(arch_env->bp->reg_class, bl, curr_sp);
338 be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
339 arch_register_req_type_ignore);
341 /* beware: the copy must be done before any other sp use */
342 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
343 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
344 arch_register_req_type_produces_sp);
346 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
347 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
356 * Generate the routine epilogue.
357 * @param self The callback object.
358 * @param bl The block for the epilog
359 * @param mem A pointer to the mem node. Update this if you define new memory.
360 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
361 * @return The register which shall be used as a stack frame base.
363 * All nodes which define registers in @p reg_map must keep @p reg_map current.
365 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
367 ia32_abi_env_t *env = self;
368 const arch_env_t *arch_env = env->aenv;
369 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
370 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
372 if (env->flags.try_omit_fp) {
373 /* simply remove the stack frame here */
374 curr_sp = be_new_IncSP(arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
376 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
378 if (ia32_cg_config.use_leave) {
382 leave = new_bd_ia32_Leave(NULL, bl, curr_bp);
383 curr_bp = new_r_Proj(bl, leave, mode_bp, pn_ia32_Leave_frame);
384 curr_sp = new_r_Proj(bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
388 /* the old SP is not needed anymore (kill the proj) */
389 assert(is_Proj(curr_sp));
392 /* copy ebp to esp */
393 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], bl, curr_bp);
394 arch_set_irn_register(curr_sp, arch_env->sp);
395 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
396 arch_register_req_type_ignore);
399 pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
400 curr_bp = new_r_Proj(bl, pop, mode_bp, pn_ia32_Pop_res);
401 curr_sp = new_r_Proj(bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
403 *mem = new_r_Proj(bl, pop, mode_M, pn_ia32_Pop_M);
405 arch_set_irn_register(curr_sp, arch_env->sp);
406 arch_set_irn_register(curr_bp, arch_env->bp);
409 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
410 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
414 * Initialize the callback object.
415 * @param call The call object.
416 * @param aenv The architecture environment.
417 * @param irg The graph with the method.
418 * @return Some pointer. This pointer is passed to all other callback functions as self object.
420 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
422 ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
423 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
424 env->flags = fl.bits;
431 * Destroy the callback object.
432 * @param self The callback object.
434 static void ia32_abi_done(void *self)
440 * Build the between type and entities if not already build.
442 static void ia32_build_between_type(void)
444 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
445 if (! between_type) {
446 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
447 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
449 between_type = new_type_struct(IDENT("ia32_between_type"));
450 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
451 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
453 set_entity_offset(old_bp_ent, 0);
454 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
455 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
456 set_type_state(between_type, layout_fixed);
458 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
459 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
461 set_entity_offset(omit_fp_ret_addr_ent, 0);
462 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
463 set_type_state(omit_fp_between_type, layout_fixed);
469 * Produces the type which sits between the stack args and the locals on the stack.
470 * it will contain the return address and space to store the old base pointer.
471 * @return The Firm type modeling the ABI between type.
473 static ir_type *ia32_abi_get_between_type(void *self)
475 ia32_abi_env_t *env = self;
477 ia32_build_between_type();
478 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
482 * Return the stack entity that contains the return address.
484 ir_entity *ia32_get_return_address_entity(void)
486 ia32_build_between_type();
487 return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent;
491 * Return the stack entity that contains the frame address.
493 ir_entity *ia32_get_frame_address_entity(void)
495 ia32_build_between_type();
496 return ia32_curr_fp_ommitted ? NULL : old_bp_ent;
500 * Get the estimated cycle count for @p irn.
502 * @param self The this pointer.
503 * @param irn The node.
505 * @return The estimated cycle count for this operation
507 static int ia32_get_op_estimated_cost(const ir_node *irn)
510 ia32_op_type_t op_tp;
514 if (!is_ia32_irn(irn))
517 assert(is_ia32_irn(irn));
519 cost = get_ia32_latency(irn);
520 op_tp = get_ia32_op_type(irn);
522 if (is_ia32_CopyB(irn)) {
525 else if (is_ia32_CopyB_i(irn)) {
526 int size = get_ia32_copyb_size(irn);
527 cost = 20 + (int)ceil((4/3) * size);
529 /* in case of address mode operations add additional cycles */
530 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
532 In case of stack access and access to fixed addresses add 5 cycles
533 (we assume they are in cache), other memory operations cost 20
536 if (is_ia32_use_frame(irn) || (
537 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
538 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
550 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
552 * @param irn The original operation
553 * @param i Index of the argument we want the inverse operation to yield
554 * @param inverse struct to be filled with the resulting inverse op
555 * @param obstack The obstack to use for allocation of the returned nodes array
556 * @return The inverse operation or NULL if operation invertible
558 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
562 ir_node *block, *noreg, *nomem;
565 /* we cannot invert non-ia32 irns */
566 if (! is_ia32_irn(irn))
569 /* operand must always be a real operand (not base, index or mem) */
570 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
573 /* we don't invert address mode operations */
574 if (get_ia32_op_type(irn) != ia32_Normal)
577 /* TODO: adjust for new immediates... */
578 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
582 block = get_nodes_block(irn);
583 mode = get_irn_mode(irn);
584 irn_mode = get_irn_mode(irn);
585 noreg = get_irn_n(irn, 0);
587 dbg = get_irn_dbg_info(irn);
589 /* initialize structure */
590 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
594 switch (get_ia32_irn_opcode(irn)) {
597 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
598 /* we have an add with a const here */
599 /* invers == add with negated const */
600 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
602 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
603 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
604 set_ia32_commutative(inverse->nodes[0]);
606 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
607 /* we have an add with a symconst here */
608 /* invers == sub with const */
609 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
611 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
614 /* normal add: inverse == sub */
615 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
622 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
623 /* we have a sub with a const/symconst here */
624 /* invers == add with this const */
625 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
626 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
627 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
631 if (i == n_ia32_binary_left) {
632 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
635 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
643 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
644 /* xor with const: inverse = xor */
645 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
646 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
647 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
651 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
657 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
662 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
667 /* inverse operation not supported */
674 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
676 if(mode_is_float(mode))
683 * Get the mode that should be used for spilling value node
685 static ir_mode *get_spill_mode(const ir_node *node)
687 ir_mode *mode = get_irn_mode(node);
688 return get_spill_mode_mode(mode);
692 * Checks whether an addressmode reload for a node with mode mode is compatible
693 * with a spillslot of mode spill_mode
695 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
697 return !mode_is_float(mode) || mode == spillmode;
701 * Check if irn can load its operand at position i from memory (source addressmode).
702 * @param irn The irn to be checked
703 * @param i The operands position
704 * @return Non-Zero if operand can be loaded
706 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
708 ir_node *op = get_irn_n(irn, i);
709 const ir_mode *mode = get_irn_mode(op);
710 const ir_mode *spillmode = get_spill_mode(op);
712 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
713 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
714 !ia32_is_spillmode_compatible(mode, spillmode) ||
715 is_ia32_use_frame(irn)) /* must not already use frame */
718 switch (get_ia32_am_support(irn)) {
723 if (i != n_ia32_unary_op)
729 case n_ia32_binary_left: {
730 const arch_register_req_t *req;
731 if (!is_ia32_commutative(irn))
734 /* we can't swap left/right for limited registers
735 * (As this (currently) breaks constraint handling copies)
737 req = get_ia32_in_req(irn, n_ia32_binary_left);
738 if (req->type & arch_register_req_type_limited)
743 case n_ia32_binary_right:
752 panic("Unknown AM type");
755 /* HACK: must not already use "real" memory.
756 * This can happen for Call and Div */
757 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
763 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
767 ir_mode *dest_op_mode;
769 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
771 set_ia32_op_type(irn, ia32_AddrModeS);
773 load_mode = get_irn_mode(get_irn_n(irn, i));
774 dest_op_mode = get_ia32_ls_mode(irn);
775 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
776 set_ia32_ls_mode(irn, load_mode);
778 set_ia32_use_frame(irn);
779 set_ia32_need_stackent(irn);
781 if (i == n_ia32_binary_left &&
782 get_ia32_am_support(irn) == ia32_am_binary &&
783 /* immediates are only allowed on the right side */
784 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
785 ia32_swap_left_right(irn);
786 i = n_ia32_binary_right;
789 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
791 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
792 set_irn_n(irn, n_ia32_mem, spill);
793 set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i));
794 set_ia32_is_reload(irn);
797 static const be_abi_callbacks_t ia32_abi_callbacks = {
800 ia32_abi_get_between_type,
805 /* register allocator interface */
806 static const arch_irn_ops_t ia32_irn_ops = {
809 ia32_get_frame_entity,
810 ia32_set_frame_entity,
811 ia32_set_frame_offset,
814 ia32_get_op_estimated_cost,
815 ia32_possible_memory_operand,
816 ia32_perform_memory_operand,
819 /* special register allocator interface for SwitchJmp
820 as it possibly has a WIDE range of Proj numbers.
821 We don't want to allocate output for register constraints for
823 static const arch_irn_ops_t ia32_SwitchJmp_irn_ops = {
824 /* Note: we also use SwitchJmp_out_req for the inputs too:
825 This is because the bearch API has a conceptual problem at the moment.
826 Querying for negative proj numbers which can happen for switchs
827 isn't possible and will result in inputs getting queried */
828 get_ia32_SwitchJmp_out_req,
830 ia32_get_frame_entity,
831 ia32_set_frame_entity,
832 ia32_set_frame_offset,
835 ia32_get_op_estimated_cost,
836 ia32_possible_memory_operand,
837 ia32_perform_memory_operand,
840 /**************************************************
843 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
844 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
845 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
846 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
849 **************************************************/
851 static ir_entity *mcount = NULL;
853 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
855 static void ia32_before_abi(void *self)
857 lower_mode_b_config_t lower_mode_b_config = {
858 mode_Iu, /* lowered mode */
859 mode_Bu, /* preferred mode for set */
860 0, /* don't lower direct compares */
862 ia32_code_gen_t *cg = self;
864 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
866 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
868 if (mcount == NULL) {
869 ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
870 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
871 /* FIXME: enter the right ld_ident here */
872 set_entity_ld_ident(mcount, get_entity_ident(mcount));
873 set_entity_visibility(mcount, visibility_external_allocated);
875 instrument_initcall(cg->irg, mcount);
880 * Transforms the standard firm graph into
883 static void ia32_prepare_graph(void *self)
885 ia32_code_gen_t *cg = self;
887 switch (be_transformer) {
888 case TRANSFORMER_DEFAULT:
889 /* transform remaining nodes into assembler instructions */
890 ia32_transform_graph(cg);
894 case TRANSFORMER_PBQP:
895 case TRANSFORMER_RAND:
896 /* transform nodes into assembler instructions by PBQP magic */
897 ia32_transform_graph_by_pbqp(cg);
902 panic("invalid transformer");
905 /* do local optimizations (mainly CSE) */
906 optimize_graph_df(cg->irg);
909 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
911 /* optimize address mode */
912 ia32_optimize_graph(cg);
914 /* do code placement, to optimize the position of constants */
918 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
921 ir_node *turn_back_am(ir_node *node)
923 dbg_info *dbgi = get_irn_dbg_info(node);
924 ir_node *block = get_nodes_block(node);
925 ir_node *base = get_irn_n(node, n_ia32_base);
926 ir_node *index = get_irn_n(node, n_ia32_index);
927 ir_node *mem = get_irn_n(node, n_ia32_mem);
930 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
931 ir_node *load_res = new_rd_Proj(dbgi, block, load, mode_Iu, pn_ia32_Load_res);
933 ia32_copy_am_attrs(load, node);
934 if (is_ia32_is_reload(node))
935 set_ia32_is_reload(load);
936 set_irn_n(node, n_ia32_mem, new_NoMem());
938 switch (get_ia32_am_support(node)) {
940 set_irn_n(node, n_ia32_unary_op, load_res);
944 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
945 set_irn_n(node, n_ia32_binary_left, load_res);
947 set_irn_n(node, n_ia32_binary_right, load_res);
952 panic("Unknown AM type");
954 noreg = ia32_new_NoReg_gp(ia32_current_cg);
955 set_irn_n(node, n_ia32_base, noreg);
956 set_irn_n(node, n_ia32_index, noreg);
957 set_ia32_am_offs_int(node, 0);
958 set_ia32_am_sc(node, NULL);
959 set_ia32_am_scale(node, 0);
960 clear_ia32_am_sc_sign(node);
962 /* rewire mem-proj */
963 if (get_irn_mode(node) == mode_T) {
964 const ir_edge_t *edge;
965 foreach_out_edge(node, edge) {
966 ir_node *out = get_edge_src_irn(edge);
967 if (get_irn_mode(out) == mode_M) {
968 set_Proj_pred(out, load);
969 set_Proj_proj(out, pn_ia32_Load_M);
975 set_ia32_op_type(node, ia32_Normal);
976 if (sched_is_scheduled(node))
977 sched_add_before(node, load);
982 static ir_node *flags_remat(ir_node *node, ir_node *after)
984 /* we should turn back source address mode when rematerializing nodes */
989 if (is_Block(after)) {
992 block = get_nodes_block(after);
995 type = get_ia32_op_type(node);
1001 case ia32_AddrModeD:
1002 /* TODO implement this later... */
1003 panic("found DestAM with flag user %+F this should not happen", node);
1006 default: assert(type == ia32_Normal); break;
1009 copy = exact_copy(node);
1010 set_nodes_block(copy, block);
1011 sched_add_after(after, copy);
1017 * Called before the register allocator.
1019 static void ia32_before_ra(void *self)
1021 ia32_code_gen_t *cg = self;
1023 /* setup fpu rounding modes */
1024 ia32_setup_fpu_mode(cg);
1027 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1030 ia32_add_missing_keeps(cg);
1035 * Transforms a be_Reload into a ia32 Load.
1037 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node)
1039 ir_graph *irg = get_irn_irg(node);
1040 dbg_info *dbg = get_irn_dbg_info(node);
1041 ir_node *block = get_nodes_block(node);
1042 ir_entity *ent = be_get_frame_entity(node);
1043 ir_mode *mode = get_irn_mode(node);
1044 ir_mode *spillmode = get_spill_mode(node);
1045 ir_node *noreg = ia32_new_NoReg_gp(cg);
1046 ir_node *sched_point = NULL;
1047 ir_node *ptr = get_irg_frame(irg);
1048 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1049 ir_node *new_op, *proj;
1050 const arch_register_t *reg;
1052 if (sched_is_scheduled(node)) {
1053 sched_point = sched_prev(node);
1056 if (mode_is_float(spillmode)) {
1057 if (ia32_cg_config.use_sse2)
1058 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
1060 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
1062 else if (get_mode_size_bits(spillmode) == 128) {
1063 /* Reload 128 bit SSE registers */
1064 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
1067 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
1069 set_ia32_op_type(new_op, ia32_AddrModeS);
1070 set_ia32_ls_mode(new_op, spillmode);
1071 set_ia32_frame_ent(new_op, ent);
1072 set_ia32_use_frame(new_op);
1073 set_ia32_is_reload(new_op);
1075 DBG_OPT_RELOAD2LD(node, new_op);
1077 proj = new_rd_Proj(dbg, block, new_op, mode, pn_ia32_Load_res);
1080 sched_add_after(sched_point, new_op);
1084 /* copy the register from the old node to the new Load */
1085 reg = arch_get_irn_register(node);
1086 arch_set_irn_register(proj, reg);
1088 SET_IA32_ORIG_NODE(new_op, node);
1090 exchange(node, proj);
1094 * Transforms a be_Spill node into a ia32 Store.
1096 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node)
1098 ir_graph *irg = get_irn_irg(node);
1099 dbg_info *dbg = get_irn_dbg_info(node);
1100 ir_node *block = get_nodes_block(node);
1101 ir_entity *ent = be_get_frame_entity(node);
1102 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1103 ir_mode *mode = get_spill_mode(spillval);
1104 ir_node *noreg = ia32_new_NoReg_gp(cg);
1105 ir_node *nomem = new_NoMem();
1106 ir_node *ptr = get_irg_frame(irg);
1107 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1109 ir_node *sched_point = NULL;
1111 if (sched_is_scheduled(node)) {
1112 sched_point = sched_prev(node);
1115 /* No need to spill unknown values... */
1116 if(is_ia32_Unknown_GP(val) ||
1117 is_ia32_Unknown_VFP(val) ||
1118 is_ia32_Unknown_XMM(val)) {
1123 exchange(node, store);
1127 if (mode_is_float(mode)) {
1128 if (ia32_cg_config.use_sse2)
1129 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
1131 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
1132 } else if (get_mode_size_bits(mode) == 128) {
1133 /* Spill 128 bit SSE registers */
1134 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
1135 } else if (get_mode_size_bits(mode) == 8) {
1136 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
1138 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
1141 set_ia32_op_type(store, ia32_AddrModeD);
1142 set_ia32_ls_mode(store, mode);
1143 set_ia32_frame_ent(store, ent);
1144 set_ia32_use_frame(store);
1145 set_ia32_is_spill(store);
1146 SET_IA32_ORIG_NODE(store, node);
1147 DBG_OPT_SPILL2ST(node, store);
1150 sched_add_after(sched_point, store);
1154 exchange(node, store);
1157 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
1159 dbg_info *dbg = get_irn_dbg_info(node);
1160 ir_node *block = get_nodes_block(node);
1161 ir_node *noreg = ia32_new_NoReg_gp(cg);
1162 ir_graph *irg = get_irn_irg(node);
1163 ir_node *frame = get_irg_frame(irg);
1165 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
1167 set_ia32_frame_ent(push, ent);
1168 set_ia32_use_frame(push);
1169 set_ia32_op_type(push, ia32_AddrModeS);
1170 set_ia32_ls_mode(push, mode_Is);
1171 set_ia32_is_spill(push);
1173 sched_add_before(schedpoint, push);
1177 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
1179 dbg_info *dbg = get_irn_dbg_info(node);
1180 ir_node *block = get_nodes_block(node);
1181 ir_node *noreg = ia32_new_NoReg_gp(cg);
1182 ir_graph *irg = get_irn_irg(node);
1183 ir_node *frame = get_irg_frame(irg);
1185 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
1187 set_ia32_frame_ent(pop, ent);
1188 set_ia32_use_frame(pop);
1189 set_ia32_op_type(pop, ia32_AddrModeD);
1190 set_ia32_ls_mode(pop, mode_Is);
1191 set_ia32_is_reload(pop);
1193 sched_add_before(schedpoint, pop);
1198 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1200 dbg_info *dbg = get_irn_dbg_info(node);
1201 ir_node *block = get_nodes_block(node);
1202 ir_mode *spmode = mode_Iu;
1203 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1206 sp = new_rd_Proj(dbg, block, pred, spmode, pos);
1207 arch_set_irn_register(sp, spreg);
1213 * Transform MemPerm, currently we do this the ugly way and produce
1214 * push/pop into/from memory cascades. This is possible without using
1217 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
1219 ir_node *block = get_nodes_block(node);
1220 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1221 int arity = be_get_MemPerm_entity_arity(node);
1222 ir_node **pops = ALLOCAN(ir_node*, arity);
1226 const ir_edge_t *edge;
1227 const ir_edge_t *next;
1230 for(i = 0; i < arity; ++i) {
1231 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1232 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1233 ir_type *enttype = get_entity_type(inent);
1234 unsigned entsize = get_type_size_bytes(enttype);
1235 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1236 ir_node *mem = get_irn_n(node, i + 1);
1239 /* work around cases where entities have different sizes */
1240 if(entsize2 < entsize)
1242 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1244 push = create_push(cg, node, node, sp, mem, inent);
1245 sp = create_spproj(node, push, pn_ia32_Push_stack);
1247 /* add another push after the first one */
1248 push = create_push(cg, node, node, sp, mem, inent);
1249 add_ia32_am_offs_int(push, 4);
1250 sp = create_spproj(node, push, pn_ia32_Push_stack);
1253 set_irn_n(node, i, new_Bad());
1257 for(i = arity - 1; i >= 0; --i) {
1258 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1259 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1260 ir_type *enttype = get_entity_type(outent);
1261 unsigned entsize = get_type_size_bytes(enttype);
1262 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1265 /* work around cases where entities have different sizes */
1266 if(entsize2 < entsize)
1268 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1270 pop = create_pop(cg, node, node, sp, outent);
1271 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1273 add_ia32_am_offs_int(pop, 4);
1275 /* add another pop after the first one */
1276 pop = create_pop(cg, node, node, sp, outent);
1277 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1284 keep = be_new_Keep(block, 1, in);
1285 sched_add_before(node, keep);
1287 /* exchange memprojs */
1288 foreach_out_edge_safe(node, edge, next) {
1289 ir_node *proj = get_edge_src_irn(edge);
1290 int p = get_Proj_proj(proj);
1294 set_Proj_pred(proj, pops[p]);
1295 set_Proj_proj(proj, pn_ia32_Pop_M);
1298 /* remove memperm */
1299 arity = get_irn_arity(node);
1300 for(i = 0; i < arity; ++i) {
1301 set_irn_n(node, i, new_Bad());
1307 * Block-Walker: Calls the transform functions Spill and Reload.
1309 static void ia32_after_ra_walker(ir_node *block, void *env)
1311 ir_node *node, *prev;
1312 ia32_code_gen_t *cg = env;
1314 /* beware: the schedule is changed here */
1315 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1316 prev = sched_prev(node);
1318 if (be_is_Reload(node)) {
1319 transform_to_Load(cg, node);
1320 } else if (be_is_Spill(node)) {
1321 transform_to_Store(cg, node);
1322 } else if (be_is_MemPerm(node)) {
1323 transform_MemPerm(cg, node);
1329 * Collects nodes that need frame entities assigned.
1331 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1333 be_fec_env_t *env = data;
1334 const ir_mode *mode;
1337 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1338 mode = get_spill_mode_mode(get_irn_mode(node));
1339 align = get_mode_size_bytes(mode);
1340 } else if (is_ia32_irn(node) &&
1341 get_ia32_frame_ent(node) == NULL &&
1342 is_ia32_use_frame(node)) {
1343 if (is_ia32_need_stackent(node))
1346 switch (get_ia32_irn_opcode(node)) {
1348 case iro_ia32_Load: {
1349 const ia32_attr_t *attr = get_ia32_attr_const(node);
1351 if (attr->data.need_32bit_stackent) {
1353 } else if (attr->data.need_64bit_stackent) {
1356 mode = get_ia32_ls_mode(node);
1357 if (is_ia32_is_reload(node))
1358 mode = get_spill_mode_mode(mode);
1360 align = get_mode_size_bytes(mode);
1364 case iro_ia32_vfild:
1366 case iro_ia32_xLoad: {
1367 mode = get_ia32_ls_mode(node);
1372 case iro_ia32_FldCW: {
1373 /* although 2 byte would be enough 4 byte performs best */
1381 panic("unexpected frame user while collection frame entity nodes");
1383 case iro_ia32_FnstCW:
1384 case iro_ia32_Store8Bit:
1385 case iro_ia32_Store:
1388 case iro_ia32_vfist:
1389 case iro_ia32_vfisttp:
1391 case iro_ia32_xStore:
1392 case iro_ia32_xStoreSimple:
1399 be_node_needs_frame_entity(env, node, mode, align);
1403 * We transform Spill and Reload here. This needs to be done before
1404 * stack biasing otherwise we would miss the corrected offset for these nodes.
1406 static void ia32_after_ra(void *self)
1408 ia32_code_gen_t *cg = self;
1409 ir_graph *irg = cg->irg;
1410 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1412 /* create and coalesce frame entities */
1413 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1414 be_assign_entities(fec_env);
1415 be_free_frame_entity_coalescer(fec_env);
1417 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1421 * Last touchups for the graph before emit: x87 simulation to replace the
1422 * virtual with real x87 instructions, creating a block schedule and peephole
1425 static void ia32_finish(void *self)
1427 ia32_code_gen_t *cg = self;
1428 ir_graph *irg = cg->irg;
1430 ia32_finish_irg(irg, cg);
1432 /* we might have to rewrite x87 virtual registers */
1433 if (cg->do_x87_sim) {
1434 x87_simulate_graph(cg->birg);
1437 /* do peephole optimisations */
1438 ia32_peephole_optimization(cg);
1440 /* create block schedule, this also removes empty blocks which might
1441 * produce critical edges */
1442 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1446 * Emits the code, closes the output file and frees
1447 * the code generator interface.
1449 static void ia32_codegen(void *self)
1451 ia32_code_gen_t *cg = self;
1452 ir_graph *irg = cg->irg;
1454 if (ia32_cg_config.emit_machcode) {
1455 ia32_gen_binary_routine(cg, irg);
1457 ia32_gen_routine(cg, irg);
1460 /* remove it from the isa */
1463 assert(ia32_current_cg == cg);
1464 ia32_current_cg = NULL;
1466 /* de-allocate code generator */
1471 * Returns the node representing the PIC base.
1473 static ir_node *ia32_get_pic_base(void *self)
1476 ia32_code_gen_t *cg = self;
1477 ir_node *get_eip = cg->get_eip;
1478 if (get_eip != NULL)
1481 block = get_irg_start_block(cg->irg);
1482 get_eip = new_bd_ia32_GetEIP(NULL, block);
1483 cg->get_eip = get_eip;
1485 be_dep_on_frame(get_eip);
1489 static void *ia32_cg_init(be_irg_t *birg);
1491 static const arch_code_generator_if_t ia32_code_gen_if = {
1493 ia32_get_pic_base, /* return node used as base in pic code addresses */
1494 ia32_before_abi, /* before abi introduce hook */
1497 ia32_before_ra, /* before register allocation hook */
1498 ia32_after_ra, /* after register allocation hook */
1499 ia32_finish, /* called before codegen */
1500 ia32_codegen /* emit && done */
1504 * Initializes a IA32 code generator.
1506 static void *ia32_cg_init(be_irg_t *birg)
1508 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
1509 ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t);
1511 cg->impl = &ia32_code_gen_if;
1512 cg->irg = birg->irg;
1515 cg->blk_sched = NULL;
1516 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1517 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1520 /* Linux gprof implementation needs base pointer */
1521 birg->main_env->options->omit_fp = 0;
1528 if (isa->name_obst) {
1529 obstack_free(isa->name_obst, NULL);
1530 obstack_init(isa->name_obst);
1534 assert(ia32_current_cg == NULL);
1535 ia32_current_cg = cg;
1537 return (arch_code_generator_t *)cg;
1542 /*****************************************************************
1543 * ____ _ _ _____ _____
1544 * | _ \ | | | | |_ _|/ ____| /\
1545 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1546 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1547 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1548 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1550 *****************************************************************/
1553 * Set output modes for GCC
1555 static const tarval_mode_info mo_integer = {
1562 * set the tarval output mode of all integer modes to decimal
1564 static void set_tarval_output_modes(void)
1568 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1569 ir_mode *mode = get_irp_mode(i);
1571 if (mode_is_int(mode))
1572 set_tarval_mode_output_option(mode, &mo_integer);
1576 const arch_isa_if_t ia32_isa_if;
1579 * The template that generates a new ISA object.
1580 * Note that this template can be changed by command line
1583 static ia32_isa_t ia32_isa_template = {
1585 &ia32_isa_if, /* isa interface implementation */
1586 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1587 &ia32_gp_regs[REG_EBP], /* base pointer register */
1588 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1589 -1, /* stack direction */
1590 2, /* power of two stack alignment, 2^2 == 4 */
1591 NULL, /* main environment */
1592 7, /* costs for a spill instruction */
1593 5, /* costs for a reload instruction */
1595 NULL, /* 16bit register names */
1596 NULL, /* 8bit register names */
1597 NULL, /* 8bit register names high */
1600 NULL, /* current code generator */
1601 NULL, /* abstract machine */
1603 NULL, /* name obstack */
1607 static void init_asm_constraints(void)
1609 be_init_default_asm_constraint_flags();
1611 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1612 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1613 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1614 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1615 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1616 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1617 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1618 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1619 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1620 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1621 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1622 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1623 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1624 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1625 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1626 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1627 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1628 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1629 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1630 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1632 /* no support for autodecrement/autoincrement */
1633 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1634 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1635 /* no float consts */
1636 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1637 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1638 /* makes no sense on x86 */
1639 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1640 /* no support for sse consts yet */
1641 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1642 /* no support for x87 consts yet */
1643 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1644 /* no support for mmx registers yet */
1645 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1646 /* not available in 32bit mode */
1647 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1648 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1650 /* no code yet to determine register class needed... */
1651 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1655 * Initializes the backend ISA.
1657 static arch_env_t *ia32_init(FILE *file_handle)
1659 static int inited = 0;
1667 set_tarval_output_modes();
1669 isa = XMALLOC(ia32_isa_t);
1670 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1672 if(mode_fpcw == NULL) {
1673 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1676 ia32_register_init();
1677 ia32_create_opcodes(&ia32_irn_ops);
1678 /* special handling for SwitchJmp */
1679 op_ia32_SwitchJmp->ops.be_ops = &ia32_SwitchJmp_irn_ops;
1681 be_emit_init(file_handle);
1682 isa->regs_16bit = pmap_create();
1683 isa->regs_8bit = pmap_create();
1684 isa->regs_8bit_high = pmap_create();
1685 isa->types = pmap_create();
1686 isa->tv_ent = pmap_create();
1687 isa->cpu = ia32_init_machine_description();
1689 ia32_build_16bit_reg_map(isa->regs_16bit);
1690 ia32_build_8bit_reg_map(isa->regs_8bit);
1691 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1694 isa->name_obst = XMALLOC(struct obstack);
1695 obstack_init(isa->name_obst);
1698 /* enter the ISA object into the intrinsic environment */
1699 intrinsic_env.isa = isa;
1701 /* emit asm includes */
1702 n = get_irp_n_asms();
1703 for (i = 0; i < n; ++i) {
1704 be_emit_cstring("#APP\n");
1705 be_emit_ident(get_irp_asm(i));
1706 be_emit_cstring("\n#NO_APP\n");
1709 /* needed for the debug support */
1710 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1711 be_emit_cstring(".Ltext0:\n");
1712 be_emit_write_line();
1714 /* we mark referenced global entities, so we can only emit those which
1715 * are actually referenced. (Note: you mustn't use the type visited flag
1716 * elsewhere in the backend)
1718 inc_master_type_visited();
1720 return &isa->arch_env;
1726 * Closes the output file and frees the ISA structure.
1728 static void ia32_done(void *self)
1730 ia32_isa_t *isa = self;
1732 /* emit now all global declarations */
1733 be_gas_emit_decls(isa->arch_env.main_env, 1);
1735 pmap_destroy(isa->regs_16bit);
1736 pmap_destroy(isa->regs_8bit);
1737 pmap_destroy(isa->regs_8bit_high);
1738 pmap_destroy(isa->tv_ent);
1739 pmap_destroy(isa->types);
1742 obstack_free(isa->name_obst, NULL);
1752 * Return the number of register classes for this architecture.
1753 * We report always these:
1754 * - the general purpose registers
1755 * - the SSE floating point register set
1756 * - the virtual floating point registers
1757 * - the SSE vector register set
1759 static unsigned ia32_get_n_reg_class(void)
1765 * Return the register class for index i.
1767 static const arch_register_class_t *ia32_get_reg_class(unsigned i)
1769 assert(i < N_CLASSES);
1770 return &ia32_reg_classes[i];
1774 * Get the register class which shall be used to store a value of a given mode.
1775 * @param self The this pointer.
1776 * @param mode The mode in question.
1777 * @return A register class which can hold values of the given mode.
1779 const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1781 if (mode_is_float(mode)) {
1782 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1785 return &ia32_reg_classes[CLASS_ia32_gp];
1789 * Returns the register for parameter nr.
1791 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1792 const ir_mode *mode)
1794 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1795 &ia32_gp_regs[REG_ECX],
1796 &ia32_gp_regs[REG_EDX],
1799 static const unsigned MAXNUM_GPREG_ARGS = 3;
1801 static const arch_register_t *gpreg_param_reg_regparam[] = {
1802 &ia32_gp_regs[REG_EAX],
1803 &ia32_gp_regs[REG_EDX],
1804 &ia32_gp_regs[REG_ECX]
1807 static const arch_register_t *gpreg_param_reg_this[] = {
1808 &ia32_gp_regs[REG_ECX],
1813 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1814 &ia32_xmm_regs[REG_XMM0],
1815 &ia32_xmm_regs[REG_XMM1],
1816 &ia32_xmm_regs[REG_XMM2],
1817 &ia32_xmm_regs[REG_XMM3],
1818 &ia32_xmm_regs[REG_XMM4],
1819 &ia32_xmm_regs[REG_XMM5],
1820 &ia32_xmm_regs[REG_XMM6],
1821 &ia32_xmm_regs[REG_XMM7]
1824 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1825 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1827 static const unsigned MAXNUM_SSE_ARGS = 8;
1829 if ((cc & cc_this_call) && nr == 0)
1830 return gpreg_param_reg_this[0];
1832 if (! (cc & cc_reg_param))
1835 if (mode_is_float(mode)) {
1836 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1838 if (nr >= MAXNUM_SSE_ARGS)
1841 if (cc & cc_this_call) {
1842 return fpreg_sse_param_reg_this[nr];
1844 return fpreg_sse_param_reg_std[nr];
1845 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1846 unsigned num_regparam;
1848 if (get_mode_size_bits(mode) > 32)
1851 if (nr >= MAXNUM_GPREG_ARGS)
1854 if (cc & cc_this_call) {
1855 return gpreg_param_reg_this[nr];
1857 num_regparam = cc & ~cc_bits;
1858 if (num_regparam == 0) {
1859 /* default fastcall */
1860 return gpreg_param_reg_fastcall[nr];
1862 if (nr < num_regparam)
1863 return gpreg_param_reg_regparam[nr];
1867 panic("unknown argument mode");
1871 * Get the ABI restrictions for procedure calls.
1872 * @param self The this pointer.
1873 * @param method_type The type of the method (procedure) in question.
1874 * @param abi The abi object to be modified
1876 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1884 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1888 /* set abi flags for calls */
1889 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1890 call_flags.bits.store_args_sequential = 0;
1891 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1892 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1893 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1895 /* set parameter passing style */
1896 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1898 cc = get_method_calling_convention(method_type);
1899 if (get_method_variadicity(method_type) == variadicity_variadic) {
1900 /* pass all parameters of a variadic function on the stack */
1901 cc = cc_cdecl_set | (cc & cc_this_call);
1903 if (get_method_additional_properties(method_type) & mtp_property_private &&
1904 ia32_cg_config.optimize_cc) {
1905 /* set the fast calling conventions (allowing up to 3) */
1906 cc = SET_FASTCALL(cc) | 3;
1910 /* we have to pop the shadow parameter ourself for compound calls */
1911 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1912 && !(cc & cc_reg_param)) {
1913 pop_amount += get_mode_size_bytes(mode_P_data);
1916 n = get_method_n_params(method_type);
1917 for (i = regnum = 0; i < n; i++) {
1919 const arch_register_t *reg = NULL;
1921 tp = get_method_param_type(method_type, i);
1922 mode = get_type_mode(tp);
1924 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1927 be_abi_call_param_reg(abi, i, reg);
1930 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1931 * movl has a shorter opcode than mov[sz][bw]l */
1932 ir_mode *load_mode = mode;
1935 unsigned size = get_mode_size_bytes(mode);
1937 if (cc & cc_callee_clear_stk) {
1938 pop_amount += (size + 3U) & ~3U;
1941 if (size < 4) load_mode = mode_Iu;
1944 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1948 be_abi_call_set_pop(abi, pop_amount);
1950 /* set return registers */
1951 n = get_method_n_ress(method_type);
1953 assert(n <= 2 && "more than two results not supported");
1955 /* In case of 64bit returns, we will have two 32bit values */
1957 tp = get_method_res_type(method_type, 0);
1958 mode = get_type_mode(tp);
1960 assert(!mode_is_float(mode) && "two FP results not supported");
1962 tp = get_method_res_type(method_type, 1);
1963 mode = get_type_mode(tp);
1965 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1967 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1968 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1971 const arch_register_t *reg;
1973 tp = get_method_res_type(method_type, 0);
1974 assert(is_atomic_type(tp));
1975 mode = get_type_mode(tp);
1977 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1979 be_abi_call_res_reg(abi, 0, reg);
1983 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1987 if(!is_ia32_irn(irn)) {
1991 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1992 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1993 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1994 || is_ia32_Immediate(irn))
2001 * Initializes the code generator interface.
2003 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
2006 return &ia32_code_gen_if;
2010 * Returns the estimated execution time of an ia32 irn.
2012 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn)
2015 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
2018 list_sched_selector_t ia32_sched_selector;
2021 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
2023 static const list_sched_selector_t *ia32_get_list_sched_selector(
2024 const void *self, list_sched_selector_t *selector)
2027 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
2028 ia32_sched_selector.exectime = ia32_sched_exectime;
2029 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
2030 return &ia32_sched_selector;
2033 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
2040 * Returns the necessary byte alignment for storing a register of given class.
2042 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
2044 ir_mode *mode = arch_register_class_mode(cls);
2045 int bytes = get_mode_size_bytes(mode);
2047 if (mode_is_float(mode) && bytes > 8)
2052 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
2055 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
2056 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
2057 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
2060 static const be_execution_unit_t *_allowed_units_GP[] = {
2061 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
2062 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
2063 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
2064 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
2065 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
2066 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
2067 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2070 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2071 &be_machine_execution_units_DUMMY[0],
2074 static const be_execution_unit_t **_units_callret[] = {
2075 _allowed_units_BRANCH,
2078 static const be_execution_unit_t **_units_other[] = {
2082 static const be_execution_unit_t **_units_dummy[] = {
2083 _allowed_units_DUMMY,
2086 const be_execution_unit_t ***ret;
2088 if (is_ia32_irn(irn)) {
2089 ret = get_ia32_exec_units(irn);
2090 } else if (is_be_node(irn)) {
2091 if (be_is_Return(irn)) {
2092 ret = _units_callret;
2093 } else if (be_is_Barrier(irn)) {
2107 * Return the abstract ia32 machine.
2109 static const be_machine_t *ia32_get_machine(const void *self)
2111 const ia32_isa_t *isa = self;
2116 * Return irp irgs in the desired order.
2118 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2125 static void ia32_mark_remat(ir_node *node)
2127 if (is_ia32_irn(node)) {
2128 set_ia32_is_remat(node);
2133 * Check for Abs or -Abs.
2135 static int psi_is_Abs_or_Nabs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f)
2143 /* must be <, <=, >=, > */
2144 pnc = get_Proj_proj(sel);
2145 if (pnc != pn_Cmp_Ge && pnc != pn_Cmp_Gt &&
2146 pnc != pn_Cmp_Le && pnc != pn_Cmp_Lt)
2149 l = get_Cmp_left(cmp);
2150 r = get_Cmp_right(cmp);
2152 /* must be x cmp 0 */
2153 if ((l != t && l != f) || !is_Const(r) || !is_Const_null(r))
2156 if ((!is_Minus(t) || get_Minus_op(t) != f) &&
2157 (!is_Minus(f) || get_Minus_op(f) != t))
2163 * Check for Abs only
2165 static int psi_is_Abs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f)
2173 /* must be <, <=, >=, > */
2174 pnc = get_Proj_proj(sel);
2175 if (pnc != pn_Cmp_Ge && pnc != pn_Cmp_Gt &&
2176 pnc != pn_Cmp_Le && pnc != pn_Cmp_Lt)
2179 l = get_Cmp_left(cmp);
2180 r = get_Cmp_right(cmp);
2182 /* must be x cmp 0 */
2183 if ((l != t && l != f) || !is_Const(r) || !is_Const_null(r))
2186 if ((!is_Minus(t) || get_Minus_op(t) != f) &&
2187 (!is_Minus(f) || get_Minus_op(f) != t))
2190 if (pnc & pn_Cmp_Gt) {
2191 /* x >= 0 ? -x : x is NABS */
2195 /* x < 0 ? x : -x is NABS */
2204 * Allows or disallows the creation of Mux nodes for the given Phi nodes.
2206 * @param sel A selector of a Cond.
2207 * @param phi_list List of Phi nodes about to be converted (linked via get_Phi_next() field)
2208 * @param i First data predecessor involved in if conversion
2209 * @param j Second data predecessor involved in if conversion
2211 * @return 1 if allowed, 0 otherwise
2213 static int ia32_is_mux_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2220 /* we can't handle Muxs with 64bit compares yet */
2222 cmp = get_Proj_pred(sel);
2224 ir_node *left = get_Cmp_left(cmp);
2225 ir_mode *cmp_mode = get_irn_mode(left);
2226 if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32) {
2227 /* 64bit Abs IS supported */
2228 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2229 ir_node *t = get_Phi_pred(phi, i);
2230 ir_node *f = get_Phi_pred(phi, j);
2232 if (! psi_is_Abs(cmp, sel, t, f))
2238 /* we do not support nodes without Cmp yet */
2242 /* we do not support nodes without Cmp yet */
2246 pn = get_Proj_proj(sel);
2247 cl = get_Cmp_left(cmp);
2248 cr = get_Cmp_right(cmp);
2250 if (ia32_cg_config.use_cmov) {
2251 if (ia32_cg_config.use_sse2) {
2252 /* check the Phi nodes: no 64bit and no floating point cmov */
2253 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2254 ir_mode *mode = get_irn_mode(phi);
2256 if (mode_is_float(mode)) {
2257 /* check for Min, Max */
2258 ir_node *t = get_Phi_pred(phi, i);
2259 ir_node *f = get_Phi_pred(phi, j);
2261 /* SSE2 supports Min & Max */
2262 if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2263 if (cl == t && cr == f) {
2264 /* Mux(a <=/>= b, a, b) => MIN, MAX */
2266 } else if (cl == f && cr == t) {
2267 /* Mux(a <=/>= b, b, a) => MAX, MIN */
2272 } else if (get_mode_size_bits(mode) > 32) {
2278 /* check the Phi nodes: no 64bit and no floating point cmov */
2279 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2280 ir_mode *mode = get_irn_mode(phi);
2282 if (mode_is_float(mode)) {
2283 ir_node *t = get_Phi_pred(phi, i);
2284 ir_node *f = get_Phi_pred(phi, j);
2286 /* always support Mux(!float, C1, C2) */
2287 if (is_Const(t) && is_Const(f) && !mode_is_float(get_irn_mode(cl))) {
2288 switch (be_transformer) {
2289 case TRANSFORMER_DEFAULT:
2290 /* always support Mux(!float, C1, C2) */
2292 #ifdef FIRM_GRGEN_BE
2293 case TRANSFORMER_PBQP:
2294 case TRANSFORMER_RAND:
2295 /* no support for Mux(*, C1, C2) */
2299 panic("invalid transformer");
2302 /* only abs or nabs supported */
2303 if (! psi_is_Abs_or_Nabs(cmp, sel, t, f))
2305 } else if (get_mode_size_bits(mode) > 32)
2311 } else { /* No Cmov, only some special cases */
2313 /* Now some supported cases here */
2314 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2315 ir_mode *mode = get_irn_mode(phi);
2318 t = get_Phi_pred(phi, i);
2319 f = get_Phi_pred(phi, j);
2321 if (mode_is_float(mode)) {
2322 /* always support Mux(!float, C1, C2) */
2323 if (is_Const(t) && is_Const(f) &&
2324 !mode_is_float(get_irn_mode(cl))) {
2325 switch (be_transformer) {
2326 case TRANSFORMER_DEFAULT:
2327 /* always support Mux(!float, C1, C2) */
2329 #ifdef FIRM_GRGEN_BE
2330 case TRANSFORMER_PBQP:
2331 case TRANSFORMER_RAND:
2332 /* no support for Mux(*, C1, C2) */
2336 panic("invalid transformer");
2339 /* only abs or nabs supported */
2340 if (! psi_is_Abs_or_Nabs(cmp, sel, t, f))
2342 } else if (get_mode_size_bits(mode) > 32) {
2347 if (is_Const(t) && is_Const(f)) {
2348 if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
2349 /* always support Mux(x, C1, C2) */
2352 } else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2354 if (cl == t && cr == f) {
2355 /* Mux(a <=/>= b, a, b) => Min, Max */
2358 if (cl == f && cr == t) {
2359 /* Mux(a <=/>= b, b, a) => Max, Min */
2363 if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
2364 is_Const(f) && is_Const_null(f) && is_Sub(t) &&
2365 get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
2366 /* Mux(a >=u b, a - b, 0) unsigned Doz */
2369 if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
2370 is_Const(t) && is_Const_null(t) && is_Sub(f) &&
2371 get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
2372 /* Mux(a <=u b, 0, a - b) unsigned Doz */
2375 if (is_Const(cr) && is_Const_null(cr)) {
2376 if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
2377 /* Mux(a <=/>= 0 ? a : -a) Nabs/Abs */
2379 } else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
2380 /* Mux(a <=/>= 0 ? -a : a) Abs/Nabs */
2387 /* all checks passed */
2393 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2397 /* we already added all our simple flags to the flags modifier list in
2398 * init, so this flag we don't know. */
2399 return ASM_CONSTRAINT_FLAG_INVALID;
2402 static int ia32_is_valid_clobber(const char *clobber)
2404 return ia32_get_clobber_register(clobber) != NULL;
2408 * Create the trampoline code.
2410 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2412 ir_node *st, *p = trampoline;
2413 ir_mode *mode = get_irn_mode(p);
2416 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xb9), 0);
2417 mem = new_r_Proj(block, st, mode_M, pn_Store_M);
2418 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2419 st = new_r_Store(block, mem, p, env, 0);
2420 mem = new_r_Proj(block, st, mode_M, pn_Store_M);
2421 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2423 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xe9), 0);
2424 mem = new_r_Proj(block, st, mode_M, pn_Store_M);
2425 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2426 st = new_r_Store(block, mem, p, callee, 0);
2427 mem = new_r_Proj(block, st, mode_M, pn_Store_M);
2428 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2434 * Returns the libFirm configuration parameter for this backend.
2436 static const backend_params *ia32_get_libfirm_params(void)
2438 static const ir_settings_if_conv_t ifconv = {
2439 4, /* maxdepth, doesn't matter for Mux-conversion */
2440 ia32_is_mux_allowed /* allows or disallows Mux creation for given selector */
2442 static const ir_settings_arch_dep_t ad = {
2443 1, /* also use subs */
2444 4, /* maximum shifts */
2445 31, /* maximum shift amount */
2446 ia32_evaluate_insn, /* evaluate the instruction sequence */
2448 1, /* allow Mulhs */
2449 1, /* allow Mulus */
2450 32, /* Mulh allowed up to 32 bit */
2452 static backend_params p = {
2453 1, /* need dword lowering */
2454 1, /* support inline assembly */
2455 NULL, /* will be set later */
2456 ia32_create_intrinsic_fkt,
2457 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2458 NULL, /* ifconv info will be set below */
2459 NULL, /* float arithmetic mode, will be set below */
2460 12, /* size of trampoline code */
2461 4, /* alignment of trampoline code */
2462 ia32_create_trampoline_fkt,
2463 4 /* alignment of stack parameter */
2466 ia32_setup_cg_config();
2468 /* doesn't really belong here, but this is the earliest place the backend
2470 init_asm_constraints();
2473 p.if_conv_info = &ifconv;
2474 if (! ia32_cg_config.use_sse2)
2475 p.mode_float_arithmetic = mode_E;
2479 static const lc_opt_enum_int_items_t gas_items[] = {
2480 { "elf", GAS_FLAVOUR_ELF },
2481 { "mingw", GAS_FLAVOUR_MINGW },
2482 { "yasm", GAS_FLAVOUR_YASM },
2483 { "macho", GAS_FLAVOUR_MACH_O },
2487 static lc_opt_enum_int_var_t gas_var = {
2488 (int*) &be_gas_flavour, gas_items
2491 #ifdef FIRM_GRGEN_BE
2492 static const lc_opt_enum_int_items_t transformer_items[] = {
2493 { "default", TRANSFORMER_DEFAULT },
2494 { "pbqp", TRANSFORMER_PBQP },
2495 { "random", TRANSFORMER_RAND },
2499 static lc_opt_enum_int_var_t transformer_var = {
2500 (int*)&be_transformer, transformer_items
2504 static const lc_opt_table_entry_t ia32_options[] = {
2505 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2506 #ifdef FIRM_GRGEN_BE
2507 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2509 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2510 &ia32_isa_template.arch_env.stack_alignment),
2514 const arch_isa_if_t ia32_isa_if = {
2517 ia32_handle_intrinsics,
2518 ia32_get_n_reg_class,
2520 ia32_get_reg_class_for_mode,
2522 ia32_get_code_generator_if,
2523 ia32_get_list_sched_selector,
2524 ia32_get_ilp_sched_selector,
2525 ia32_get_reg_class_alignment,
2526 ia32_get_libfirm_params,
2527 ia32_get_allowed_execution_units,
2531 ia32_parse_asm_constraint,
2532 ia32_is_valid_clobber
2535 void be_init_arch_ia32(void)
2537 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2538 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2540 lc_opt_add_table(ia32_grp, ia32_options);
2541 be_register_isa_if("ia32", &ia32_isa_if);
2543 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2545 ia32_init_emitter();
2547 ia32_init_optimize();
2548 ia32_init_transform();
2550 ia32_init_architecture();
2553 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);