2 * This is the main ia32 firm backend driver.
17 #include "pseudo_irg.h"
21 #include "iredges_t.h"
29 #include "../beabi.h" /* the general register allocator interface */
30 #include "../benode_t.h"
31 #include "../belower.h"
32 #include "../besched_t.h"
34 #include "bearch_ia32_t.h"
36 #include "ia32_new_nodes.h" /* ia32 nodes interface */
37 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
38 #include "ia32_gen_decls.h" /* interface declaration emitter */
39 #include "ia32_transform.h"
40 #include "ia32_emitter.h"
41 #include "ia32_map_regs.h"
42 #include "ia32_optimize.h"
45 #define DEBUG_MODULE "firm.be.ia32.isa"
48 static set *cur_reg_set = NULL;
51 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
53 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
54 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
57 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
58 return be_abi_get_callee_save_irn(cg->birg->abi,
59 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
62 /**************************************************
65 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
66 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
67 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
68 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
71 **************************************************/
73 static ir_node *my_skip_proj(const ir_node *n) {
81 * Return register requirements for an ia32 node.
82 * If the node returns a tuple (mode_T) then the proj's
83 * will be asked for this information.
85 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
86 const ia32_irn_ops_t *ops = self;
87 const ia32_register_req_t *irn_req;
88 long node_pos = pos == -1 ? 0 : pos;
89 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
90 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
92 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
93 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
97 if (mode == mode_T && pos < 0) {
98 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
102 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
106 node_pos = ia32_translate_proj_pos(irn);
112 irn = my_skip_proj(irn);
114 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
117 if (is_ia32_irn(irn)) {
119 irn_req = get_ia32_in_req(irn, pos);
122 irn_req = get_ia32_out_req(irn, node_pos);
125 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
127 memcpy(req, &(irn_req->req), sizeof(*req));
129 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
130 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
131 req->other_same = get_irn_n(irn, irn_req->same_pos);
134 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
135 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
136 req->other_different = get_irn_n(irn, irn_req->different_pos);
140 /* treat Phi like Const with default requirements */
142 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
143 if (mode_is_float(mode)) {
144 if (USE_SSE2(ops->cg))
145 memcpy(req, &(ia32_default_req_ia32_xmm.req), sizeof(*req));
147 memcpy(req, &(ia32_default_req_ia32_vfp.req), sizeof(*req));
149 else if (mode_is_int(mode) || mode_is_reference(mode))
150 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
151 else if (mode == mode_T || mode == mode_M) {
152 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
156 assert(0 && "unsupported Phi-Mode");
159 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
167 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
169 const ia32_irn_ops_t *ops = self;
171 if (get_irn_mode(irn) == mode_X) {
175 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
178 pos = ia32_translate_proj_pos(irn);
179 irn = my_skip_proj(irn);
182 if (is_ia32_irn(irn)) {
183 const arch_register_t **slots;
185 slots = get_ia32_slots(irn);
189 ia32_set_firm_reg(irn, reg, cur_reg_set);
193 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
195 const arch_register_t *reg = NULL;
199 if (get_irn_mode(irn) == mode_X) {
203 pos = ia32_translate_proj_pos(irn);
204 irn = my_skip_proj(irn);
207 if (is_ia32_irn(irn)) {
208 const arch_register_t **slots;
209 slots = get_ia32_slots(irn);
213 reg = ia32_get_firm_reg(irn, cur_reg_set);
219 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
220 irn = my_skip_proj(irn);
222 return arch_irn_class_branch;
223 else if (is_ia32_irn(irn))
224 return arch_irn_class_normal;
229 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
230 irn = my_skip_proj(irn);
231 if (is_ia32_irn(irn))
232 return get_ia32_flags(irn);
238 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
239 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
242 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
244 const ia32_irn_ops_t *ops = self;
246 if (is_ia32_use_frame(irn) && bias != 0) {
247 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
249 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
250 snprintf(buf, sizeof(buf), "%d", bias);
251 add_ia32_am_offs(irn, buf);
253 set_ia32_am_flavour(irn, am_flav);
258 be_abi_call_flags_bits_t flags;
259 const arch_isa_t *isa;
263 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
265 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
266 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
267 env->flags = fl.bits;
269 env->isa = aenv->isa;
273 static void ia32_abi_dont_save_regs(void *self, pset *s)
275 ia32_abi_env_t *env = self;
276 if(env->flags.try_omit_fp)
277 pset_insert_ptr(s, env->isa->bp);
280 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
282 ia32_abi_env_t *env = self;
283 const arch_register_t *frame_reg = env->isa->sp;
285 if(!env->flags.try_omit_fp) {
286 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
287 ir_node *bl = get_irg_start_block(env->irg);
288 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
289 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
290 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
293 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_expand);
294 store_bp = new_rd_ia32_Store(NULL, env->irg, bl, curr_sp, curr_no_reg, curr_bp, *mem, mode_T);
295 set_ia32_am_support(store_bp, ia32_am_Dest);
296 set_ia32_am_flavour(store_bp, ia32_B);
297 set_ia32_op_type(store_bp, ia32_AddrModeD);
298 *mem = new_r_Proj(env->irg, bl, store_bp, mode_M, 0);
299 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
300 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
301 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
303 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
304 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
310 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
312 ia32_abi_env_t *env = self;
313 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
314 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
315 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
317 if(env->flags.try_omit_fp) {
318 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
323 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
325 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
326 load_bp = new_rd_ia32_Load(NULL, env->irg, bl, curr_sp, curr_no_reg, *mem, mode_T);
327 set_ia32_am_support(load_bp, ia32_am_Source);
328 set_ia32_am_flavour(load_bp, ia32_B);
329 set_ia32_op_type(load_bp, ia32_AddrModeS);
330 set_ia32_ls_mode(load_bp, mode_bp);
331 curr_bp = new_r_Proj(env->irg, bl, load_bp, mode_bp, 0);
332 *mem = new_r_Proj(env->irg, bl, load_bp, mode_M, 1);
335 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
336 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
340 * Produces the type which sits between the stack args and the locals on the stack.
341 * it will contain the return address and space to store the old base pointer.
342 * @return The Firm type modeling the ABI between type.
344 static ir_type *ia32_abi_get_between_type(void *self)
346 static ir_type *omit_fp_between_type = NULL;
347 static ir_type *between_type = NULL;
349 ia32_abi_env_t *env = self;
353 entity *ret_addr_ent;
354 entity *omit_fp_ret_addr_ent;
356 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
357 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
359 between_type = new_type_class(new_id_from_str("ia32_between_type"));
360 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
361 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
363 set_entity_offset_bytes(old_bp_ent, 0);
364 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
365 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
367 omit_fp_between_type = new_type_class(new_id_from_str("ia32_between_type_omit_fp"));
368 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, new_id_from_str("ret_addr"), ret_addr_type);
370 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
371 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
374 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
377 static const be_abi_callbacks_t ia32_abi_callbacks = {
380 ia32_abi_get_between_type,
381 ia32_abi_dont_save_regs,
386 /* fill register allocator interface */
388 static const arch_irn_ops_if_t ia32_irn_ops_if = {
389 ia32_get_irn_reg_req,
394 ia32_get_frame_entity,
398 ia32_irn_ops_t ia32_irn_ops = {
405 /**************************************************
408 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
409 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
410 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
411 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
414 **************************************************/
417 * Transforms the standard firm graph into
420 static void ia32_prepare_graph(void *self) {
421 ia32_code_gen_t *cg = self;
422 firm_dbg_module_t *old_mod = cg->mod;
424 cg->mod = firm_dbg_register("firm.be.ia32.transform");
425 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
426 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
431 edges_deactivate(cg->irg);
432 //dead_node_elimination(cg->irg);
433 edges_activate(cg->irg);
435 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
436 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
442 * Insert copies for all ia32 nodes where the should_be_same requirement
444 * Transform Sub into Neg -- Add if IN2 == OUT
446 static void ia32_finish_irg_walker(ir_node *irn, void *env) {
447 ia32_code_gen_t *cg = env;
448 const ia32_register_req_t **reqs;
449 const arch_register_t *out_reg, *in_reg;
451 ir_node *copy, *in_node, *block;
452 ia32_op_type_t op_tp;
454 if (! is_ia32_irn(irn))
457 /* AM Dest nodes don't produce any values */
458 op_tp = get_ia32_op_type(irn);
459 if (op_tp == ia32_AddrModeD)
462 reqs = get_ia32_out_req_all(irn);
463 n_res = get_ia32_n_res(irn);
464 block = get_nodes_block(irn);
466 /* check all OUT requirements, if there is a should_be_same */
467 if (op_tp == ia32_Normal) {
468 for (i = 0; i < n_res; i++) {
469 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
470 /* get in and out register */
471 out_reg = get_ia32_out_reg(irn, i);
472 in_node = get_irn_n(irn, reqs[i]->same_pos);
473 in_reg = arch_get_irn_register(cg->arch_env, in_node);
475 /* don't copy ignore nodes */
476 if (arch_irn_is(cg->arch_env, in_node, ignore))
479 /* check if in and out register are equal */
480 if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
481 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
483 /* create copy from in register */
484 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
486 /* destination is the out register */
487 arch_set_irn_register(cg->arch_env, copy, out_reg);
489 /* insert copy before the node into the schedule */
490 sched_add_before(irn, copy);
493 set_irn_n(irn, reqs[i]->same_pos, copy);
499 /* check if there is a sub which need to be transformed */
500 ia32_transform_sub_to_neg_add(irn, cg);
502 /* transform a LEA into an Add if possible */
503 ia32_transform_lea_to_add(irn, cg);
505 /* check for peephole optimization */
506 ia32_peephole_optimization(irn, cg);
510 * Add Copy nodes for not fulfilled should_be_equal constraints
512 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
513 irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
519 * Dummy functions for hooks we don't need but which must be filled.
521 static void ia32_before_sched(void *self) {
525 * Called before the register allocator.
526 * Calculate a block schedule here. We need it for the x87
527 * simulator and the emitter.
529 static void ia32_before_ra(void *self) {
530 ia32_code_gen_t *cg = self;
532 cg->blk_sched = sched_create_block_schedule(cg->irg);
537 * Transforms a be node into a Load.
539 static void transform_to_Load(ia32_transform_env_t *env) {
540 ir_node *irn = env->irn;
541 entity *ent = be_get_frame_entity(irn);
542 ir_mode *mode = env->mode;
543 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
544 ir_node *nomem = new_rd_NoMem(env->irg);
545 ir_node *sched_point = NULL;
546 ir_node *ptr = get_irn_n(irn, 0);
547 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
548 ir_node *new_op, *proj;
549 const arch_register_t *reg;
551 if (sched_is_scheduled(irn)) {
552 sched_point = sched_prev(irn);
555 if (mode_is_float(mode)) {
556 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
559 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
562 set_ia32_am_support(new_op, ia32_am_Source);
563 set_ia32_op_type(new_op, ia32_AddrModeS);
564 set_ia32_am_flavour(new_op, ia32_B);
565 set_ia32_ls_mode(new_op, mode);
566 set_ia32_frame_ent(new_op, ent);
567 set_ia32_use_frame(new_op);
569 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
572 sched_add_after(sched_point, new_op);
573 sched_add_after(new_op, proj);
578 /* copy the register from the old node to the new Load */
579 reg = arch_get_irn_register(env->cg->arch_env, irn);
580 arch_set_irn_register(env->cg->arch_env, new_op, reg);
587 * Transforms a be node into a Store.
589 static void transform_to_Store(ia32_transform_env_t *env) {
590 ir_node *irn = env->irn;
591 entity *ent = be_get_frame_entity(irn);
592 ir_mode *mode = env->mode;
593 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
594 ir_node *nomem = new_rd_NoMem(env->irg);
595 ir_node *ptr = get_irn_n(irn, 0);
596 ir_node *val = get_irn_n(irn, 1);
597 ir_node *new_op, *proj;
598 ir_node *sched_point = NULL;
600 if (sched_is_scheduled(irn)) {
601 sched_point = sched_prev(irn);
604 if (mode_is_float(mode)) {
605 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
607 else if (get_mode_size_bits(mode) == 8) {
608 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
611 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
614 set_ia32_am_support(new_op, ia32_am_Dest);
615 set_ia32_op_type(new_op, ia32_AddrModeD);
616 set_ia32_am_flavour(new_op, ia32_B);
617 set_ia32_ls_mode(new_op, get_irn_mode(val));
618 set_ia32_frame_ent(new_op, ent);
619 set_ia32_use_frame(new_op);
621 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
624 sched_add_after(sched_point, new_op);
625 sched_add_after(new_op, proj);
635 * Calls the transform functions for StackParam, Spill and Reload.
637 static void ia32_after_ra_walker(ir_node *node, void *env) {
638 ia32_code_gen_t *cg = env;
639 ia32_transform_env_t tenv;
644 tenv.block = get_nodes_block(node);
645 tenv.dbg = get_irn_dbg_info(node);
646 tenv.irg = current_ir_graph;
649 tenv.mode = get_irn_mode(node);
652 /* be_is_StackParam(node) || */
653 if (be_is_Reload(node)) {
654 transform_to_Load(&tenv);
656 else if (be_is_Spill(node)) {
657 tenv.mode = get_irn_mode(be_get_Spill_context(node));
658 transform_to_Store(&tenv);
663 * We transform StackParam, Spill and Reload here. This needs to be done before
664 * stack biasing otherwise we would miss the corrected offset for these nodes.
666 static void ia32_after_ra(void *self) {
667 ia32_code_gen_t *cg = self;
668 irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
670 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
672 x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
673 be_dump(cg->irg, "-x87", dump_ir_extblock_graph_sched);
679 * Emits the code, closes the output file and frees
680 * the code generator interface.
682 static void ia32_codegen(void *self) {
683 ia32_code_gen_t *cg = self;
684 ir_graph *irg = cg->irg;
687 if (cg->emit_decls) {
688 ia32_gen_decls(cg->out);
692 ia32_finish_irg(irg, cg);
693 be_dump(irg, "-finished", dump_ir_block_graph_sched);
694 ia32_gen_routine(out, irg, cg);
698 pmap_destroy(cg->tv_ent);
699 pmap_destroy(cg->types);
701 /* de-allocate code generator */
702 del_set(cg->reg_set);
706 static void *ia32_cg_init(FILE *F, const be_irg_t *birg);
708 static const arch_code_generator_if_t ia32_code_gen_if = {
710 NULL, /* before abi introduce hook */
712 ia32_before_sched, /* before scheduling hook */
713 ia32_before_ra, /* before register allocation hook */
714 ia32_after_ra, /* after register allocation hook */
715 ia32_codegen /* emit && done */
719 * Initializes the code generator.
721 static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
722 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
723 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
725 cg->impl = &ia32_code_gen_if;
727 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
728 cg->mod = firm_dbg_register("firm.be.ia32.cg");
730 cg->arch_env = birg->main_env->arch_env;
731 cg->types = pmap_create();
732 cg->tv_ent = pmap_create();
734 cg->blk_sched = NULL;
735 cg->fp_kind = isa->fp_kind;
737 /* set optimizations */
740 cg->opt.placecnst = 1;
745 if (isa->name_obst_size) {
746 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
747 isa->name_obst_size = 0;
748 obstack_free(isa->name_obst, NULL);
749 obstack_init(isa->name_obst);
755 if (isa->num_codegens > 1)
760 cur_reg_set = cg->reg_set;
762 ia32_irn_ops.cg = cg;
764 return (arch_code_generator_t *)cg;
769 /*****************************************************************
770 * ____ _ _ _____ _____
771 * | _ \ | | | | |_ _|/ ____| /\
772 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
773 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
774 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
775 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
777 *****************************************************************/
779 static ia32_isa_t ia32_isa_template = {
780 &ia32_isa_if, /* isa interface implementation */
781 &ia32_gp_regs[REG_ESP], /* stack pointer register */
782 &ia32_gp_regs[REG_EBP], /* base pointer register */
783 -1, /* stack direction */
784 0, /* number of code generator objects so far */
785 NULL, /* 16bit register names */
786 NULL, /* 8bit register names */
787 fp_sse2, /* use SSE2 unit for fp operations */
789 NULL, /* name obstack */
790 0 /* name obst size */
795 * Initializes the backend ISA.
797 static void *ia32_init(void) {
798 static int inited = 0;
804 isa = xcalloc(1, sizeof(*isa));
805 memcpy(isa, &ia32_isa_template, sizeof(*isa));
807 ia32_register_init(isa);
808 ia32_create_opcodes();
809 ia32_register_copy_attr_func();
811 isa->regs_16bit = pmap_create();
812 isa->regs_8bit = pmap_create();
813 // isa->fp_kind = fp_x87;
815 ia32_build_16bit_reg_map(isa->regs_16bit);
816 ia32_build_8bit_reg_map(isa->regs_8bit);
819 isa->name_obst = xcalloc(1, sizeof(*(isa->name_obst)));
820 obstack_init(isa->name_obst);
821 isa->name_obst_size = 0;
832 * Closes the output file and frees the ISA structure.
834 static void ia32_done(void *self) {
835 ia32_isa_t *isa = self;
837 pmap_destroy(isa->regs_16bit);
838 pmap_destroy(isa->regs_8bit);
841 //printf("name obst size = %d bytes\n", isa->name_obst_size);
842 obstack_free(isa->name_obst, NULL);
850 * Return the number of register classes for this architecture.
851 * We report always these:
852 * - the general purpose registers
853 * - the floating point register set (depending on the unit used for FP)
854 * - MMX/SE registers (currently not supported)
856 static int ia32_get_n_reg_class(const void *self) {
861 * Return the register class for index i.
863 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
864 const ia32_isa_t *isa = self;
865 assert(i >= 0 && i < 2 && "Invalid ia32 register class requested.");
867 return &ia32_reg_classes[CLASS_ia32_gp];
868 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
872 * Get the register class which shall be used to store a value of a given mode.
873 * @param self The this pointer.
874 * @param mode The mode in question.
875 * @return A register class which can hold values of the given mode.
877 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
878 const ia32_isa_t *isa = self;
879 if (mode_is_float(mode)) {
880 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
883 return &ia32_reg_classes[CLASS_ia32_gp];
887 * Get the ABI restrictions for procedure calls.
888 * @param self The this pointer.
889 * @param method_type The type of the method (procedure) in question.
890 * @param abi The abi object to be modified
892 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
893 const ia32_isa_t *isa = self;
896 unsigned cc = get_method_calling_convention(method_type);
897 int n = get_method_n_params(method_type);
900 int i, ignore_1, ignore_2;
902 const arch_register_t *reg;
903 be_abi_call_flags_t call_flags;
905 /* set abi flags for calls */
906 call_flags.bits.left_to_right = 0;
907 call_flags.bits.store_args_sequential = 0;
908 call_flags.bits.try_omit_fp = 1;
909 call_flags.bits.fp_free = 0;
910 call_flags.bits.call_has_imm = 1;
912 /* set stack parameter passing style */
913 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
915 /* collect the mode for each type */
916 modes = alloca(n * sizeof(modes[0]));
918 for (i = 0; i < n; i++) {
919 tp = get_method_param_type(method_type, i);
920 modes[i] = get_type_mode(tp);
923 /* set register parameters */
924 if (cc & cc_reg_param) {
925 /* determine the number of parameters passed via registers */
926 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
928 /* loop over all parameters and set the register requirements */
929 for (i = 0; i <= biggest_n; i++) {
930 reg = ia32_get_RegParam_reg(n, modes, i, cc);
931 assert(reg && "kaputt");
932 be_abi_call_param_reg(abi, i, reg);
939 /* set stack parameters */
940 for (i = stack_idx; i < n; i++) {
941 be_abi_call_param_stack(abi, i, 1, 0, 0);
945 /* set return registers */
946 n = get_method_n_ress(method_type);
948 assert(n <= 2 && "more than two results not supported");
950 /* In case of 64bit returns, we will have two 32bit values */
952 tp = get_method_res_type(method_type, 0);
953 mode = get_type_mode(tp);
955 assert(!mode_is_float(mode) && "two FP results not supported");
957 tp = get_method_res_type(method_type, 1);
958 mode = get_type_mode(tp);
960 assert(!mode_is_float(mode) && "two FP results not supported");
962 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
963 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
966 const arch_register_t *reg;
968 tp = get_method_res_type(method_type, 0);
969 assert(is_atomic_type(tp));
970 mode = get_type_mode(tp);
972 reg = mode_is_float(mode) ?
973 (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
974 &ia32_gp_regs[REG_EAX];
976 be_abi_call_res_reg(abi, 0, reg);
981 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
982 return &ia32_irn_ops;
985 const arch_irn_handler_t ia32_irn_handler = {
989 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
990 return &ia32_irn_handler;
993 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
994 return is_ia32_irn(irn);
998 * Initializes the code generator interface.
1000 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1001 return &ia32_code_gen_if;
1004 list_sched_selector_t ia32_sched_selector;
1007 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1009 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
1010 memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1011 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1012 return &ia32_sched_selector;
1016 static void ia32_register_options(lc_opt_entry_t *ent)
1019 #endif /* WITH_LIBCORE */
1021 const arch_isa_if_t ia32_isa_if = {
1023 ia32_register_options,
1027 ia32_get_n_reg_class,
1029 ia32_get_reg_class_for_mode,
1031 ia32_get_irn_handler,
1032 ia32_get_code_generator_if,
1033 ia32_get_list_sched_selector