2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
37 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
57 #include "../benode.h"
58 #include "../belower.h"
59 #include "../besched.h"
62 #include "../beirgmod.h"
63 #include "../be_dbgout.h"
64 #include "../beblocksched.h"
65 #include "../bemachine.h"
66 #include "../beilpsched.h"
67 #include "../bespillslots.h"
68 #include "../bemodule.h"
69 #include "../begnuas.h"
70 #include "../bestate.h"
71 #include "../beflags.h"
72 #include "../betranshlp.h"
73 #include "../belistsched.h"
75 #include "bearch_ia32_t.h"
77 #include "ia32_new_nodes.h"
78 #include "gen_ia32_regalloc_if.h"
79 #include "gen_ia32_machine.h"
80 #include "ia32_common_transform.h"
81 #include "ia32_transform.h"
82 #include "ia32_emitter.h"
83 #include "ia32_map_regs.h"
84 #include "ia32_optimize.h"
86 #include "ia32_dbg_stat.h"
87 #include "ia32_finish.h"
88 #include "ia32_util.h"
90 #include "ia32_architecture.h"
93 #include "ia32_pbqp_transform.h"
95 transformer_t be_transformer = TRANSFORMER_DEFAULT;
98 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
100 ir_mode *mode_fpcw = NULL;
101 ia32_code_gen_t *ia32_current_cg = NULL;
103 /** The current omit-fp state */
104 static unsigned ia32_curr_fp_ommitted = 0;
105 static ir_type *omit_fp_between_type = NULL;
106 static ir_type *between_type = NULL;
107 static ir_entity *old_bp_ent = NULL;
108 static ir_entity *ret_addr_ent = NULL;
109 static ir_entity *omit_fp_ret_addr_ent = NULL;
112 * The environment for the intrinsic mapping.
114 static ia32_intrinsic_env_t intrinsic_env = {
116 NULL, /* the irg, these entities belong to */
117 NULL, /* entity for __divdi3 library call */
118 NULL, /* entity for __moddi3 library call */
119 NULL, /* entity for __udivdi3 library call */
120 NULL, /* entity for __umoddi3 library call */
124 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
127 * Used to create per-graph unique pseudo nodes.
129 static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
130 create_const_node_func func,
131 const arch_register_t* reg)
133 ir_node *block, *res;
138 block = get_irg_start_block(cg->irg);
139 res = func(NULL, block);
140 arch_set_irn_register(res, reg);
146 /* Creates the unique per irg GP NoReg node. */
147 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg)
149 return create_const(cg, &cg->noreg_gp, new_bd_ia32_NoReg_GP,
150 &ia32_gp_regs[REG_GP_NOREG]);
153 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg)
155 return create_const(cg, &cg->noreg_vfp, new_bd_ia32_NoReg_VFP,
156 &ia32_vfp_regs[REG_VFP_NOREG]);
159 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg)
161 return create_const(cg, &cg->noreg_xmm, new_bd_ia32_NoReg_XMM,
162 &ia32_xmm_regs[REG_XMM_NOREG]);
165 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg)
167 return create_const(cg, &cg->fpu_trunc_mode, new_bd_ia32_ChangeCW,
168 &ia32_fp_cw_regs[REG_FPCW]);
173 * Returns the admissible noreg register node for input register pos of node irn.
175 static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
177 const arch_register_req_t *req = arch_get_register_req(irn, pos);
179 assert(req != NULL && "Missing register requirements");
180 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
181 return ia32_new_NoReg_gp(cg);
183 if (ia32_cg_config.use_sse2) {
184 return ia32_new_NoReg_xmm(cg);
186 return ia32_new_NoReg_vfp(cg);
191 static const arch_register_req_t *get_ia32_SwitchJmp_out_req(
192 const ir_node *node, int pos)
196 return arch_no_register_req;
199 static arch_irn_class_t ia32_classify(const ir_node *irn)
201 arch_irn_class_t classification = 0;
203 assert(is_ia32_irn(irn));
205 if (is_ia32_is_reload(irn))
206 classification |= arch_irn_class_reload;
208 if (is_ia32_is_spill(irn))
209 classification |= arch_irn_class_spill;
211 if (is_ia32_is_remat(irn))
212 classification |= arch_irn_class_remat;
214 return classification;
218 * The IA32 ABI callback object.
221 be_abi_call_flags_bits_t flags; /**< The call flags. */
222 ir_graph *irg; /**< The associated graph. */
225 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
227 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
230 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
232 if (is_be_node(node))
233 be_node_set_frame_entity(node, entity);
235 set_ia32_frame_ent(node, entity);
238 static void ia32_set_frame_offset(ir_node *irn, int bias)
240 if (get_ia32_frame_ent(irn) == NULL)
243 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
244 ir_graph *irg = get_irn_irg(irn);
245 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
246 if (layout->sp_relative) {
247 /* Pop nodes modify the stack pointer before calculating the
248 * destination address, so fix this here
253 add_ia32_am_offs_int(irn, bias);
256 static int ia32_get_sp_bias(const ir_node *node)
258 if (is_ia32_Call(node))
259 return -(int)get_ia32_call_attr_const(node)->pop;
261 if (is_ia32_Push(node))
264 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
271 * Generate the routine prologue.
273 * @param self The callback object.
274 * @param mem A pointer to the mem node. Update this if you define new memory.
275 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
276 * @param stack_bias Points to the current stack bias, can be modified if needed.
278 * @return The register which shall be used as a stack frame base.
280 * All nodes which define registers in @p reg_map must keep @p reg_map current.
282 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
284 ia32_abi_env_t *env = self;
285 ia32_code_gen_t *cg = ia32_current_cg;
286 const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
288 ia32_curr_fp_ommitted = env->flags.try_omit_fp;
289 if (! env->flags.try_omit_fp) {
290 ir_node *bl = get_irg_start_block(env->irg);
291 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
292 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
293 ir_node *noreg = ia32_new_NoReg_gp(cg);
296 /* mark bp register as ignore */
297 be_set_constr_single_reg_out(get_Proj_pred(curr_bp),
298 get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
301 push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
302 curr_sp = new_r_Proj(push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
303 *mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
305 /* the push must have SP out register */
306 arch_set_irn_register(curr_sp, arch_env->sp);
308 /* this modifies the stack bias, because we pushed 32bit */
311 /* move esp to ebp */
312 curr_bp = be_new_Copy(arch_env->bp->reg_class, bl, curr_sp);
313 be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
314 arch_register_req_type_ignore);
316 /* beware: the copy must be done before any other sp use */
317 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
318 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
319 arch_register_req_type_produces_sp);
321 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
322 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
331 * Generate the routine epilogue.
332 * @param self The callback object.
333 * @param bl The block for the epilog
334 * @param mem A pointer to the mem node. Update this if you define new memory.
335 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
336 * @return The register which shall be used as a stack frame base.
338 * All nodes which define registers in @p reg_map must keep @p reg_map current.
340 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
342 ia32_abi_env_t *env = self;
343 const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
344 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
345 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
347 if (env->flags.try_omit_fp) {
348 /* simply remove the stack frame here */
349 curr_sp = be_new_IncSP(arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
351 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
353 if (ia32_cg_config.use_leave) {
357 leave = new_bd_ia32_Leave(NULL, bl, curr_bp);
358 curr_bp = new_r_Proj(leave, mode_bp, pn_ia32_Leave_frame);
359 curr_sp = new_r_Proj(leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
363 /* the old SP is not needed anymore (kill the proj) */
364 assert(is_Proj(curr_sp));
367 /* copy ebp to esp */
368 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], bl, curr_bp);
369 arch_set_irn_register(curr_sp, arch_env->sp);
370 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
371 arch_register_req_type_ignore);
374 pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
375 curr_bp = new_r_Proj(pop, mode_bp, pn_ia32_Pop_res);
376 curr_sp = new_r_Proj(pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
378 *mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
380 arch_set_irn_register(curr_sp, arch_env->sp);
381 arch_set_irn_register(curr_bp, arch_env->bp);
384 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
385 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
389 * Initialize the callback object.
390 * @param call The call object.
391 * @param irg The graph with the method.
392 * @return Some pointer. This pointer is passed to all other callback functions as self object.
394 static void *ia32_abi_init(const be_abi_call_t *call, ir_graph *irg)
396 ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
397 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
398 env->flags = fl.bits;
404 * Destroy the callback object.
405 * @param self The callback object.
407 static void ia32_abi_done(void *self)
413 * Build the between type and entities if not already build.
415 static void ia32_build_between_type(void)
417 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
418 if (! between_type) {
419 ir_type *old_bp_type = new_type_primitive(mode_Iu);
420 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
422 between_type = new_type_struct(IDENT("ia32_between_type"));
423 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
424 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
426 set_entity_offset(old_bp_ent, 0);
427 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
428 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
429 set_type_state(between_type, layout_fixed);
431 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
432 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
434 set_entity_offset(omit_fp_ret_addr_ent, 0);
435 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
436 set_type_state(omit_fp_between_type, layout_fixed);
442 * Produces the type which sits between the stack args and the locals on the stack.
443 * it will contain the return address and space to store the old base pointer.
444 * @return The Firm type modeling the ABI between type.
446 static ir_type *ia32_abi_get_between_type(void *self)
448 ia32_abi_env_t *env = self;
450 ia32_build_between_type();
451 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
455 * Return the stack entity that contains the return address.
457 ir_entity *ia32_get_return_address_entity(void)
459 ia32_build_between_type();
460 return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent;
464 * Return the stack entity that contains the frame address.
466 ir_entity *ia32_get_frame_address_entity(void)
468 ia32_build_between_type();
469 return ia32_curr_fp_ommitted ? NULL : old_bp_ent;
473 * Get the estimated cycle count for @p irn.
475 * @param self The this pointer.
476 * @param irn The node.
478 * @return The estimated cycle count for this operation
480 static int ia32_get_op_estimated_cost(const ir_node *irn)
483 ia32_op_type_t op_tp;
487 if (!is_ia32_irn(irn))
490 assert(is_ia32_irn(irn));
492 cost = get_ia32_latency(irn);
493 op_tp = get_ia32_op_type(irn);
495 if (is_ia32_CopyB(irn)) {
498 else if (is_ia32_CopyB_i(irn)) {
499 int size = get_ia32_copyb_size(irn);
500 cost = 20 + (int)ceil((4/3) * size);
502 /* in case of address mode operations add additional cycles */
503 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
505 In case of stack access and access to fixed addresses add 5 cycles
506 (we assume they are in cache), other memory operations cost 20
509 if (is_ia32_use_frame(irn) || (
510 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
511 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
523 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
525 * @param irn The original operation
526 * @param i Index of the argument we want the inverse operation to yield
527 * @param inverse struct to be filled with the resulting inverse op
528 * @param obstack The obstack to use for allocation of the returned nodes array
529 * @return The inverse operation or NULL if operation invertible
531 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
542 ir_node *block, *noreg, *nomem;
545 /* we cannot invert non-ia32 irns */
546 if (! is_ia32_irn(irn))
549 /* operand must always be a real operand (not base, index or mem) */
550 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
553 /* we don't invert address mode operations */
554 if (get_ia32_op_type(irn) != ia32_Normal)
557 /* TODO: adjust for new immediates... */
558 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
562 block = get_nodes_block(irn);
563 mode = get_irn_mode(irn);
564 irn_mode = get_irn_mode(irn);
565 noreg = get_irn_n(irn, 0);
567 dbg = get_irn_dbg_info(irn);
569 /* initialize structure */
570 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
574 switch (get_ia32_irn_opcode(irn)) {
577 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
578 /* we have an add with a const here */
579 /* invers == add with negated const */
580 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
582 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
583 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
584 set_ia32_commutative(inverse->nodes[0]);
586 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
587 /* we have an add with a symconst here */
588 /* invers == sub with const */
589 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
591 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
594 /* normal add: inverse == sub */
595 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
602 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
603 /* we have a sub with a const/symconst here */
604 /* invers == add with this const */
605 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
606 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
607 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
611 if (i == n_ia32_binary_left) {
612 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
615 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
623 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
624 /* xor with const: inverse = xor */
625 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
626 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
627 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
631 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
637 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
642 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
647 /* inverse operation not supported */
655 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
657 if (mode_is_float(mode))
664 * Get the mode that should be used for spilling value node
666 static ir_mode *get_spill_mode(const ir_node *node)
668 ir_mode *mode = get_irn_mode(node);
669 return get_spill_mode_mode(mode);
673 * Checks whether an addressmode reload for a node with mode mode is compatible
674 * with a spillslot of mode spill_mode
676 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
678 return !mode_is_float(mode) || mode == spillmode;
682 * Check if irn can load its operand at position i from memory (source addressmode).
683 * @param irn The irn to be checked
684 * @param i The operands position
685 * @return Non-Zero if operand can be loaded
687 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
689 ir_node *op = get_irn_n(irn, i);
690 const ir_mode *mode = get_irn_mode(op);
691 const ir_mode *spillmode = get_spill_mode(op);
693 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
694 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
695 !ia32_is_spillmode_compatible(mode, spillmode) ||
696 is_ia32_use_frame(irn)) /* must not already use frame */
699 switch (get_ia32_am_support(irn)) {
704 if (i != n_ia32_unary_op)
710 case n_ia32_binary_left: {
711 const arch_register_req_t *req;
712 if (!is_ia32_commutative(irn))
715 /* we can't swap left/right for limited registers
716 * (As this (currently) breaks constraint handling copies)
718 req = get_ia32_in_req(irn, n_ia32_binary_left);
719 if (req->type & arch_register_req_type_limited)
724 case n_ia32_binary_right:
733 panic("Unknown AM type");
736 /* HACK: must not already use "real" memory.
737 * This can happen for Call and Div */
738 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
744 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
748 ir_mode *dest_op_mode;
750 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
752 set_ia32_op_type(irn, ia32_AddrModeS);
754 load_mode = get_irn_mode(get_irn_n(irn, i));
755 dest_op_mode = get_ia32_ls_mode(irn);
756 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
757 set_ia32_ls_mode(irn, load_mode);
759 set_ia32_use_frame(irn);
760 set_ia32_need_stackent(irn);
762 if (i == n_ia32_binary_left &&
763 get_ia32_am_support(irn) == ia32_am_binary &&
764 /* immediates are only allowed on the right side */
765 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
766 ia32_swap_left_right(irn);
767 i = n_ia32_binary_right;
770 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
772 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
773 set_irn_n(irn, n_ia32_mem, spill);
774 set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i));
775 set_ia32_is_reload(irn);
778 static const be_abi_callbacks_t ia32_abi_callbacks = {
781 ia32_abi_get_between_type,
786 /* register allocator interface */
787 static const arch_irn_ops_t ia32_irn_ops = {
790 ia32_get_frame_entity,
791 ia32_set_frame_offset,
794 ia32_get_op_estimated_cost,
795 ia32_possible_memory_operand,
796 ia32_perform_memory_operand,
799 /* special register allocator interface for SwitchJmp
800 as it possibly has a WIDE range of Proj numbers.
801 We don't want to allocate output for register constraints for
803 static const arch_irn_ops_t ia32_SwitchJmp_irn_ops = {
804 /* Note: we also use SwitchJmp_out_req for the inputs too:
805 This is because the bearch API has a conceptual problem at the moment.
806 Querying for negative proj numbers which can happen for switchs
807 isn't possible and will result in inputs getting queried */
808 get_ia32_SwitchJmp_out_req,
810 ia32_get_frame_entity,
811 ia32_set_frame_offset,
814 ia32_get_op_estimated_cost,
815 ia32_possible_memory_operand,
816 ia32_perform_memory_operand,
820 static ir_entity *mcount = NULL;
822 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
824 static void ia32_before_abi(void *self)
826 lower_mode_b_config_t lower_mode_b_config = {
827 mode_Iu, /* lowered mode */
828 mode_Bu, /* preferred mode for set */
829 0, /* don't lower direct compares */
831 ia32_code_gen_t *cg = self;
833 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
835 dump_ir_graph(cg->irg, "lower_modeb");
838 if (mcount == NULL) {
839 ir_type *tp = new_type_method(0, 0);
840 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
841 /* FIXME: enter the right ld_ident here */
842 set_entity_ld_ident(mcount, get_entity_ident(mcount));
843 set_entity_visibility(mcount, ir_visibility_external);
845 instrument_initcall(cg->irg, mcount);
850 * Transforms the standard firm graph into
853 static void ia32_prepare_graph(void *self)
855 ia32_code_gen_t *cg = self;
858 switch (be_transformer) {
859 case TRANSFORMER_DEFAULT:
860 /* transform remaining nodes into assembler instructions */
861 ia32_transform_graph(cg);
864 case TRANSFORMER_PBQP:
865 case TRANSFORMER_RAND:
866 /* transform nodes into assembler instructions by PBQP magic */
867 ia32_transform_graph_by_pbqp(cg);
871 panic("invalid transformer");
874 ia32_transform_graph(cg);
877 /* do local optimizations (mainly CSE) */
878 optimize_graph_df(cg->irg);
881 dump_ir_graph(cg->irg, "transformed");
883 /* optimize address mode */
884 ia32_optimize_graph(cg);
886 /* do code placement, to optimize the position of constants */
890 dump_ir_graph(cg->irg, "place");
893 ir_node *turn_back_am(ir_node *node)
895 dbg_info *dbgi = get_irn_dbg_info(node);
896 ir_node *block = get_nodes_block(node);
897 ir_node *base = get_irn_n(node, n_ia32_base);
898 ir_node *index = get_irn_n(node, n_ia32_index);
899 ir_node *mem = get_irn_n(node, n_ia32_mem);
902 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
903 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
905 ia32_copy_am_attrs(load, node);
906 if (is_ia32_is_reload(node))
907 set_ia32_is_reload(load);
908 set_irn_n(node, n_ia32_mem, new_NoMem());
910 switch (get_ia32_am_support(node)) {
912 set_irn_n(node, n_ia32_unary_op, load_res);
916 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
917 set_irn_n(node, n_ia32_binary_left, load_res);
919 set_irn_n(node, n_ia32_binary_right, load_res);
924 panic("Unknown AM type");
926 noreg = ia32_new_NoReg_gp(ia32_current_cg);
927 set_irn_n(node, n_ia32_base, noreg);
928 set_irn_n(node, n_ia32_index, noreg);
929 set_ia32_am_offs_int(node, 0);
930 set_ia32_am_sc(node, NULL);
931 set_ia32_am_scale(node, 0);
932 clear_ia32_am_sc_sign(node);
934 /* rewire mem-proj */
935 if (get_irn_mode(node) == mode_T) {
936 const ir_edge_t *edge;
937 foreach_out_edge(node, edge) {
938 ir_node *out = get_edge_src_irn(edge);
939 if (get_irn_mode(out) == mode_M) {
940 set_Proj_pred(out, load);
941 set_Proj_proj(out, pn_ia32_Load_M);
947 set_ia32_op_type(node, ia32_Normal);
948 if (sched_is_scheduled(node))
949 sched_add_before(node, load);
954 static ir_node *flags_remat(ir_node *node, ir_node *after)
956 /* we should turn back source address mode when rematerializing nodes */
961 if (is_Block(after)) {
964 block = get_nodes_block(after);
967 type = get_ia32_op_type(node);
974 /* TODO implement this later... */
975 panic("found DestAM with flag user %+F this should not happen", node);
978 default: assert(type == ia32_Normal); break;
981 copy = exact_copy(node);
982 set_nodes_block(copy, block);
983 sched_add_after(after, copy);
989 * Called before the register allocator.
991 static void ia32_before_ra(void *self)
993 ia32_code_gen_t *cg = self;
995 /* setup fpu rounding modes */
996 ia32_setup_fpu_mode(cg);
999 be_sched_fix_flags(cg->irg, &ia32_reg_classes[CLASS_ia32_flags],
1002 ia32_add_missing_keeps(cg);
1007 * Transforms a be_Reload into a ia32 Load.
1009 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node)
1011 ir_graph *irg = get_irn_irg(node);
1012 dbg_info *dbg = get_irn_dbg_info(node);
1013 ir_node *block = get_nodes_block(node);
1014 ir_entity *ent = be_get_frame_entity(node);
1015 ir_mode *mode = get_irn_mode(node);
1016 ir_mode *spillmode = get_spill_mode(node);
1017 ir_node *noreg = ia32_new_NoReg_gp(cg);
1018 ir_node *sched_point = NULL;
1019 ir_node *ptr = get_irg_frame(irg);
1020 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1021 ir_node *new_op, *proj;
1022 const arch_register_t *reg;
1024 if (sched_is_scheduled(node)) {
1025 sched_point = sched_prev(node);
1028 if (mode_is_float(spillmode)) {
1029 if (ia32_cg_config.use_sse2)
1030 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
1032 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
1034 else if (get_mode_size_bits(spillmode) == 128) {
1035 /* Reload 128 bit SSE registers */
1036 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
1039 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
1041 set_ia32_op_type(new_op, ia32_AddrModeS);
1042 set_ia32_ls_mode(new_op, spillmode);
1043 set_ia32_frame_ent(new_op, ent);
1044 set_ia32_use_frame(new_op);
1045 set_ia32_is_reload(new_op);
1047 DBG_OPT_RELOAD2LD(node, new_op);
1049 proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
1052 sched_add_after(sched_point, new_op);
1056 /* copy the register from the old node to the new Load */
1057 reg = arch_get_irn_register(node);
1058 arch_set_irn_register(proj, reg);
1060 SET_IA32_ORIG_NODE(new_op, node);
1062 exchange(node, proj);
1066 * Transforms a be_Spill node into a ia32 Store.
1068 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node)
1070 ir_graph *irg = get_irn_irg(node);
1071 dbg_info *dbg = get_irn_dbg_info(node);
1072 ir_node *block = get_nodes_block(node);
1073 ir_entity *ent = be_get_frame_entity(node);
1074 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1075 ir_mode *mode = get_spill_mode(spillval);
1076 ir_node *noreg = ia32_new_NoReg_gp(cg);
1077 ir_node *nomem = new_NoMem();
1078 ir_node *ptr = get_irg_frame(irg);
1079 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1081 ir_node *sched_point = NULL;
1083 if (sched_is_scheduled(node)) {
1084 sched_point = sched_prev(node);
1087 if (mode_is_float(mode)) {
1088 if (ia32_cg_config.use_sse2)
1089 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
1091 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
1092 } else if (get_mode_size_bits(mode) == 128) {
1093 /* Spill 128 bit SSE registers */
1094 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
1095 } else if (get_mode_size_bits(mode) == 8) {
1096 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
1098 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
1101 set_ia32_op_type(store, ia32_AddrModeD);
1102 set_ia32_ls_mode(store, mode);
1103 set_ia32_frame_ent(store, ent);
1104 set_ia32_use_frame(store);
1105 set_ia32_is_spill(store);
1106 SET_IA32_ORIG_NODE(store, node);
1107 DBG_OPT_SPILL2ST(node, store);
1110 sched_add_after(sched_point, store);
1114 exchange(node, store);
1117 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
1119 dbg_info *dbg = get_irn_dbg_info(node);
1120 ir_node *block = get_nodes_block(node);
1121 ir_node *noreg = ia32_new_NoReg_gp(cg);
1122 ir_graph *irg = get_irn_irg(node);
1123 ir_node *frame = get_irg_frame(irg);
1125 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
1127 set_ia32_frame_ent(push, ent);
1128 set_ia32_use_frame(push);
1129 set_ia32_op_type(push, ia32_AddrModeS);
1130 set_ia32_ls_mode(push, mode_Is);
1131 set_ia32_is_spill(push);
1133 sched_add_before(schedpoint, push);
1137 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
1139 dbg_info *dbg = get_irn_dbg_info(node);
1140 ir_node *block = get_nodes_block(node);
1141 ir_node *noreg = ia32_new_NoReg_gp(cg);
1142 ir_graph *irg = get_irn_irg(node);
1143 ir_node *frame = get_irg_frame(irg);
1145 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
1147 set_ia32_frame_ent(pop, ent);
1148 set_ia32_use_frame(pop);
1149 set_ia32_op_type(pop, ia32_AddrModeD);
1150 set_ia32_ls_mode(pop, mode_Is);
1151 set_ia32_is_reload(pop);
1153 sched_add_before(schedpoint, pop);
1158 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1160 dbg_info *dbg = get_irn_dbg_info(node);
1161 ir_mode *spmode = mode_Iu;
1162 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1165 sp = new_rd_Proj(dbg, pred, spmode, pos);
1166 arch_set_irn_register(sp, spreg);
1172 * Transform MemPerm, currently we do this the ugly way and produce
1173 * push/pop into/from memory cascades. This is possible without using
1176 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
1178 ir_node *block = get_nodes_block(node);
1179 ir_node *sp = be_abi_get_ignore_irn(be_get_irg_abi(cg->irg), &ia32_gp_regs[REG_ESP]);
1180 int arity = be_get_MemPerm_entity_arity(node);
1181 ir_node **pops = ALLOCAN(ir_node*, arity);
1185 const ir_edge_t *edge;
1186 const ir_edge_t *next;
1189 for (i = 0; i < arity; ++i) {
1190 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1191 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1192 ir_type *enttype = get_entity_type(inent);
1193 unsigned entsize = get_type_size_bytes(enttype);
1194 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1195 ir_node *mem = get_irn_n(node, i + 1);
1198 /* work around cases where entities have different sizes */
1199 if (entsize2 < entsize)
1201 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1203 push = create_push(cg, node, node, sp, mem, inent);
1204 sp = create_spproj(node, push, pn_ia32_Push_stack);
1206 /* add another push after the first one */
1207 push = create_push(cg, node, node, sp, mem, inent);
1208 add_ia32_am_offs_int(push, 4);
1209 sp = create_spproj(node, push, pn_ia32_Push_stack);
1212 set_irn_n(node, i, new_Bad());
1216 for (i = arity - 1; i >= 0; --i) {
1217 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1218 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1219 ir_type *enttype = get_entity_type(outent);
1220 unsigned entsize = get_type_size_bytes(enttype);
1221 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1224 /* work around cases where entities have different sizes */
1225 if (entsize2 < entsize)
1227 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1229 pop = create_pop(cg, node, node, sp, outent);
1230 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1232 add_ia32_am_offs_int(pop, 4);
1234 /* add another pop after the first one */
1235 pop = create_pop(cg, node, node, sp, outent);
1236 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1243 keep = be_new_Keep(block, 1, in);
1244 sched_add_before(node, keep);
1246 /* exchange memprojs */
1247 foreach_out_edge_safe(node, edge, next) {
1248 ir_node *proj = get_edge_src_irn(edge);
1249 int p = get_Proj_proj(proj);
1253 set_Proj_pred(proj, pops[p]);
1254 set_Proj_proj(proj, pn_ia32_Pop_M);
1257 /* remove memperm */
1258 arity = get_irn_arity(node);
1259 for (i = 0; i < arity; ++i) {
1260 set_irn_n(node, i, new_Bad());
1266 * Block-Walker: Calls the transform functions Spill and Reload.
1268 static void ia32_after_ra_walker(ir_node *block, void *env)
1270 ir_node *node, *prev;
1271 ia32_code_gen_t *cg = env;
1273 /* beware: the schedule is changed here */
1274 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1275 prev = sched_prev(node);
1277 if (be_is_Reload(node)) {
1278 transform_to_Load(cg, node);
1279 } else if (be_is_Spill(node)) {
1280 transform_to_Store(cg, node);
1281 } else if (be_is_MemPerm(node)) {
1282 transform_MemPerm(cg, node);
1288 * Collects nodes that need frame entities assigned.
1290 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1292 be_fec_env_t *env = data;
1293 const ir_mode *mode;
1296 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1297 mode = get_spill_mode_mode(get_irn_mode(node));
1298 align = get_mode_size_bytes(mode);
1299 } else if (is_ia32_irn(node) &&
1300 get_ia32_frame_ent(node) == NULL &&
1301 is_ia32_use_frame(node)) {
1302 if (is_ia32_need_stackent(node))
1305 switch (get_ia32_irn_opcode(node)) {
1307 case iro_ia32_Load: {
1308 const ia32_attr_t *attr = get_ia32_attr_const(node);
1310 if (attr->data.need_32bit_stackent) {
1312 } else if (attr->data.need_64bit_stackent) {
1315 mode = get_ia32_ls_mode(node);
1316 if (is_ia32_is_reload(node))
1317 mode = get_spill_mode_mode(mode);
1319 align = get_mode_size_bytes(mode);
1323 case iro_ia32_vfild:
1325 case iro_ia32_xLoad: {
1326 mode = get_ia32_ls_mode(node);
1331 case iro_ia32_FldCW: {
1332 /* although 2 byte would be enough 4 byte performs best */
1340 panic("unexpected frame user while collection frame entity nodes");
1342 case iro_ia32_FnstCW:
1343 case iro_ia32_Store8Bit:
1344 case iro_ia32_Store:
1347 case iro_ia32_vfist:
1348 case iro_ia32_vfisttp:
1350 case iro_ia32_xStore:
1351 case iro_ia32_xStoreSimple:
1358 be_node_needs_frame_entity(env, node, mode, align);
1362 * We transform Spill and Reload here. This needs to be done before
1363 * stack biasing otherwise we would miss the corrected offset for these nodes.
1365 static void ia32_after_ra(void *self)
1367 ia32_code_gen_t *cg = self;
1368 ir_graph *irg = cg->irg;
1369 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->irg);
1371 /* create and coalesce frame entities */
1372 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1373 be_assign_entities(fec_env, ia32_set_frame_entity);
1374 be_free_frame_entity_coalescer(fec_env);
1376 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1380 * Last touchups for the graph before emit: x87 simulation to replace the
1381 * virtual with real x87 instructions, creating a block schedule and peephole
1384 static void ia32_finish(void *self)
1386 ia32_code_gen_t *cg = self;
1387 ir_graph *irg = cg->irg;
1389 ia32_finish_irg(irg, cg);
1391 /* we might have to rewrite x87 virtual registers */
1392 if (cg->do_x87_sim) {
1393 x87_simulate_graph(cg->irg);
1396 /* do peephole optimisations */
1397 ia32_peephole_optimization(cg);
1399 /* create block schedule, this also removes empty blocks which might
1400 * produce critical edges */
1401 cg->blk_sched = be_create_block_schedule(irg);
1405 * Emits the code, closes the output file and frees
1406 * the code generator interface.
1408 static void ia32_codegen(void *self)
1410 ia32_code_gen_t *cg = self;
1411 ir_graph *irg = cg->irg;
1413 if (ia32_cg_config.emit_machcode) {
1414 ia32_gen_binary_routine(cg, irg);
1416 ia32_gen_routine(cg, irg);
1419 /* remove it from the isa */
1422 assert(ia32_current_cg == cg);
1423 ia32_current_cg = NULL;
1425 /* de-allocate code generator */
1430 * Returns the node representing the PIC base.
1432 static ir_node *ia32_get_pic_base(void *self)
1435 ia32_code_gen_t *cg = self;
1436 ir_node *get_eip = cg->get_eip;
1437 if (get_eip != NULL)
1440 block = get_irg_start_block(cg->irg);
1441 get_eip = new_bd_ia32_GetEIP(NULL, block);
1442 cg->get_eip = get_eip;
1444 be_dep_on_frame(get_eip);
1448 static void *ia32_cg_init(ir_graph *irg);
1450 static const arch_code_generator_if_t ia32_code_gen_if = {
1452 ia32_get_pic_base, /* return node used as base in pic code addresses */
1453 ia32_before_abi, /* before abi introduce hook */
1456 ia32_before_ra, /* before register allocation hook */
1457 ia32_after_ra, /* after register allocation hook */
1458 ia32_finish, /* called before codegen */
1459 ia32_codegen /* emit && done */
1463 * Initializes a IA32 code generator.
1465 static void *ia32_cg_init(ir_graph *irg)
1467 ia32_isa_t *isa = (ia32_isa_t *)be_get_irg_arch_env(irg);
1468 ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t);
1470 cg->impl = &ia32_code_gen_if;
1473 cg->blk_sched = NULL;
1474 cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
1475 cg->gprof = (be_get_irg_options(irg)->gprof) ? 1 : 0;
1478 /* Linux gprof implementation needs base pointer */
1479 be_get_irg_options(irg)->omit_fp = 0;
1486 if (isa->name_obst) {
1487 obstack_free(isa->name_obst, NULL);
1488 obstack_init(isa->name_obst);
1492 assert(ia32_current_cg == NULL);
1493 ia32_current_cg = cg;
1495 return (arch_code_generator_t *)cg;
1500 * Set output modes for GCC
1502 static const tarval_mode_info mo_integer = {
1509 * set the tarval output mode of all integer modes to decimal
1511 static void set_tarval_output_modes(void)
1515 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1516 ir_mode *mode = get_irp_mode(i);
1518 if (mode_is_int(mode))
1519 set_tarval_mode_output_option(mode, &mo_integer);
1523 const arch_isa_if_t ia32_isa_if;
1526 * The template that generates a new ISA object.
1527 * Note that this template can be changed by command line
1530 static ia32_isa_t ia32_isa_template = {
1532 &ia32_isa_if, /* isa interface implementation */
1533 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1534 &ia32_gp_regs[REG_EBP], /* base pointer register */
1535 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1536 -1, /* stack direction */
1537 2, /* power of two stack alignment, 2^2 == 4 */
1538 NULL, /* main environment */
1539 7, /* costs for a spill instruction */
1540 5, /* costs for a reload instruction */
1541 false, /* no custom abi handling */
1543 NULL, /* 16bit register names */
1544 NULL, /* 8bit register names */
1545 NULL, /* 8bit register names high */
1548 NULL, /* current code generator */
1549 NULL, /* abstract machine */
1551 NULL, /* name obstack */
1555 static void init_asm_constraints(void)
1557 be_init_default_asm_constraint_flags();
1559 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1560 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1561 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1562 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1563 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1564 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1565 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1566 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1567 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1568 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1569 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1570 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1571 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1572 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1573 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1574 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1575 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1576 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1577 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1578 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1580 /* no support for autodecrement/autoincrement */
1581 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1582 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1583 /* no float consts */
1584 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1585 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1586 /* makes no sense on x86 */
1587 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1588 /* no support for sse consts yet */
1589 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1590 /* no support for x87 consts yet */
1591 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1592 /* no support for mmx registers yet */
1593 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1594 /* not available in 32bit mode */
1595 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1596 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1598 /* no code yet to determine register class needed... */
1599 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1603 * Initializes the backend ISA.
1605 static arch_env_t *ia32_init(FILE *file_handle)
1607 static int inited = 0;
1615 set_tarval_output_modes();
1617 isa = XMALLOC(ia32_isa_t);
1618 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1620 if (mode_fpcw == NULL) {
1621 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1624 ia32_register_init();
1625 ia32_create_opcodes(&ia32_irn_ops);
1626 /* special handling for SwitchJmp */
1627 op_ia32_SwitchJmp->ops.be_ops = &ia32_SwitchJmp_irn_ops;
1629 be_emit_init(file_handle);
1630 isa->regs_16bit = pmap_create();
1631 isa->regs_8bit = pmap_create();
1632 isa->regs_8bit_high = pmap_create();
1633 isa->types = pmap_create();
1634 isa->tv_ent = pmap_create();
1635 isa->cpu = ia32_init_machine_description();
1637 ia32_build_16bit_reg_map(isa->regs_16bit);
1638 ia32_build_8bit_reg_map(isa->regs_8bit);
1639 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1642 isa->name_obst = XMALLOC(struct obstack);
1643 obstack_init(isa->name_obst);
1646 /* enter the ISA object into the intrinsic environment */
1647 intrinsic_env.isa = isa;
1649 /* emit asm includes */
1650 n = get_irp_n_asms();
1651 for (i = 0; i < n; ++i) {
1652 be_emit_cstring("#APP\n");
1653 be_emit_ident(get_irp_asm(i));
1654 be_emit_cstring("\n#NO_APP\n");
1657 /* needed for the debug support */
1658 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1659 be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
1660 be_emit_write_line();
1668 * Closes the output file and frees the ISA structure.
1670 static void ia32_done(void *self)
1672 ia32_isa_t *isa = self;
1674 /* emit now all global declarations */
1675 be_gas_emit_decls(isa->base.main_env);
1677 pmap_destroy(isa->regs_16bit);
1678 pmap_destroy(isa->regs_8bit);
1679 pmap_destroy(isa->regs_8bit_high);
1680 pmap_destroy(isa->tv_ent);
1681 pmap_destroy(isa->types);
1684 obstack_free(isa->name_obst, NULL);
1694 * Return the number of register classes for this architecture.
1695 * We report always these:
1696 * - the general purpose registers
1697 * - the SSE floating point register set
1698 * - the virtual floating point registers
1699 * - the SSE vector register set
1701 static unsigned ia32_get_n_reg_class(void)
1707 * Return the register class for index i.
1709 static const arch_register_class_t *ia32_get_reg_class(unsigned i)
1711 assert(i < N_CLASSES);
1712 return &ia32_reg_classes[i];
1716 * Get the register class which shall be used to store a value of a given mode.
1717 * @param self The this pointer.
1718 * @param mode The mode in question.
1719 * @return A register class which can hold values of the given mode.
1721 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1723 if (mode_is_float(mode)) {
1724 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1727 return &ia32_reg_classes[CLASS_ia32_gp];
1731 * Returns the register for parameter nr.
1733 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1734 const ir_mode *mode)
1736 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1737 &ia32_gp_regs[REG_ECX],
1738 &ia32_gp_regs[REG_EDX],
1741 static const unsigned MAXNUM_GPREG_ARGS = 3;
1743 static const arch_register_t *gpreg_param_reg_regparam[] = {
1744 &ia32_gp_regs[REG_EAX],
1745 &ia32_gp_regs[REG_EDX],
1746 &ia32_gp_regs[REG_ECX]
1749 static const arch_register_t *gpreg_param_reg_this[] = {
1750 &ia32_gp_regs[REG_ECX],
1755 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1756 &ia32_xmm_regs[REG_XMM0],
1757 &ia32_xmm_regs[REG_XMM1],
1758 &ia32_xmm_regs[REG_XMM2],
1759 &ia32_xmm_regs[REG_XMM3],
1760 &ia32_xmm_regs[REG_XMM4],
1761 &ia32_xmm_regs[REG_XMM5],
1762 &ia32_xmm_regs[REG_XMM6],
1763 &ia32_xmm_regs[REG_XMM7]
1766 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1767 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1769 static const unsigned MAXNUM_SSE_ARGS = 8;
1771 if ((cc & cc_this_call) && nr == 0)
1772 return gpreg_param_reg_this[0];
1774 if (! (cc & cc_reg_param))
1777 if (mode_is_float(mode)) {
1778 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1780 if (nr >= MAXNUM_SSE_ARGS)
1783 if (cc & cc_this_call) {
1784 return fpreg_sse_param_reg_this[nr];
1786 return fpreg_sse_param_reg_std[nr];
1787 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1788 unsigned num_regparam;
1790 if (get_mode_size_bits(mode) > 32)
1793 if (nr >= MAXNUM_GPREG_ARGS)
1796 if (cc & cc_this_call) {
1797 return gpreg_param_reg_this[nr];
1799 num_regparam = cc & ~cc_bits;
1800 if (num_regparam == 0) {
1801 /* default fastcall */
1802 return gpreg_param_reg_fastcall[nr];
1804 if (nr < num_regparam)
1805 return gpreg_param_reg_regparam[nr];
1809 panic("unknown argument mode");
1813 * Get the ABI restrictions for procedure calls.
1814 * @param self The this pointer.
1815 * @param method_type The type of the method (procedure) in question.
1816 * @param abi The abi object to be modified
1818 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1826 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1830 /* set abi flags for calls */
1831 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1832 call_flags.bits.store_args_sequential = 0;
1833 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1834 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1835 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1837 /* set parameter passing style */
1838 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1840 cc = get_method_calling_convention(method_type);
1841 if (get_method_variadicity(method_type) == variadicity_variadic) {
1842 /* pass all parameters of a variadic function on the stack */
1843 cc = cc_cdecl_set | (cc & cc_this_call);
1845 if (get_method_additional_properties(method_type) & mtp_property_private &&
1846 ia32_cg_config.optimize_cc) {
1847 /* set the fast calling conventions (allowing up to 3) */
1848 cc = SET_FASTCALL(cc) | 3;
1852 /* we have to pop the shadow parameter ourself for compound calls */
1853 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1854 && !(cc & cc_reg_param)) {
1855 pop_amount += get_mode_size_bytes(mode_P_data);
1858 n = get_method_n_params(method_type);
1859 for (i = regnum = 0; i < n; i++) {
1861 const arch_register_t *reg = NULL;
1863 tp = get_method_param_type(method_type, i);
1864 mode = get_type_mode(tp);
1866 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1869 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1872 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1873 * movl has a shorter opcode than mov[sz][bw]l */
1874 ir_mode *load_mode = mode;
1877 unsigned size = get_mode_size_bytes(mode);
1879 if (cc & cc_callee_clear_stk) {
1880 pop_amount += (size + 3U) & ~3U;
1883 if (size < 4) load_mode = mode_Iu;
1886 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1890 be_abi_call_set_pop(abi, pop_amount);
1892 /* set return registers */
1893 n = get_method_n_ress(method_type);
1895 assert(n <= 2 && "more than two results not supported");
1897 /* In case of 64bit returns, we will have two 32bit values */
1899 tp = get_method_res_type(method_type, 0);
1900 mode = get_type_mode(tp);
1902 assert(!mode_is_float(mode) && "two FP results not supported");
1904 tp = get_method_res_type(method_type, 1);
1905 mode = get_type_mode(tp);
1907 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1909 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX], ABI_CONTEXT_BOTH);
1910 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX], ABI_CONTEXT_BOTH);
1913 const arch_register_t *reg;
1915 tp = get_method_res_type(method_type, 0);
1916 assert(is_atomic_type(tp));
1917 mode = get_type_mode(tp);
1919 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1921 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1925 static int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1929 if (!is_ia32_irn(irn)) {
1933 if (is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1934 || is_ia32_ChangeCW(irn) || is_ia32_Immediate(irn))
1941 * Initializes the code generator interface.
1943 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1946 return &ia32_code_gen_if;
1950 * Returns the estimated execution time of an ia32 irn.
1952 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn)
1955 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
1958 list_sched_selector_t ia32_sched_selector;
1961 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1963 static const list_sched_selector_t *ia32_get_list_sched_selector(
1964 const void *self, list_sched_selector_t *selector)
1967 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1968 ia32_sched_selector.exectime = ia32_sched_exectime;
1969 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1970 return &ia32_sched_selector;
1973 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1980 * Returns the necessary byte alignment for storing a register of given class.
1982 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
1984 ir_mode *mode = arch_register_class_mode(cls);
1985 int bytes = get_mode_size_bytes(mode);
1987 if (mode_is_float(mode) && bytes > 8)
1992 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1995 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1996 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1997 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
2000 static const be_execution_unit_t *_allowed_units_GP[] = {
2001 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
2002 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
2003 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
2004 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
2005 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
2006 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
2007 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2010 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2011 &be_machine_execution_units_DUMMY[0],
2014 static const be_execution_unit_t **_units_callret[] = {
2015 _allowed_units_BRANCH,
2018 static const be_execution_unit_t **_units_other[] = {
2022 static const be_execution_unit_t **_units_dummy[] = {
2023 _allowed_units_DUMMY,
2026 const be_execution_unit_t ***ret;
2028 if (is_ia32_irn(irn)) {
2029 ret = get_ia32_exec_units(irn);
2030 } else if (is_be_node(irn)) {
2031 if (be_is_Return(irn)) {
2032 ret = _units_callret;
2033 } else if (be_is_Barrier(irn)) {
2047 * Return the abstract ia32 machine.
2049 static const be_machine_t *ia32_get_machine(const void *self)
2051 const ia32_isa_t *isa = self;
2056 * Return irp irgs in the desired order.
2058 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2065 static void ia32_mark_remat(ir_node *node)
2067 if (is_ia32_irn(node)) {
2068 set_ia32_is_remat(node);
2073 * Check if Mux(sel, t, f) would represent an Abs (or -Abs).
2075 static bool mux_is_abs(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
2084 cmp = get_Proj_pred(sel);
2088 /* must be <, <=, >=, > */
2089 pnc = get_Proj_proj(sel);
2104 if (!is_negated_value(mux_true, mux_false))
2107 /* must be x cmp 0 */
2108 cmp_right = get_Cmp_right(cmp);
2109 if (!is_Const(cmp_right) || !is_Const_null(cmp_right))
2112 cmp_left = get_Cmp_left(cmp);
2113 if (cmp_left != mux_true && cmp_left != mux_false)
2120 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
2122 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
2132 cmp = get_Proj_pred(sel);
2136 cmp_l = get_Cmp_left(cmp);
2137 cmp_r = get_Cmp_right(cmp);
2138 if (!mode_is_float(get_irn_mode(cmp_l)))
2141 /* check for min/max. They're defined as (C-Semantik):
2142 * min(a, b) = a < b ? a : b
2143 * or min(a, b) = a <= b ? a : b
2144 * max(a, b) = a > b ? a : b
2145 * or max(a, b) = a >= b ? a : b
2146 * (Note we only handle float min/max here)
2148 pnc = get_Proj_proj(sel);
2153 if (cmp_l == mux_true && cmp_r == mux_false)
2159 if (cmp_l == mux_true && cmp_r == mux_false)
2165 if (cmp_l == mux_false && cmp_r == mux_true)
2171 if (cmp_l == mux_false && cmp_r == mux_true)
2182 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
2184 ir_mode *mode = get_irn_mode(mux_true);
2187 if (!mode_is_int(mode) && !mode_is_reference(mode)
2191 if (is_Const(mux_true) && is_Const(mux_false)) {
2192 /* we can create a set plus up two 3 instructions for any combination of constants */
2199 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
2204 if (!mode_is_float(get_irn_mode(mux_true)))
2207 return is_Const(mux_true) && is_Const(mux_false);
2210 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
2221 cmp = get_Proj_pred(sel);
2225 mode = get_irn_mode(mux_true);
2226 if (mode_is_signed(mode) || mode_is_float(mode))
2229 pn = get_Proj_proj(sel);
2230 cmp_left = get_Cmp_left(cmp);
2231 cmp_right = get_Cmp_right(cmp);
2232 if ((pn & pn_Cmp_Gt) &&
2233 is_Const(mux_false) && is_Const_null(mux_false) && is_Sub(mux_true) &&
2234 get_Sub_left(mux_true) == cmp_left &&
2235 get_Sub_right(mux_true) == cmp_right) {
2236 /* Mux(a >=u b, a - b, 0) unsigned Doz */
2239 if ((pn & pn_Cmp_Lt) &&
2240 is_Const(mux_true) && is_Const_null(mux_true) && is_Sub(mux_false) &&
2241 get_Sub_left(mux_false) == cmp_left &&
2242 get_Sub_right(mux_false) == cmp_right) {
2243 /* Mux(a <=u b, 0, a - b) unsigned Doz */
2250 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
2255 /* we can handle Abs for all modes and compares */
2256 if (mux_is_abs(sel, mux_true, mux_false))
2258 /* we can handle Set for all modes and compares */
2259 if (mux_is_set(sel, mux_true, mux_false))
2261 /* SSE has own min/max operations */
2262 if (ia32_cg_config.use_sse2
2263 && mux_is_float_min_max(sel, mux_true, mux_false))
2265 /* we can handle Mux(?, Const[f], Const[f]) */
2266 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
2267 #ifdef FIRM_GRGEN_BE
2268 /* well, some code selectors can't handle it */
2269 if (be_transformer != TRANSFORMER_PBQP
2270 || be_transformer != TRANSFORMER_RAND)
2277 /* no support for 64bit inputs to cmov */
2278 mode = get_irn_mode(mux_true);
2279 if (get_mode_size_bits(mode) > 32)
2281 /* we can't handle MuxF yet */
2282 if (mode_is_float(mode))
2285 if (mux_is_doz(sel, mux_true, mux_false))
2288 /* Check Cmp before the node */
2290 ir_node *cmp = get_Proj_pred(sel);
2292 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(cmp));
2294 /* we can't handle 64bit compares */
2295 if (get_mode_size_bits(cmp_mode) > 32)
2298 /* we can't handle float compares */
2299 if (mode_is_float(cmp_mode))
2304 /* did we disable cmov generation? */
2305 if (!ia32_cg_config.use_cmov)
2308 /* we can use a cmov */
2312 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2316 /* we already added all our simple flags to the flags modifier list in
2317 * init, so this flag we don't know. */
2318 return ASM_CONSTRAINT_FLAG_INVALID;
2321 static int ia32_is_valid_clobber(const char *clobber)
2323 return ia32_get_clobber_register(clobber) != NULL;
2327 * Create the trampoline code.
2329 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2331 ir_node *st, *p = trampoline;
2332 ir_mode *mode = get_irn_mode(p);
2335 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xb9), 0);
2336 mem = new_r_Proj(st, mode_M, pn_Store_M);
2337 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2338 st = new_r_Store(block, mem, p, env, 0);
2339 mem = new_r_Proj(st, mode_M, pn_Store_M);
2340 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2342 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xe9), 0);
2343 mem = new_r_Proj(st, mode_M, pn_Store_M);
2344 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2345 st = new_r_Store(block, mem, p, callee, 0);
2346 mem = new_r_Proj(st, mode_M, pn_Store_M);
2347 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2353 * Returns the libFirm configuration parameter for this backend.
2355 static const backend_params *ia32_get_libfirm_params(void)
2357 static const ir_settings_if_conv_t ifconv = {
2358 4, /* maxdepth, doesn't matter for Mux-conversion */
2359 ia32_is_mux_allowed /* allows or disallows Mux creation for given selector */
2361 static const ir_settings_arch_dep_t ad = {
2362 1, /* also use subs */
2363 4, /* maximum shifts */
2364 31, /* maximum shift amount */
2365 ia32_evaluate_insn, /* evaluate the instruction sequence */
2367 1, /* allow Mulhs */
2368 1, /* allow Mulus */
2369 32, /* Mulh allowed up to 32 bit */
2371 static backend_params p = {
2372 1, /* need dword lowering */
2373 1, /* support inline assembly */
2374 NULL, /* will be set later */
2375 ia32_create_intrinsic_fkt,
2376 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2377 NULL, /* ifconv info will be set below */
2378 NULL, /* float arithmetic mode, will be set below */
2379 12, /* size of trampoline code */
2380 4, /* alignment of trampoline code */
2381 ia32_create_trampoline_fkt,
2382 4 /* alignment of stack parameter */
2385 ia32_setup_cg_config();
2387 /* doesn't really belong here, but this is the earliest place the backend
2389 init_asm_constraints();
2392 p.if_conv_info = &ifconv;
2393 if (! ia32_cg_config.use_sse2)
2394 p.mode_float_arithmetic = mode_E;
2398 static const lc_opt_enum_int_items_t gas_items[] = {
2399 { "elf", OBJECT_FILE_FORMAT_ELF },
2400 { "mingw", OBJECT_FILE_FORMAT_COFF },
2401 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2405 static lc_opt_enum_int_var_t gas_var = {
2406 (int*) &be_gas_object_file_format, gas_items
2409 #ifdef FIRM_GRGEN_BE
2410 static const lc_opt_enum_int_items_t transformer_items[] = {
2411 { "default", TRANSFORMER_DEFAULT },
2412 { "pbqp", TRANSFORMER_PBQP },
2413 { "random", TRANSFORMER_RAND },
2417 static lc_opt_enum_int_var_t transformer_var = {
2418 (int*)&be_transformer, transformer_items
2422 static const lc_opt_table_entry_t ia32_options[] = {
2423 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2424 #ifdef FIRM_GRGEN_BE
2425 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2427 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2428 &ia32_isa_template.base.stack_alignment),
2432 const arch_isa_if_t ia32_isa_if = {
2435 ia32_handle_intrinsics,
2436 ia32_get_n_reg_class,
2438 ia32_get_reg_class_for_mode,
2440 ia32_get_code_generator_if,
2441 ia32_get_list_sched_selector,
2442 ia32_get_ilp_sched_selector,
2443 ia32_get_reg_class_alignment,
2444 ia32_get_libfirm_params,
2445 ia32_get_allowed_execution_units,
2449 ia32_parse_asm_constraint,
2450 ia32_is_valid_clobber
2453 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
2454 void be_init_arch_ia32(void)
2456 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2457 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2459 lc_opt_add_table(ia32_grp, ia32_options);
2460 be_register_isa_if("ia32", &ia32_isa_if);
2462 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2464 ia32_init_emitter();
2466 ia32_init_optimize();
2467 ia32_init_transform();
2469 ia32_init_architecture();