2 * This is the main ia32 firm backend driver.
17 #include "pseudo_irg.h"
21 #include "iredges_t.h"
28 #include "../beabi.h" /* the general register allocator interface */
29 #include "../benode_t.h"
30 #include "../belower.h"
31 #include "../besched_t.h"
33 #include "bearch_ia32_t.h"
35 #include "ia32_new_nodes.h" /* ia32 nodes interface */
36 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
37 #include "ia32_gen_decls.h" /* interface declaration emitter */
38 #include "ia32_transform.h"
39 #include "ia32_emitter.h"
40 #include "ia32_map_regs.h"
41 #include "ia32_optimize.h"
43 #define DEBUG_MODULE "firm.be.ia32.isa"
46 static set *cur_reg_set = NULL;
49 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
51 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
52 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_XXX]);
55 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
56 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_fp_regs[REG_XXXX]);
59 /**************************************************
62 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
63 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
64 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
65 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
68 **************************************************/
70 static ir_node *my_skip_proj(const ir_node *n) {
77 * Return register requirements for an ia32 node.
78 * If the node returns a tuple (mode_T) then the proj's
79 * will be asked for this information.
81 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
82 const ia32_register_req_t *irn_req;
83 long node_pos = pos == -1 ? 0 : pos;
84 ir_mode *mode = get_irn_mode(irn);
85 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
87 if (mode == mode_T || mode == mode_M) {
88 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
92 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
97 node_pos = ia32_translate_proj_pos(irn);
103 irn = my_skip_proj(irn);
105 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
108 if (is_ia32_irn(irn)) {
110 irn_req = get_ia32_in_req(irn, pos);
113 irn_req = get_ia32_out_req(irn, node_pos);
116 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
118 memcpy(req, &(irn_req->req), sizeof(*req));
120 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
121 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
122 req->other_same = get_irn_n(irn, irn_req->same_pos);
125 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
126 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
127 req->other_different = get_irn_n(irn, irn_req->different_pos);
131 /* treat Phi like Const with default requirements */
133 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
134 if (mode_is_float(mode))
135 memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req));
136 else if (mode_is_int(mode) || mode_is_reference(mode))
137 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
138 else if (mode == mode_T || mode == mode_M) {
139 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
143 assert(0 && "unsupported Phi-Mode");
146 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
154 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
158 pos = ia32_translate_proj_pos(irn);
159 irn = my_skip_proj(irn);
162 if (is_ia32_irn(irn)) {
163 const arch_register_t **slots;
165 slots = get_ia32_slots(irn);
169 ia32_set_firm_reg(irn, reg, cur_reg_set);
173 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
175 const arch_register_t *reg = NULL;
178 pos = ia32_translate_proj_pos(irn);
179 irn = my_skip_proj(irn);
182 if (is_ia32_irn(irn)) {
183 const arch_register_t **slots;
184 slots = get_ia32_slots(irn);
188 reg = ia32_get_firm_reg(irn, cur_reg_set);
194 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
195 irn = my_skip_proj(irn);
197 return arch_irn_class_branch;
198 else if (is_ia32_irn(irn))
199 return arch_irn_class_normal;
204 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
205 irn = my_skip_proj(irn);
206 if (is_ia32_irn(irn))
207 return get_ia32_flags(irn);
213 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
214 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
217 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
219 const ia32_irn_ops_t *ops = self;
221 if (is_ia32_use_frame(irn) && bias != 0) {
222 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
224 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
225 snprintf(buf, sizeof(buf), "%d", bias);
226 add_ia32_am_offs(irn, buf);
228 set_ia32_am_flavour(irn, am_flav);
232 /* fill register allocator interface */
234 static const arch_irn_ops_if_t ia32_irn_ops_if = {
235 ia32_get_irn_reg_req,
240 ia32_get_frame_entity,
244 ia32_irn_ops_t ia32_irn_ops = {
251 /**************************************************
254 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
255 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
256 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
257 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
260 **************************************************/
263 * Transforms the standard firm graph into
266 static void ia32_prepare_graph(void *self) {
267 ia32_code_gen_t *cg = self;
268 firm_dbg_module_t *old_mod = cg->mod;
270 cg->mod = firm_dbg_register("firm.be.ia32.transform");
271 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
272 dump_ir_block_graph_sched(cg->irg, "-transformed");
277 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
278 dump_ir_block_graph_sched(cg->irg, "-am");
284 * Insert copies for all ia32 nodes where the should_be_same requirement
287 static void ia32_finish_irg_walker(ir_node *irn, void *env) {
288 ia32_code_gen_t *cg = env;
289 const ia32_register_req_t **reqs;
290 const arch_register_t *out_reg, *in_reg;
292 ir_node *copy, *in_node, *block;
294 if (! is_ia32_irn(irn))
297 /* nodes with destination address mode don't produce values */
298 if (get_ia32_op_type(irn) == ia32_AddrModeD)
301 reqs = get_ia32_out_req_all(irn);
302 n_res = get_ia32_n_res(irn);
303 block = get_nodes_block(irn);
305 /* check all OUT requirements, if there is a should_be_same */
306 for (i = 0; i < n_res; i++) {
307 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
308 /* get in and out register */
309 out_reg = get_ia32_out_reg(irn, i);
310 in_node = get_irn_n(irn, reqs[i]->same_pos);
311 in_reg = arch_get_irn_register(cg->arch_env, in_node);
313 /* check if in and out register are equal */
314 if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
315 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
317 /* create copy from in register */
318 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
320 /* destination is the out register */
321 arch_set_irn_register(cg->arch_env, copy, out_reg);
323 /* insert copy before the node into the schedule */
324 sched_add_before(irn, copy);
327 set_irn_n(irn, reqs[i]->same_pos, copy);
334 * Add Copy nodes for not fulfilled should_be_equal constraints
336 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
337 irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
343 * Dummy functions for hooks we don't need but which must be filled.
345 static void ia32_before_sched(void *self) {
348 static void ia32_before_ra(void *self) {
354 * Transforms a be node into a Load.
356 static void transform_to_Load(ia32_transform_env_t *env) {
357 ir_node *irn = env->irn;
358 entity *ent = be_get_frame_entity(irn);
359 ir_mode *mode = env->mode;
360 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
361 ir_node *nomem = new_rd_NoMem(env->irg);
362 ir_node *sched_point = NULL;
363 ir_node *ptr = get_irn_n(irn, 0);
364 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
365 ir_node *new_op, *proj;
366 const arch_register_t *reg;
368 if (sched_is_scheduled(irn)) {
369 sched_point = sched_prev(irn);
372 if (mode_is_float(mode)) {
373 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
376 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
379 set_ia32_am_support(new_op, ia32_am_Source);
380 set_ia32_op_type(new_op, ia32_AddrModeS);
381 set_ia32_am_flavour(new_op, ia32_B);
382 set_ia32_ls_mode(new_op, mode);
383 set_ia32_frame_ent(new_op, ent);
384 set_ia32_use_frame(new_op);
386 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
389 sched_add_after(sched_point, new_op);
390 sched_add_after(new_op, proj);
395 /* copy the register from the old node to the new Load */
396 reg = arch_get_irn_register(env->cg->arch_env, irn);
397 arch_set_irn_register(env->cg->arch_env, new_op, reg);
404 * Transforms a be node into a Store.
406 static void transform_to_Store(ia32_transform_env_t *env) {
407 ir_node *irn = env->irn;
408 entity *ent = be_get_frame_entity(irn);
409 ir_mode *mode = env->mode;
410 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
411 ir_node *nomem = new_rd_NoMem(env->irg);
412 ir_node *ptr = get_irn_n(irn, 0);
413 ir_node *val = get_irn_n(irn, 1);
414 ir_node *new_op, *proj;
415 ir_node *sched_point = NULL;
417 if (sched_is_scheduled(irn)) {
418 sched_point = sched_prev(irn);
421 if (mode_is_float(mode)) {
422 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
425 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
428 set_ia32_am_support(new_op, ia32_am_Dest);
429 set_ia32_op_type(new_op, ia32_AddrModeD);
430 set_ia32_am_flavour(new_op, ia32_B);
431 set_ia32_ls_mode(new_op, get_irn_mode(val));
432 set_ia32_frame_ent(new_op, ent);
433 set_ia32_use_frame(new_op);
435 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
438 sched_add_after(sched_point, new_op);
439 sched_add_after(new_op, proj);
449 * Calls the transform functions for StackParam, Spill and Reload.
451 static void ia32_after_ra_walker(ir_node *node, void *env) {
452 ia32_code_gen_t *cg = env;
453 ia32_transform_env_t tenv;
458 tenv.block = get_nodes_block(node);
459 tenv.dbg = get_irn_dbg_info(node);
460 tenv.irg = current_ir_graph;
463 tenv.mode = get_irn_mode(node);
466 if (be_is_StackParam(node) || be_is_Reload(node)) {
467 transform_to_Load(&tenv);
469 else if (be_is_Spill(node)) {
470 transform_to_Store(&tenv);
475 * We transform StackParam, Spill and Reload here. This needs to be done before
476 * stack biasing otherwise we would miss the corrected offset for these nodes.
478 static void ia32_after_ra(void *self) {
479 ia32_code_gen_t *cg = self;
480 irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
485 * Emits the code, closes the output file and frees
486 * the code generator interface.
488 static void ia32_codegen(void *self) {
489 ia32_code_gen_t *cg = self;
490 ir_graph *irg = cg->irg;
493 if (cg->emit_decls) {
494 ia32_gen_decls(cg->out);
498 ia32_finish_irg(irg, cg);
499 dump_ir_block_graph_sched(irg, "-finished");
500 ia32_gen_routine(out, irg, cg);
504 pmap_destroy(cg->tv_ent);
505 pmap_destroy(cg->types);
507 /* de-allocate code generator */
508 del_set(cg->reg_set);
512 static void *ia32_cg_init(FILE *F, const be_irg_t *birg);
514 static const arch_code_generator_if_t ia32_code_gen_if = {
516 NULL, /* before abi introduce hook */
518 ia32_before_sched, /* before scheduling hook */
519 ia32_before_ra, /* before register allocation hook */
520 ia32_after_ra, /* after register allocation hook */
521 ia32_codegen /* emit && done */
525 * Initializes the code generator.
527 static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
528 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
529 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
531 cg->impl = &ia32_code_gen_if;
533 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
534 cg->mod = firm_dbg_register("firm.be.ia32.cg");
536 cg->arch_env = birg->main_env->arch_env;
537 cg->types = pmap_create();
538 cg->tv_ent = pmap_create();
541 /* set optimizations */
544 cg->opt.placecnst = 1;
548 if (isa->name_obst_size) {
549 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
550 isa->name_obst_size = 0;
551 obstack_free(isa->name_obst, NULL);
552 obstack_init(isa->name_obst);
558 if (isa->num_codegens > 1)
563 cur_reg_set = cg->reg_set;
565 ia32_irn_ops.cg = cg;
567 return (arch_code_generator_t *)cg;
572 /*****************************************************************
573 * ____ _ _ _____ _____
574 * | _ \ | | | | |_ _|/ ____| /\
575 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
576 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
577 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
578 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
580 *****************************************************************/
582 static ia32_isa_t ia32_isa_template = {
583 &ia32_isa_if, /* isa interface implementation */
584 &ia32_gp_regs[REG_ESP], /* stack pointer register */
585 &ia32_gp_regs[REG_EBP], /* base pointer register */
586 -1, /* stack direction */
587 0, /* number of code generator objects so far */
588 NULL /* name obstack */
592 * Initializes the backend ISA.
594 static void *ia32_init(void) {
595 static int inited = 0;
601 isa = xcalloc(1, sizeof(*isa));
602 memcpy(isa, &ia32_isa_template, sizeof(*isa));
604 ia32_register_init(isa);
605 ia32_create_opcodes();
608 isa->name_obst = xcalloc(1, sizeof(*(isa->name_obst)));
609 obstack_init(isa->name_obst);
610 isa->name_obst_size = 0;
621 * Closes the output file and frees the ISA structure.
623 static void ia32_done(void *self) {
624 ia32_isa_t *isa = self;
627 //printf("name obst size = %d bytes\n", isa->name_obst_size);
628 obstack_free(isa->name_obst, NULL);
636 static int ia32_get_n_reg_class(const void *self) {
640 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
641 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
642 return &ia32_reg_classes[i];
646 * Get the register class which shall be used to store a value of a given mode.
647 * @param self The this pointer.
648 * @param mode The mode in question.
649 * @return A register class which can hold values of the given mode.
651 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
652 if (mode_is_float(mode))
653 return &ia32_reg_classes[CLASS_ia32_fp];
655 return &ia32_reg_classes[CLASS_ia32_gp];
659 * Produces the type which sits between the stack args and the locals on the stack.
660 * it will contain the return address and space to store the old base pointer.
661 * @return The Firm type modeling the ABI between type.
663 static ir_type *get_between_type(void)
665 static ir_type *between_type = NULL;
666 static entity *old_bp_ent = NULL;
669 entity *ret_addr_ent;
670 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
671 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
673 between_type = new_type_class(new_id_from_str("ia32_between_type"));
674 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
675 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
677 set_entity_offset_bytes(old_bp_ent, 0);
678 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
679 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
686 * Get the ABI restrictions for procedure calls.
687 * @param self The this pointer.
688 * @param method_type The type of the method (procedure) in question.
689 * @param abi The abi object to be modified
691 void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
692 ir_type *between_type;
695 unsigned cc = get_method_calling_convention(method_type);
696 int n = get_method_n_params(method_type);
701 const arch_register_t *reg;
702 be_abi_call_flags_t call_flags;
704 /* set abi flags for calls */
705 call_flags.bits.left_to_right = 0;
706 call_flags.bits.store_args_sequential = 0;
707 call_flags.bits.try_omit_fp = 1;
708 call_flags.bits.fp_free = 0;
709 call_flags.bits.call_has_imm = 1;
711 /* get the between type and the frame pointer save entity */
712 between_type = get_between_type();
714 /* set stack parameter passing style */
715 be_abi_call_set_flags(abi, call_flags, between_type);
717 /* collect the mode for each type */
718 modes = alloca(n * sizeof(modes[0]));
720 for (i = 0; i < n; i++) {
721 tp = get_method_param_type(method_type, i);
722 modes[i] = get_type_mode(tp);
725 /* set register parameters */
726 if (cc & cc_reg_param) {
727 /* determine the number of parameters passed via registers */
728 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore, &ignore);
730 /* loop over all parameters and set the register requirements */
731 for (i = 0; i <= biggest_n; i++) {
732 reg = ia32_get_RegParam_reg(n, modes, i, cc);
733 assert(reg && "kaputt");
734 be_abi_call_param_reg(abi, i, reg);
741 /* set stack parameters */
742 for (i = stack_idx; i < n; i++) {
743 be_abi_call_param_stack(abi, i);
747 /* set return registers */
748 n = get_method_n_ress(method_type);
750 assert(n <= 2 && "more than two results not supported");
752 /* In case of 64bit returns, we will have two 32bit values */
754 tp = get_method_res_type(method_type, 0);
755 mode = get_type_mode(tp);
757 assert(!mode_is_float(mode) && "two FP results not supported");
759 tp = get_method_res_type(method_type, 1);
760 mode = get_type_mode(tp);
762 assert(!mode_is_float(mode) && "two FP results not supported");
764 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
765 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
768 tp = get_method_res_type(method_type, 0);
769 assert(is_atomic_type(tp));
770 mode = get_type_mode(tp);
772 be_abi_call_res_reg(abi, 0, mode_is_float(mode) ? &ia32_fp_regs[REG_XMM0] : &ia32_gp_regs[REG_EAX]);
777 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
778 return &ia32_irn_ops;
781 const arch_irn_handler_t ia32_irn_handler = {
785 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
786 return &ia32_irn_handler;
789 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
790 return is_ia32_irn(irn);
794 * Initializes the code generator interface.
796 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
797 return &ia32_code_gen_if;
800 list_sched_selector_t ia32_sched_selector;
803 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
805 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
806 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
807 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
808 return &ia32_sched_selector;
812 static void ia32_register_options(lc_opt_entry_t *ent)
815 #endif /* WITH_LIBCORE */
817 const arch_isa_if_t ia32_isa_if = {
819 ia32_register_options,
823 ia32_get_n_reg_class,
825 ia32_get_reg_class_for_mode,
827 ia32_get_irn_handler,
828 ia32_get_code_generator_if,
829 ia32_get_list_sched_selector