2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
19 #include <libcore/lc_opts.h>
20 #include <libcore/lc_opts_enum.h>
21 #endif /* WITH_LIBCORE */
25 #include "pseudo_irg.h"
29 #include "iredges_t.h"
38 #include "../beabi.h" /* the general register allocator interface */
39 #include "../benode_t.h"
40 #include "../belower.h"
41 #include "../besched_t.h"
44 #include "../beirgmod.h"
45 #include "../be_dbgout.h"
46 #include "../beblocksched.h"
47 #include "../bemachine.h"
48 #include "../beilpsched.h"
49 #include "../bespillslots.h"
50 #include "../bemodule.h"
52 #include "bearch_ia32_t.h"
54 #include "ia32_new_nodes.h" /* ia32 nodes interface */
55 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
56 #include "gen_ia32_machine.h"
57 #include "ia32_gen_decls.h" /* interface declaration emitter */
58 #include "ia32_transform.h"
59 #include "ia32_emitter.h"
60 #include "ia32_map_regs.h"
61 #include "ia32_optimize.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_finish.h"
65 #include "ia32_util.h"
67 #define DEBUG_MODULE "firm.be.ia32.isa"
70 static set *cur_reg_set = NULL;
72 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
74 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
75 create_const_node_func func, arch_register_t* reg)
85 block = get_irg_start_block(cg->irg);
86 res = func(NULL, cg->irg, block);
87 arch_set_irn_register(cg->arch_env, res, reg);
90 /* keep the node so it isn't accidently removed when unused ... */
92 keep = be_new_Keep(arch_register_get_class(reg), cg->irg, block, 1, in);
94 /* schedule the node if we already have a scheduled program */
95 startnode = get_irg_start(cg->irg);
96 if(sched_is_scheduled(startnode)) {
97 sched_add_after(startnode, res);
98 sched_add_after(res, keep);
104 /* Creates the unique per irg GP NoReg node. */
105 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
106 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
107 &ia32_gp_regs[REG_GP_NOREG]);
110 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
111 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
112 &ia32_vfp_regs[REG_VFP_NOREG]);
115 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
116 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
117 &ia32_xmm_regs[REG_XMM_NOREG]);
120 /* Creates the unique per irg FP NoReg node. */
121 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
122 return USE_SSE2(cg) ? ia32_new_NoReg_xmm(cg) : ia32_new_NoReg_vfp(cg);
125 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
126 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
127 &ia32_gp_regs[REG_GP_UKNWN]);
130 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
131 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
132 &ia32_vfp_regs[REG_VFP_UKNWN]);
135 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
136 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
137 &ia32_xmm_regs[REG_XMM_UKNWN]);
142 * Returns gp_noreg or fp_noreg, depending in input requirements.
144 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
145 arch_register_req_t req;
146 const arch_register_req_t *p_req;
148 p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
149 assert(p_req && "Missing register requirements");
150 if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
151 return ia32_new_NoReg_gp(cg);
153 return ia32_new_NoReg_fp(cg);
156 /**************************************************
159 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
160 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
161 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
162 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
165 **************************************************/
168 * Return register requirements for an ia32 node.
169 * If the node returns a tuple (mode_T) then the proj's
170 * will be asked for this information.
172 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
173 const ia32_irn_ops_t *ops = self;
174 const ia32_register_req_t *irn_req;
175 long node_pos = pos == -1 ? 0 : pos;
176 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
177 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
179 if (is_Block(irn) || mode == mode_X) {
180 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
184 if (mode == mode_T && pos < 0) {
185 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
189 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
196 DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
200 node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
201 irn = skip_Proj_const(irn);
203 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
206 if (is_ia32_irn(irn)) {
207 irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
208 if (irn_req == NULL) {
209 /* no requirements */
213 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
215 memcpy(req, &(irn_req->req), sizeof(*req));
217 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
218 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
219 req->other_same = get_irn_n(irn, irn_req->same_pos);
222 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
223 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
224 req->other_different = get_irn_n(irn, irn_req->different_pos);
228 /* treat Unknowns like Const with default requirements */
229 if (is_Unknown(irn)) {
230 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
231 if (mode_is_float(mode)) {
232 if (USE_SSE2(ops->cg))
233 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
235 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
237 else if (mode_is_int(mode) || mode_is_reference(mode))
238 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
239 else if (mode == mode_T || mode == mode_M) {
240 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
244 assert(0 && "unsupported Unknown-Mode");
247 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
255 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
257 const ia32_irn_ops_t *ops = self;
259 if (get_irn_mode(irn) == mode_X) {
263 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
266 pos = get_Proj_proj(irn);
267 irn = skip_Proj(irn);
270 if (is_ia32_irn(irn)) {
271 const arch_register_t **slots;
273 slots = get_ia32_slots(irn);
277 ia32_set_firm_reg(irn, reg, cur_reg_set);
281 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
283 const arch_register_t *reg = NULL;
287 if (get_irn_mode(irn) == mode_X) {
291 pos = get_Proj_proj(irn);
292 irn = skip_Proj_const(irn);
295 if (is_ia32_irn(irn)) {
296 const arch_register_t **slots;
297 slots = get_ia32_slots(irn);
301 reg = ia32_get_firm_reg(irn, cur_reg_set);
307 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
308 arch_irn_class_t classification = arch_irn_class_normal;
310 irn = skip_Proj_const(irn);
313 classification |= arch_irn_class_branch;
315 if (! is_ia32_irn(irn))
316 return classification & ~arch_irn_class_normal;
318 if (is_ia32_Cnst(irn))
319 classification |= arch_irn_class_const;
322 classification |= arch_irn_class_load;
324 if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
325 classification |= arch_irn_class_store;
327 if (is_ia32_need_stackent(irn))
328 classification |= arch_irn_class_reload;
330 return classification;
333 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
334 arch_irn_flags_t flags = arch_irn_flags_none;
337 return arch_irn_flags_ignore;
339 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
340 ir_node *pred = get_Proj_pred(irn);
342 if(is_ia32_irn(pred)) {
343 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
349 if (is_ia32_irn(irn)) {
350 flags |= get_ia32_flags(irn);
357 * The IA32 ABI callback object.
360 be_abi_call_flags_bits_t flags; /**< The call flags. */
361 const arch_isa_t *isa; /**< The ISA handle. */
362 const arch_env_t *aenv; /**< The architecture environment. */
363 ir_graph *irg; /**< The associated graph. */
366 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
367 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
370 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
371 set_ia32_frame_ent(irn, ent);
374 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
375 const ia32_irn_ops_t *ops = self;
377 if (get_ia32_frame_ent(irn)) {
378 ia32_am_flavour_t am_flav;
380 if (is_ia32_Pop(irn)) {
381 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
383 /* Pop nodes modify the stack pointer before calculating the destination
384 * address, so fix this here
390 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
392 am_flav = get_ia32_am_flavour(irn);
394 set_ia32_am_flavour(irn, am_flav);
396 add_ia32_am_offs_int(irn, bias);
400 static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
402 long proj = get_Proj_proj(irn);
403 ir_node *pred = get_Proj_pred(irn);
405 if (is_ia32_Push(pred) && proj == pn_ia32_Push_stack)
407 if (is_ia32_Pop(pred) && proj == pn_ia32_Pop_stack)
415 * Put all registers which are saved by the prologue/epilogue in a set.
417 * @param self The callback object.
418 * @param s The result set.
420 static void ia32_abi_dont_save_regs(void *self, pset *s)
422 ia32_abi_env_t *env = self;
423 if(env->flags.try_omit_fp)
424 pset_insert_ptr(s, env->isa->bp);
428 static unsigned count_callee_saves(ia32_code_gen_t *cg)
430 unsigned callee_saves = 0;
431 int c, num_reg_classes;
434 num_reg_classes = arch_isa_get_n_reg_class(isa);
435 for(c = 0; c < num_reg_classes; ++c) {
436 int r, num_registers;
437 arch_register_class_t *regclass = arch_isa_get_reg_class(isa, c);
439 num_registers = arch_register_class_n_regs(regclass);
440 for(r = 0; r < num_registers; ++r) {
441 arch_register_t *reg = arch_register_for_index(regclass, r);
442 if(arch_register_type_is(reg, callee_save))
450 static void create_callee_save_regprojs(ia32_code_gen_t *cg, ir_node *regparams)
452 int c, num_reg_classes;
456 num_reg_classes = arch_isa_get_n_reg_class(isa);
457 cg->initial_regs = obstack_alloc(cg->obst,
458 num_reg_classes * sizeof(cg->initial_regs[0]));
460 for(c = 0; c < num_reg_classes; ++c) {
461 int r, num_registers;
462 ir_node **initial_regclass;
463 arch_register_class_t *regclass = arch_isa_get_reg_class(isa, c);
465 num_registers = arch_register_class_n_regs(regclass);
466 initial_regclass = obstack_alloc(num_registers * sizeof(initial_regclass[0]));
467 for(r = 0; r < num_registers; ++r) {
469 arch_register_t *reg = arch_register_for_index(regclass, r);
470 if(!arch_register_type_is(reg, callee_save))
473 proj = new_r_Proj(irg, start_block, regparams, n);
474 be_set_constr_single_reg(regparams, n, reg);
475 arch_set_irn_register(cg->arch_env, proj, reg);
477 initial_regclass[r] = proj;
480 cg->initial_regs[c] = initial_regclass;
484 static void callee_saves_obstack_grow(ia32_code_gen_t *cg)
486 int c, num_reg_classes;
489 for(c = 0; c < num_reg_classes; ++c) {
490 int r, num_registers;
492 num_registers = arch_register_class_n_regs(regclass);
493 for(r = 0; r < num_registers; ++r) {
495 arch_register_t *reg = arch_register_for_index(regclass, r);
496 if(!arch_register_type_is(reg, callee_save))
499 proj = cg->initial_regs[c][r];
500 obstack_ptr_grow(cg->obst, proj);
505 static unsigned count_parameters_in_regs(ia32_code_gen_t *cg)
510 static void ia32_gen_prologue(ia32_code_gen_t *cg)
512 ir_graph *irg = cg->irg;
513 ir_node *start_block = get_irg_start_block(irg);
518 /* Create the regparams node */
519 n_regparams_out = count_callee_saves(cg) + count_parameters_in_regs(cg);
520 regparams = be_new_RegParams(irg, start_block, n_regparams_out);
522 create_callee_save_regprojs(cg, regparams);
524 /* Setup the stack */
526 ir_node *bl = get_irg_start_block(env->irg);
527 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
528 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
529 ir_node *noreg = ia32_new_NoReg_gp(cg);
533 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
534 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
535 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
537 /* the push must have SP out register */
538 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
539 set_ia32_flags(push, arch_irn_flags_ignore);
541 /* move esp to ebp */
542 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
543 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
544 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
545 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
547 /* beware: the copy must be done before any other sp use */
548 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
549 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
550 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
551 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
553 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
554 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
557 sp = be_new_IncSP(sp, irg, start_block, initialsp, BE_STACK_FRAME_SIZE_EXPAND);
558 set_irg_frame(irg, sp);
561 static void ia32_gen_epilogue(ia32_code_gen_t *cg)
563 int n_callee_saves = count_callee_saves(cg);
564 int n_results_regs = 0;
567 ir_node *end_block = get_irg_end_block(irg);
570 /* We have to make sure that all reloads occur before the stack frame
571 gets destroyed, so we create a barrier for all callee-save and return
573 barrier_size = n_callee_saves + n_results_regs;
574 barrier = be_new_Barrier(irg, end_block, barrier_size,
576 /* simply remove the stack frame here */
577 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
578 add_irn_dep(curr_sp, *mem);
583 * Generate the routine prologue.
585 * @param self The callback object.
586 * @param mem A pointer to the mem node. Update this if you define new memory.
587 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
589 * @return The register which shall be used as a stack frame base.
591 * All nodes which define registers in @p reg_map must keep @p reg_map current.
593 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
595 ia32_abi_env_t *env = self;
596 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
597 ia32_code_gen_t *cg = isa->cg;
599 if (! env->flags.try_omit_fp) {
600 ir_node *bl = get_irg_start_block(env->irg);
601 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
602 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
603 ir_node *noreg = ia32_new_NoReg_gp(cg);
607 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
608 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
609 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
611 /* the push must have SP out register */
612 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
613 set_ia32_flags(push, arch_irn_flags_ignore);
615 /* move esp to ebp */
616 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
617 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
618 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
619 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
621 /* beware: the copy must be done before any other sp use */
622 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
623 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
624 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
625 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
627 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
628 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
637 * Generate the routine epilogue.
638 * @param self The callback object.
639 * @param bl The block for the epilog
640 * @param mem A pointer to the mem node. Update this if you define new memory.
641 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
642 * @return The register which shall be used as a stack frame base.
644 * All nodes which define registers in @p reg_map must keep @p reg_map current.
646 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
648 ia32_abi_env_t *env = self;
649 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
650 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
652 if (env->flags.try_omit_fp) {
653 /* simply remove the stack frame here */
654 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
655 add_irn_dep(curr_sp, *mem);
657 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
658 ia32_code_gen_t *cg = isa->cg;
659 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
661 /* gcc always emits a leave at the end of a routine */
662 if (1 || ARCH_AMD(isa->opt_arch)) {
666 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
667 set_ia32_flags(leave, arch_irn_flags_ignore);
668 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
669 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
671 ir_node *noreg = ia32_new_NoReg_gp(cg);
674 /* copy ebp to esp */
675 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
678 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
679 set_ia32_flags(pop, arch_irn_flags_ignore);
680 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
681 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
683 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
685 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
686 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
689 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
690 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
694 * Initialize the callback object.
695 * @param call The call object.
696 * @param aenv The architecture environment.
697 * @param irg The graph with the method.
698 * @return Some pointer. This pointer is passed to all other callback functions as self object.
700 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
702 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
703 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
704 env->flags = fl.bits;
707 env->isa = aenv->isa;
712 * Destroy the callback object.
713 * @param self The callback object.
715 static void ia32_abi_done(void *self) {
720 * Produces the type which sits between the stack args and the locals on the stack.
721 * it will contain the return address and space to store the old base pointer.
722 * @return The Firm type modeling the ABI between type.
724 static ir_type *ia32_abi_get_between_type(void *self)
726 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
727 static ir_type *omit_fp_between_type = NULL;
728 static ir_type *between_type = NULL;
730 ia32_abi_env_t *env = self;
732 if (! between_type) {
733 ir_entity *old_bp_ent;
734 ir_entity *ret_addr_ent;
735 ir_entity *omit_fp_ret_addr_ent;
737 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
738 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
740 between_type = new_type_struct(IDENT("ia32_between_type"));
741 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
742 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
744 set_entity_offset(old_bp_ent, 0);
745 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
746 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
747 set_type_state(between_type, layout_fixed);
749 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
750 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
752 set_entity_offset(omit_fp_ret_addr_ent, 0);
753 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
754 set_type_state(omit_fp_between_type, layout_fixed);
757 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
762 * Get the estimated cycle count for @p irn.
764 * @param self The this pointer.
765 * @param irn The node.
767 * @return The estimated cycle count for this operation
769 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
772 ia32_op_type_t op_tp;
773 const ia32_irn_ops_t *ops = self;
777 if (!is_ia32_irn(irn))
780 assert(is_ia32_irn(irn));
782 cost = get_ia32_latency(irn);
783 op_tp = get_ia32_op_type(irn);
785 if (is_ia32_CopyB(irn)) {
787 if (ARCH_INTEL(ops->cg->arch))
790 else if (is_ia32_CopyB_i(irn)) {
791 int size = get_tarval_long(get_ia32_Immop_tarval(irn));
792 cost = 20 + (int)ceil((4/3) * size);
793 if (ARCH_INTEL(ops->cg->arch))
796 /* in case of address mode operations add additional cycles */
797 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
799 In case of stack access add 5 cycles (we assume stack is in cache),
800 other memory operations cost 20 cycles.
802 cost += is_ia32_use_frame(irn) ? 5 : 20;
809 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
811 * @param irn The original operation
812 * @param i Index of the argument we want the inverse operation to yield
813 * @param inverse struct to be filled with the resulting inverse op
814 * @param obstack The obstack to use for allocation of the returned nodes array
815 * @return The inverse operation or NULL if operation invertible
817 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
821 ir_node *block, *noreg, *nomem;
824 /* we cannot invert non-ia32 irns */
825 if (! is_ia32_irn(irn))
828 /* operand must always be a real operand (not base, index or mem) */
829 if (i != 2 && i != 3)
832 /* we don't invert address mode operations */
833 if (get_ia32_op_type(irn) != ia32_Normal)
836 irg = get_irn_irg(irn);
837 block = get_nodes_block(irn);
838 mode = get_irn_mode(irn);
839 irn_mode = get_irn_mode(irn);
840 noreg = get_irn_n(irn, 0);
841 nomem = new_r_NoMem(irg);
842 dbg = get_irn_dbg_info(irn);
844 /* initialize structure */
845 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
849 switch (get_ia32_irn_opcode(irn)) {
851 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
852 /* we have an add with a const here */
853 /* invers == add with negated const */
854 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
856 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
857 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
858 set_ia32_commutative(inverse->nodes[0]);
860 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
861 /* we have an add with a symconst here */
862 /* invers == sub with const */
863 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
865 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
868 /* normal add: inverse == sub */
869 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, i ^ 1), nomem);
874 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
875 /* we have a sub with a const/symconst here */
876 /* invers == add with this const */
877 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
878 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
879 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
884 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, 3), nomem);
887 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, 2), (ir_node*) irn, nomem);
893 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
894 /* xor with const: inverse = xor */
895 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
896 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
897 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
901 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem);
906 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
911 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
916 /* inverse operation not supported */
923 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
925 if(mode_is_float(mode))
932 * Get the mode that should be used for spilling value node
934 static ir_mode *get_spill_mode(const ir_node *node)
936 ir_mode *mode = get_irn_mode(node);
937 return get_spill_mode_mode(mode);
941 * Checks wether an addressmode reload for a node with mode mode is compatible
942 * with a spillslot of mode spill_mode
944 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
946 if(mode_is_float(mode)) {
947 return mode == spillmode;
954 * Check if irn can load it's operand at position i from memory (source addressmode).
955 * @param self Pointer to irn ops itself
956 * @param irn The irn to be checked
957 * @param i The operands position
958 * @return Non-Zero if operand can be loaded
960 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
961 ir_node *op = get_irn_n(irn, i);
962 const ir_mode *mode = get_irn_mode(op);
963 const ir_mode *spillmode = get_spill_mode(op);
965 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
966 get_irn_arity(irn) != 5 || /* must be a binary operation */
967 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
968 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
969 ! ia32_is_spillmode_compatible(mode, spillmode) ||
970 (i != 2 && i != 3) || /* a "real" operand position must be requested */
971 (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
972 is_ia32_use_frame(irn)) /* must not already use frame */
978 static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
979 const ia32_irn_ops_t *ops = self;
980 ia32_code_gen_t *cg = ops->cg;
982 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
985 ir_node *tmp = get_irn_n(irn, 3);
986 set_irn_n(irn, 3, get_irn_n(irn, 2));
987 set_irn_n(irn, 2, tmp);
990 set_ia32_am_support(irn, ia32_am_Source);
991 set_ia32_op_type(irn, ia32_AddrModeS);
992 set_ia32_am_flavour(irn, ia32_B);
993 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
994 set_ia32_use_frame(irn);
995 set_ia32_need_stackent(irn);
997 set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
998 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
999 set_irn_n(irn, 4, spill);
1001 //FIXME DBG_OPT_AM_S(reload, irn);
1004 static const be_abi_callbacks_t ia32_abi_callbacks = {
1007 ia32_abi_get_between_type,
1008 ia32_abi_dont_save_regs,
1013 /* fill register allocator interface */
1015 static const arch_irn_ops_if_t ia32_irn_ops_if = {
1016 ia32_get_irn_reg_req,
1021 ia32_get_frame_entity,
1022 ia32_set_frame_entity,
1023 ia32_set_frame_offset,
1026 ia32_get_op_estimated_cost,
1027 ia32_possible_memory_operand,
1028 ia32_perform_memory_operand,
1031 ia32_irn_ops_t ia32_irn_ops = {
1038 /**************************************************
1041 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
1042 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
1043 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
1044 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
1047 **************************************************/
1050 * Transforms the standard firm graph into
1051 * an ia32 firm graph
1053 static void ia32_prepare_graph(void *self) {
1054 ia32_code_gen_t *cg = self;
1055 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
1057 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
1059 /* 1st: transform psi condition trees */
1060 ia32_pre_transform_phase(cg);
1062 /* 2nd: transform all remaining nodes */
1063 ia32_transform_graph(cg);
1064 // Matze: disabled for now. Because after transformation start block has no
1065 // self-loop anymore so it might be merged with its successor block. This
1066 // will bring several nodes to the startblock which sometimes get scheduled
1067 // before the initial IncSP/Barrier
1068 //local_optimize_graph(cg->irg);
1071 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
1073 /* 3rd: optimize address mode */
1074 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
1075 ia32_optimize_addressmode(cg);
1078 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
1080 DEBUG_ONLY(cg->mod = old_mod;)
1084 * Dummy functions for hooks we don't need but which must be filled.
1086 static void ia32_before_sched(void *self) {
1089 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
1092 ir_node *mem_proj = NULL;
1097 mode = get_irn_mode(irn);
1099 /* check if we already saw this node or the node has more than one user */
1100 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) {
1104 /* mark irn visited */
1105 bitset_add_irn(already_visited, irn);
1107 /* non-Tuple nodes with one user: ok, return */
1108 if (get_irn_n_edges(irn) >= 1 && mode != mode_T) {
1112 /* tuple node has one user which is not the mem proj-> ok */
1113 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
1114 mem_proj = ia32_get_proj_for_mode(irn, mode_M);
1115 if (mem_proj == NULL) {
1120 arity = get_irn_arity(irn);
1121 for (i = 0; i < arity; ++i) {
1122 ir_node *pred = get_irn_n(irn, i);
1124 /* do not follow memory edges or we will accidentally remove stores */
1125 if (get_irn_mode(pred) == mode_M) {
1126 if(mem_proj != NULL) {
1127 edges_reroute(mem_proj, pred, get_irn_irg(mem_proj));
1133 set_irn_n(irn, i, new_Bad());
1136 The current node is about to be removed: if the predecessor
1137 has only this node as user, it need to be removed as well.
1139 if (get_irn_n_edges(pred) <= 1)
1140 remove_unused_nodes(pred, already_visited);
1143 // we need to set the presd to Bad again to also get the memory edges
1144 arity = get_irn_arity(irn);
1145 for (i = 0; i < arity; ++i) {
1146 set_irn_n(irn, i, new_Bad());
1149 if (sched_is_scheduled(irn)) {
1154 static void remove_unused_loads_walker(ir_node *irn, void *env) {
1155 bitset_t *already_visited = env;
1156 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
1157 remove_unused_nodes(irn, env);
1161 * Called before the register allocator.
1162 * Calculate a block schedule here. We need it for the x87
1163 * simulator and the emitter.
1165 static void ia32_before_ra(void *self) {
1166 ia32_code_gen_t *cg = self;
1167 bitset_t *already_visited = bitset_irg_alloca(cg->irg);
1170 Handle special case:
1171 There are sometimes unused loads, only pinned by memory.
1172 We need to remove those Loads and all other nodes which won't be used
1173 after removing the Load from schedule.
1175 irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
1180 * Transforms a be_Reload into a ia32 Load.
1182 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1183 ir_graph *irg = get_irn_irg(node);
1184 dbg_info *dbg = get_irn_dbg_info(node);
1185 ir_node *block = get_nodes_block(node);
1186 ir_entity *ent = be_get_frame_entity(node);
1187 ir_mode *mode = get_irn_mode(node);
1188 ir_mode *spillmode = get_spill_mode(node);
1189 ir_node *noreg = ia32_new_NoReg_gp(cg);
1190 ir_node *sched_point = NULL;
1191 ir_node *ptr = get_irg_frame(irg);
1192 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1193 ir_node *new_op, *proj;
1194 const arch_register_t *reg;
1196 if (sched_is_scheduled(node)) {
1197 sched_point = sched_prev(node);
1200 if (mode_is_float(spillmode)) {
1202 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem);
1204 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem);
1207 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1209 set_ia32_am_support(new_op, ia32_am_Source);
1210 set_ia32_op_type(new_op, ia32_AddrModeS);
1211 set_ia32_am_flavour(new_op, ia32_B);
1212 set_ia32_ls_mode(new_op, spillmode);
1213 set_ia32_frame_ent(new_op, ent);
1214 set_ia32_use_frame(new_op);
1216 DBG_OPT_RELOAD2LD(node, new_op);
1218 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1221 sched_add_after(sched_point, new_op);
1222 sched_add_after(new_op, proj);
1227 /* copy the register from the old node to the new Load */
1228 reg = arch_get_irn_register(cg->arch_env, node);
1229 arch_set_irn_register(cg->arch_env, new_op, reg);
1231 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1233 exchange(node, proj);
1237 * Transforms a be_Spill node into a ia32 Store.
1239 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1240 ir_graph *irg = get_irn_irg(node);
1241 dbg_info *dbg = get_irn_dbg_info(node);
1242 ir_node *block = get_nodes_block(node);
1243 ir_entity *ent = be_get_frame_entity(node);
1244 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1245 ir_mode *mode = get_spill_mode(spillval);
1246 ir_node *noreg = ia32_new_NoReg_gp(cg);
1247 ir_node *nomem = new_rd_NoMem(irg);
1248 ir_node *ptr = get_irg_frame(irg);
1249 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1251 ir_node *sched_point = NULL;
1253 if (sched_is_scheduled(node)) {
1254 sched_point = sched_prev(node);
1257 if (mode_is_float(mode)) {
1259 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem);
1261 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem);
1263 else if (get_mode_size_bits(mode) == 8) {
1264 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem);
1267 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem);
1270 set_ia32_am_support(store, ia32_am_Dest);
1271 set_ia32_op_type(store, ia32_AddrModeD);
1272 set_ia32_am_flavour(store, ia32_B);
1273 set_ia32_ls_mode(store, mode);
1274 set_ia32_frame_ent(store, ent);
1275 set_ia32_use_frame(store);
1277 DBG_OPT_SPILL2ST(node, store);
1278 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1281 sched_add_after(sched_point, store);
1285 exchange(node, store);
1288 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1289 ir_graph *irg = get_irn_irg(node);
1290 dbg_info *dbg = get_irn_dbg_info(node);
1291 ir_node *block = get_nodes_block(node);
1292 ir_node *noreg = ia32_new_NoReg_gp(cg);
1293 ir_node *frame = get_irg_frame(irg);
1295 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, noreg, sp, mem);
1297 set_ia32_frame_ent(push, ent);
1298 set_ia32_use_frame(push);
1299 set_ia32_op_type(push, ia32_AddrModeS);
1300 set_ia32_am_flavour(push, ia32_B);
1301 set_ia32_ls_mode(push, mode_Is);
1303 sched_add_before(schedpoint, push);
1307 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1308 ir_graph *irg = get_irn_irg(node);
1309 dbg_info *dbg = get_irn_dbg_info(node);
1310 ir_node *block = get_nodes_block(node);
1311 ir_node *noreg = ia32_new_NoReg_gp(cg);
1312 ir_node *frame = get_irg_frame(irg);
1314 ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, sp, new_NoMem());
1316 set_ia32_frame_ent(pop, ent);
1317 set_ia32_use_frame(pop);
1318 set_ia32_op_type(pop, ia32_AddrModeD);
1319 set_ia32_am_flavour(pop, ia32_am_OB);
1320 set_ia32_ls_mode(pop, mode_Is);
1322 sched_add_before(schedpoint, pop);
1327 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos, ir_node *schedpoint) {
1328 ir_graph *irg = get_irn_irg(node);
1329 dbg_info *dbg = get_irn_dbg_info(node);
1330 ir_node *block = get_nodes_block(node);
1331 ir_mode *spmode = mode_Iu;
1332 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1335 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1336 arch_set_irn_register(cg->arch_env, sp, spreg);
1337 sched_add_before(schedpoint, sp);
1343 * Transform memperm, currently we do this the ugly way and produce
1344 * push/pop into/from memory cascades. This is possible without using
1347 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1348 ir_graph *irg = get_irn_irg(node);
1349 ir_node *block = get_nodes_block(node);
1353 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1354 const ir_edge_t *edge;
1355 const ir_edge_t *next;
1358 arity = be_get_MemPerm_entity_arity(node);
1359 pops = alloca(arity * sizeof(pops[0]));
1362 for(i = 0; i < arity; ++i) {
1363 ir_entity *ent = be_get_MemPerm_in_entity(node, i);
1364 ir_type *enttype = get_entity_type(ent);
1365 int entbits = get_type_size_bits(enttype);
1366 ir_node *mem = get_irn_n(node, i + 1);
1369 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1371 push = create_push(cg, node, node, sp, mem, ent);
1372 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1374 // add another push after the first one
1375 push = create_push(cg, node, node, sp, mem, ent);
1376 add_ia32_am_offs_int(push, 4);
1377 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1380 set_irn_n(node, i, new_Bad());
1384 for(i = arity - 1; i >= 0; --i) {
1385 ir_entity *ent = be_get_MemPerm_out_entity(node, i);
1386 ir_type *enttype = get_entity_type(ent);
1387 int entbits = get_type_size_bits(enttype);
1391 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1393 pop = create_pop(cg, node, node, sp, ent);
1394 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1396 add_ia32_am_offs_int(pop, 4);
1398 // add another pop after the first one
1399 pop = create_pop(cg, node, node, sp, ent);
1400 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1407 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1408 sched_add_before(node, keep);
1410 // exchange memprojs
1411 foreach_out_edge_safe(node, edge, next) {
1412 ir_node *proj = get_edge_src_irn(edge);
1413 int p = get_Proj_proj(proj);
1417 set_Proj_pred(proj, pops[p]);
1418 set_Proj_proj(proj, 3);
1422 arity = get_irn_arity(node);
1423 for(i = 0; i < arity; ++i) {
1424 set_irn_n(node, i, new_Bad());
1430 * Block-Walker: Calls the transform functions Spill and Reload.
1432 static void ia32_after_ra_walker(ir_node *block, void *env) {
1433 ir_node *node, *prev;
1434 ia32_code_gen_t *cg = env;
1436 /* beware: the schedule is changed here */
1437 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1438 prev = sched_prev(node);
1440 if (be_is_Reload(node)) {
1441 transform_to_Load(cg, node);
1442 } else if (be_is_Spill(node)) {
1443 transform_to_Store(cg, node);
1444 } else if(be_is_MemPerm(node)) {
1445 transform_MemPerm(cg, node);
1451 * Collects nodes that need frame entities assigned.
1453 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1455 be_fec_env_t *env = data;
1457 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1458 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1459 int align = get_mode_size_bytes(mode);
1460 be_node_needs_frame_entity(env, node, mode, align);
1461 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1462 && is_ia32_use_frame(node)) {
1463 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1464 const ir_mode *mode = get_ia32_ls_mode(node);
1465 int align = get_mode_size_bytes(mode);
1466 be_node_needs_frame_entity(env, node, mode, align);
1467 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)) {
1468 const ir_mode *mode = get_ia32_ls_mode(node);
1470 be_node_needs_frame_entity(env, node, mode, align);
1471 } else if (is_ia32_SetST0(node)) {
1472 const ir_mode *mode = get_ia32_ls_mode(node);
1474 be_node_needs_frame_entity(env, node, mode, align);
1477 if(!is_ia32_Store(node)
1478 && !is_ia32_xStore(node)
1479 && !is_ia32_xStoreSimple(node)
1480 && !is_ia32_vfist(node)
1481 && !is_ia32_GetST0(node)) {
1490 * We transform Spill and Reload here. This needs to be done before
1491 * stack biasing otherwise we would miss the corrected offset for these nodes.
1493 static void ia32_after_ra(void *self) {
1494 ia32_code_gen_t *cg = self;
1495 ir_graph *irg = cg->irg;
1496 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1498 /* create and coalesce frame entities */
1499 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1500 be_assign_entities(fec_env);
1501 be_free_frame_entity_coalescer(fec_env);
1503 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1505 ia32_finish_irg(irg, cg);
1509 * Last touchups for the graph before emit: x87 simulation to replace the
1510 * virtual with real x87 instructions, creating a block schedule and peephole
1513 static void ia32_finish(void *self) {
1514 ia32_code_gen_t *cg = self;
1515 ir_graph *irg = cg->irg;
1517 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1518 if (cg->used_fp == fp_x87 || cg->force_sim) {
1519 x87_simulate_graph(cg->arch_env, cg->birg);
1522 /* create block schedule, this also removes empty blocks which might
1523 * produce critical edges */
1524 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1526 /* do peephole optimisations */
1527 ia32_peephole_optimization(irg, cg);
1531 * Emits the code, closes the output file and frees
1532 * the code generator interface.
1534 static void ia32_codegen(void *self) {
1535 ia32_code_gen_t *cg = self;
1536 ir_graph *irg = cg->irg;
1538 ia32_gen_routine(cg, cg->isa->out, irg);
1542 /* remove it from the isa */
1545 /* de-allocate code generator */
1546 del_set(cg->reg_set);
1550 static void *ia32_cg_init(be_irg_t *birg);
1552 static const arch_code_generator_if_t ia32_code_gen_if = {
1554 NULL, /* before abi introduce hook */
1557 ia32_before_sched, /* before scheduling hook */
1558 ia32_before_ra, /* before register allocation hook */
1559 ia32_after_ra, /* after register allocation hook */
1560 ia32_finish, /* called before codegen */
1561 ia32_codegen /* emit && done */
1565 * Initializes a IA32 code generator.
1567 static void *ia32_cg_init(be_irg_t *birg) {
1568 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1569 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1571 cg->impl = &ia32_code_gen_if;
1572 cg->irg = birg->irg;
1573 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1574 cg->arch_env = birg->main_env->arch_env;
1577 cg->blk_sched = NULL;
1578 cg->fp_kind = isa->fp_kind;
1579 cg->used_fp = fp_none;
1580 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1582 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1584 /* copy optimizations from isa for easier access */
1586 cg->arch = isa->arch;
1587 cg->opt_arch = isa->opt_arch;
1593 if (isa->name_obst) {
1594 obstack_free(isa->name_obst, NULL);
1595 obstack_init(isa->name_obst);
1599 cur_reg_set = cg->reg_set;
1601 ia32_irn_ops.cg = cg;
1603 return (arch_code_generator_t *)cg;
1608 /*****************************************************************
1609 * ____ _ _ _____ _____
1610 * | _ \ | | | | |_ _|/ ____| /\
1611 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1612 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1613 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1614 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1616 *****************************************************************/
1619 * Set output modes for GCC
1621 static const tarval_mode_info mo_integer = {
1628 * set the tarval output mode of all integer modes to decimal
1630 static void set_tarval_output_modes(void)
1634 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1635 ir_mode *mode = get_irp_mode(i);
1637 if (mode_is_int(mode))
1638 set_tarval_mode_output_option(mode, &mo_integer);
1642 const arch_isa_if_t ia32_isa_if;
1645 * The template that generates a new ISA object.
1646 * Note that this template can be changed by command line
1649 static ia32_isa_t ia32_isa_template = {
1651 &ia32_isa_if, /* isa interface implementation */
1652 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1653 &ia32_gp_regs[REG_EBP], /* base pointer register */
1654 -1, /* stack direction */
1655 NULL, /* main environment */
1657 NULL, /* 16bit register names */
1658 NULL, /* 8bit register names */
1662 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1663 IA32_OPT_DOAM | /* optimize address mode default: on */
1664 IA32_OPT_LEA | /* optimize for LEAs default: on */
1665 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1666 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1667 IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
1668 arch_pentium_4, /* instruction architecture */
1669 arch_pentium_4, /* optimize for architecture */
1670 fp_sse2, /* use sse2 unit */
1671 NULL, /* current code generator */
1672 NULL, /* output file */
1674 NULL, /* name obstack */
1675 0 /* name obst size */
1680 * Initializes the backend ISA.
1682 static void *ia32_init(FILE *file_handle) {
1683 static int inited = 0;
1689 set_tarval_output_modes();
1691 isa = xmalloc(sizeof(*isa));
1692 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1694 ia32_register_init(isa);
1695 ia32_create_opcodes();
1696 ia32_register_copy_attr_func();
1698 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1699 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1700 /* no SSE2 for these cpu's */
1701 isa->fp_kind = fp_x87;
1703 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1704 /* Pentium 4 don't like inc and dec instructions */
1705 isa->opt &= ~IA32_OPT_INCDEC;
1708 isa->regs_16bit = pmap_create();
1709 isa->regs_8bit = pmap_create();
1710 isa->types = pmap_create();
1711 isa->tv_ent = pmap_create();
1712 isa->out = file_handle;
1713 isa->cpu = ia32_init_machine_description();
1715 ia32_build_16bit_reg_map(isa->regs_16bit);
1716 ia32_build_8bit_reg_map(isa->regs_8bit);
1718 /* patch register names of x87 registers */
1719 ia32_st_regs[0].name = "st";
1720 ia32_st_regs[1].name = "st(1)";
1721 ia32_st_regs[2].name = "st(2)";
1722 ia32_st_regs[3].name = "st(3)";
1723 ia32_st_regs[4].name = "st(4)";
1724 ia32_st_regs[5].name = "st(5)";
1725 ia32_st_regs[6].name = "st(6)";
1726 ia32_st_regs[7].name = "st(7)";
1729 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1730 obstack_init(isa->name_obst);
1733 ia32_handle_intrinsics();
1734 ia32_switch_section(isa->out, NO_SECTION);
1736 /* needed for the debug support */
1737 ia32_switch_section(isa->out, SECTION_TEXT);
1738 fprintf(isa->out, ".Ltext0:\n");
1748 * Closes the output file and frees the ISA structure.
1750 static void ia32_done(void *self) {
1751 ia32_isa_t *isa = self;
1753 /* emit now all global declarations */
1754 ia32_gen_decls(isa->out, isa->arch_isa.main_env);
1756 pmap_destroy(isa->regs_16bit);
1757 pmap_destroy(isa->regs_8bit);
1758 pmap_destroy(isa->tv_ent);
1759 pmap_destroy(isa->types);
1762 obstack_free(isa->name_obst, NULL);
1770 * Return the number of register classes for this architecture.
1771 * We report always these:
1772 * - the general purpose registers
1773 * - the SSE floating point register set
1774 * - the virtual floating point registers
1776 static int ia32_get_n_reg_class(const void *self) {
1781 * Return the register class for index i.
1783 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1784 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1786 return &ia32_reg_classes[CLASS_ia32_gp];
1788 return &ia32_reg_classes[CLASS_ia32_xmm];
1790 return &ia32_reg_classes[CLASS_ia32_vfp];
1794 * Get the register class which shall be used to store a value of a given mode.
1795 * @param self The this pointer.
1796 * @param mode The mode in question.
1797 * @return A register class which can hold values of the given mode.
1799 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1800 const ia32_isa_t *isa = self;
1801 if (mode_is_float(mode)) {
1802 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1805 return &ia32_reg_classes[CLASS_ia32_gp];
1809 * Get the ABI restrictions for procedure calls.
1810 * @param self The this pointer.
1811 * @param method_type The type of the method (procedure) in question.
1812 * @param abi The abi object to be modified
1814 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1815 const ia32_isa_t *isa = self;
1818 unsigned cc = get_method_calling_convention(method_type);
1819 int n = get_method_n_params(method_type);
1822 int i, ignore_1, ignore_2;
1824 const arch_register_t *reg;
1825 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1827 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1829 /* set abi flags for calls */
1830 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1831 call_flags.bits.store_args_sequential = use_push;
1832 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1833 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1834 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1836 /* set stack parameter passing style */
1837 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1839 /* collect the mode for each type */
1840 modes = alloca(n * sizeof(modes[0]));
1842 for (i = 0; i < n; i++) {
1843 tp = get_method_param_type(method_type, i);
1844 modes[i] = get_type_mode(tp);
1847 /* set register parameters */
1848 if (cc & cc_reg_param) {
1849 /* determine the number of parameters passed via registers */
1850 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1852 /* loop over all parameters and set the register requirements */
1853 for (i = 0; i <= biggest_n; i++) {
1854 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1855 assert(reg && "kaputt");
1856 be_abi_call_param_reg(abi, i, reg);
1863 /* set stack parameters */
1864 for (i = stack_idx; i < n; i++) {
1865 /* parameters on the stack are 32 bit aligned */
1866 be_abi_call_param_stack(abi, i, 4, 0, 0);
1870 /* set return registers */
1871 n = get_method_n_ress(method_type);
1873 assert(n <= 2 && "more than two results not supported");
1875 /* In case of 64bit returns, we will have two 32bit values */
1877 tp = get_method_res_type(method_type, 0);
1878 mode = get_type_mode(tp);
1880 assert(!mode_is_float(mode) && "two FP results not supported");
1882 tp = get_method_res_type(method_type, 1);
1883 mode = get_type_mode(tp);
1885 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1887 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1888 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1891 const arch_register_t *reg;
1893 tp = get_method_res_type(method_type, 0);
1894 assert(is_atomic_type(tp));
1895 mode = get_type_mode(tp);
1897 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1899 be_abi_call_res_reg(abi, 0, reg);
1904 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1905 return &ia32_irn_ops;
1908 const arch_irn_handler_t ia32_irn_handler = {
1912 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1913 return &ia32_irn_handler;
1916 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1917 return is_ia32_irn(irn) ? 1 : -1;
1921 * Initializes the code generator interface.
1923 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1924 return &ia32_code_gen_if;
1928 * Returns the estimated execution time of an ia32 irn.
1930 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1931 const arch_env_t *arch_env = env;
1932 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1935 list_sched_selector_t ia32_sched_selector;
1938 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1940 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1941 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1942 ia32_sched_selector.exectime = ia32_sched_exectime;
1943 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1944 return &ia32_sched_selector;
1947 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self) {
1952 * Returns the necessary byte alignment for storing a register of given class.
1954 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1955 ir_mode *mode = arch_register_class_mode(cls);
1956 int bytes = get_mode_size_bytes(mode);
1958 if (mode_is_float(mode) && bytes > 8)
1963 static const be_execution_unit_t ***ia32_get_allowed_execution_units(const void *self, const ir_node *irn) {
1964 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1965 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1966 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1969 static const be_execution_unit_t *_allowed_units_GP[] = {
1970 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1971 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1972 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1973 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1974 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1975 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1976 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1979 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1980 &be_machine_execution_units_DUMMY[0],
1983 static const be_execution_unit_t **_units_callret[] = {
1984 _allowed_units_BRANCH,
1987 static const be_execution_unit_t **_units_other[] = {
1991 static const be_execution_unit_t **_units_dummy[] = {
1992 _allowed_units_DUMMY,
1995 const be_execution_unit_t ***ret;
1997 if (is_ia32_irn(irn)) {
1998 ret = get_ia32_exec_units(irn);
2000 else if (is_be_node(irn)) {
2001 if (be_is_Call(irn) || be_is_Return(irn)) {
2002 ret = _units_callret;
2004 else if (be_is_Barrier(irn)) {
2019 * Return the abstract ia32 machine.
2021 static const be_machine_t *ia32_get_machine(const void *self) {
2022 const ia32_isa_t *isa = self;
2027 * Return irp irgs in the desired order.
2029 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list) {
2034 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2035 * @return 1 if allowed, 0 otherwise
2037 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2039 ir_node *cmp, *cmp_a, *phi;
2042 /* we don't want long long an floating point Psi */
2043 #define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2045 if (get_irn_mode(sel) != mode_b)
2048 cmp = get_Proj_pred(sel);
2049 cmp_a = get_Cmp_left(cmp);
2050 mode = get_irn_mode(cmp_a);
2052 if (IS_BAD_PSI_MODE(mode))
2055 /* check the Phi nodes */
2056 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
2057 ir_node *pred_i = get_irn_n(phi, i);
2058 ir_node *pred_j = get_irn_n(phi, j);
2059 ir_mode *mode_i = get_irn_mode(pred_i);
2060 ir_mode *mode_j = get_irn_mode(pred_j);
2062 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
2066 #undef IS_BAD_PSI_MODE
2071 static ia32_intrinsic_env_t intrinsic_env = {
2072 NULL, /**< the irg, these entities belong to */
2073 NULL, /**< entity for first div operand (move into FPU) */
2074 NULL, /**< entity for second div operand (move into FPU) */
2075 NULL, /**< entity for converts ll -> d */
2076 NULL, /**< entity for converts d -> ll */
2080 * Returns the libFirm configuration parameter for this backend.
2082 static const backend_params *ia32_get_libfirm_params(void) {
2083 static const opt_if_conv_info_t ifconv = {
2084 4, /* maxdepth, doesn't matter for Psi-conversion */
2085 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2087 static const arch_dep_params_t ad = {
2088 1, /* also use subs */
2089 4, /* maximum shifts */
2090 31, /* maximum shift amount */
2092 1, /* allow Mulhs */
2093 1, /* allow Mulus */
2094 32 /* Mulh allowed up to 32 bit */
2096 static backend_params p = {
2097 NULL, /* no additional opcodes */
2098 NULL, /* will be set later */
2099 1, /* need dword lowering */
2100 ia32_create_intrinsic_fkt,
2101 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2102 NULL, /* will be set later */
2106 p.if_conv_info = &ifconv;
2111 /* instruction set architectures. */
2112 static const lc_opt_enum_int_items_t arch_items[] = {
2113 { "386", arch_i386, },
2114 { "486", arch_i486, },
2115 { "pentium", arch_pentium, },
2116 { "586", arch_pentium, },
2117 { "pentiumpro", arch_pentium_pro, },
2118 { "686", arch_pentium_pro, },
2119 { "pentiummmx", arch_pentium_mmx, },
2120 { "pentium2", arch_pentium_2, },
2121 { "p2", arch_pentium_2, },
2122 { "pentium3", arch_pentium_3, },
2123 { "p3", arch_pentium_3, },
2124 { "pentium4", arch_pentium_4, },
2125 { "p4", arch_pentium_4, },
2126 { "pentiumm", arch_pentium_m, },
2127 { "pm", arch_pentium_m, },
2128 { "core", arch_core, },
2130 { "athlon", arch_athlon, },
2131 { "athlon64", arch_athlon_64, },
2132 { "opteron", arch_opteron, },
2136 static lc_opt_enum_int_var_t arch_var = {
2137 &ia32_isa_template.arch, arch_items
2140 static lc_opt_enum_int_var_t opt_arch_var = {
2141 &ia32_isa_template.opt_arch, arch_items
2144 static const lc_opt_enum_int_items_t fp_unit_items[] = {
2146 { "sse2", fp_sse2 },
2150 static lc_opt_enum_int_var_t fp_unit_var = {
2151 &ia32_isa_template.fp_kind, fp_unit_items
2154 static const lc_opt_enum_int_items_t gas_items[] = {
2155 { "linux", ASM_LINUX_GAS },
2156 { "mingw", ASM_MINGW_GAS },
2160 static lc_opt_enum_int_var_t gas_var = {
2161 (int *)&asm_flavour, gas_items
2164 static const lc_opt_table_entry_t ia32_options[] = {
2165 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
2166 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
2167 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
2168 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
2169 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
2170 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
2171 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
2172 LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
2173 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2176 #endif /* WITH_LIBCORE */
2178 const arch_isa_if_t ia32_isa_if = {
2181 ia32_get_n_reg_class,
2183 ia32_get_reg_class_for_mode,
2185 ia32_get_irn_handler,
2186 ia32_get_code_generator_if,
2187 ia32_get_list_sched_selector,
2188 ia32_get_ilp_sched_selector,
2189 ia32_get_reg_class_alignment,
2190 ia32_get_libfirm_params,
2191 ia32_get_allowed_execution_units,
2196 void be_init_arch_ia32(void)
2198 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2199 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2201 lc_opt_add_table(ia32_grp, ia32_options);
2202 be_register_isa_if("ia32", &ia32_isa_if);
2205 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);