2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
31 #include "lc_opts_enum.h"
35 #include "pseudo_irg.h"
40 #include "iredges_t.h"
46 #include "irdump_grgen.h"
53 #include "iroptimize.h"
54 #include "instrument.h"
57 #include "../beirg_t.h"
58 #include "../benode_t.h"
59 #include "../belower.h"
60 #include "../besched_t.h"
63 #include "../beirgmod.h"
64 #include "../be_dbgout.h"
65 #include "../beblocksched.h"
66 #include "../bemachine.h"
67 #include "../beilpsched.h"
68 #include "../bespillslots.h"
69 #include "../bemodule.h"
70 #include "../begnuas.h"
71 #include "../bestate.h"
72 #include "../beflags.h"
74 #include "bearch_ia32_t.h"
76 #include "ia32_new_nodes.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "gen_ia32_machine.h"
79 #include "ia32_transform.h"
80 #include "ia32_emitter.h"
81 #include "ia32_map_regs.h"
82 #include "ia32_optimize.h"
84 #include "ia32_dbg_stat.h"
85 #include "ia32_finish.h"
86 #include "ia32_util.h"
88 #include "ia32_architecture.h"
91 #include "ia32_pbqp_transform.h"
94 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
97 static set *cur_reg_set = NULL;
99 ir_mode *mode_fpcw = NULL;
100 ia32_code_gen_t *ia32_current_cg = NULL;
103 * The environment for the intrinsic mapping.
105 static ia32_intrinsic_env_t intrinsic_env = {
107 NULL, /* the irg, these entities belong to */
108 NULL, /* entity for first div operand (move into FPU) */
109 NULL, /* entity for second div operand (move into FPU) */
110 NULL, /* entity for converts ll -> d */
111 NULL, /* entity for converts d -> ll */
112 NULL, /* entity for __divdi3 library call */
113 NULL, /* entity for __moddi3 library call */
114 NULL, /* entity for __udivdi3 library call */
115 NULL, /* entity for __umoddi3 library call */
116 NULL, /* bias value for conversion from float to unsigned 64 */
120 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
122 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
123 create_const_node_func func,
124 const arch_register_t* reg)
126 ir_node *block, *res;
131 block = get_irg_start_block(cg->irg);
132 res = func(NULL, cg->irg, block);
133 arch_set_irn_register(cg->arch_env, res, reg);
136 add_irn_dep(get_irg_end(cg->irg), res);
137 /* add_irn_dep(get_irg_start(cg->irg), res); */
142 /* Creates the unique per irg GP NoReg node. */
143 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
144 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
145 &ia32_gp_regs[REG_GP_NOREG]);
148 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
149 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
150 &ia32_vfp_regs[REG_VFP_NOREG]);
153 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
154 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
155 &ia32_xmm_regs[REG_XMM_NOREG]);
158 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
159 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
160 &ia32_gp_regs[REG_GP_UKNWN]);
163 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
164 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
165 &ia32_vfp_regs[REG_VFP_UKNWN]);
168 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
169 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
170 &ia32_xmm_regs[REG_XMM_UKNWN]);
173 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
174 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
175 &ia32_fp_cw_regs[REG_FPCW]);
180 * Returns gp_noreg or fp_noreg, depending in input requirements.
182 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
183 const arch_register_req_t *req;
185 req = arch_get_register_req(cg->arch_env, irn, pos);
186 assert(req != NULL && "Missing register requirements");
187 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
188 return ia32_new_NoReg_gp(cg);
190 if (ia32_cg_config.use_sse2) {
191 return ia32_new_NoReg_xmm(cg);
193 return ia32_new_NoReg_vfp(cg);
197 /**************************************************
200 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
201 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
202 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
203 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
206 **************************************************/
209 * Return register requirements for an ia32 node.
210 * If the node returns a tuple (mode_T) then the proj's
211 * will be asked for this information.
213 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
217 long node_pos = pos == -1 ? 0 : pos;
218 ir_mode *mode = is_Block(node) ? NULL : get_irn_mode(node);
221 if (is_Block(node) || mode == mode_X) {
222 return arch_no_register_req;
225 if (mode == mode_T && pos < 0) {
226 return arch_no_register_req;
231 return arch_no_register_req;
234 return arch_no_register_req;
237 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
238 node = skip_Proj_const(node);
241 if (is_ia32_irn(node)) {
242 const arch_register_req_t *req;
244 req = get_ia32_in_req(node, pos);
246 req = get_ia32_out_req(node, node_pos);
253 /* unknowns should be transformed already */
254 assert(!is_Unknown(node));
256 return arch_no_register_req;
259 static void ia32_set_irn_reg(const void *self, ir_node *irn,
260 const arch_register_t *reg)
265 if (get_irn_mode(irn) == mode_X) {
270 pos = get_Proj_proj(irn);
271 irn = skip_Proj(irn);
274 if (is_ia32_irn(irn)) {
275 const arch_register_t **slots;
277 slots = get_ia32_slots(irn);
280 ia32_set_firm_reg(irn, reg, cur_reg_set);
284 static const arch_register_t *ia32_get_irn_reg(const void *self,
288 const arch_register_t *reg = NULL;
293 if (get_irn_mode(irn) == mode_X) {
297 pos = get_Proj_proj(irn);
298 irn = skip_Proj_const(irn);
301 if (is_ia32_irn(irn)) {
302 const arch_register_t **slots;
303 slots = get_ia32_slots(irn);
304 assert(pos < get_ia32_n_res(irn));
307 reg = ia32_get_firm_reg(irn, cur_reg_set);
313 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
314 arch_irn_class_t classification = arch_irn_class_normal;
317 irn = skip_Proj_const(irn);
320 classification |= arch_irn_class_branch;
322 if (! is_ia32_irn(irn))
323 return classification & ~arch_irn_class_normal;
326 classification |= arch_irn_class_load;
329 classification |= arch_irn_class_store;
331 if (is_ia32_need_stackent(irn))
332 classification |= arch_irn_class_reload;
334 return classification;
337 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
338 arch_irn_flags_t flags = arch_irn_flags_none;
342 return arch_irn_flags_ignore;
344 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
345 ir_node *pred = get_Proj_pred(irn);
347 if(is_ia32_irn(pred)) {
348 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
354 if (is_ia32_irn(irn)) {
355 flags |= get_ia32_flags(irn);
362 * The IA32 ABI callback object.
365 be_abi_call_flags_bits_t flags; /**< The call flags. */
366 const arch_isa_t *isa; /**< The ISA handle. */
367 const arch_env_t *aenv; /**< The architecture environment. */
368 ir_graph *irg; /**< The associated graph. */
371 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
373 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
376 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
378 set_ia32_frame_ent(irn, ent);
381 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias)
383 const ia32_irn_ops_t *ops = self;
385 if (get_ia32_frame_ent(irn) == NULL)
388 if (is_ia32_Pop(irn)) {
389 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
391 /* Pop nodes modify the stack pointer before calculating the
392 * destination address, so fix this here
397 add_ia32_am_offs_int(irn, bias);
400 static int ia32_get_sp_bias(const void *self, const ir_node *node)
404 if (is_ia32_Push(node))
407 if (is_ia32_Pop(node))
414 * Put all registers which are saved by the prologue/epilogue in a set.
416 * @param self The callback object.
417 * @param s The result set.
419 static void ia32_abi_dont_save_regs(void *self, pset *s)
421 ia32_abi_env_t *env = self;
422 if(env->flags.try_omit_fp)
423 pset_insert_ptr(s, env->isa->bp);
427 * Generate the routine prologue.
429 * @param self The callback object.
430 * @param mem A pointer to the mem node. Update this if you define new memory.
431 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
433 * @return The register which shall be used as a stack frame base.
435 * All nodes which define registers in @p reg_map must keep @p reg_map current.
437 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
439 ia32_abi_env_t *env = self;
440 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
441 ia32_code_gen_t *cg = isa->cg;
443 if (! env->flags.try_omit_fp) {
444 ir_node *bl = get_irg_start_block(env->irg);
445 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
446 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
447 ir_node *noreg = ia32_new_NoReg_gp(cg);
450 /* ALL nodes representing bp must be set to ignore. */
451 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
454 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp, curr_bp);
455 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
456 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
458 /* the push must have SP out register */
459 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
460 set_ia32_flags(push, arch_irn_flags_ignore);
462 /* move esp to ebp */
463 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
464 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
465 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
466 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
468 /* beware: the copy must be done before any other sp use */
469 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
470 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
471 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
472 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
474 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
475 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
484 * Generate the routine epilogue.
485 * @param self The callback object.
486 * @param bl The block for the epilog
487 * @param mem A pointer to the mem node. Update this if you define new memory.
488 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
489 * @return The register which shall be used as a stack frame base.
491 * All nodes which define registers in @p reg_map must keep @p reg_map current.
493 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
495 ia32_abi_env_t *env = self;
496 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
497 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
499 if (env->flags.try_omit_fp) {
500 /* simply remove the stack frame here */
501 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
502 add_irn_dep(curr_sp, *mem);
504 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
505 ir_graph *irg = current_ir_graph;
507 if (ia32_cg_config.use_leave) {
511 leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
512 set_ia32_flags(leave, arch_irn_flags_ignore);
513 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
514 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
518 /* the old SP is not needed anymore (kill the proj) */
519 assert(is_Proj(curr_sp));
520 be_kill_node(curr_sp);
522 /* copy ebp to esp */
523 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
524 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
525 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
528 pop = new_rd_ia32_Pop(NULL, env->irg, bl, *mem, curr_sp);
529 set_ia32_flags(pop, arch_irn_flags_ignore);
530 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
531 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
533 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
535 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
536 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
539 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
540 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
544 * Initialize the callback object.
545 * @param call The call object.
546 * @param aenv The architecture environment.
547 * @param irg The graph with the method.
548 * @return Some pointer. This pointer is passed to all other callback functions as self object.
550 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
552 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
553 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
554 env->flags = fl.bits;
557 env->isa = aenv->isa;
562 * Destroy the callback object.
563 * @param self The callback object.
565 static void ia32_abi_done(void *self) {
570 * Produces the type which sits between the stack args and the locals on the stack.
571 * it will contain the return address and space to store the old base pointer.
572 * @return The Firm type modeling the ABI between type.
574 static ir_type *ia32_abi_get_between_type(void *self)
576 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
577 static ir_type *omit_fp_between_type = NULL;
578 static ir_type *between_type = NULL;
580 ia32_abi_env_t *env = self;
582 if (! between_type) {
583 ir_entity *old_bp_ent;
584 ir_entity *ret_addr_ent;
585 ir_entity *omit_fp_ret_addr_ent;
587 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
588 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
590 between_type = new_type_struct(IDENT("ia32_between_type"));
591 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
592 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
594 set_entity_offset(old_bp_ent, 0);
595 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
596 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
597 set_type_state(between_type, layout_fixed);
599 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
600 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
602 set_entity_offset(omit_fp_ret_addr_ent, 0);
603 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
604 set_type_state(omit_fp_between_type, layout_fixed);
607 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
612 * Get the estimated cycle count for @p irn.
614 * @param self The this pointer.
615 * @param irn The node.
617 * @return The estimated cycle count for this operation
619 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
622 ia32_op_type_t op_tp;
627 if (!is_ia32_irn(irn))
630 assert(is_ia32_irn(irn));
632 cost = get_ia32_latency(irn);
633 op_tp = get_ia32_op_type(irn);
635 if (is_ia32_CopyB(irn)) {
638 else if (is_ia32_CopyB_i(irn)) {
639 int size = get_ia32_copyb_size(irn);
640 cost = 20 + (int)ceil((4/3) * size);
642 /* in case of address mode operations add additional cycles */
643 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
645 In case of stack access and access to fixed addresses add 5 cycles
646 (we assume they are in cache), other memory operations cost 20
649 if(is_ia32_use_frame(irn) ||
650 (is_ia32_NoReg_GP(get_irn_n(irn, 0)) &&
651 is_ia32_NoReg_GP(get_irn_n(irn, 1)))) {
662 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
664 * @param irn The original operation
665 * @param i Index of the argument we want the inverse operation to yield
666 * @param inverse struct to be filled with the resulting inverse op
667 * @param obstack The obstack to use for allocation of the returned nodes array
668 * @return The inverse operation or NULL if operation invertible
670 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
674 ir_node *block, *noreg, *nomem;
678 /* we cannot invert non-ia32 irns */
679 if (! is_ia32_irn(irn))
682 /* operand must always be a real operand (not base, index or mem) */
683 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
686 /* we don't invert address mode operations */
687 if (get_ia32_op_type(irn) != ia32_Normal)
690 /* TODO: adjust for new immediates... */
691 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
695 irg = get_irn_irg(irn);
696 block = get_nodes_block(irn);
697 mode = get_irn_mode(irn);
698 irn_mode = get_irn_mode(irn);
699 noreg = get_irn_n(irn, 0);
700 nomem = new_r_NoMem(irg);
701 dbg = get_irn_dbg_info(irn);
703 /* initialize structure */
704 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
708 switch (get_ia32_irn_opcode(irn)) {
711 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
712 /* we have an add with a const here */
713 /* invers == add with negated const */
714 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
716 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
717 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
718 set_ia32_commutative(inverse->nodes[0]);
720 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
721 /* we have an add with a symconst here */
722 /* invers == sub with const */
723 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
725 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
728 /* normal add: inverse == sub */
729 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
736 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
737 /* we have a sub with a const/symconst here */
738 /* invers == add with this const */
739 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
740 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
741 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
745 if (i == n_ia32_binary_left) {
746 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
749 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
757 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
758 /* xor with const: inverse = xor */
759 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
760 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
761 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
765 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
771 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
776 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
781 /* inverse operation not supported */
788 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
790 if(mode_is_float(mode))
797 * Get the mode that should be used for spilling value node
799 static ir_mode *get_spill_mode(const ir_node *node)
801 ir_mode *mode = get_irn_mode(node);
802 return get_spill_mode_mode(mode);
806 * Checks whether an addressmode reload for a node with mode mode is compatible
807 * with a spillslot of mode spill_mode
809 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
811 if(mode_is_float(mode)) {
812 return mode == spillmode;
819 * Check if irn can load it's operand at position i from memory (source addressmode).
820 * @param self Pointer to irn ops itself
821 * @param irn The irn to be checked
822 * @param i The operands position
823 * @return Non-Zero if operand can be loaded
825 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
826 ir_node *op = get_irn_n(irn, i);
827 const ir_mode *mode = get_irn_mode(op);
828 const ir_mode *spillmode = get_spill_mode(op);
831 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
832 get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */
833 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
834 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
835 ! ia32_is_spillmode_compatible(mode, spillmode) ||
836 (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
837 is_ia32_use_frame(irn)) /* must not already use frame */
840 if (i == n_ia32_binary_left) {
841 const arch_register_req_t *req;
842 if(!is_ia32_commutative(irn))
844 /* we can't swap left/right for limited registers
845 * (As this (currently) breaks constraint handling copies)
847 req = get_ia32_in_req(irn, n_ia32_binary_left);
848 if(req->type & arch_register_req_type_limited) {
856 static void ia32_perform_memory_operand(const void *self, ir_node *irn,
857 ir_node *spill, unsigned int i)
859 const ia32_irn_ops_t *ops = self;
860 ia32_code_gen_t *cg = ops->cg;
862 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
864 if (i == n_ia32_binary_left) {
865 ia32_swap_left_right(irn);
868 set_ia32_op_type(irn, ia32_AddrModeS);
869 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
870 set_ia32_use_frame(irn);
871 set_ia32_need_stackent(irn);
873 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
874 set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
875 set_irn_n(irn, n_ia32_mem, spill);
877 /* immediates are only allowed on the right side */
878 if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
879 ia32_swap_left_right(irn);
883 static const be_abi_callbacks_t ia32_abi_callbacks = {
886 ia32_abi_get_between_type,
887 ia32_abi_dont_save_regs,
892 /* fill register allocator interface */
894 static const arch_irn_ops_if_t ia32_irn_ops_if = {
895 ia32_get_irn_reg_req,
900 ia32_get_frame_entity,
901 ia32_set_frame_entity,
902 ia32_set_frame_offset,
905 ia32_get_op_estimated_cost,
906 ia32_possible_memory_operand,
907 ia32_perform_memory_operand,
910 static ia32_irn_ops_t ia32_irn_ops = {
917 /**************************************************
920 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
921 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
922 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
923 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
926 **************************************************/
928 static ir_entity *mcount = NULL;
930 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
932 static void ia32_before_abi(void *self) {
933 lower_mode_b_config_t lower_mode_b_config = {
934 mode_Iu, /* lowered mode */
935 mode_Bu, /* prefered mode for set */
936 0, /* don't lower direct compares */
938 ia32_code_gen_t *cg = self;
940 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
942 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
944 if (mcount == NULL) {
945 ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
946 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
947 /* FIXME: enter the right ld_ident here */
948 set_entity_ld_ident(mcount, get_entity_ident(mcount));
949 set_entity_visibility(mcount, visibility_external_allocated);
951 instrument_initcall(cg->irg, mcount);
956 * Transforms the standard firm graph into
959 static void ia32_prepare_graph(void *self) {
960 ia32_code_gen_t *cg = self;
962 /* do local optimisations */
963 optimize_graph_df(cg->irg);
965 /* TODO: we often have dead code reachable through out-edges here. So for
966 * now we rebuild edges (as we need correct user count for code selection)
969 edges_deactivate(cg->irg);
970 edges_activate(cg->irg);
974 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
977 /* transform nodes into assembler instructions by PBQP magic */
978 ia32_transform_graph_by_pbqp(cg);
982 be_dump(cg->irg, "-after_pbqp_transform", dump_ir_block_graph_sched);
984 /* transform remaining nodes into assembler instructions */
985 ia32_transform_graph(cg);
987 /* do local optimisations (mainly CSE) */
988 optimize_graph_df(cg->irg);
991 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
993 /* optimize address mode */
994 ia32_optimize_graph(cg);
997 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
999 /* do code placement, to optimize the position of constants */
1000 place_code(cg->irg);
1003 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
1007 * Dummy functions for hooks we don't need but which must be filled.
1009 static void ia32_before_sched(void *self) {
1013 static void turn_back_am(ir_node *node)
1015 ir_graph *irg = current_ir_graph;
1016 dbg_info *dbgi = get_irn_dbg_info(node);
1017 ir_node *block = get_nodes_block(node);
1018 ir_node *base = get_irn_n(node, n_ia32_base);
1019 ir_node *index = get_irn_n(node, n_ia32_index);
1020 ir_node *mem = get_irn_n(node, n_ia32_mem);
1021 ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg);
1025 const ir_edge_t *edge;
1027 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1028 load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1030 ia32_copy_am_attrs(load, node);
1031 set_irn_n(node, n_ia32_mem, new_NoMem());
1033 switch (get_ia32_am_arity(node)) {
1035 set_irn_n(node, n_ia32_unary_op, load_res);
1038 case ia32_am_binary:
1039 if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
1040 assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) ||
1041 is_ia32_Test(node) || is_ia32_Test8Bit(node));
1042 set_irn_n(node, n_ia32_binary_left, load_res);
1044 set_irn_n(node, n_ia32_binary_right, load_res);
1048 case ia32_am_ternary:
1049 set_irn_n(node, n_ia32_binary_right, load_res);
1054 set_irn_n(node, n_ia32_base, noreg);
1055 set_irn_n(node, n_ia32_index, noreg);
1056 set_ia32_am_offs_int(node, 0);
1057 set_ia32_am_sc(node, NULL);
1058 set_ia32_am_scale(node, 0);
1059 clear_ia32_am_sc_sign(node);
1061 /* rewire mem-proj */
1062 if (get_irn_mode(node) == mode_T) {
1064 foreach_out_edge(node, edge) {
1065 ir_node *out = get_edge_src_irn(edge);
1066 if(get_Proj_proj(out) == pn_ia32_mem) {
1072 if(mem_proj != NULL) {
1073 set_Proj_pred(mem_proj, load);
1074 set_Proj_proj(mem_proj, pn_ia32_Load_M);
1078 set_ia32_op_type(node, ia32_Normal);
1079 if (sched_is_scheduled(node))
1080 sched_add_before(node, load);
1083 static ir_node *flags_remat(ir_node *node, ir_node *after)
1085 /* we should turn back source address mode when rematerializing nodes */
1086 ia32_op_type_t type = get_ia32_op_type(node);
1090 if (is_Block(after)) {
1093 block = get_nodes_block(after);
1097 case ia32_AddrModeS: turn_back_am(node); break;
1099 case ia32_AddrModeD:
1100 /* TODO implement this later... */
1101 panic("found DestAM with flag user %+F this should not happen", node);
1104 default: assert(type == ia32_Normal); break;
1107 copy = exact_copy(node);
1108 set_nodes_block(copy, block);
1109 sched_add_after(after, copy);
1115 * Called before the register allocator.
1116 * Calculate a block schedule here. We need it for the x87
1117 * simulator and the emitter.
1119 static void ia32_before_ra(void *self) {
1120 ia32_code_gen_t *cg = self;
1122 /* setup fpu rounding modes */
1123 ia32_setup_fpu_mode(cg);
1126 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1129 ia32_add_missing_keeps(cg);
1134 * Transforms a be_Reload into a ia32 Load.
1136 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1137 ir_graph *irg = get_irn_irg(node);
1138 dbg_info *dbg = get_irn_dbg_info(node);
1139 ir_node *block = get_nodes_block(node);
1140 ir_entity *ent = be_get_frame_entity(node);
1141 ir_mode *mode = get_irn_mode(node);
1142 ir_mode *spillmode = get_spill_mode(node);
1143 ir_node *noreg = ia32_new_NoReg_gp(cg);
1144 ir_node *sched_point = NULL;
1145 ir_node *ptr = get_irg_frame(irg);
1146 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1147 ir_node *new_op, *proj;
1148 const arch_register_t *reg;
1150 if (sched_is_scheduled(node)) {
1151 sched_point = sched_prev(node);
1154 if (mode_is_float(spillmode)) {
1155 if (ia32_cg_config.use_sse2)
1156 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
1158 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
1160 else if (get_mode_size_bits(spillmode) == 128) {
1161 // Reload 128 bit sse registers
1162 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1165 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1167 set_ia32_op_type(new_op, ia32_AddrModeS);
1168 set_ia32_ls_mode(new_op, spillmode);
1169 set_ia32_frame_ent(new_op, ent);
1170 set_ia32_use_frame(new_op);
1172 DBG_OPT_RELOAD2LD(node, new_op);
1174 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1177 sched_add_after(sched_point, new_op);
1181 /* copy the register from the old node to the new Load */
1182 reg = arch_get_irn_register(cg->arch_env, node);
1183 arch_set_irn_register(cg->arch_env, new_op, reg);
1185 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1187 exchange(node, proj);
1191 * Transforms a be_Spill node into a ia32 Store.
1193 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1194 ir_graph *irg = get_irn_irg(node);
1195 dbg_info *dbg = get_irn_dbg_info(node);
1196 ir_node *block = get_nodes_block(node);
1197 ir_entity *ent = be_get_frame_entity(node);
1198 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1199 ir_mode *mode = get_spill_mode(spillval);
1200 ir_node *noreg = ia32_new_NoReg_gp(cg);
1201 ir_node *nomem = new_rd_NoMem(irg);
1202 ir_node *ptr = get_irg_frame(irg);
1203 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1205 ir_node *sched_point = NULL;
1207 if (sched_is_scheduled(node)) {
1208 sched_point = sched_prev(node);
1211 /* No need to spill unknown values... */
1212 if(is_ia32_Unknown_GP(val) ||
1213 is_ia32_Unknown_VFP(val) ||
1214 is_ia32_Unknown_XMM(val)) {
1219 exchange(node, store);
1223 if (mode_is_float(mode)) {
1224 if (ia32_cg_config.use_sse2)
1225 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
1227 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
1228 } else if (get_mode_size_bits(mode) == 128) {
1229 // Spill 128 bit SSE registers
1230 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
1231 } else if (get_mode_size_bits(mode) == 8) {
1232 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
1234 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
1237 set_ia32_op_type(store, ia32_AddrModeD);
1238 set_ia32_ls_mode(store, mode);
1239 set_ia32_frame_ent(store, ent);
1240 set_ia32_use_frame(store);
1241 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1242 DBG_OPT_SPILL2ST(node, store);
1245 sched_add_after(sched_point, store);
1249 exchange(node, store);
1252 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1253 ir_graph *irg = get_irn_irg(node);
1254 dbg_info *dbg = get_irn_dbg_info(node);
1255 ir_node *block = get_nodes_block(node);
1256 ir_node *noreg = ia32_new_NoReg_gp(cg);
1257 ir_node *frame = get_irg_frame(irg);
1259 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, sp, noreg);
1261 set_ia32_frame_ent(push, ent);
1262 set_ia32_use_frame(push);
1263 set_ia32_op_type(push, ia32_AddrModeS);
1264 set_ia32_ls_mode(push, mode_Is);
1266 sched_add_before(schedpoint, push);
1270 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1271 ir_graph *irg = get_irn_irg(node);
1272 dbg_info *dbg = get_irn_dbg_info(node);
1273 ir_node *block = get_nodes_block(node);
1274 ir_node *noreg = ia32_new_NoReg_gp(cg);
1275 ir_node *frame = get_irg_frame(irg);
1277 ir_node *pop = new_rd_ia32_PopMem(dbg, irg, block, frame, noreg, new_NoMem(), sp);
1279 set_ia32_frame_ent(pop, ent);
1280 set_ia32_use_frame(pop);
1281 set_ia32_op_type(pop, ia32_AddrModeD);
1282 set_ia32_ls_mode(pop, mode_Is);
1284 sched_add_before(schedpoint, pop);
1289 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
1290 ir_graph *irg = get_irn_irg(node);
1291 dbg_info *dbg = get_irn_dbg_info(node);
1292 ir_node *block = get_nodes_block(node);
1293 ir_mode *spmode = mode_Iu;
1294 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1297 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1298 arch_set_irn_register(cg->arch_env, sp, spreg);
1304 * Transform memperm, currently we do this the ugly way and produce
1305 * push/pop into/from memory cascades. This is possible without using
1308 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1309 ir_graph *irg = get_irn_irg(node);
1310 ir_node *block = get_nodes_block(node);
1314 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1315 const ir_edge_t *edge;
1316 const ir_edge_t *next;
1319 arity = be_get_MemPerm_entity_arity(node);
1320 pops = alloca(arity * sizeof(pops[0]));
1323 for(i = 0; i < arity; ++i) {
1324 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1325 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1326 ir_type *enttype = get_entity_type(inent);
1327 unsigned entsize = get_type_size_bytes(enttype);
1328 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1329 ir_node *mem = get_irn_n(node, i + 1);
1332 /* work around cases where entities have different sizes */
1333 if(entsize2 < entsize)
1335 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1337 push = create_push(cg, node, node, sp, mem, inent);
1338 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1340 /* add another push after the first one */
1341 push = create_push(cg, node, node, sp, mem, inent);
1342 add_ia32_am_offs_int(push, 4);
1343 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1346 set_irn_n(node, i, new_Bad());
1350 for(i = arity - 1; i >= 0; --i) {
1351 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1352 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1353 ir_type *enttype = get_entity_type(outent);
1354 unsigned entsize = get_type_size_bytes(enttype);
1355 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1358 /* work around cases where entities have different sizes */
1359 if(entsize2 < entsize)
1361 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1363 pop = create_pop(cg, node, node, sp, outent);
1364 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1366 add_ia32_am_offs_int(pop, 4);
1368 /* add another pop after the first one */
1369 pop = create_pop(cg, node, node, sp, outent);
1370 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1377 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1378 sched_add_before(node, keep);
1380 /* exchange memprojs */
1381 foreach_out_edge_safe(node, edge, next) {
1382 ir_node *proj = get_edge_src_irn(edge);
1383 int p = get_Proj_proj(proj);
1387 set_Proj_pred(proj, pops[p]);
1388 set_Proj_proj(proj, pn_ia32_Pop_M);
1391 /* remove memperm */
1392 arity = get_irn_arity(node);
1393 for(i = 0; i < arity; ++i) {
1394 set_irn_n(node, i, new_Bad());
1400 * Block-Walker: Calls the transform functions Spill and Reload.
1402 static void ia32_after_ra_walker(ir_node *block, void *env) {
1403 ir_node *node, *prev;
1404 ia32_code_gen_t *cg = env;
1406 /* beware: the schedule is changed here */
1407 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1408 prev = sched_prev(node);
1410 if (be_is_Reload(node)) {
1411 transform_to_Load(cg, node);
1412 } else if (be_is_Spill(node)) {
1413 transform_to_Store(cg, node);
1414 } else if(be_is_MemPerm(node)) {
1415 transform_MemPerm(cg, node);
1421 * Collects nodes that need frame entities assigned.
1423 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1425 be_fec_env_t *env = data;
1427 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1428 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1429 int align = get_mode_size_bytes(mode);
1430 be_node_needs_frame_entity(env, node, mode, align);
1431 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1432 && is_ia32_use_frame(node)) {
1433 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1434 const ir_mode *mode = get_ia32_ls_mode(node);
1435 const ia32_attr_t *attr = get_ia32_attr_const(node);
1436 int align = get_mode_size_bytes(mode);
1438 if(attr->data.need_64bit_stackent) {
1441 if(attr->data.need_32bit_stackent) {
1444 be_node_needs_frame_entity(env, node, mode, align);
1445 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
1446 || is_ia32_vfld(node)) {
1447 const ir_mode *mode = get_ia32_ls_mode(node);
1449 be_node_needs_frame_entity(env, node, mode, align);
1450 } else if(is_ia32_FldCW(node)) {
1451 /* although 2 byte would be enough 4 byte performs best */
1452 const ir_mode *mode = mode_Iu;
1454 be_node_needs_frame_entity(env, node, mode, align);
1457 assert(is_ia32_St(node) ||
1458 is_ia32_xStoreSimple(node) ||
1459 is_ia32_vfst(node) ||
1460 is_ia32_vfist(node) ||
1461 is_ia32_FnstCW(node));
1468 * We transform Spill and Reload here. This needs to be done before
1469 * stack biasing otherwise we would miss the corrected offset for these nodes.
1471 static void ia32_after_ra(void *self) {
1472 ia32_code_gen_t *cg = self;
1473 ir_graph *irg = cg->irg;
1474 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1476 /* create and coalesce frame entities */
1477 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1478 be_assign_entities(fec_env);
1479 be_free_frame_entity_coalescer(fec_env);
1481 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1485 * Last touchups for the graph before emit: x87 simulation to replace the
1486 * virtual with real x87 instructions, creating a block schedule and peephole
1489 static void ia32_finish(void *self) {
1490 ia32_code_gen_t *cg = self;
1491 ir_graph *irg = cg->irg;
1493 ia32_finish_irg(irg, cg);
1495 /* we might have to rewrite x87 virtual registers */
1496 if (cg->do_x87_sim) {
1497 x87_simulate_graph(cg->arch_env, cg->birg);
1500 /* do peephole optimisations */
1501 ia32_peephole_optimization(cg);
1503 /* create block schedule, this also removes empty blocks which might
1504 * produce critical edges */
1505 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1509 * Emits the code, closes the output file and frees
1510 * the code generator interface.
1512 static void ia32_codegen(void *self) {
1513 ia32_code_gen_t *cg = self;
1514 ir_graph *irg = cg->irg;
1516 ia32_gen_routine(cg, irg);
1520 /* remove it from the isa */
1523 assert(ia32_current_cg == cg);
1524 ia32_current_cg = NULL;
1526 /* de-allocate code generator */
1527 del_set(cg->reg_set);
1532 * Returns the node representing the PIC base.
1534 static ir_node *ia32_get_pic_base(void *self) {
1536 ia32_code_gen_t *cg = self;
1537 ir_node *get_eip = cg->get_eip;
1538 if (get_eip != NULL)
1541 block = get_irg_start_block(cg->irg);
1542 get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block);
1543 cg->get_eip = get_eip;
1545 add_irn_dep(get_eip, get_irg_frame(cg->irg));
1550 static void *ia32_cg_init(be_irg_t *birg);
1552 static const arch_code_generator_if_t ia32_code_gen_if = {
1554 ia32_get_pic_base, /* return node used as base in pic code addresses */
1555 ia32_before_abi, /* before abi introduce hook */
1558 ia32_before_sched, /* before scheduling hook */
1559 ia32_before_ra, /* before register allocation hook */
1560 ia32_after_ra, /* after register allocation hook */
1561 ia32_finish, /* called before codegen */
1562 ia32_codegen /* emit && done */
1566 * Initializes a IA32 code generator.
1568 static void *ia32_cg_init(be_irg_t *birg) {
1569 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env.isa;
1570 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1572 cg->impl = &ia32_code_gen_if;
1573 cg->irg = birg->irg;
1574 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1575 cg->arch_env = &birg->main_env->arch_env;
1578 cg->blk_sched = NULL;
1579 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1580 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1583 /* Linux gprof implementation needs base pointer */
1584 birg->main_env->options->omit_fp = 0;
1591 if (isa->name_obst) {
1592 obstack_free(isa->name_obst, NULL);
1593 obstack_init(isa->name_obst);
1597 cur_reg_set = cg->reg_set;
1599 ia32_irn_ops.cg = cg;
1601 assert(ia32_current_cg == NULL);
1602 ia32_current_cg = cg;
1604 return (arch_code_generator_t *)cg;
1609 /*****************************************************************
1610 * ____ _ _ _____ _____
1611 * | _ \ | | | | |_ _|/ ____| /\
1612 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1613 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1614 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1615 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1617 *****************************************************************/
1620 * Set output modes for GCC
1622 static const tarval_mode_info mo_integer = {
1629 * set the tarval output mode of all integer modes to decimal
1631 static void set_tarval_output_modes(void)
1635 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1636 ir_mode *mode = get_irp_mode(i);
1638 if (mode_is_int(mode))
1639 set_tarval_mode_output_option(mode, &mo_integer);
1643 const arch_isa_if_t ia32_isa_if;
1646 * The template that generates a new ISA object.
1647 * Note that this template can be changed by command line
1650 static ia32_isa_t ia32_isa_template = {
1652 &ia32_isa_if, /* isa interface implementation */
1653 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1654 &ia32_gp_regs[REG_EBP], /* base pointer register */
1655 -1, /* stack direction */
1656 16, /* stack alignment */
1657 NULL, /* main environment */
1658 7, /* costs for a spill instruction */
1659 5, /* costs for a reload instruction */
1661 NULL, /* 16bit register names */
1662 NULL, /* 8bit register names */
1663 NULL, /* 8bit register names high */
1666 NULL, /* current code generator */
1667 NULL, /* abstract machine */
1669 NULL, /* name obstack */
1674 * Initializes the backend ISA.
1676 static void *ia32_init(FILE *file_handle) {
1677 static int inited = 0;
1684 set_tarval_output_modes();
1686 isa = xmalloc(sizeof(*isa));
1687 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1689 if(mode_fpcw == NULL) {
1690 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1693 ia32_register_init();
1694 ia32_create_opcodes();
1696 be_emit_init(file_handle);
1697 isa->regs_16bit = pmap_create();
1698 isa->regs_8bit = pmap_create();
1699 isa->regs_8bit_high = pmap_create();
1700 isa->types = pmap_create();
1701 isa->tv_ent = pmap_create();
1702 isa->cpu = ia32_init_machine_description();
1704 ia32_build_16bit_reg_map(isa->regs_16bit);
1705 ia32_build_8bit_reg_map(isa->regs_8bit);
1706 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1709 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1710 obstack_init(isa->name_obst);
1713 /* enter the ISA object into the intrinsic environment */
1714 intrinsic_env.isa = isa;
1715 ia32_handle_intrinsics();
1717 /* needed for the debug support */
1718 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1719 be_emit_cstring(".Ltext0:\n");
1720 be_emit_write_line();
1722 /* we mark referenced global entities, so we can only emit those which
1723 * are actually referenced. (Note: you mustn't use the type visited flag
1724 * elsewhere in the backend)
1726 inc_master_type_visited();
1734 * Closes the output file and frees the ISA structure.
1736 static void ia32_done(void *self) {
1737 ia32_isa_t *isa = self;
1739 /* emit now all global declarations */
1740 be_gas_emit_decls(isa->arch_isa.main_env, 1);
1742 pmap_destroy(isa->regs_16bit);
1743 pmap_destroy(isa->regs_8bit);
1744 pmap_destroy(isa->regs_8bit_high);
1745 pmap_destroy(isa->tv_ent);
1746 pmap_destroy(isa->types);
1749 obstack_free(isa->name_obst, NULL);
1759 * Return the number of register classes for this architecture.
1760 * We report always these:
1761 * - the general purpose registers
1762 * - the SSE floating point register set
1763 * - the virtual floating point registers
1764 * - the SSE vector register set
1766 static unsigned ia32_get_n_reg_class(const void *self) {
1772 * Return the register class for index i.
1774 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1778 assert(i < N_CLASSES);
1779 return &ia32_reg_classes[i];
1783 * Get the register class which shall be used to store a value of a given mode.
1784 * @param self The this pointer.
1785 * @param mode The mode in question.
1786 * @return A register class which can hold values of the given mode.
1788 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1789 const ir_mode *mode)
1793 if (mode_is_float(mode)) {
1794 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1797 return &ia32_reg_classes[CLASS_ia32_gp];
1801 * Get the ABI restrictions for procedure calls.
1802 * @param self The this pointer.
1803 * @param method_type The type of the method (procedure) in question.
1804 * @param abi The abi object to be modified
1806 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1813 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1816 /* set abi flags for calls */
1817 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1818 call_flags.bits.store_args_sequential = 0;
1819 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1820 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1821 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1823 /* set parameter passing style */
1824 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1826 if (get_method_variadicity(method_type) == variadicity_variadic) {
1827 /* pass all parameters of a variadic function on the stack */
1830 cc = get_method_calling_convention(method_type);
1831 if (get_method_additional_properties(method_type) & mtp_property_private
1832 && (ia32_cg_config.optimize_cc)) {
1833 /* set the calling conventions to register parameter */
1834 cc = (cc & ~cc_bits) | cc_reg_param;
1838 /* we have to pop the shadow parameter ourself for compound calls */
1839 if( (get_method_calling_convention(method_type) & cc_compound_ret)
1840 && !(cc & cc_reg_param)) {
1841 be_abi_call_set_pop(abi, get_mode_size_bytes(mode_P_data));
1844 n = get_method_n_params(method_type);
1845 for (i = regnum = 0; i < n; i++) {
1847 const arch_register_t *reg = NULL;
1849 tp = get_method_param_type(method_type, i);
1850 mode = get_type_mode(tp);
1852 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1855 be_abi_call_param_reg(abi, i, reg);
1858 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1859 * movl has a shorter opcode than mov[sz][bw]l */
1860 ir_mode *load_mode = mode;
1861 if (mode != NULL && get_mode_size_bytes(mode) < 4) load_mode = mode_Iu;
1862 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1866 /* set return registers */
1867 n = get_method_n_ress(method_type);
1869 assert(n <= 2 && "more than two results not supported");
1871 /* In case of 64bit returns, we will have two 32bit values */
1873 tp = get_method_res_type(method_type, 0);
1874 mode = get_type_mode(tp);
1876 assert(!mode_is_float(mode) && "two FP results not supported");
1878 tp = get_method_res_type(method_type, 1);
1879 mode = get_type_mode(tp);
1881 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1883 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1884 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1887 const arch_register_t *reg;
1889 tp = get_method_res_type(method_type, 0);
1890 assert(is_atomic_type(tp));
1891 mode = get_type_mode(tp);
1893 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1895 be_abi_call_res_reg(abi, 0, reg);
1900 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self,
1905 return &ia32_irn_ops;
1908 const arch_irn_handler_t ia32_irn_handler = {
1912 const arch_irn_handler_t *ia32_get_irn_handler(const void *self)
1915 return &ia32_irn_handler;
1918 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1922 if(!is_ia32_irn(irn)) {
1926 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1927 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1928 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1929 || is_ia32_Immediate(irn))
1936 * Initializes the code generator interface.
1938 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1941 return &ia32_code_gen_if;
1945 * Returns the estimated execution time of an ia32 irn.
1947 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1948 const arch_env_t *arch_env = env;
1949 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1952 list_sched_selector_t ia32_sched_selector;
1955 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1957 static const list_sched_selector_t *ia32_get_list_sched_selector(
1958 const void *self, list_sched_selector_t *selector)
1961 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1962 ia32_sched_selector.exectime = ia32_sched_exectime;
1963 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1964 return &ia32_sched_selector;
1967 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1974 * Returns the necessary byte alignment for storing a register of given class.
1976 static int ia32_get_reg_class_alignment(const void *self,
1977 const arch_register_class_t *cls)
1979 ir_mode *mode = arch_register_class_mode(cls);
1980 int bytes = get_mode_size_bytes(mode);
1983 if (mode_is_float(mode) && bytes > 8)
1988 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1989 const void *self, const ir_node *irn)
1991 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1992 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1993 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1996 static const be_execution_unit_t *_allowed_units_GP[] = {
1997 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1998 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1999 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
2000 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
2001 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
2002 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
2003 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2006 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2007 &be_machine_execution_units_DUMMY[0],
2010 static const be_execution_unit_t **_units_callret[] = {
2011 _allowed_units_BRANCH,
2014 static const be_execution_unit_t **_units_other[] = {
2018 static const be_execution_unit_t **_units_dummy[] = {
2019 _allowed_units_DUMMY,
2022 const be_execution_unit_t ***ret;
2025 if (is_ia32_irn(irn)) {
2026 ret = get_ia32_exec_units(irn);
2028 else if (is_be_node(irn)) {
2029 if (be_is_Call(irn) || be_is_Return(irn)) {
2030 ret = _units_callret;
2032 else if (be_is_Barrier(irn)) {
2047 * Return the abstract ia32 machine.
2049 static const be_machine_t *ia32_get_machine(const void *self) {
2050 const ia32_isa_t *isa = self;
2055 * Return irp irgs in the desired order.
2057 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2065 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2066 * @return 1 if allowed, 0 otherwise
2068 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2076 if(!ia32_cg_config.use_cmov) {
2077 /* TODO: we could still handle abs(x)... */
2081 /* we can't handle psis with 64bit compares yet */
2083 ir_node *pred = get_Proj_pred(sel);
2085 ir_node *left = get_Cmp_left(pred);
2086 ir_mode *cmp_mode = get_irn_mode(left);
2087 if(!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
2092 /* check the Phi nodes */
2093 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
2094 ir_mode *mode = get_irn_mode(phi);
2096 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2104 * Returns the libFirm configuration parameter for this backend.
2106 static const backend_params *ia32_get_libfirm_params(void) {
2107 static const ir_settings_if_conv_t ifconv = {
2108 4, /* maxdepth, doesn't matter for Psi-conversion */
2109 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2111 static const ir_settings_arch_dep_t ad = {
2112 1, /* also use subs */
2113 4, /* maximum shifts */
2114 31, /* maximum shift amount */
2115 ia32_evaluate_insn, /* evaluate the instruction sequence */
2117 1, /* allow Mulhs */
2118 1, /* allow Mulus */
2119 32 /* Mulh allowed up to 32 bit */
2121 static backend_params p = {
2122 1, /* need dword lowering */
2123 1, /* support inline assembly */
2124 NULL, /* no additional opcodes */
2125 NULL, /* will be set later */
2126 ia32_create_intrinsic_fkt,
2127 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2128 NULL, /* will be set below */
2131 ia32_setup_cg_config();
2134 p.if_conv_info = &ifconv;
2138 static const lc_opt_enum_int_items_t gas_items[] = {
2139 { "elf", GAS_FLAVOUR_ELF },
2140 { "mingw", GAS_FLAVOUR_MINGW },
2141 { "yasm", GAS_FLAVOUR_YASM },
2142 { "macho", GAS_FLAVOUR_MACH_O },
2146 static lc_opt_enum_int_var_t gas_var = {
2147 (int*) &be_gas_flavour, gas_items
2150 static const lc_opt_table_entry_t ia32_options[] = {
2151 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2152 LC_OPT_ENT_INT("stackalign", "set stack alignment for calls",
2153 &ia32_isa_template.arch_isa.stack_alignment),
2157 const arch_isa_if_t ia32_isa_if = {
2160 ia32_get_n_reg_class,
2162 ia32_get_reg_class_for_mode,
2164 ia32_get_irn_handler,
2165 ia32_get_code_generator_if,
2166 ia32_get_list_sched_selector,
2167 ia32_get_ilp_sched_selector,
2168 ia32_get_reg_class_alignment,
2169 ia32_get_libfirm_params,
2170 ia32_get_allowed_execution_units,
2175 void ia32_init_emitter(void);
2176 void ia32_init_finish(void);
2177 void ia32_init_optimize(void);
2178 void ia32_init_transform(void);
2179 void ia32_init_x87(void);
2181 void be_init_arch_ia32(void)
2183 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2184 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2186 lc_opt_add_table(ia32_grp, ia32_options);
2187 be_register_isa_if("ia32", &ia32_isa_if);
2189 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2191 ia32_init_emitter();
2193 ia32_init_optimize();
2194 ia32_init_transform();
2196 ia32_init_architecture();
2199 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);