2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
26 #include "pseudo_irg.h"
30 #include "iredges_t.h"
39 #include "../beabi.h" /* the general register allocator interface */
40 #include "../benode_t.h"
41 #include "../belower.h"
42 #include "../besched_t.h"
45 #include "../beirgmod.h"
46 #include "../be_dbgout.h"
47 #include "../beblocksched.h"
48 #include "../bemachine.h"
49 #include "../beilpsched.h"
51 #include "bearch_ia32_t.h"
53 #include "ia32_new_nodes.h" /* ia32 nodes interface */
54 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
55 #include "gen_ia32_machine.h"
56 #include "ia32_gen_decls.h" /* interface declaration emitter */
57 #include "ia32_transform.h"
58 #include "ia32_emitter.h"
59 #include "ia32_map_regs.h"
60 #include "ia32_optimize.h"
62 #include "ia32_dbg_stat.h"
63 #include "ia32_finish.h"
64 #include "ia32_util.h"
66 #define DEBUG_MODULE "firm.be.ia32.isa"
69 static set *cur_reg_set = NULL;
71 /* Creates the unique per irg GP NoReg node. */
72 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
73 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
76 /* Creates the unique per irg FP NoReg node. */
77 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
78 return be_abi_get_callee_save_irn(cg->birg->abi,
79 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
83 * Returns gp_noreg or fp_noreg, depending in input requirements.
85 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
86 arch_register_req_t req;
87 const arch_register_req_t *p_req;
89 p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
90 assert(p_req && "Missing register requirements");
91 if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
92 return ia32_new_NoReg_gp(cg);
94 return ia32_new_NoReg_fp(cg);
97 /**************************************************
100 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
101 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
102 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
103 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
106 **************************************************/
109 * Return register requirements for an ia32 node.
110 * If the node returns a tuple (mode_T) then the proj's
111 * will be asked for this information.
113 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
114 const ia32_irn_ops_t *ops = self;
115 const ia32_register_req_t *irn_req;
116 long node_pos = pos == -1 ? 0 : pos;
117 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
118 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
120 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
121 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
125 if (mode == mode_T && pos < 0) {
126 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
130 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
134 DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
138 node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
139 irn = skip_Proj(irn);
141 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
144 if (is_ia32_irn(irn)) {
145 irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
146 if (irn_req == NULL) {
147 /* no requirements */
151 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
153 memcpy(req, &(irn_req->req), sizeof(*req));
155 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
156 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
157 req->other_same = get_irn_n(irn, irn_req->same_pos);
160 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
161 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
162 req->other_different = get_irn_n(irn, irn_req->different_pos);
166 /* treat Unknowns like Const with default requirements */
167 if (is_Unknown(irn)) {
168 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
169 if (mode_is_float(mode)) {
170 if (USE_SSE2(ops->cg))
171 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
173 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
175 else if (mode_is_int(mode) || mode_is_reference(mode))
176 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
177 else if (mode == mode_T || mode == mode_M) {
178 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
182 assert(0 && "unsupported Unknown-Mode");
185 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
193 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
195 const ia32_irn_ops_t *ops = self;
197 if (get_irn_mode(irn) == mode_X) {
201 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
204 pos = get_Proj_proj(irn);
205 irn = skip_Proj(irn);
208 if (is_ia32_irn(irn)) {
209 const arch_register_t **slots;
211 slots = get_ia32_slots(irn);
215 ia32_set_firm_reg(irn, reg, cur_reg_set);
219 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
221 const arch_register_t *reg = NULL;
225 if (get_irn_mode(irn) == mode_X) {
229 pos = get_Proj_proj(irn);
230 irn = skip_Proj(irn);
233 if (is_ia32_irn(irn)) {
234 const arch_register_t **slots;
235 slots = get_ia32_slots(irn);
239 reg = ia32_get_firm_reg(irn, cur_reg_set);
245 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
246 arch_irn_class_t classification = arch_irn_class_normal;
248 irn = skip_Proj(irn);
251 classification |= arch_irn_class_branch;
253 if (! is_ia32_irn(irn))
254 return classification & ~arch_irn_class_normal;
256 if (is_ia32_Cnst(irn))
257 classification |= arch_irn_class_const;
260 classification |= arch_irn_class_load;
262 if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
263 classification |= arch_irn_class_store;
265 if (is_ia32_got_reload(irn))
266 classification |= arch_irn_class_reload;
268 return classification;
271 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
272 arch_irn_flags_t flags;
273 ir_node *pred = is_Proj(irn) && mode_is_datab(get_irn_mode(irn)) ? get_Proj_pred(irn) : NULL;
276 flags = arch_irn_flags_ignore;
278 /* pred is only set, if we have a Proj */
279 flags = pred && is_ia32_irn(pred) ? get_ia32_out_flags(pred, get_Proj_proj(irn)) : arch_irn_flags_none;
281 irn = skip_Proj(irn);
282 if (is_ia32_irn(irn))
283 flags |= get_ia32_flags(irn);
290 * The IA32 ABI callback object.
293 be_abi_call_flags_bits_t flags; /**< The call flags. */
294 const arch_isa_t *isa; /**< The ISA handle. */
295 const arch_env_t *aenv; /**< The architecture environment. */
296 ir_graph *irg; /**< The associated graph. */
299 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
300 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
303 static void ia32_set_frame_entity(const void *self, ir_node *irn, entity *ent) {
304 set_ia32_frame_ent(irn, ent);
307 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
309 const ia32_irn_ops_t *ops = self;
311 if (get_ia32_frame_ent(irn)) {
312 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
314 if(is_ia32_Pop(irn)) {
315 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
317 /* Pop nodes modify the stack pointer before calculating the destination
318 * address, so fix this here
324 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
326 snprintf(buf, sizeof(buf), "%d", bias);
328 if (get_ia32_op_type(irn) == ia32_Normal) {
329 set_ia32_cnst(irn, buf);
331 add_ia32_am_offs(irn, buf);
333 set_ia32_am_flavour(irn, am_flav);
338 static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
340 long proj = get_Proj_proj(irn);
341 ir_node *pred = get_Proj_pred(irn);
343 if (proj == pn_ia32_Push_stack && is_ia32_Push(pred))
345 if (proj == pn_ia32_Pop_stack && is_ia32_Pop(pred))
353 * Put all registers which are saved by the prologue/epilogue in a set.
355 * @param self The callback object.
356 * @param s The result set.
358 static void ia32_abi_dont_save_regs(void *self, pset *s)
360 ia32_abi_env_t *env = self;
361 if(env->flags.try_omit_fp)
362 pset_insert_ptr(s, env->isa->bp);
366 * Generate the routine prologue.
368 * @param self The callback object.
369 * @param mem A pointer to the mem node. Update this if you define new memory.
370 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
372 * @return The register which shall be used as a stack frame base.
374 * All nodes which define registers in @p reg_map must keep @p reg_map current.
376 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
378 ia32_abi_env_t *env = self;
380 if (! env->flags.try_omit_fp) {
381 ir_node *bl = get_irg_start_block(env->irg);
382 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
383 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
384 ir_node *noreg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
388 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
389 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
390 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
392 /* the push must have SP out register */
393 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
394 set_ia32_flags(push, arch_irn_flags_ignore);
396 /* move esp to ebp */
397 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
398 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
399 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
400 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
402 /* beware: the copy must be done before any other sp use */
403 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
404 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
405 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
406 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
408 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
409 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
418 * Generate the routine epilogue.
419 * @param self The callback object.
420 * @param bl The block for the epilog
421 * @param mem A pointer to the mem node. Update this if you define new memory.
422 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
423 * @return The register which shall be used as a stack frame base.
425 * All nodes which define registers in @p reg_map must keep @p reg_map current.
427 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
429 ia32_abi_env_t *env = self;
430 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
431 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
433 if (env->flags.try_omit_fp) {
434 /* simply remove the stack frame here */
435 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
436 add_irn_dep(curr_sp, *mem);
439 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
440 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
442 /* gcc always emits a leave at the end of a routine */
443 if (1 || ARCH_AMD(isa->opt_arch)) {
447 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
448 set_ia32_flags(leave, arch_irn_flags_ignore);
449 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
450 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
451 *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
454 ir_node *noreg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
457 /* copy ebp to esp */
458 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
461 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
462 set_ia32_flags(pop, arch_irn_flags_ignore);
463 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
464 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
465 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
467 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
468 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
471 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
472 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
476 * Initialize the callback object.
477 * @param call The call object.
478 * @param aenv The architecture environment.
479 * @param irg The graph with the method.
480 * @return Some pointer. This pointer is passed to all other callback functions as self object.
482 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
484 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
485 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
486 env->flags = fl.bits;
489 env->isa = aenv->isa;
494 * Destroy the callback object.
495 * @param self The callback object.
497 static void ia32_abi_done(void *self) {
502 * Produces the type which sits between the stack args and the locals on the stack.
503 * it will contain the return address and space to store the old base pointer.
504 * @return The Firm type modeling the ABI between type.
506 static ir_type *ia32_abi_get_between_type(void *self)
508 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
509 static ir_type *omit_fp_between_type = NULL;
510 static ir_type *between_type = NULL;
512 ia32_abi_env_t *env = self;
514 if (! between_type) {
516 entity *ret_addr_ent;
517 entity *omit_fp_ret_addr_ent;
519 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_P);
520 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_P);
522 between_type = new_type_struct(IDENT("ia32_between_type"));
523 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
524 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
526 set_entity_offset_bytes(old_bp_ent, 0);
527 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
528 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
529 set_type_state(between_type, layout_fixed);
531 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
532 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
534 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
535 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
536 set_type_state(omit_fp_between_type, layout_fixed);
539 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
544 * Get the estimated cycle count for @p irn.
546 * @param self The this pointer.
547 * @param irn The node.
549 * @return The estimated cycle count for this operation
551 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
554 ia32_op_type_t op_tp;
555 const ia32_irn_ops_t *ops = self;
559 if (!is_ia32_irn(irn))
562 assert(is_ia32_irn(irn));
564 cost = get_ia32_latency(irn);
565 op_tp = get_ia32_op_type(irn);
567 if (is_ia32_CopyB(irn)) {
569 if (ARCH_INTEL(ops->cg->arch))
572 else if (is_ia32_CopyB_i(irn)) {
573 int size = get_tarval_long(get_ia32_Immop_tarval(irn));
574 cost = 20 + (int)ceil((4/3) * size);
575 if (ARCH_INTEL(ops->cg->arch))
578 /* in case of address mode operations add additional cycles */
579 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
581 In case of stack access add 5 cycles (we assume stack is in cache),
582 other memory operations cost 20 cycles.
584 cost += is_ia32_use_frame(irn) ? 5 : 20;
591 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
593 * @param irn The original operation
594 * @param i Index of the argument we want the inverse operation to yield
595 * @param inverse struct to be filled with the resulting inverse op
596 * @param obstack The obstack to use for allocation of the returned nodes array
597 * @return The inverse operation or NULL if operation invertible
599 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
602 ir_node *block, *noreg, *nomem;
605 /* we cannot invert non-ia32 irns */
606 if (! is_ia32_irn(irn))
609 /* operand must always be a real operand (not base, index or mem) */
610 if (i != 2 && i != 3)
613 /* we don't invert address mode operations */
614 if (get_ia32_op_type(irn) != ia32_Normal)
617 irg = get_irn_irg(irn);
618 block = get_nodes_block(irn);
619 mode = get_ia32_res_mode(irn);
620 noreg = get_irn_n(irn, 0);
621 nomem = new_r_NoMem(irg);
623 /* initialize structure */
624 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
628 switch (get_ia32_irn_opcode(irn)) {
630 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
631 /* we have an add with a const here */
632 /* invers == add with negated const */
633 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
634 pnc = pn_ia32_Add_res;
636 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
637 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
638 set_ia32_commutative(inverse->nodes[0]);
640 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
641 /* we have an add with a symconst here */
642 /* invers == sub with const */
643 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
644 pnc = pn_ia32_Sub_res;
646 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
649 /* normal add: inverse == sub */
650 ir_node *proj = ia32_get_res_proj(irn);
653 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, i ^ 1), nomem);
654 pnc = pn_ia32_Sub_res;
659 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
660 /* we have a sub with a const/symconst here */
661 /* invers == add with this const */
662 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
663 pnc = pn_ia32_Add_res;
664 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
665 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
669 ir_node *proj = ia32_get_res_proj(irn);
673 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, 3), nomem);
676 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, 2), proj, nomem);
678 pnc = pn_ia32_Sub_res;
683 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
684 /* xor with const: inverse = xor */
685 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
686 pnc = pn_ia32_Eor_res;
687 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
688 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
692 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, (ir_node *)irn, get_irn_n(irn, i), nomem);
693 pnc = pn_ia32_Eor_res;
698 ir_node *proj = ia32_get_res_proj(irn);
701 inverse->nodes[0] = new_rd_ia32_Not(NULL, irg, block, noreg, noreg, proj, nomem);
702 pnc = pn_ia32_Not_res;
706 case iro_ia32_Minus: {
707 ir_node *proj = ia32_get_res_proj(irn);
710 inverse->nodes[0] = new_rd_ia32_Minus(NULL, irg, block, noreg, noreg, proj, nomem);
711 pnc = pn_ia32_Minus_res;
716 /* inverse operation not supported */
720 set_ia32_res_mode(inverse->nodes[0], mode);
721 inverse->nodes[1] = new_r_Proj(irg, block, inverse->nodes[0], mode, pnc);
727 * Check if irn can load it's operand at position i from memory (source addressmode).
728 * @param self Pointer to irn ops itself
729 * @param irn The irn to be checked
730 * @param i The operands position
731 * @return Non-Zero if operand can be loaded
733 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
734 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
735 get_irn_arity(irn) != 5 || /* must be a binary operation */
736 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
737 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
738 (i != 2 && i != 3) || /* a "real" operand position must be requested */
739 (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
740 is_ia32_use_frame(irn)) /* must not already use frame */
746 static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
747 const ia32_irn_ops_t *ops = self;
748 ia32_code_gen_t *cg = ops->cg;
750 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
753 ir_node *tmp = get_irn_n(irn, 3);
754 set_irn_n(irn, 3, get_irn_n(irn, 2));
755 set_irn_n(irn, 2, tmp);
758 set_ia32_am_support(irn, ia32_am_Source);
759 set_ia32_op_type(irn, ia32_AddrModeS);
760 set_ia32_am_flavour(irn, ia32_B);
761 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
762 set_ia32_use_frame(irn);
763 set_ia32_got_reload(irn);
765 set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
766 set_irn_n(irn, 4, spill);
769 Input at position one is index register, which is NoReg.
770 We would need cg object to get a real noreg, but we cannot
773 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
775 //FIXME DBG_OPT_AM_S(reload, irn);
778 static const be_abi_callbacks_t ia32_abi_callbacks = {
781 ia32_abi_get_between_type,
782 ia32_abi_dont_save_regs,
787 /* fill register allocator interface */
789 static const arch_irn_ops_if_t ia32_irn_ops_if = {
790 ia32_get_irn_reg_req,
795 ia32_get_frame_entity,
796 ia32_set_frame_entity,
797 ia32_set_frame_offset,
800 ia32_get_op_estimated_cost,
801 ia32_possible_memory_operand,
802 ia32_perform_memory_operand,
805 ia32_irn_ops_t ia32_irn_ops = {
812 /**************************************************
815 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
816 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
817 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
818 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
821 **************************************************/
823 static void ia32_kill_convs(ia32_code_gen_t *cg) {
826 /* BEWARE: the Projs are inserted in the set */
827 foreach_nodeset(cg->kill_conv, irn) {
828 ir_node *in = get_irn_n(get_Proj_pred(irn), 2);
829 edges_reroute(irn, in, cg->birg->irg);
834 * Transform the Thread Local Store base.
836 static void transform_tls(ir_graph *irg) {
837 ir_node *irn = get_irg_tls(irg);
840 dbg_info *dbg = get_irn_dbg_info(irn);
841 ir_node *blk = get_nodes_block(irn);
843 newn = new_rd_ia32_LdTls(dbg, irg, blk, get_irn_mode(irn));
850 * Transforms the standard firm graph into
853 static void ia32_prepare_graph(void *self) {
854 ia32_code_gen_t *cg = self;
855 dom_front_info_t *dom;
856 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
858 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
860 /* 1st: transform constants and psi condition trees */
861 ia32_pre_transform_phase(cg);
863 /* 2nd: transform all remaining nodes */
864 ia32_register_transformers();
865 dom = be_compute_dominance_frontiers(cg->irg);
867 cg->kill_conv = new_nodeset(5);
868 transform_tls(cg->irg);
869 edges_deactivate(cg->irg);
870 edges_activate(cg->irg);
871 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
873 del_nodeset(cg->kill_conv);
875 be_free_dominance_frontiers(dom);
878 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
880 /* 3rd: optimize address mode */
881 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
882 ia32_optimize_addressmode(cg);
885 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
887 DEBUG_ONLY(cg->mod = old_mod;)
891 * Dummy functions for hooks we don't need but which must be filled.
893 static void ia32_before_sched(void *self) {
896 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
899 ir_node *mem_proj = NULL;
904 mode = get_irn_mode(irn);
906 /* check if we already saw this node or the node has more than one user */
907 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) {
911 /* mark irn visited */
912 bitset_add_irn(already_visited, irn);
914 /* non-Tuple nodes with one user: ok, return */
915 if (get_irn_n_edges(irn) >= 1 && mode != mode_T) {
919 /* tuple node has one user which is not the mem proj-> ok */
920 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
921 mem_proj = ia32_get_proj_for_mode(irn, mode_M);
922 if (mem_proj == NULL) {
927 arity = get_irn_arity(irn);
928 for (i = 0; i < arity; ++i) {
929 ir_node *pred = get_irn_n(irn, i);
931 /* do not follow memory edges or we will accidentally remove stores */
932 if (get_irn_mode(pred) == mode_M) {
933 if(mem_proj != NULL) {
934 edges_reroute(mem_proj, pred, get_irn_irg(mem_proj));
940 set_irn_n(irn, i, new_Bad());
943 The current node is about to be removed: if the predecessor
944 has only this node as user, it need to be removed as well.
946 if (get_irn_n_edges(pred) <= 1)
947 remove_unused_nodes(pred, already_visited);
950 // we need to set the presd to Bad again to also get the memory edges
951 arity = get_irn_arity(irn);
952 for (i = 0; i < arity; ++i) {
953 set_irn_n(irn, i, new_Bad());
956 if (sched_is_scheduled(irn)) {
961 static void remove_unused_loads_walker(ir_node *irn, void *env) {
962 bitset_t *already_visited = env;
963 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
964 remove_unused_nodes(irn, env);
968 * Called before the register allocator.
969 * Calculate a block schedule here. We need it for the x87
970 * simulator and the emitter.
972 static void ia32_before_ra(void *self) {
973 ia32_code_gen_t *cg = self;
974 bitset_t *already_visited = bitset_irg_alloca(cg->irg);
978 There are sometimes unused loads, only pinned by memory.
979 We need to remove those Loads and all other nodes which won't be used
980 after removing the Load from schedule.
982 irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
987 * Transforms a be node into a Load.
989 static void transform_to_Load(ia32_transform_env_t *env) {
990 ir_node *irn = env->irn;
991 entity *ent = be_get_frame_entity(irn);
992 ir_mode *mode = env->mode;
993 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
994 ir_node *nomem = new_rd_NoMem(env->irg);
995 ir_node *sched_point = NULL;
996 ir_node *ptr = get_irn_n(irn, 0);
997 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
998 ir_node *new_op, *proj;
999 const arch_register_t *reg;
1001 if (sched_is_scheduled(irn)) {
1002 sched_point = sched_prev(irn);
1005 if (mode_is_float(mode)) {
1006 if (USE_SSE2(env->cg))
1007 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1009 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1012 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1014 set_ia32_am_support(new_op, ia32_am_Source);
1015 set_ia32_op_type(new_op, ia32_AddrModeS);
1016 set_ia32_am_flavour(new_op, ia32_B);
1017 set_ia32_ls_mode(new_op, mode);
1018 set_ia32_frame_ent(new_op, ent);
1019 set_ia32_use_frame(new_op);
1021 DBG_OPT_RELOAD2LD(irn, new_op);
1023 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1026 sched_add_after(sched_point, new_op);
1027 sched_add_after(new_op, proj);
1032 /* copy the register from the old node to the new Load */
1033 reg = arch_get_irn_register(env->cg->arch_env, irn);
1034 arch_set_irn_register(env->cg->arch_env, new_op, reg);
1036 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
1038 exchange(irn, proj);
1042 * Transforms a be node into a Store.
1044 static void transform_to_Store(ia32_transform_env_t *env) {
1045 ir_node *irn = env->irn;
1046 entity *ent = be_get_frame_entity(irn);
1047 ir_mode *mode = env->mode;
1048 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1049 ir_node *nomem = new_rd_NoMem(env->irg);
1050 ir_node *ptr = get_irn_n(irn, 0);
1051 ir_node *val = get_irn_n(irn, 1);
1052 ir_node *new_op, *proj;
1053 ir_node *sched_point = NULL;
1055 if (sched_is_scheduled(irn)) {
1056 sched_point = sched_prev(irn);
1059 if (mode_is_float(mode)) {
1060 if (USE_SSE2(env->cg))
1061 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1063 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1065 else if (get_mode_size_bits(mode) == 8) {
1066 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1069 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1072 set_ia32_am_support(new_op, ia32_am_Dest);
1073 set_ia32_op_type(new_op, ia32_AddrModeD);
1074 set_ia32_am_flavour(new_op, ia32_B);
1075 set_ia32_ls_mode(new_op, mode);
1076 set_ia32_frame_ent(new_op, ent);
1077 set_ia32_use_frame(new_op);
1079 DBG_OPT_SPILL2ST(irn, new_op);
1081 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
1084 sched_add_after(sched_point, new_op);
1088 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
1090 exchange(irn, proj);
1093 static ir_node *create_push(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, ir_node *mem, entity *ent) {
1094 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1095 ir_node *frame = get_irg_frame(env->irg);
1097 ir_node *push = new_rd_ia32_Push(env->dbg, env->irg, env->block, frame, noreg, noreg, sp, mem);
1099 set_ia32_frame_ent(push, ent);
1100 set_ia32_use_frame(push);
1101 set_ia32_op_type(push, ia32_AddrModeS);
1102 set_ia32_am_flavour(push, ia32_B);
1103 set_ia32_ls_mode(push, mode_Is);
1105 sched_add_before(schedpoint, push);
1109 static ir_node *create_pop(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, entity *ent) {
1110 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1111 ir_node *frame = get_irg_frame(env->irg);
1113 ir_node *pop = new_rd_ia32_Pop(env->dbg, env->irg, env->block, frame, noreg, sp, new_NoMem());
1115 set_ia32_frame_ent(pop, ent);
1116 set_ia32_use_frame(pop);
1117 set_ia32_op_type(pop, ia32_AddrModeD);
1118 set_ia32_am_flavour(pop, ia32_B);
1119 set_ia32_ls_mode(pop, mode_Is);
1121 sched_add_before(schedpoint, pop);
1126 static ir_node* create_spproj(ia32_transform_env_t *env, ir_node *pred, int pos, ir_node *schedpoint) {
1127 ir_mode *spmode = mode_Iu;
1128 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1131 sp = new_rd_Proj(env->dbg, env->irg, env->block, pred, spmode, pos);
1132 arch_set_irn_register(env->cg->arch_env, sp, spreg);
1133 sched_add_before(schedpoint, sp);
1139 * Transform memperm, currently we do this the ugly way and produce
1140 * push/pop into/from memory cascades. This is possible without using
1143 static void transform_MemPerm(ia32_transform_env_t *env) {
1144 ir_node *node = env->irn;
1146 ir_node *sp = be_abi_get_ignore_irn(env->cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1147 const ir_edge_t *edge;
1148 const ir_edge_t *next;
1151 arity = be_get_MemPerm_entity_arity(node);
1152 pops = alloca(arity * sizeof(pops[0]));
1155 for(i = 0; i < arity; ++i) {
1156 entity *ent = be_get_MemPerm_in_entity(node, i);
1157 ir_type *enttype = get_entity_type(ent);
1158 int entbits = get_type_size_bits(enttype);
1159 ir_node *mem = get_irn_n(node, i + 1);
1162 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1164 push = create_push(env, node, sp, mem, ent);
1165 sp = create_spproj(env, push, 0, node);
1167 // add another push after the first one
1168 push = create_push(env, node, sp, mem, ent);
1169 add_ia32_am_offs_int(push, 4);
1170 sp = create_spproj(env, push, 0, node);
1173 set_irn_n(node, i, new_Bad());
1177 for(i = arity - 1; i >= 0; --i) {
1178 entity *ent = be_get_MemPerm_out_entity(node, i);
1179 ir_type *enttype = get_entity_type(ent);
1180 int entbits = get_type_size_bits(enttype);
1184 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1186 pop = create_pop(env, node, sp, ent);
1188 // add another pop after the first one
1189 sp = create_spproj(env, pop, 1, node);
1190 pop = create_pop(env, node, sp, ent);
1191 add_ia32_am_offs_int(pop, 4);
1193 sp = create_spproj(env, pop, 1, node);
1198 // exchange memprojs
1199 foreach_out_edge_safe(node, edge, next) {
1200 ir_node *proj = get_edge_src_irn(edge);
1201 int p = get_Proj_proj(proj);
1205 set_Proj_pred(proj, pops[p]);
1206 set_Proj_proj(proj, 3);
1210 arity = get_irn_arity(node);
1211 for(i = 0; i < arity; ++i) {
1212 set_irn_n(node, i, new_Bad());
1218 * Fix the mode of Spill/Reload
1220 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
1222 if (mode_is_float(mode)) {
1234 * Block-Walker: Calls the transform functions Spill and Reload.
1236 static void ia32_after_ra_walker(ir_node *block, void *env) {
1237 ir_node *node, *prev;
1238 ia32_code_gen_t *cg = env;
1239 ia32_transform_env_t tenv;
1242 tenv.irg = current_ir_graph;
1244 DEBUG_ONLY(tenv.mod = cg->mod;)
1246 /* beware: the schedule is changed here */
1247 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1248 prev = sched_prev(node);
1249 if (be_is_Reload(node)) {
1250 /* we always reload the whole register */
1251 tenv.dbg = get_irn_dbg_info(node);
1253 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
1254 transform_to_Load(&tenv);
1256 else if (be_is_Spill(node)) {
1257 ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1258 /* we always spill the whole register */
1259 tenv.dbg = get_irn_dbg_info(node);
1261 tenv.mode = fix_spill_mode(cg, get_irn_mode(spillval));
1262 transform_to_Store(&tenv);
1264 else if(be_is_MemPerm(node)) {
1265 tenv.dbg = get_irn_dbg_info(node);
1267 transform_MemPerm(&tenv);
1273 * We transform Spill and Reload here. This needs to be done before
1274 * stack biasing otherwise we would miss the corrected offset for these nodes.
1276 * If x87 instruction should be emitted, run the x87 simulator and patch
1277 * the virtual instructions. This must obviously be done after register allocation.
1279 static void ia32_after_ra(void *self) {
1280 ia32_code_gen_t *cg = self;
1281 ir_graph *irg = cg->irg;
1283 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1285 ia32_finish_irg(irg, cg);
1289 * Last touchups for the graph before emit
1291 static void ia32_finish(void *self) {
1292 ia32_code_gen_t *cg = self;
1293 ir_graph *irg = cg->irg;
1295 //be_remove_empty_blocks(irg);
1296 cg->blk_sched = be_create_block_schedule(irg, cg->birg->execfreqs);
1298 //cg->blk_sched = sched_create_block_schedule(cg->irg, cg->birg->execfreqs);
1300 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1301 if (cg->used_fp == fp_x87 || cg->force_sim) {
1302 x87_simulate_graph(cg->arch_env, irg, cg->blk_sched);
1305 ia32_peephole_optimization(irg, cg);
1309 * Emits the code, closes the output file and frees
1310 * the code generator interface.
1312 static void ia32_codegen(void *self) {
1313 ia32_code_gen_t *cg = self;
1314 ir_graph *irg = cg->irg;
1316 ia32_gen_routine(cg->isa->out, irg, cg);
1320 /* remove it from the isa */
1323 /* de-allocate code generator */
1324 del_set(cg->reg_set);
1328 static void *ia32_cg_init(const be_irg_t *birg);
1330 static const arch_code_generator_if_t ia32_code_gen_if = {
1332 NULL, /* before abi introduce hook */
1334 ia32_before_sched, /* before scheduling hook */
1335 ia32_before_ra, /* before register allocation hook */
1336 ia32_after_ra, /* after register allocation hook */
1337 ia32_finish, /* called before codegen */
1338 ia32_codegen /* emit && done */
1342 * Initializes a IA32 code generator.
1344 static void *ia32_cg_init(const be_irg_t *birg) {
1345 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1346 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1348 cg->impl = &ia32_code_gen_if;
1349 cg->irg = birg->irg;
1350 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1351 cg->arch_env = birg->main_env->arch_env;
1354 cg->blk_sched = NULL;
1355 cg->fp_to_gp = NULL;
1356 cg->gp_to_fp = NULL;
1357 cg->fp_kind = isa->fp_kind;
1358 cg->used_fp = fp_none;
1359 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1361 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1363 /* copy optimizations from isa for easier access */
1365 cg->arch = isa->arch;
1366 cg->opt_arch = isa->opt_arch;
1372 if (isa->name_obst) {
1373 obstack_free(isa->name_obst, NULL);
1374 obstack_init(isa->name_obst);
1378 cur_reg_set = cg->reg_set;
1380 ia32_irn_ops.cg = cg;
1382 return (arch_code_generator_t *)cg;
1387 /*****************************************************************
1388 * ____ _ _ _____ _____
1389 * | _ \ | | | | |_ _|/ ____| /\
1390 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1391 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1392 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1393 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1395 *****************************************************************/
1398 * Set output modes for GCC
1400 static const tarval_mode_info mo_integer = {
1407 * set the tarval output mode of all integer modes to decimal
1409 static void set_tarval_output_modes(void)
1413 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1414 ir_mode *mode = get_irp_mode(i);
1416 if (mode_is_int(mode))
1417 set_tarval_mode_output_option(mode, &mo_integer);
1423 * The template that generates a new ISA object.
1424 * Note that this template can be changed by command line
1427 static ia32_isa_t ia32_isa_template = {
1429 &ia32_isa_if, /* isa interface implementation */
1430 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1431 &ia32_gp_regs[REG_EBP], /* base pointer register */
1432 -1, /* stack direction */
1433 NULL, /* main environment */
1435 NULL, /* 16bit register names */
1436 NULL, /* 8bit register names */
1440 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1441 IA32_OPT_DOAM | /* optimize address mode default: on */
1442 IA32_OPT_LEA | /* optimize for LEAs default: on */
1443 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1444 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1445 IA32_OPT_EXTBB | /* use extended basic block scheduling, default: on */
1446 IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
1447 arch_pentium_4, /* instruction architecture */
1448 arch_pentium_4, /* optimize for architecture */
1449 fp_sse2, /* use sse2 unit */
1450 NULL, /* current code generator */
1451 NULL, /* output file */
1453 NULL, /* name obstack */
1454 0 /* name obst size */
1459 * Initializes the backend ISA.
1461 static void *ia32_init(FILE *file_handle) {
1462 static int inited = 0;
1468 set_tarval_output_modes();
1470 isa = xmalloc(sizeof(*isa));
1471 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1473 ia32_register_init(isa);
1474 ia32_create_opcodes();
1476 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1477 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1478 /* no SSE2 for these cpu's */
1479 isa->fp_kind = fp_x87;
1481 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1482 /* Pentium 4 don't like inc and dec instructions */
1483 isa->opt &= ~IA32_OPT_INCDEC;
1486 isa->regs_16bit = pmap_create();
1487 isa->regs_8bit = pmap_create();
1488 isa->types = pmap_create();
1489 isa->tv_ent = pmap_create();
1490 isa->out = file_handle;
1491 isa->cpu = ia32_init_machine_description();
1493 ia32_build_16bit_reg_map(isa->regs_16bit);
1494 ia32_build_8bit_reg_map(isa->regs_8bit);
1496 /* patch register names of x87 registers */
1497 ia32_st_regs[0].name = "st";
1498 ia32_st_regs[1].name = "st(1)";
1499 ia32_st_regs[2].name = "st(2)";
1500 ia32_st_regs[3].name = "st(3)";
1501 ia32_st_regs[4].name = "st(4)";
1502 ia32_st_regs[5].name = "st(5)";
1503 ia32_st_regs[6].name = "st(6)";
1504 ia32_st_regs[7].name = "st(7)";
1507 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1508 obstack_init(isa->name_obst);
1511 ia32_handle_intrinsics();
1512 ia32_switch_section(isa->out, NO_SECTION);
1513 fprintf(isa->out, "\t.intel_syntax\n");
1515 /* needed for the debug support */
1516 ia32_switch_section(isa->out, SECTION_TEXT);
1517 fprintf(isa->out, ".Ltext0:\n");
1527 * Closes the output file and frees the ISA structure.
1529 static void ia32_done(void *self) {
1530 ia32_isa_t *isa = self;
1532 /* emit now all global declarations */
1533 ia32_gen_decls(isa->out, isa->arch_isa.main_env);
1535 pmap_destroy(isa->regs_16bit);
1536 pmap_destroy(isa->regs_8bit);
1537 pmap_destroy(isa->tv_ent);
1538 pmap_destroy(isa->types);
1541 obstack_free(isa->name_obst, NULL);
1549 * Return the number of register classes for this architecture.
1550 * We report always these:
1551 * - the general purpose registers
1552 * - the SSE floating point register set
1553 * - the virtual floating point registers
1555 static int ia32_get_n_reg_class(const void *self) {
1560 * Return the register class for index i.
1562 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1563 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1565 return &ia32_reg_classes[CLASS_ia32_gp];
1567 return &ia32_reg_classes[CLASS_ia32_xmm];
1569 return &ia32_reg_classes[CLASS_ia32_vfp];
1573 * Get the register class which shall be used to store a value of a given mode.
1574 * @param self The this pointer.
1575 * @param mode The mode in question.
1576 * @return A register class which can hold values of the given mode.
1578 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1579 const ia32_isa_t *isa = self;
1580 if (mode_is_float(mode)) {
1581 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1584 return &ia32_reg_classes[CLASS_ia32_gp];
1588 * Get the ABI restrictions for procedure calls.
1589 * @param self The this pointer.
1590 * @param method_type The type of the method (procedure) in question.
1591 * @param abi The abi object to be modified
1593 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1594 const ia32_isa_t *isa = self;
1597 unsigned cc = get_method_calling_convention(method_type);
1598 int n = get_method_n_params(method_type);
1601 int i, ignore_1, ignore_2;
1603 const arch_register_t *reg;
1604 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1606 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1608 /* set abi flags for calls */
1609 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1610 call_flags.bits.store_args_sequential = use_push;
1611 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1612 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1613 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1615 /* set stack parameter passing style */
1616 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1618 /* collect the mode for each type */
1619 modes = alloca(n * sizeof(modes[0]));
1621 for (i = 0; i < n; i++) {
1622 tp = get_method_param_type(method_type, i);
1623 modes[i] = get_type_mode(tp);
1626 /* set register parameters */
1627 if (cc & cc_reg_param) {
1628 /* determine the number of parameters passed via registers */
1629 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1631 /* loop over all parameters and set the register requirements */
1632 for (i = 0; i <= biggest_n; i++) {
1633 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1634 assert(reg && "kaputt");
1635 be_abi_call_param_reg(abi, i, reg);
1642 /* set stack parameters */
1643 for (i = stack_idx; i < n; i++) {
1644 /* parameters on the stack are 32 bit aligned */
1645 be_abi_call_param_stack(abi, i, 4, 0, 0);
1649 /* set return registers */
1650 n = get_method_n_ress(method_type);
1652 assert(n <= 2 && "more than two results not supported");
1654 /* In case of 64bit returns, we will have two 32bit values */
1656 tp = get_method_res_type(method_type, 0);
1657 mode = get_type_mode(tp);
1659 assert(!mode_is_float(mode) && "two FP results not supported");
1661 tp = get_method_res_type(method_type, 1);
1662 mode = get_type_mode(tp);
1664 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1666 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1667 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1670 const arch_register_t *reg;
1672 tp = get_method_res_type(method_type, 0);
1673 assert(is_atomic_type(tp));
1674 mode = get_type_mode(tp);
1676 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1678 be_abi_call_res_reg(abi, 0, reg);
1683 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1684 return &ia32_irn_ops;
1687 const arch_irn_handler_t ia32_irn_handler = {
1691 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1692 return &ia32_irn_handler;
1695 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1696 return is_ia32_irn(irn) ? 1 : -1;
1700 * Initializes the code generator interface.
1702 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1703 return &ia32_code_gen_if;
1707 * Returns the estimated execution time of an ia32 irn.
1709 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1710 const arch_env_t *arch_env = env;
1711 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1714 list_sched_selector_t ia32_sched_selector;
1717 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1719 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1720 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1721 ia32_sched_selector.exectime = ia32_sched_exectime;
1722 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1723 return &ia32_sched_selector;
1726 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self) {
1731 * Returns the necessary byte alignment for storing a register of given class.
1733 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1734 ir_mode *mode = arch_register_class_mode(cls);
1735 int bytes = get_mode_size_bytes(mode);
1737 if (mode_is_float(mode) && bytes > 8)
1742 static const be_execution_unit_t ***ia32_get_allowed_execution_units(const void *self, const ir_node *irn) {
1743 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1744 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1745 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1748 static const be_execution_unit_t *_allowed_units_ALU[] = {
1749 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU1],
1750 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU2],
1751 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU3],
1752 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU4],
1755 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1756 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY1],
1757 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY2],
1758 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY3],
1759 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY4],
1762 static const be_execution_unit_t **_units_callret[] = {
1763 _allowed_units_BRANCH,
1766 static const be_execution_unit_t **_units_other[] = {
1770 static const be_execution_unit_t **_units_dummy[] = {
1771 _allowed_units_DUMMY,
1774 const be_execution_unit_t ***ret;
1776 if (is_ia32_irn(irn)) {
1777 ret = get_ia32_exec_units(irn);
1779 else if (is_be_node(irn)) {
1780 if (be_is_Call(irn) || be_is_Return(irn)) {
1781 ret = _units_callret;
1783 else if (be_is_Barrier(irn)) {
1798 * Return the abstract ia32 machine.
1800 static const be_machine_t *ia32_get_machine(const void *self) {
1801 const ia32_isa_t *isa = self;
1806 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1807 * @return 1 if allowed, 0 otherwise
1809 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
1811 ir_node *cmp, *cmp_a, *phi;
1814 /* we don't want long long an floating point Psi */
1815 #define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
1817 if (get_irn_mode(sel) != mode_b)
1820 cmp = get_Proj_pred(sel);
1821 cmp_a = get_Cmp_left(cmp);
1822 mode = get_irn_mode(cmp_a);
1824 if (IS_BAD_PSI_MODE(mode))
1827 /* check the Phi nodes */
1828 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1829 ir_node *pred_i = get_irn_n(phi, i);
1830 ir_node *pred_j = get_irn_n(phi, j);
1831 ir_mode *mode_i = get_irn_mode(pred_i);
1832 ir_mode *mode_j = get_irn_mode(pred_j);
1834 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1838 #undef IS_BAD_PSI_MODE
1843 static ia32_intrinsic_env_t intrinsic_env = {
1844 NULL, /**< the irg, these entities belong to */
1845 NULL, /**< entity for first div operand (move into FPU) */
1846 NULL, /**< entity for second div operand (move into FPU) */
1847 NULL, /**< entity for converts ll -> d */
1848 NULL, /**< entity for converts d -> ll */
1852 * Returns the libFirm configuration parameter for this backend.
1854 static const backend_params *ia32_get_libfirm_params(void) {
1855 static const opt_if_conv_info_t ifconv = {
1856 4, /* maxdepth, doesn't matter for Psi-conversion */
1857 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
1859 static const arch_dep_params_t ad = {
1860 1, /* also use subs */
1861 4, /* maximum shifts */
1862 31, /* maximum shift amount */
1864 1, /* allow Mulhs */
1865 1, /* allow Mulus */
1866 32 /* Mulh allowed up to 32 bit */
1868 static backend_params p = {
1869 NULL, /* no additional opcodes */
1870 NULL, /* will be set later */
1871 1, /* need dword lowering */
1872 ia32_create_intrinsic_fkt,
1873 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1874 NULL, /* will be set later */
1878 p.if_conv_info = &ifconv;
1883 /* instruction set architectures. */
1884 static const lc_opt_enum_int_items_t arch_items[] = {
1885 { "386", arch_i386, },
1886 { "486", arch_i486, },
1887 { "pentium", arch_pentium, },
1888 { "586", arch_pentium, },
1889 { "pentiumpro", arch_pentium_pro, },
1890 { "686", arch_pentium_pro, },
1891 { "pentiummmx", arch_pentium_mmx, },
1892 { "pentium2", arch_pentium_2, },
1893 { "p2", arch_pentium_2, },
1894 { "pentium3", arch_pentium_3, },
1895 { "p3", arch_pentium_3, },
1896 { "pentium4", arch_pentium_4, },
1897 { "p4", arch_pentium_4, },
1898 { "pentiumm", arch_pentium_m, },
1899 { "pm", arch_pentium_m, },
1900 { "core", arch_core, },
1902 { "athlon", arch_athlon, },
1903 { "athlon64", arch_athlon_64, },
1904 { "opteron", arch_opteron, },
1908 static lc_opt_enum_int_var_t arch_var = {
1909 &ia32_isa_template.arch, arch_items
1912 static lc_opt_enum_int_var_t opt_arch_var = {
1913 &ia32_isa_template.opt_arch, arch_items
1916 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1918 { "sse2", fp_sse2 },
1922 static lc_opt_enum_int_var_t fp_unit_var = {
1923 &ia32_isa_template.fp_kind, fp_unit_items
1926 static const lc_opt_enum_int_items_t gas_items[] = {
1927 { "linux", ASM_LINUX_GAS },
1928 { "mingw", ASM_MINGW_GAS },
1932 static lc_opt_enum_int_var_t gas_var = {
1933 (int *)&asm_flavour, gas_items
1936 static const lc_opt_table_entry_t ia32_options[] = {
1937 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1938 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1939 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1940 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1941 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
1942 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1943 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1944 LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
1945 LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
1946 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
1951 * Register command line options for the ia32 backend.
1955 * ia32-arch=arch create instruction for arch
1956 * ia32-opt=arch optimize for run on arch
1957 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1958 * ia32-incdec optimize for inc/dec
1959 * ia32-noaddrmode do not use address mode
1960 * ia32-nolea do not optimize for LEAs
1961 * ia32-noplacecnst do not place constants,
1962 * ia32-noimmop no operations with immediates
1963 * ia32-noextbb do not use extended basic block scheduling
1964 * ia32-nopushargs do not create pushs for function argument passing
1965 * ia32-gasmode set the GAS compatibility mode
1967 static void ia32_register_options(lc_opt_entry_t *ent)
1969 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1970 lc_opt_add_table(be_grp_ia32, ia32_options);
1972 #endif /* WITH_LIBCORE */
1974 const arch_isa_if_t ia32_isa_if = {
1977 ia32_get_n_reg_class,
1979 ia32_get_reg_class_for_mode,
1981 ia32_get_irn_handler,
1982 ia32_get_code_generator_if,
1983 ia32_get_list_sched_selector,
1984 ia32_get_ilp_sched_selector,
1985 ia32_get_reg_class_alignment,
1986 ia32_get_libfirm_params,
1987 ia32_get_allowed_execution_units,
1990 ia32_register_options