2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
24 #include "pseudo_irg.h"
28 #include "iredges_t.h"
36 #include "../beabi.h" /* the general register allocator interface */
37 #include "../benode_t.h"
38 #include "../belower.h"
39 #include "../besched_t.h"
41 #include "bearch_ia32_t.h"
43 #include "ia32_new_nodes.h" /* ia32 nodes interface */
44 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
45 #include "ia32_gen_decls.h" /* interface declaration emitter */
46 #include "ia32_transform.h"
47 #include "ia32_emitter.h"
48 #include "ia32_map_regs.h"
49 #include "ia32_optimize.h"
51 #include "ia32_dbg_stat.h"
52 #include "ia32_finish.h"
53 #include "ia32_util.h"
55 #define DEBUG_MODULE "firm.be.ia32.isa"
58 static set *cur_reg_set = NULL;
61 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
63 /* Creates the unique per irg GP NoReg node. */
64 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
65 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
68 /* Creates the unique per irg FP NoReg node. */
69 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
70 return be_abi_get_callee_save_irn(cg->birg->abi,
71 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
74 /**************************************************
77 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
78 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
79 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
80 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
83 **************************************************/
85 static ir_node *my_skip_proj(const ir_node *n) {
93 * Return register requirements for an ia32 node.
94 * If the node returns a tuple (mode_T) then the proj's
95 * will be asked for this information.
97 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
98 const ia32_irn_ops_t *ops = self;
99 const ia32_register_req_t *irn_req;
100 long node_pos = pos == -1 ? 0 : pos;
101 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
102 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
104 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
105 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
109 if (mode == mode_T && pos < 0) {
110 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
114 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
118 node_pos = ia32_translate_proj_pos(irn);
124 irn = my_skip_proj(irn);
126 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
129 if (is_ia32_irn(irn)) {
131 irn_req = get_ia32_in_req(irn, pos);
134 irn_req = get_ia32_out_req(irn, node_pos);
137 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
139 memcpy(req, &(irn_req->req), sizeof(*req));
141 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
142 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
143 req->other_same = get_irn_n(irn, irn_req->same_pos);
146 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
147 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
148 req->other_different = get_irn_n(irn, irn_req->different_pos);
152 /* treat Unknowns like Const with default requirements */
153 if (is_Unknown(irn)) {
154 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
155 if (mode_is_float(mode)) {
156 if (USE_SSE2(ops->cg))
157 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
159 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
161 else if (mode_is_int(mode) || mode_is_reference(mode))
162 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
163 else if (mode == mode_T || mode == mode_M) {
164 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
168 assert(0 && "unsupported Unknown-Mode");
171 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
179 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
181 const ia32_irn_ops_t *ops = self;
183 if (get_irn_mode(irn) == mode_X) {
187 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
190 pos = ia32_translate_proj_pos(irn);
191 irn = my_skip_proj(irn);
194 if (is_ia32_irn(irn)) {
195 const arch_register_t **slots;
197 slots = get_ia32_slots(irn);
201 ia32_set_firm_reg(irn, reg, cur_reg_set);
205 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
207 const arch_register_t *reg = NULL;
211 if (get_irn_mode(irn) == mode_X) {
215 pos = ia32_translate_proj_pos(irn);
216 irn = my_skip_proj(irn);
219 if (is_ia32_irn(irn)) {
220 const arch_register_t **slots;
221 slots = get_ia32_slots(irn);
225 reg = ia32_get_firm_reg(irn, cur_reg_set);
231 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
232 arch_irn_class_t classification = arch_irn_class_normal;
234 irn = my_skip_proj(irn);
237 classification |= arch_irn_class_branch;
239 if (! is_ia32_irn(irn))
240 return classification & ~arch_irn_class_normal;
242 if (is_ia32_Cnst(irn))
243 classification |= arch_irn_class_const;
246 classification |= arch_irn_class_load;
248 if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
249 classification |= arch_irn_class_store;
251 if (is_ia32_got_reload(irn))
252 classification |= arch_irn_class_reload;
254 return classification;
257 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
258 irn = my_skip_proj(irn);
259 if (is_ia32_irn(irn))
260 return get_ia32_flags(irn);
263 return arch_irn_flags_ignore;
268 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
269 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
272 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
274 const ia32_irn_ops_t *ops = self;
276 if (get_ia32_frame_ent(irn)) {
277 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
279 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
280 snprintf(buf, sizeof(buf), "%d", bias);
282 if (get_ia32_op_type(irn) == ia32_Normal) {
283 set_ia32_cnst(irn, buf);
286 add_ia32_am_offs(irn, buf);
288 set_ia32_am_flavour(irn, am_flav);
294 be_abi_call_flags_bits_t flags;
295 const arch_isa_t *isa;
296 const arch_env_t *aenv;
300 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
302 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
303 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
304 env->flags = fl.bits;
307 env->isa = aenv->isa;
312 * Put all registers which are saved by the prologue/epilogue in a set.
314 * @param self The callback object.
315 * @param s The result set.
317 static void ia32_abi_dont_save_regs(void *self, pset *s)
319 ia32_abi_env_t *env = self;
320 if(env->flags.try_omit_fp)
321 pset_insert_ptr(s, env->isa->bp);
325 * Generate the routine prologue.
327 * @param self The callback object.
328 * @param mem A pointer to the mem node. Update this if you define new memory.
329 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
331 * @return The register which shall be used as a stack frame base.
333 * All nodes which define registers in @p reg_map must keep @p reg_map current.
335 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
337 ia32_abi_env_t *env = self;
339 if (!env->flags.try_omit_fp) {
340 ir_node *bl = get_irg_start_block(env->irg);
341 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
342 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
346 push = new_rd_ia32_Push(NULL, env->irg, bl, curr_sp, curr_bp, *mem);
347 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
348 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
350 /* the push must have SP out register */
351 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
352 set_ia32_flags(push, arch_irn_flags_ignore);
354 /* move esp to ebp */
355 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
356 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
357 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
358 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
360 /* beware: the copy must be done before any other sp use */
361 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
362 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
363 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
364 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
366 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
367 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
376 * Generate the routine epilogue.
377 * @param self The callback object.
378 * @param bl The block for the epilog
379 * @param mem A pointer to the mem node. Update this if you define new memory.
380 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
381 * @return The register which shall be used as a stack frame base.
383 * All nodes which define registers in @p reg_map must keep @p reg_map current.
385 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
387 ia32_abi_env_t *env = self;
388 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
389 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
391 if (env->flags.try_omit_fp) {
392 /* simply remove the stack frame here */
393 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
396 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
397 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
399 /* gcc always emits a leave at the end of a routine */
400 if (1 || ARCH_AMD(isa->opt_arch)) {
404 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, *mem);
405 set_ia32_flags(leave, arch_irn_flags_ignore);
406 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
407 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
408 *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
413 /* copy ebp to esp */
414 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
417 pop = new_rd_ia32_Pop(NULL, env->irg, bl, curr_sp, *mem);
418 set_ia32_flags(pop, arch_irn_flags_ignore);
419 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
420 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
421 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
423 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
424 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
427 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
428 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
432 * Produces the type which sits between the stack args and the locals on the stack.
433 * it will contain the return address and space to store the old base pointer.
434 * @return The Firm type modeling the ABI between type.
436 static ir_type *ia32_abi_get_between_type(void *self)
438 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
439 static ir_type *omit_fp_between_type = NULL;
440 static ir_type *between_type = NULL;
442 ia32_abi_env_t *env = self;
444 if ( !between_type) {
446 entity *ret_addr_ent;
447 entity *omit_fp_ret_addr_ent;
449 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_P);
450 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_P);
452 between_type = new_type_struct(IDENT("ia32_between_type"));
453 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
454 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
456 set_entity_offset_bytes(old_bp_ent, 0);
457 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
458 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
459 set_type_state(between_type, layout_fixed);
461 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
462 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
464 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
465 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
466 set_type_state(omit_fp_between_type, layout_fixed);
469 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
474 * Get the estimated cycle count for @p irn.
476 * @param self The this pointer.
477 * @param irn The node.
479 * @return The estimated cycle count for this operation
481 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
488 switch (get_ia32_irn_opcode(irn)) {
490 case iro_ia32_DivMod:
495 case iro_ia32_l_Load:
505 case iro_ia32_xStore:
506 case iro_ia32_l_Store:
508 case iro_ia32_Store8Bit:
516 case iro_ia32_l_MulS:
529 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
531 * @param irn The original operation
532 * @param i Index of the argument we want the inverse operation to yield
533 * @param inverse struct to be filled with the resulting inverse op
534 * @param obstack The obstack to use for allocation of the returned nodes array
535 * @return The inverse operation or NULL if operation invertible
537 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
540 ir_node *block, *noreg, *nomem;
543 /* we cannot invert non-ia32 irns */
544 if (! is_ia32_irn(irn))
547 /* operand must always be a real operand (not base, index or mem) */
548 if (i != 2 && i != 3)
551 /* we don't invert address mode operations */
552 if (get_ia32_op_type(irn) != ia32_Normal)
555 irg = get_irn_irg(irn);
556 block = get_nodes_block(irn);
557 mode = get_ia32_res_mode(irn);
558 noreg = get_irn_n(irn, 0);
559 nomem = new_r_NoMem(irg);
561 /* initialize structure */
562 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
566 switch (get_ia32_irn_opcode(irn)) {
568 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
569 /* we have an add with a const here */
570 /* invers == add with negated const */
571 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
572 pnc = pn_ia32_Add_res;
574 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
575 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
576 set_ia32_commutative(inverse->nodes[0]);
578 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
579 /* we have an add with a symconst here */
580 /* invers == sub with const */
581 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
582 pnc = pn_ia32_Sub_res;
584 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
587 /* normal add: inverse == sub */
588 ir_node *proj = ia32_get_res_proj(irn);
591 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, i ^ 1), nomem);
592 pnc = pn_ia32_Sub_res;
597 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
598 /* we have a sub with a const/symconst here */
599 /* invers == add with this const */
600 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
601 pnc = pn_ia32_Add_res;
602 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
603 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
607 ir_node *proj = ia32_get_res_proj(irn);
611 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, 3), nomem);
614 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, 2), proj, nomem);
616 pnc = pn_ia32_Sub_res;
621 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
622 /* xor with const: inverse = xor */
623 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
624 pnc = pn_ia32_Eor_res;
625 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
626 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
630 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, (ir_node *)irn, get_irn_n(irn, i), nomem);
631 pnc = pn_ia32_Eor_res;
636 ir_node *proj = ia32_get_res_proj(irn);
639 inverse->nodes[0] = new_rd_ia32_Not(NULL, irg, block, noreg, noreg, proj, nomem);
640 pnc = pn_ia32_Not_res;
644 case iro_ia32_Minus: {
645 ir_node *proj = ia32_get_res_proj(irn);
648 inverse->nodes[0] = new_rd_ia32_Minus(NULL, irg, block, noreg, noreg, proj, nomem);
649 pnc = pn_ia32_Minus_res;
654 /* inverse operation not supported */
658 set_ia32_res_mode(inverse->nodes[0], mode);
659 inverse->nodes[1] = new_r_Proj(irg, block, inverse->nodes[0], mode, pnc);
665 * Check if irn can load it's operand at position i from memory (source addressmode).
666 * @param self Pointer to irn ops itself
667 * @param irn The irn to be checked
668 * @param i The operands position
669 * @return Non-Zero if operand can be loaded
671 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
672 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
673 get_irn_arity(irn) != 5 || /* must be a binary operation */
674 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
675 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
676 (i != 2 && i != 3) || /* a "real" operand position must be requested */
677 (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
678 is_ia32_use_frame(irn)) /* must not already use frame */
684 static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *reload, unsigned int i) {
685 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
686 assert(get_nodes_block(reload) == get_nodes_block(irn) && "Reload must be in same block as irn.");
688 if (get_irn_n_edges(reload) > 1)
692 ir_node *tmp = get_irn_n(irn, 3);
693 set_irn_n(irn, 3, get_irn_n(irn, 2));
694 set_irn_n(irn, 2, tmp);
697 set_ia32_am_support(irn, ia32_am_Source);
698 set_ia32_op_type(irn, ia32_AddrModeS);
699 set_ia32_am_flavour(irn, ia32_B);
700 set_ia32_ls_mode(irn, get_irn_mode(reload));
701 set_ia32_frame_ent(irn, be_get_frame_entity(reload));
702 set_ia32_use_frame(irn);
703 set_ia32_got_reload(irn);
705 set_irn_n(irn, 0, be_get_Reload_frame(reload));
706 set_irn_n(irn, 4, be_get_Reload_mem(reload));
709 Input at position one is index register, which is NoReg.
710 We would need cg object to get a real noreg, but we cannot
713 set_irn_n(irn, 3, get_irn_n(irn, 1));
715 DBG_OPT_AM_S(reload, irn);
718 static const be_abi_callbacks_t ia32_abi_callbacks = {
721 ia32_abi_get_between_type,
722 ia32_abi_dont_save_regs,
727 /* fill register allocator interface */
729 static const arch_irn_ops_if_t ia32_irn_ops_if = {
730 ia32_get_irn_reg_req,
735 ia32_get_frame_entity,
738 ia32_get_op_estimated_cost,
739 ia32_possible_memory_operand,
740 ia32_perform_memory_operand,
743 ia32_irn_ops_t ia32_irn_ops = {
750 /**************************************************
753 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
754 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
755 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
756 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
759 **************************************************/
762 * Transforms the standard firm graph into
765 static void ia32_prepare_graph(void *self) {
766 ia32_code_gen_t *cg = self;
767 dom_front_info_t *dom;
768 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
770 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
772 /* 1st: transform constants and psi condition trees */
773 ia32_pre_transform_phase(cg);
775 /* 2nd: transform all remaining nodes */
776 ia32_register_transformers();
777 dom = be_compute_dominance_frontiers(cg->irg);
778 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
779 be_free_dominance_frontiers(dom);
782 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
784 /* 3rd: optimize address mode */
785 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
786 ia32_optimize_addressmode(cg);
789 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
791 DEBUG_ONLY(cg->mod = old_mod;)
795 * Dummy functions for hooks we don't need but which must be filled.
797 static void ia32_before_sched(void *self) {
800 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
808 mode = get_irn_mode(irn);
810 /* check if we already saw this node or the node has more than one user */
811 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1)
814 /* mark irn visited */
815 bitset_add_irn(already_visited, irn);
817 /* non-Tuple nodes with one user: ok, return */
818 if (get_irn_n_edges(irn) >= 1 && mode != mode_T)
821 /* tuple node has one user which is not the mem proj-> ok */
822 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
823 mem_proj = ia32_get_proj_for_mode(irn, mode_M);
828 for (i = get_irn_arity(irn) - 1; i >= 0; i--) {
829 ir_node *pred = get_irn_n(irn, i);
831 /* do not follow memory edges or we will accidentally remove stores */
832 if (is_Proj(pred) && get_irn_mode(pred) == mode_M)
835 set_irn_n(irn, i, new_Bad());
838 The current node is about to be removed: if the predecessor
839 has only this node as user, it need to be removed as well.
841 if (get_irn_n_edges(pred) <= 1)
842 remove_unused_nodes(pred, already_visited);
845 if (sched_is_scheduled(irn))
849 static void remove_unused_loads_walker(ir_node *irn, void *env) {
850 bitset_t *already_visited = env;
851 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
852 remove_unused_nodes(irn, env);
856 * Called before the register allocator.
857 * Calculate a block schedule here. We need it for the x87
858 * simulator and the emitter.
860 static void ia32_before_ra(void *self) {
861 ia32_code_gen_t *cg = self;
862 bitset_t *already_visited = bitset_irg_malloc(cg->irg);
864 cg->blk_sched = sched_create_block_schedule(cg->irg);
868 There are sometimes unused loads, only pinned by memory.
869 We need to remove those Loads and all other nodes which won't be used
870 after removing the Load from schedule.
872 irg_walk_graph(cg->irg, remove_unused_loads_walker, NULL, already_visited);
873 bitset_free(already_visited);
878 * Transforms a be node into a Load.
880 static void transform_to_Load(ia32_transform_env_t *env) {
881 ir_node *irn = env->irn;
882 entity *ent = be_get_frame_entity(irn);
883 ir_mode *mode = env->mode;
884 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
885 ir_node *nomem = new_rd_NoMem(env->irg);
886 ir_node *sched_point = NULL;
887 ir_node *ptr = get_irn_n(irn, 0);
888 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
889 ir_node *new_op, *proj;
890 const arch_register_t *reg;
892 if (sched_is_scheduled(irn)) {
893 sched_point = sched_prev(irn);
896 if (mode_is_float(mode)) {
897 if (USE_SSE2(env->cg))
898 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
900 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
903 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
906 set_ia32_am_support(new_op, ia32_am_Source);
907 set_ia32_op_type(new_op, ia32_AddrModeS);
908 set_ia32_am_flavour(new_op, ia32_B);
909 set_ia32_ls_mode(new_op, mode);
910 set_ia32_frame_ent(new_op, ent);
911 set_ia32_use_frame(new_op);
913 DBG_OPT_RELOAD2LD(irn, new_op);
915 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
918 sched_add_after(sched_point, new_op);
919 sched_add_after(new_op, proj);
924 /* copy the register from the old node to the new Load */
925 reg = arch_get_irn_register(env->cg->arch_env, irn);
926 arch_set_irn_register(env->cg->arch_env, new_op, reg);
928 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
934 * Transforms a be node into a Store.
936 static void transform_to_Store(ia32_transform_env_t *env) {
937 ir_node *irn = env->irn;
938 entity *ent = be_get_frame_entity(irn);
939 ir_mode *mode = env->mode;
940 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
941 ir_node *nomem = new_rd_NoMem(env->irg);
942 ir_node *ptr = get_irn_n(irn, 0);
943 ir_node *val = get_irn_n(irn, 1);
944 ir_node *new_op, *proj;
945 ir_node *sched_point = NULL;
947 if (sched_is_scheduled(irn)) {
948 sched_point = sched_prev(irn);
951 if (mode_is_float(mode)) {
952 if (USE_SSE2(env->cg))
953 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
955 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
957 else if (get_mode_size_bits(mode) == 8) {
958 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
961 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
964 set_ia32_am_support(new_op, ia32_am_Dest);
965 set_ia32_op_type(new_op, ia32_AddrModeD);
966 set_ia32_am_flavour(new_op, ia32_B);
967 set_ia32_ls_mode(new_op, mode);
968 set_ia32_frame_ent(new_op, ent);
969 set_ia32_use_frame(new_op);
971 DBG_OPT_SPILL2ST(irn, new_op);
973 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
976 sched_add_after(sched_point, new_op);
980 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
985 static ir_node *create_push(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, ir_node *mem, entity *ent, const char *offset) {
986 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
988 ir_node *push = new_rd_ia32_Push(env->dbg, env->irg, env->block, sp, noreg, mem);
990 set_ia32_frame_ent(push, ent);
991 set_ia32_use_frame(push);
992 set_ia32_op_type(push, ia32_AddrModeS);
993 set_ia32_am_flavour(push, ia32_B);
994 set_ia32_ls_mode(push, mode_Is);
996 add_ia32_am_offs(push, offset);
998 sched_add_before(schedpoint, push);
1002 static ir_node *create_pop(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, entity *ent, const char *offset) {
1003 ir_node *pop = new_rd_ia32_Pop(env->dbg, env->irg, env->block, sp, new_NoMem());
1005 set_ia32_frame_ent(pop, ent);
1006 set_ia32_use_frame(pop);
1007 set_ia32_op_type(pop, ia32_AddrModeD);
1008 set_ia32_am_flavour(pop, ia32_B);
1009 set_ia32_ls_mode(pop, mode_Is);
1011 add_ia32_am_offs(pop, offset);
1013 sched_add_before(schedpoint, pop);
1018 static ir_node* create_spproj(ia32_transform_env_t *env, ir_node *pred, ir_node *schedpoint, const ir_node *oldsp) {
1019 ir_mode *spmode = get_irn_mode(oldsp);
1020 const arch_register_t *spreg = arch_get_irn_register(env->cg->arch_env, oldsp);
1023 sp = new_rd_Proj(env->dbg, env->irg, env->block, pred, spmode, 0);
1024 arch_set_irn_register(env->cg->arch_env, sp, spreg);
1025 sched_add_before(schedpoint, sp);
1030 static void transform_MemPerm(ia32_transform_env_t *env) {
1032 * Transform memperm, currently we do this the ugly way and produce
1033 * push/pop into/from memory cascades. This is possible without using
1036 ir_node *node = env->irn;
1038 ir_node *sp = get_irn_n(node, 0);
1039 const ir_edge_t *edge;
1040 const ir_edge_t *next;
1043 arity = be_get_MemPerm_entity_arity(node);
1044 pops = alloca(arity * sizeof(pops[0]));
1047 for(i = 0; i < arity; ++i) {
1048 entity *ent = be_get_MemPerm_in_entity(node, i);
1049 ir_type *enttype = get_entity_type(ent);
1050 int entbits = get_type_size_bits(enttype);
1051 ir_node *mem = get_irn_n(node, i + 1);
1054 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1056 push = create_push(env, node, sp, mem, ent, NULL);
1057 sp = create_spproj(env, push, node, sp);
1059 // add another push after the first one
1060 push = create_push(env, node, sp, mem, ent, "4");
1061 sp = create_spproj(env, push, node, sp);
1064 set_irn_n(node, i, new_Bad());
1068 for(i = arity - 1; i >= 0; --i) {
1069 entity *ent = be_get_MemPerm_out_entity(node, i);
1070 ir_type *enttype = get_entity_type(ent);
1071 int entbits = get_type_size_bits(enttype);
1075 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1077 pop = create_pop(env, node, sp, ent, NULL);
1079 // add another pop after the first one
1080 sp = create_spproj(env, pop, node, sp);
1081 pop = create_pop(env, node, sp, ent, "4");
1084 sp = create_spproj(env, pop, node, sp);
1090 // exchange memprojs
1091 foreach_out_edge_safe(node, edge, next) {
1092 ir_node *proj = get_edge_src_irn(edge);
1093 int p = get_Proj_proj(proj);
1097 set_Proj_pred(proj, pops[p]);
1098 set_Proj_proj(proj, 3);
1105 * Fix the mode of Spill/Reload
1107 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
1109 if (mode_is_float(mode)) {
1121 * Block-Walker: Calls the transform functions Spill and Reload.
1123 static void ia32_after_ra_walker(ir_node *block, void *env) {
1124 ir_node *node, *prev;
1125 ia32_code_gen_t *cg = env;
1126 ia32_transform_env_t tenv;
1129 tenv.irg = current_ir_graph;
1131 DEBUG_ONLY(tenv.mod = cg->mod;)
1133 /* beware: the schedule is changed here */
1134 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1135 prev = sched_prev(node);
1136 if (be_is_Reload(node)) {
1137 /* we always reload the whole register */
1138 tenv.dbg = get_irn_dbg_info(node);
1140 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
1141 transform_to_Load(&tenv);
1143 else if (be_is_Spill(node)) {
1144 ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1145 /* we always spill the whole register */
1146 tenv.dbg = get_irn_dbg_info(node);
1148 tenv.mode = fix_spill_mode(cg, get_irn_mode(spillval));
1149 transform_to_Store(&tenv);
1151 else if(be_is_MemPerm(node)) {
1152 tenv.dbg = get_irn_dbg_info(node);
1154 transform_MemPerm(&tenv);
1160 * We transform Spill and Reload here. This needs to be done before
1161 * stack biasing otherwise we would miss the corrected offset for these nodes.
1163 * If x87 instruction should be emitted, run the x87 simulator and patch
1164 * the virtual instructions. This must obviously be done after register allocation.
1166 static void ia32_after_ra(void *self) {
1167 ia32_code_gen_t *cg = self;
1169 irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self);
1171 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1172 if (cg->used_fp == fp_x87 || cg->force_sim) {
1173 x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
1178 * Last touchups for the graph before emit
1180 static void ia32_finish(void *self) {
1181 ia32_code_gen_t *cg = self;
1182 ir_graph *irg = cg->irg;
1184 ia32_finish_irg(irg, cg);
1188 * Emits the code, closes the output file and frees
1189 * the code generator interface.
1191 static void ia32_codegen(void *self) {
1192 ia32_code_gen_t *cg = self;
1193 ir_graph *irg = cg->irg;
1195 ia32_gen_routine(cg->isa->out, irg, cg);
1199 /* remove it from the isa */
1202 /* de-allocate code generator */
1203 del_set(cg->reg_set);
1207 static void *ia32_cg_init(const be_irg_t *birg);
1209 static const arch_code_generator_if_t ia32_code_gen_if = {
1211 NULL, /* before abi introduce hook */
1213 ia32_before_sched, /* before scheduling hook */
1214 ia32_before_ra, /* before register allocation hook */
1215 ia32_after_ra, /* after register allocation hook */
1216 ia32_finish, /* called before codegen */
1217 ia32_codegen /* emit && done */
1221 * Initializes a IA32 code generator.
1223 static void *ia32_cg_init(const be_irg_t *birg) {
1224 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1225 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1227 cg->impl = &ia32_code_gen_if;
1228 cg->irg = birg->irg;
1229 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1230 cg->arch_env = birg->main_env->arch_env;
1233 cg->blk_sched = NULL;
1234 cg->fp_to_gp = NULL;
1235 cg->gp_to_fp = NULL;
1236 cg->fp_kind = isa->fp_kind;
1237 cg->used_fp = fp_none;
1238 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1240 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1242 /* copy optimizations from isa for easier access */
1244 cg->arch = isa->arch;
1245 cg->opt_arch = isa->opt_arch;
1251 if (isa->name_obst_size) {
1252 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
1253 isa->name_obst_size = 0;
1254 obstack_free(isa->name_obst, NULL);
1255 obstack_init(isa->name_obst);
1259 cur_reg_set = cg->reg_set;
1261 ia32_irn_ops.cg = cg;
1263 return (arch_code_generator_t *)cg;
1268 /*****************************************************************
1269 * ____ _ _ _____ _____
1270 * | _ \ | | | | |_ _|/ ____| /\
1271 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1272 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1273 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1274 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1276 *****************************************************************/
1279 * Set output modes for GCC
1281 static const tarval_mode_info mo_integer = {
1288 * set the tarval output mode to C-semantics
1290 static void set_tarval_output_modes(void)
1292 set_tarval_mode_output_option(get_modeLs(), &mo_integer);
1293 set_tarval_mode_output_option(get_modeLu(), &mo_integer);
1294 set_tarval_mode_output_option(get_modeIs(), &mo_integer);
1295 set_tarval_mode_output_option(get_modeIu(), &mo_integer);
1296 set_tarval_mode_output_option(get_modeHs(), &mo_integer);
1297 set_tarval_mode_output_option(get_modeHu(), &mo_integer);
1298 set_tarval_mode_output_option(get_modeBs(), &mo_integer);
1299 set_tarval_mode_output_option(get_modeBu(), &mo_integer);
1300 set_tarval_mode_output_option(get_modeC(), &mo_integer);
1301 set_tarval_mode_output_option(get_modeU(), &mo_integer);
1302 set_tarval_mode_output_option(get_modeIu(), &mo_integer);
1307 * The template that generates a new ISA object.
1308 * Note that this template can be changed by command line
1311 static ia32_isa_t ia32_isa_template = {
1313 &ia32_isa_if, /* isa interface implementation */
1314 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1315 &ia32_gp_regs[REG_EBP], /* base pointer register */
1316 -1, /* stack direction */
1318 NULL, /* 16bit register names */
1319 NULL, /* 8bit register names */
1323 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1324 IA32_OPT_DOAM | /* optimize address mode default: on */
1325 IA32_OPT_LEA | /* optimize for LEAs default: on */
1326 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1327 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1328 IA32_OPT_EXTBB), /* use extended basic block scheduling, default: on */
1329 arch_pentium_4, /* instruction architecture */
1330 arch_pentium_4, /* optimize for architecture */
1331 fp_sse2, /* use sse2 unit */
1332 NULL, /* current code generator */
1334 NULL, /* name obstack */
1335 0 /* name obst size */
1340 * Initializes the backend ISA.
1342 static void *ia32_init(FILE *file_handle) {
1343 static int inited = 0;
1349 set_tarval_output_modes();
1351 isa = xmalloc(sizeof(*isa));
1352 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1354 ia32_register_init(isa);
1355 ia32_create_opcodes();
1357 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1358 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1359 /* no SSE2 for these cpu's */
1360 isa->fp_kind = fp_x87;
1362 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1363 /* Pentium 4 don't like inc and dec instructions */
1364 isa->opt &= ~IA32_OPT_INCDEC;
1367 isa->regs_16bit = pmap_create();
1368 isa->regs_8bit = pmap_create();
1369 isa->types = pmap_create();
1370 isa->tv_ent = pmap_create();
1371 isa->out = file_handle;
1373 ia32_build_16bit_reg_map(isa->regs_16bit);
1374 ia32_build_8bit_reg_map(isa->regs_8bit);
1376 /* patch register names of x87 registers */
1378 ia32_st_regs[0].name = "st";
1379 ia32_st_regs[1].name = "st(1)";
1380 ia32_st_regs[2].name = "st(2)";
1381 ia32_st_regs[3].name = "st(3)";
1382 ia32_st_regs[4].name = "st(4)";
1383 ia32_st_regs[5].name = "st(5)";
1384 ia32_st_regs[6].name = "st(6)";
1385 ia32_st_regs[7].name = "st(7)";
1389 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1390 obstack_init(isa->name_obst);
1391 isa->name_obst_size = 0;
1394 ia32_handle_intrinsics();
1395 ia32_switch_section(NULL, NO_SECTION);
1396 fprintf(isa->out, "\t.intel_syntax\n");
1406 * Closes the output file and frees the ISA structure.
1408 static void ia32_done(void *self) {
1409 ia32_isa_t *isa = self;
1411 /* emit now all global declarations */
1412 ia32_gen_decls(isa->out);
1414 pmap_destroy(isa->regs_16bit);
1415 pmap_destroy(isa->regs_8bit);
1416 pmap_destroy(isa->tv_ent);
1417 pmap_destroy(isa->types);
1420 //printf("name obst size = %d bytes\n", isa->name_obst_size);
1421 obstack_free(isa->name_obst, NULL);
1429 * Return the number of register classes for this architecture.
1430 * We report always these:
1431 * - the general purpose registers
1432 * - the SSE floating point register set
1433 * - the virtual floating point registers
1435 static int ia32_get_n_reg_class(const void *self) {
1440 * Return the register class for index i.
1442 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1443 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1445 return &ia32_reg_classes[CLASS_ia32_gp];
1447 return &ia32_reg_classes[CLASS_ia32_xmm];
1449 return &ia32_reg_classes[CLASS_ia32_vfp];
1453 * Get the register class which shall be used to store a value of a given mode.
1454 * @param self The this pointer.
1455 * @param mode The mode in question.
1456 * @return A register class which can hold values of the given mode.
1458 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1459 const ia32_isa_t *isa = self;
1460 if (mode_is_float(mode)) {
1461 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1464 return &ia32_reg_classes[CLASS_ia32_gp];
1468 * Get the ABI restrictions for procedure calls.
1469 * @param self The this pointer.
1470 * @param method_type The type of the method (procedure) in question.
1471 * @param abi The abi object to be modified
1473 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1474 const ia32_isa_t *isa = self;
1477 unsigned cc = get_method_calling_convention(method_type);
1478 int n = get_method_n_params(method_type);
1481 int i, ignore_1, ignore_2;
1483 const arch_register_t *reg;
1484 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1486 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1488 /* set abi flags for calls */
1489 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1490 call_flags.bits.store_args_sequential = use_push;
1491 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1492 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1493 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1495 /* set stack parameter passing style */
1496 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1498 /* collect the mode for each type */
1499 modes = alloca(n * sizeof(modes[0]));
1501 for (i = 0; i < n; i++) {
1502 tp = get_method_param_type(method_type, i);
1503 modes[i] = get_type_mode(tp);
1506 /* set register parameters */
1507 if (cc & cc_reg_param) {
1508 /* determine the number of parameters passed via registers */
1509 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1511 /* loop over all parameters and set the register requirements */
1512 for (i = 0; i <= biggest_n; i++) {
1513 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1514 assert(reg && "kaputt");
1515 be_abi_call_param_reg(abi, i, reg);
1522 /* set stack parameters */
1523 for (i = stack_idx; i < n; i++) {
1524 be_abi_call_param_stack(abi, i, 1, 0, 0);
1528 /* set return registers */
1529 n = get_method_n_ress(method_type);
1531 assert(n <= 2 && "more than two results not supported");
1533 /* In case of 64bit returns, we will have two 32bit values */
1535 tp = get_method_res_type(method_type, 0);
1536 mode = get_type_mode(tp);
1538 assert(!mode_is_float(mode) && "two FP results not supported");
1540 tp = get_method_res_type(method_type, 1);
1541 mode = get_type_mode(tp);
1543 assert(!mode_is_float(mode) && "two FP results not supported");
1545 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1546 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1549 const arch_register_t *reg;
1551 tp = get_method_res_type(method_type, 0);
1552 assert(is_atomic_type(tp));
1553 mode = get_type_mode(tp);
1555 reg = mode_is_float(mode) ?
1556 (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
1557 &ia32_gp_regs[REG_EAX];
1559 be_abi_call_res_reg(abi, 0, reg);
1564 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1565 return &ia32_irn_ops;
1568 const arch_irn_handler_t ia32_irn_handler = {
1572 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1573 return &ia32_irn_handler;
1576 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1577 return is_ia32_irn(irn) ? 1 : -1;
1581 * Initializes the code generator interface.
1583 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1584 return &ia32_code_gen_if;
1587 list_sched_selector_t ia32_sched_selector;
1590 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1592 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
1593 // memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1594 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
1595 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1596 return &ia32_sched_selector;
1600 * Returns the necessary byte alignment for storing a register of given class.
1602 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1603 ir_mode *mode = arch_register_class_mode(cls);
1604 int bytes = get_mode_size_bytes(mode);
1606 if (mode_is_float(mode) && bytes > 8)
1611 static ia32_intrinsic_env_t intrinsic_env = { NULL, NULL };
1614 * Returns the libFirm configuration parameter for this backend.
1616 static const backend_params *ia32_get_libfirm_params(void) {
1617 static const arch_dep_params_t ad = {
1618 1, /* also use subs */
1619 4, /* maximum shifts */
1620 31, /* maximum shift amount */
1622 1, /* allow Mulhs */
1623 1, /* allow Mulus */
1624 32 /* Mulh allowed up to 32 bit */
1626 static backend_params p = {
1627 NULL, /* no additional opcodes */
1628 NULL, /* will be set later */
1629 1, /* need dword lowering */
1630 ia32_create_intrinsic_fkt,
1631 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1639 /* instruction set architectures. */
1640 static const lc_opt_enum_int_items_t arch_items[] = {
1641 { "386", arch_i386, },
1642 { "486", arch_i486, },
1643 { "pentium", arch_pentium, },
1644 { "586", arch_pentium, },
1645 { "pentiumpro", arch_pentium_pro, },
1646 { "686", arch_pentium_pro, },
1647 { "pentiummmx", arch_pentium_mmx, },
1648 { "pentium2", arch_pentium_2, },
1649 { "p2", arch_pentium_2, },
1650 { "pentium3", arch_pentium_3, },
1651 { "p3", arch_pentium_3, },
1652 { "pentium4", arch_pentium_4, },
1653 { "p4", arch_pentium_4, },
1654 { "pentiumm", arch_pentium_m, },
1655 { "pm", arch_pentium_m, },
1656 { "core", arch_core, },
1658 { "athlon", arch_athlon, },
1659 { "athlon64", arch_athlon_64, },
1660 { "opteron", arch_opteron, },
1664 static lc_opt_enum_int_var_t arch_var = {
1665 &ia32_isa_template.arch, arch_items
1668 static lc_opt_enum_int_var_t opt_arch_var = {
1669 &ia32_isa_template.opt_arch, arch_items
1672 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1674 { "sse2", fp_sse2 },
1678 static lc_opt_enum_int_var_t fp_unit_var = {
1679 &ia32_isa_template.fp_kind, fp_unit_items
1682 static const lc_opt_enum_int_items_t gas_items[] = {
1683 { "linux", ASM_LINUX_GAS },
1684 { "mingw", ASM_MINGW_GAS },
1688 static lc_opt_enum_int_var_t gas_var = {
1689 (int *)&asm_flavour, gas_items
1692 static const lc_opt_table_entry_t ia32_options[] = {
1693 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1694 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1695 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1696 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1697 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
1698 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1699 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1700 LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
1701 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
1706 * Register command line options for the ia32 backend.
1710 * ia32-arch=arch create instruction for arch
1711 * ia32-opt=arch optimize for run on arch
1712 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1713 * ia32-incdec optimize for inc/dec
1714 * ia32-noaddrmode do not use address mode
1715 * ia32-nolea do not optimize for LEAs
1716 * ia32-noplacecnst do not place constants,
1717 * ia32-noimmop no operations with immediates
1718 * ia32-noextbb do not use extended basic block scheduling
1719 * ia32-gasmode set the GAS compatibility mode
1721 static void ia32_register_options(lc_opt_entry_t *ent)
1723 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1724 lc_opt_add_table(be_grp_ia32, ia32_options);
1726 #endif /* WITH_LIBCORE */
1728 const arch_isa_if_t ia32_isa_if = {
1731 ia32_get_n_reg_class,
1733 ia32_get_reg_class_for_mode,
1735 ia32_get_irn_handler,
1736 ia32_get_code_generator_if,
1737 ia32_get_list_sched_selector,
1738 ia32_get_reg_class_alignment,
1739 ia32_get_libfirm_params,
1741 ia32_register_options