2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
24 #include "pseudo_irg.h"
28 #include "iredges_t.h"
36 #include "../beabi.h" /* the general register allocator interface */
37 #include "../benode_t.h"
38 #include "../belower.h"
39 #include "../besched_t.h"
41 #include "bearch_ia32_t.h"
43 #include "ia32_new_nodes.h" /* ia32 nodes interface */
44 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
45 #include "ia32_gen_decls.h" /* interface declaration emitter */
46 #include "ia32_transform.h"
47 #include "ia32_emitter.h"
48 #include "ia32_map_regs.h"
49 #include "ia32_optimize.h"
51 #include "ia32_dbg_stat.h"
52 #include "ia32_finish.h"
54 #define DEBUG_MODULE "firm.be.ia32.isa"
57 static set *cur_reg_set = NULL;
60 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
62 /* Creates the unique per irg GP NoReg node. */
63 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
64 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
67 /* Creates the unique per irg FP NoReg node. */
68 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
69 return be_abi_get_callee_save_irn(cg->birg->abi,
70 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
73 /* returns the first Proj with given mode from mode_T node */
74 static ir_node *get_proj_for_mode(ir_node *node, ir_mode *mode) {
75 const ir_edge_t *edge;
77 assert(get_irn_mode(node) == mode_T && "Need mode_T node.");
79 foreach_out_edge(node, edge) {
80 ir_node *proj = get_edge_src_irn(edge);
81 if (get_irn_mode(proj) == mode)
88 /**************************************************
91 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
92 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
93 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
94 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
97 **************************************************/
99 static ir_node *my_skip_proj(const ir_node *n) {
101 n = get_Proj_pred(n);
107 * Return register requirements for an ia32 node.
108 * If the node returns a tuple (mode_T) then the proj's
109 * will be asked for this information.
111 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
112 const ia32_irn_ops_t *ops = self;
113 const ia32_register_req_t *irn_req;
114 long node_pos = pos == -1 ? 0 : pos;
115 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
116 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
118 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
119 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
123 if (mode == mode_T && pos < 0) {
124 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
128 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
132 node_pos = ia32_translate_proj_pos(irn);
138 irn = my_skip_proj(irn);
140 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
143 if (is_ia32_irn(irn)) {
145 irn_req = get_ia32_in_req(irn, pos);
148 irn_req = get_ia32_out_req(irn, node_pos);
151 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
153 memcpy(req, &(irn_req->req), sizeof(*req));
155 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
156 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
157 req->other_same = get_irn_n(irn, irn_req->same_pos);
160 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
161 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
162 req->other_different = get_irn_n(irn, irn_req->different_pos);
166 /* treat Unknowns like Const with default requirements */
167 if (is_Unknown(irn)) {
168 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
169 if (mode_is_float(mode)) {
170 if (USE_SSE2(ops->cg))
171 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
173 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
175 else if (mode_is_int(mode) || mode_is_reference(mode))
176 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
177 else if (mode == mode_T || mode == mode_M) {
178 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
182 assert(0 && "unsupported Unknown-Mode");
185 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
193 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
195 const ia32_irn_ops_t *ops = self;
197 if (get_irn_mode(irn) == mode_X) {
201 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
204 pos = ia32_translate_proj_pos(irn);
205 irn = my_skip_proj(irn);
208 if (is_ia32_irn(irn)) {
209 const arch_register_t **slots;
211 slots = get_ia32_slots(irn);
215 ia32_set_firm_reg(irn, reg, cur_reg_set);
219 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
221 const arch_register_t *reg = NULL;
225 if (get_irn_mode(irn) == mode_X) {
229 pos = ia32_translate_proj_pos(irn);
230 irn = my_skip_proj(irn);
233 if (is_ia32_irn(irn)) {
234 const arch_register_t **slots;
235 slots = get_ia32_slots(irn);
239 reg = ia32_get_firm_reg(irn, cur_reg_set);
245 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
246 irn = my_skip_proj(irn);
248 return arch_irn_class_branch;
249 else if (is_ia32_Cnst(irn))
250 return arch_irn_class_const;
251 else if (is_ia32_Ld(irn))
252 return arch_irn_class_load;
253 else if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
254 return arch_irn_class_store;
255 else if (is_ia32_irn(irn))
256 return arch_irn_class_normal;
261 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
262 irn = my_skip_proj(irn);
263 if (is_ia32_irn(irn))
264 return get_ia32_flags(irn);
267 return arch_irn_flags_ignore;
272 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
273 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
276 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
278 const ia32_irn_ops_t *ops = self;
280 if (get_ia32_frame_ent(irn)) {
281 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
283 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
284 snprintf(buf, sizeof(buf), "%d", bias);
286 if (get_ia32_op_type(irn) == ia32_Normal) {
287 set_ia32_cnst(irn, buf);
290 add_ia32_am_offs(irn, buf);
292 set_ia32_am_flavour(irn, am_flav);
298 be_abi_call_flags_bits_t flags;
299 const arch_isa_t *isa;
300 const arch_env_t *aenv;
304 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
306 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
307 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
308 env->flags = fl.bits;
311 env->isa = aenv->isa;
316 * Put all registers which are saved by the prologue/epilogue in a set.
318 * @param self The callback object.
319 * @param s The result set.
321 static void ia32_abi_dont_save_regs(void *self, pset *s)
323 ia32_abi_env_t *env = self;
324 if(env->flags.try_omit_fp)
325 pset_insert_ptr(s, env->isa->bp);
329 * Generate the routine prologue.
331 * @param self The callback object.
332 * @param mem A pointer to the mem node. Update this if you define new memory.
333 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
335 * @return The register which shall be used as a stack frame base.
337 * All nodes which define registers in @p reg_map must keep @p reg_map current.
339 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
341 ia32_abi_env_t *env = self;
343 if (!env->flags.try_omit_fp) {
344 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
345 ir_node *bl = get_irg_start_block(env->irg);
346 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
347 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
351 push = new_rd_ia32_Push(NULL, env->irg, bl, curr_sp, curr_bp, *mem);
352 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
353 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
355 /* the push must have SP out register */
356 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
357 set_ia32_flags(push, arch_irn_flags_ignore);
359 /* move esp to ebp */
360 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
361 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
362 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
363 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
365 /* beware: the copy must be done before any other sp use */
366 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
367 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
368 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
369 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
371 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
372 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
381 * Generate the routine epilogue.
382 * @param self The callback object.
383 * @param bl The block for the epilog
384 * @param mem A pointer to the mem node. Update this if you define new memory.
385 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
386 * @return The register which shall be used as a stack frame base.
388 * All nodes which define registers in @p reg_map must keep @p reg_map current.
390 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
392 ia32_abi_env_t *env = self;
393 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
394 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
396 if (env->flags.try_omit_fp) {
397 /* simply remove the stack frame here */
398 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
401 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
402 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
403 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
405 /* gcc always emits a leave at the end of a routine */
406 if (1 || ARCH_AMD(isa->opt_arch)) {
410 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, *mem);
411 set_ia32_flags(leave, arch_irn_flags_ignore);
412 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
413 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
414 *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
419 /* copy ebp to esp */
420 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
423 pop = new_rd_ia32_Pop(NULL, env->irg, bl, curr_sp, *mem);
424 set_ia32_flags(pop, arch_irn_flags_ignore);
425 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
426 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
427 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
429 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
430 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
433 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
434 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
438 * Produces the type which sits between the stack args and the locals on the stack.
439 * it will contain the return address and space to store the old base pointer.
440 * @return The Firm type modeling the ABI between type.
442 static ir_type *ia32_abi_get_between_type(void *self)
444 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
445 static ir_type *omit_fp_between_type = NULL;
446 static ir_type *between_type = NULL;
448 ia32_abi_env_t *env = self;
450 if ( !between_type) {
452 entity *ret_addr_ent;
453 entity *omit_fp_ret_addr_ent;
455 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_P);
456 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_P);
458 between_type = new_type_struct(IDENT("ia32_between_type"));
459 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
460 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
462 set_entity_offset_bytes(old_bp_ent, 0);
463 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
464 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
465 set_type_state(between_type, layout_fixed);
467 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
468 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
470 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
471 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
472 set_type_state(omit_fp_between_type, layout_fixed);
475 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
480 * Get the estimated cycle count for @p irn.
482 * @param self The this pointer.
483 * @param irn The node.
485 * @return The estimated cycle count for this operation
487 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
490 switch (get_ia32_irn_opcode(irn)) {
492 case iro_ia32_DivMod:
497 case iro_ia32_l_Load:
507 case iro_ia32_xStore:
508 case iro_ia32_l_Store:
510 case iro_ia32_Store8Bit:
518 case iro_ia32_l_MulS:
531 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
533 * @param irn The original operation
534 * @param i Index of the argument we want the inverse operation to yield
535 * @param inverse struct to be filled with the resulting inverse op
536 * @param obstack The obstack to use for allocation of the returned nodes array
537 * @return The inverse operation or NULL if operation invertible
539 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
542 ir_node *block, *noreg, *nomem;
545 /* we cannot invert non-ia32 irns */
546 if (! is_ia32_irn(irn))
549 /* operand must always be a real operand (not base, index or mem) */
550 if (i != 2 && i != 3)
553 /* we don't invert address mode operations */
554 if (get_ia32_op_type(irn) != ia32_Normal)
557 irg = get_irn_irg(irn);
558 block = get_nodes_block(irn);
559 mode = get_ia32_res_mode(irn);
560 noreg = get_irn_n(irn, 0);
561 nomem = new_r_NoMem(irg);
563 /* initialize structure */
564 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
568 switch (get_ia32_irn_opcode(irn)) {
570 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
571 /* we have an add with a const here */
572 /* invers == add with negated const */
573 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
574 pnc = pn_ia32_Add_res;
576 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
577 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
578 set_ia32_commutative(inverse->nodes[0]);
580 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
581 /* we have an add with a symconst here */
582 /* invers == sub with const */
583 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
584 pnc = pn_ia32_Sub_res;
586 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
589 /* normal add: inverse == sub */
590 ir_node *proj = get_irn_out_edge_first(irn)->src;
591 assert(proj && is_Proj(proj));
593 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, i ^ 1), nomem);
594 pnc = pn_ia32_Sub_res;
599 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
600 /* we have a sub with a const/symconst here */
601 /* invers == add with this const */
602 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
603 pnc = pn_ia32_Add_res;
604 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
605 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
609 ir_node *proj = get_irn_out_edge_first(irn)->src;
610 assert(proj && is_Proj(proj));
613 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, 3), nomem);
616 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, 2), proj, nomem);
618 pnc = pn_ia32_Sub_res;
623 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
624 /* xor with const: inverse = xor */
625 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
626 pnc = pn_ia32_Eor_res;
627 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
628 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
632 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, (ir_node *)irn, get_irn_n(irn, i), nomem);
633 pnc = pn_ia32_Eor_res;
638 ir_node *proj = get_irn_out_edge_first(irn)->src;
639 assert(proj && is_Proj(proj));
641 inverse->nodes[0] = new_rd_ia32_Not(NULL, irg, block, noreg, noreg, proj, nomem);
642 pnc = pn_ia32_Not_res;
647 ir_node *proj = get_irn_out_edge_first(irn)->src;
648 assert(proj && is_Proj(proj));
650 inverse->nodes[0] = new_rd_ia32_Minus(NULL, irg, block, noreg, noreg, proj, nomem);
651 pnc = pn_ia32_Minus_res;
655 /* inverse operation not supported */
659 set_ia32_res_mode(inverse->nodes[0], mode);
660 inverse->nodes[1] = new_r_Proj(irg, block, inverse->nodes[0], mode, pnc);
665 static const be_abi_callbacks_t ia32_abi_callbacks = {
668 ia32_abi_get_between_type,
669 ia32_abi_dont_save_regs,
674 /* fill register allocator interface */
676 static const arch_irn_ops_if_t ia32_irn_ops_if = {
677 ia32_get_irn_reg_req,
682 ia32_get_frame_entity,
685 ia32_get_op_estimated_cost
688 ia32_irn_ops_t ia32_irn_ops = {
695 /**************************************************
698 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
699 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
700 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
701 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
704 **************************************************/
707 * Transforms the standard firm graph into
710 static void ia32_prepare_graph(void *self) {
711 ia32_code_gen_t *cg = self;
712 dom_front_info_t *dom;
713 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
715 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
717 /* 1st: transform constants and psi condition trees */
718 ia32_pre_transform_phase(cg);
720 /* 2nd: transform all remaining nodes */
721 ia32_register_transformers();
722 dom = be_compute_dominance_frontiers(cg->irg);
723 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
724 be_free_dominance_frontiers(dom);
727 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
729 /* 3rd: optimize address mode */
730 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
731 ia32_optimize_addressmode(cg);
734 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
736 DEBUG_ONLY(cg->mod = old_mod;)
740 * Dummy functions for hooks we don't need but which must be filled.
742 static void ia32_before_sched(void *self) {
745 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
753 mode = get_irn_mode(irn);
755 /* check if we already saw this node or the node has more than one user */
756 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1)
759 /* mark irn visited */
760 bitset_add_irn(already_visited, irn);
762 /* non-Tuple nodes with one user: ok, return */
763 if (get_irn_n_edges(irn) >= 1 && mode != mode_T)
766 /* tuple node has one user which is not the mem proj-> ok */
767 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
768 mem_proj = get_proj_for_mode(irn, mode_M);
773 for (i = get_irn_arity(irn) - 1; i >= 0; i--) {
774 ir_node *pred = get_irn_n(irn, i);
776 /* do not follow memory edges or we will accidentally remove stores */
777 if (is_Proj(pred) && get_irn_mode(pred) == mode_M)
780 set_irn_n(irn, i, new_Bad());
783 The current node is about to be removed: if the predecessor
784 has only this node as user, it need to be removed as well.
786 if (get_irn_n_edges(pred) <= 1)
787 remove_unused_nodes(pred, already_visited);
790 if (sched_is_scheduled(irn))
794 static void remove_unused_loads_walker(ir_node *irn, void *env) {
795 bitset_t *already_visited = env;
796 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
797 remove_unused_nodes(irn, env);
801 * Called before the register allocator.
802 * Calculate a block schedule here. We need it for the x87
803 * simulator and the emitter.
805 static void ia32_before_ra(void *self) {
806 ia32_code_gen_t *cg = self;
807 bitset_t *already_visited = bitset_irg_malloc(cg->irg);
809 cg->blk_sched = sched_create_block_schedule(cg->irg);
813 There are sometimes unused loads, only pinned by memory.
814 We need to remove those Loads and all other nodes which won't be used
815 after removing the Load from schedule.
817 irg_walk_graph(cg->irg, remove_unused_loads_walker, NULL, already_visited);
818 bitset_free(already_visited);
823 * Transforms a be node into a Load.
825 static void transform_to_Load(ia32_transform_env_t *env) {
826 ir_node *irn = env->irn;
827 entity *ent = be_get_frame_entity(irn);
828 ir_mode *mode = env->mode;
829 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
830 ir_node *nomem = new_rd_NoMem(env->irg);
831 ir_node *sched_point = NULL;
832 ir_node *ptr = get_irn_n(irn, 0);
833 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
834 ir_node *new_op, *proj;
835 const arch_register_t *reg;
837 if (sched_is_scheduled(irn)) {
838 sched_point = sched_prev(irn);
841 if (mode_is_float(mode)) {
842 if (USE_SSE2(env->cg))
843 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
845 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
848 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
851 set_ia32_am_support(new_op, ia32_am_Source);
852 set_ia32_op_type(new_op, ia32_AddrModeS);
853 set_ia32_am_flavour(new_op, ia32_B);
854 set_ia32_ls_mode(new_op, mode);
855 set_ia32_frame_ent(new_op, ent);
856 set_ia32_use_frame(new_op);
858 DBG_OPT_RELOAD2LD(irn, new_op);
860 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
863 sched_add_after(sched_point, new_op);
864 sched_add_after(new_op, proj);
869 /* copy the register from the old node to the new Load */
870 reg = arch_get_irn_register(env->cg->arch_env, irn);
871 arch_set_irn_register(env->cg->arch_env, new_op, reg);
873 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
879 * Transforms a be node into a Store.
881 static void transform_to_Store(ia32_transform_env_t *env) {
882 ir_node *irn = env->irn;
883 entity *ent = be_get_frame_entity(irn);
884 ir_mode *mode = env->mode;
885 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
886 ir_node *nomem = new_rd_NoMem(env->irg);
887 ir_node *ptr = get_irn_n(irn, 0);
888 ir_node *val = get_irn_n(irn, 1);
889 ir_node *new_op, *proj;
890 ir_node *sched_point = NULL;
892 if (sched_is_scheduled(irn)) {
893 sched_point = sched_prev(irn);
896 if (mode_is_float(mode)) {
897 if (USE_SSE2(env->cg))
898 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
900 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
902 else if (get_mode_size_bits(mode) == 8) {
903 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
906 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
909 set_ia32_am_support(new_op, ia32_am_Dest);
910 set_ia32_op_type(new_op, ia32_AddrModeD);
911 set_ia32_am_flavour(new_op, ia32_B);
912 set_ia32_ls_mode(new_op, mode);
913 set_ia32_frame_ent(new_op, ent);
914 set_ia32_use_frame(new_op);
916 DBG_OPT_SPILL2ST(irn, new_op);
918 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
921 sched_add_after(sched_point, new_op);
925 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
931 * Fix the mode of Spill/Reload
933 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
935 if (mode_is_float(mode)) {
947 * Block-Walker: Calls the transform functions Spill and Reload.
949 static void ia32_after_ra_walker(ir_node *block, void *env) {
950 ir_node *node, *prev;
951 ia32_code_gen_t *cg = env;
952 ia32_transform_env_t tenv;
955 tenv.irg = current_ir_graph;
957 DEBUG_ONLY(tenv.mod = cg->mod;)
959 /* beware: the schedule is changed here */
960 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
961 prev = sched_prev(node);
962 if (be_is_Reload(node)) {
963 /* we always reload the whole register */
964 tenv.dbg = get_irn_dbg_info(node);
966 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
967 transform_to_Load(&tenv);
969 else if (be_is_Spill(node)) {
970 /* we always spill the whole register */
971 tenv.dbg = get_irn_dbg_info(node);
973 tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node)));
974 transform_to_Store(&tenv);
980 * We transform Spill and Reload here. This needs to be done before
981 * stack biasing otherwise we would miss the corrected offset for these nodes.
983 * If x87 instruction should be emitted, run the x87 simulator and patch
984 * the virtual instructions. This must obviously be done after register allocation.
986 static void ia32_after_ra(void *self) {
987 ia32_code_gen_t *cg = self;
988 irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self);
990 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
991 if (cg->used_fp == fp_x87 || cg->force_sim) {
992 x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
998 * Emits the code, closes the output file and frees
999 * the code generator interface.
1001 static void ia32_codegen(void *self) {
1002 ia32_code_gen_t *cg = self;
1003 ir_graph *irg = cg->irg;
1005 ia32_finish_irg(irg, cg);
1007 be_dump(irg, "-finished", dump_ir_block_graph_sched);
1008 ia32_gen_routine(cg->isa->out, irg, cg);
1012 /* remove it from the isa */
1015 /* de-allocate code generator */
1016 del_set(cg->reg_set);
1021 static void *ia32_cg_init(const be_irg_t *birg);
1023 static const arch_code_generator_if_t ia32_code_gen_if = {
1025 NULL, /* before abi introduce hook */
1027 ia32_before_sched, /* before scheduling hook */
1028 ia32_before_ra, /* before register allocation hook */
1029 ia32_after_ra, /* after register allocation hook */
1030 ia32_codegen /* emit && done */
1034 * Initializes a IA32 code generator.
1036 static void *ia32_cg_init(const be_irg_t *birg) {
1037 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1038 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1040 cg->impl = &ia32_code_gen_if;
1041 cg->irg = birg->irg;
1042 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1043 cg->arch_env = birg->main_env->arch_env;
1046 cg->blk_sched = NULL;
1047 cg->fp_to_gp = NULL;
1048 cg->gp_to_fp = NULL;
1049 cg->fp_kind = isa->fp_kind;
1050 cg->used_fp = fp_none;
1051 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1053 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1055 /* copy optimizations from isa for easier access */
1057 cg->arch = isa->arch;
1058 cg->opt_arch = isa->opt_arch;
1064 if (isa->name_obst_size) {
1065 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
1066 isa->name_obst_size = 0;
1067 obstack_free(isa->name_obst, NULL);
1068 obstack_init(isa->name_obst);
1072 cur_reg_set = cg->reg_set;
1074 ia32_irn_ops.cg = cg;
1076 return (arch_code_generator_t *)cg;
1081 /*****************************************************************
1082 * ____ _ _ _____ _____
1083 * | _ \ | | | | |_ _|/ ____| /\
1084 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1085 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1086 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1087 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1089 *****************************************************************/
1092 * Set output modes for GCC
1094 static const tarval_mode_info mo_integer = {
1101 * set the tarval output mode to C-semantics
1103 static void set_tarval_output_modes(void)
1105 set_tarval_mode_output_option(get_modeLs(), &mo_integer);
1106 set_tarval_mode_output_option(get_modeLu(), &mo_integer);
1107 set_tarval_mode_output_option(get_modeIs(), &mo_integer);
1108 set_tarval_mode_output_option(get_modeIu(), &mo_integer);
1109 set_tarval_mode_output_option(get_modeHs(), &mo_integer);
1110 set_tarval_mode_output_option(get_modeHu(), &mo_integer);
1111 set_tarval_mode_output_option(get_modeBs(), &mo_integer);
1112 set_tarval_mode_output_option(get_modeBu(), &mo_integer);
1113 set_tarval_mode_output_option(get_modeC(), &mo_integer);
1114 set_tarval_mode_output_option(get_modeU(), &mo_integer);
1115 set_tarval_mode_output_option(get_modeIu(), &mo_integer);
1120 * The template that generates a new ISA object.
1121 * Note that this template can be changed by command line
1124 static ia32_isa_t ia32_isa_template = {
1126 &ia32_isa_if, /* isa interface implementation */
1127 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1128 &ia32_gp_regs[REG_EBP], /* base pointer register */
1129 -1, /* stack direction */
1131 NULL, /* 16bit register names */
1132 NULL, /* 8bit register names */
1136 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1137 IA32_OPT_DOAM | /* optimize address mode default: on */
1138 IA32_OPT_LEA | /* optimize for LEAs default: on */
1139 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1140 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1141 IA32_OPT_EXTBB), /* use extended basic block scheduling, default: on */
1142 arch_pentium_4, /* instruction architecture */
1143 arch_pentium_4, /* optimize for architecture */
1144 fp_sse2, /* use sse2 unit */
1145 NULL, /* current code generator */
1147 NULL, /* name obstack */
1148 0 /* name obst size */
1153 * Initializes the backend ISA.
1155 static void *ia32_init(FILE *file_handle) {
1156 static int inited = 0;
1162 set_tarval_output_modes();
1164 isa = xmalloc(sizeof(*isa));
1165 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1167 ia32_register_init(isa);
1168 ia32_create_opcodes();
1170 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1171 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1172 /* no SSE2 for these cpu's */
1173 isa->fp_kind = fp_x87;
1175 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1176 /* Pentium 4 don't like inc and dec instructions */
1177 isa->opt &= ~IA32_OPT_INCDEC;
1180 isa->regs_16bit = pmap_create();
1181 isa->regs_8bit = pmap_create();
1182 isa->types = pmap_create();
1183 isa->tv_ent = pmap_create();
1184 isa->out = file_handle;
1186 ia32_build_16bit_reg_map(isa->regs_16bit);
1187 ia32_build_8bit_reg_map(isa->regs_8bit);
1189 /* patch register names of x87 registers */
1191 ia32_st_regs[0].name = "st";
1192 ia32_st_regs[1].name = "st(1)";
1193 ia32_st_regs[2].name = "st(2)";
1194 ia32_st_regs[3].name = "st(3)";
1195 ia32_st_regs[4].name = "st(4)";
1196 ia32_st_regs[5].name = "st(5)";
1197 ia32_st_regs[6].name = "st(6)";
1198 ia32_st_regs[7].name = "st(7)";
1202 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1203 obstack_init(isa->name_obst);
1204 isa->name_obst_size = 0;
1207 ia32_handle_intrinsics();
1208 ia32_switch_section(NULL, NO_SECTION);
1209 fprintf(isa->out, "\t.intel_syntax\n");
1219 * Closes the output file and frees the ISA structure.
1221 static void ia32_done(void *self) {
1222 ia32_isa_t *isa = self;
1224 /* emit now all global declarations */
1225 ia32_gen_decls(isa->out);
1227 pmap_destroy(isa->regs_16bit);
1228 pmap_destroy(isa->regs_8bit);
1229 pmap_destroy(isa->tv_ent);
1230 pmap_destroy(isa->types);
1233 //printf("name obst size = %d bytes\n", isa->name_obst_size);
1234 obstack_free(isa->name_obst, NULL);
1242 * Return the number of register classes for this architecture.
1243 * We report always these:
1244 * - the general purpose registers
1245 * - the SSE floating point register set
1246 * - the virtual floating point registers
1248 static int ia32_get_n_reg_class(const void *self) {
1253 * Return the register class for index i.
1255 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1256 const ia32_isa_t *isa = self;
1257 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1259 return &ia32_reg_classes[CLASS_ia32_gp];
1261 return &ia32_reg_classes[CLASS_ia32_xmm];
1263 return &ia32_reg_classes[CLASS_ia32_vfp];
1267 * Get the register class which shall be used to store a value of a given mode.
1268 * @param self The this pointer.
1269 * @param mode The mode in question.
1270 * @return A register class which can hold values of the given mode.
1272 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1273 const ia32_isa_t *isa = self;
1274 if (mode_is_float(mode)) {
1275 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1278 return &ia32_reg_classes[CLASS_ia32_gp];
1282 * Get the ABI restrictions for procedure calls.
1283 * @param self The this pointer.
1284 * @param method_type The type of the method (procedure) in question.
1285 * @param abi The abi object to be modified
1287 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1288 const ia32_isa_t *isa = self;
1291 unsigned cc = get_method_calling_convention(method_type);
1292 int n = get_method_n_params(method_type);
1295 int i, ignore_1, ignore_2;
1297 const arch_register_t *reg;
1298 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1300 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1302 /* set abi flags for calls */
1303 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1304 call_flags.bits.store_args_sequential = use_push;
1305 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1306 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1307 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1309 /* set stack parameter passing style */
1310 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1312 /* collect the mode for each type */
1313 modes = alloca(n * sizeof(modes[0]));
1315 for (i = 0; i < n; i++) {
1316 tp = get_method_param_type(method_type, i);
1317 modes[i] = get_type_mode(tp);
1320 /* set register parameters */
1321 if (cc & cc_reg_param) {
1322 /* determine the number of parameters passed via registers */
1323 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1325 /* loop over all parameters and set the register requirements */
1326 for (i = 0; i <= biggest_n; i++) {
1327 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1328 assert(reg && "kaputt");
1329 be_abi_call_param_reg(abi, i, reg);
1336 /* set stack parameters */
1337 for (i = stack_idx; i < n; i++) {
1338 be_abi_call_param_stack(abi, i, 1, 0, 0);
1342 /* set return registers */
1343 n = get_method_n_ress(method_type);
1345 assert(n <= 2 && "more than two results not supported");
1347 /* In case of 64bit returns, we will have two 32bit values */
1349 tp = get_method_res_type(method_type, 0);
1350 mode = get_type_mode(tp);
1352 assert(!mode_is_float(mode) && "two FP results not supported");
1354 tp = get_method_res_type(method_type, 1);
1355 mode = get_type_mode(tp);
1357 assert(!mode_is_float(mode) && "two FP results not supported");
1359 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1360 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1363 const arch_register_t *reg;
1365 tp = get_method_res_type(method_type, 0);
1366 assert(is_atomic_type(tp));
1367 mode = get_type_mode(tp);
1369 reg = mode_is_float(mode) ?
1370 (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
1371 &ia32_gp_regs[REG_EAX];
1373 be_abi_call_res_reg(abi, 0, reg);
1378 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1379 return &ia32_irn_ops;
1382 const arch_irn_handler_t ia32_irn_handler = {
1386 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1387 return &ia32_irn_handler;
1390 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1391 return is_ia32_irn(irn) ? 1 : -1;
1395 * Initializes the code generator interface.
1397 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1398 return &ia32_code_gen_if;
1401 list_sched_selector_t ia32_sched_selector;
1404 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1406 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
1407 // memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1408 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
1409 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1410 return &ia32_sched_selector;
1414 * Returns the necessary byte alignment for storing a register of given class.
1416 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1417 ir_mode *mode = arch_register_class_mode(cls);
1418 int bytes = get_mode_size_bytes(mode);
1420 if (mode_is_float(mode) && bytes > 8)
1425 static ia32_intrinsic_env_t intrinsic_env = { NULL, NULL };
1428 * Returns the libFirm configuration parameter for this backend.
1430 static const backend_params *ia32_get_libfirm_params(void) {
1431 static const arch_dep_params_t ad = {
1432 1, /* also use subs */
1433 4, /* maximum shifts */
1434 31, /* maximum shift amount */
1436 1, /* allow Mulhs */
1437 1, /* allow Mulus */
1438 32 /* Mulh allowed up to 32 bit */
1440 static backend_params p = {
1441 NULL, /* no additional opcodes */
1442 NULL, /* will be set later */
1443 1, /* need dword lowering */
1444 ia32_create_intrinsic_fkt,
1445 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1453 /* instruction set architectures. */
1454 static const lc_opt_enum_int_items_t arch_items[] = {
1455 { "386", arch_i386, },
1456 { "486", arch_i486, },
1457 { "pentium", arch_pentium, },
1458 { "586", arch_pentium, },
1459 { "pentiumpro", arch_pentium_pro, },
1460 { "686", arch_pentium_pro, },
1461 { "pentiummmx", arch_pentium_mmx, },
1462 { "pentium2", arch_pentium_2, },
1463 { "p2", arch_pentium_2, },
1464 { "pentium3", arch_pentium_3, },
1465 { "p3", arch_pentium_3, },
1466 { "pentium4", arch_pentium_4, },
1467 { "p4", arch_pentium_4, },
1468 { "pentiumm", arch_pentium_m, },
1469 { "pm", arch_pentium_m, },
1470 { "core", arch_core, },
1472 { "athlon", arch_athlon, },
1473 { "athlon64", arch_athlon_64, },
1474 { "opteron", arch_opteron, },
1478 static lc_opt_enum_int_var_t arch_var = {
1479 &ia32_isa_template.arch, arch_items
1482 static lc_opt_enum_int_var_t opt_arch_var = {
1483 &ia32_isa_template.opt_arch, arch_items
1486 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1488 { "sse2", fp_sse2 },
1492 static lc_opt_enum_int_var_t fp_unit_var = {
1493 &ia32_isa_template.fp_kind, fp_unit_items
1496 static const lc_opt_enum_int_items_t gas_items[] = {
1497 { "linux", ASM_LINUX_GAS },
1498 { "mingw", ASM_MINGW_GAS },
1502 static lc_opt_enum_int_var_t gas_var = {
1503 (int *)&asm_flavour, gas_items
1506 static const lc_opt_table_entry_t ia32_options[] = {
1507 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1508 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1509 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1510 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1511 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
1512 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1513 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1514 LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
1515 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
1520 * Register command line options for the ia32 backend.
1524 * ia32-arch=arch create instruction for arch
1525 * ia32-opt=arch optimize for run on arch
1526 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1527 * ia32-incdec optimize for inc/dec
1528 * ia32-noaddrmode do not use address mode
1529 * ia32-nolea do not optimize for LEAs
1530 * ia32-noplacecnst do not place constants,
1531 * ia32-noimmop no operations with immediates
1532 * ia32-noextbb do not use extended basic block scheduling
1533 * ia32-gasmode set the GAS compatibility mode
1535 static void ia32_register_options(lc_opt_entry_t *ent)
1537 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1538 lc_opt_add_table(be_grp_ia32, ia32_options);
1540 #endif /* WITH_LIBCORE */
1542 const arch_isa_if_t ia32_isa_if = {
1545 ia32_get_n_reg_class,
1547 ia32_get_reg_class_for_mode,
1549 ia32_get_irn_handler,
1550 ia32_get_code_generator_if,
1551 ia32_get_list_sched_selector,
1552 ia32_get_reg_class_alignment,
1553 ia32_get_libfirm_params,
1555 ia32_register_options