2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
31 #include "lc_opts_enum.h"
35 #include "pseudo_irg.h"
40 #include "iredges_t.h"
46 #include "irdump_grgen.h"
53 #include "iroptimize.h"
56 #include "../beirg_t.h"
57 #include "../benode_t.h"
58 #include "../belower.h"
59 #include "../besched_t.h"
62 #include "../beirgmod.h"
63 #include "../be_dbgout.h"
64 #include "../beblocksched.h"
65 #include "../bemachine.h"
66 #include "../beilpsched.h"
67 #include "../bespillslots.h"
68 #include "../bemodule.h"
69 #include "../begnuas.h"
70 #include "../bestate.h"
71 #include "../beflags.h"
73 #include "bearch_ia32_t.h"
75 #include "ia32_new_nodes.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "gen_ia32_machine.h"
78 #include "ia32_transform.h"
79 #include "ia32_emitter.h"
80 #include "ia32_map_regs.h"
81 #include "ia32_optimize.h"
83 #include "ia32_dbg_stat.h"
84 #include "ia32_finish.h"
85 #include "ia32_util.h"
87 #include "ia32_architecture.h"
90 #include "ia32_pbqp_transform.h"
93 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
96 static set *cur_reg_set = NULL;
98 ir_mode *mode_fpcw = NULL;
99 ia32_code_gen_t *ia32_current_cg = NULL;
102 * The environment for the intrinsic mapping.
104 static ia32_intrinsic_env_t intrinsic_env = {
106 NULL, /* the irg, these entities belong to */
107 NULL, /* entity for first div operand (move into FPU) */
108 NULL, /* entity for second div operand (move into FPU) */
109 NULL, /* entity for converts ll -> d */
110 NULL, /* entity for converts d -> ll */
111 NULL, /* entity for __divdi3 library call */
112 NULL, /* entity for __moddi3 library call */
113 NULL, /* entity for __udivdi3 library call */
114 NULL, /* entity for __umoddi3 library call */
115 NULL, /* bias value for conversion from float to unsigned 64 */
119 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
121 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
122 create_const_node_func func,
123 const arch_register_t* reg)
125 ir_node *block, *res;
130 block = get_irg_start_block(cg->irg);
131 res = func(NULL, cg->irg, block);
132 arch_set_irn_register(cg->arch_env, res, reg);
135 add_irn_dep(get_irg_end(cg->irg), res);
136 /* add_irn_dep(get_irg_start(cg->irg), res); */
141 /* Creates the unique per irg GP NoReg node. */
142 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
143 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
144 &ia32_gp_regs[REG_GP_NOREG]);
147 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
148 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
149 &ia32_vfp_regs[REG_VFP_NOREG]);
152 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
153 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
154 &ia32_xmm_regs[REG_XMM_NOREG]);
157 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
158 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
159 &ia32_gp_regs[REG_GP_UKNWN]);
162 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
163 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
164 &ia32_vfp_regs[REG_VFP_UKNWN]);
167 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
168 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
169 &ia32_xmm_regs[REG_XMM_UKNWN]);
172 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
173 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
174 &ia32_fp_cw_regs[REG_FPCW]);
179 * Returns gp_noreg or fp_noreg, depending in input requirements.
181 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
182 const arch_register_req_t *req;
184 req = arch_get_register_req(cg->arch_env, irn, pos);
185 assert(req != NULL && "Missing register requirements");
186 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
187 return ia32_new_NoReg_gp(cg);
189 if (ia32_cg_config.use_sse2) {
190 return ia32_new_NoReg_xmm(cg);
192 return ia32_new_NoReg_vfp(cg);
196 /**************************************************
199 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
200 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
201 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
202 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
205 **************************************************/
208 * Return register requirements for an ia32 node.
209 * If the node returns a tuple (mode_T) then the proj's
210 * will be asked for this information.
212 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
216 long node_pos = pos == -1 ? 0 : pos;
217 ir_mode *mode = is_Block(node) ? NULL : get_irn_mode(node);
220 if (is_Block(node) || mode == mode_X) {
221 return arch_no_register_req;
224 if (mode == mode_T && pos < 0) {
225 return arch_no_register_req;
230 return arch_no_register_req;
233 return arch_no_register_req;
236 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
237 node = skip_Proj_const(node);
240 if (is_ia32_irn(node)) {
241 const arch_register_req_t *req;
243 req = get_ia32_in_req(node, pos);
245 req = get_ia32_out_req(node, node_pos);
252 /* unknowns should be transformed already */
253 assert(!is_Unknown(node));
255 return arch_no_register_req;
258 static void ia32_set_irn_reg(const void *self, ir_node *irn,
259 const arch_register_t *reg)
264 if (get_irn_mode(irn) == mode_X) {
269 pos = get_Proj_proj(irn);
270 irn = skip_Proj(irn);
273 if (is_ia32_irn(irn)) {
274 const arch_register_t **slots;
276 slots = get_ia32_slots(irn);
279 ia32_set_firm_reg(irn, reg, cur_reg_set);
283 static const arch_register_t *ia32_get_irn_reg(const void *self,
287 const arch_register_t *reg = NULL;
292 if (get_irn_mode(irn) == mode_X) {
296 pos = get_Proj_proj(irn);
297 irn = skip_Proj_const(irn);
300 if (is_ia32_irn(irn)) {
301 const arch_register_t **slots;
302 slots = get_ia32_slots(irn);
303 assert(pos < get_ia32_n_res(irn));
306 reg = ia32_get_firm_reg(irn, cur_reg_set);
312 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
313 arch_irn_class_t classification = arch_irn_class_normal;
316 irn = skip_Proj_const(irn);
319 classification |= arch_irn_class_branch;
321 if (! is_ia32_irn(irn))
322 return classification & ~arch_irn_class_normal;
325 classification |= arch_irn_class_load;
328 classification |= arch_irn_class_store;
330 if (is_ia32_need_stackent(irn))
331 classification |= arch_irn_class_reload;
333 return classification;
336 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
337 arch_irn_flags_t flags = arch_irn_flags_none;
341 return arch_irn_flags_ignore;
343 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
344 ir_node *pred = get_Proj_pred(irn);
346 if(is_ia32_irn(pred)) {
347 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
353 if (is_ia32_irn(irn)) {
354 flags |= get_ia32_flags(irn);
361 * The IA32 ABI callback object.
364 be_abi_call_flags_bits_t flags; /**< The call flags. */
365 const arch_isa_t *isa; /**< The ISA handle. */
366 const arch_env_t *aenv; /**< The architecture environment. */
367 ir_graph *irg; /**< The associated graph. */
370 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
372 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
375 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
377 set_ia32_frame_ent(irn, ent);
380 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
381 const ia32_irn_ops_t *ops = self;
383 if (get_ia32_frame_ent(irn)) {
384 if (is_ia32_Pop(irn)) {
385 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
387 /* Pop nodes modify the stack pointer before calculating the destination
388 * address, so fix this here
394 add_ia32_am_offs_int(irn, bias);
398 static int ia32_get_sp_bias(const void *self, const ir_node *node)
402 if (is_ia32_Push(node))
405 if (is_ia32_Pop(node))
412 * Put all registers which are saved by the prologue/epilogue in a set.
414 * @param self The callback object.
415 * @param s The result set.
417 static void ia32_abi_dont_save_regs(void *self, pset *s)
419 ia32_abi_env_t *env = self;
420 if(env->flags.try_omit_fp)
421 pset_insert_ptr(s, env->isa->bp);
425 * Generate the routine prologue.
427 * @param self The callback object.
428 * @param mem A pointer to the mem node. Update this if you define new memory.
429 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
431 * @return The register which shall be used as a stack frame base.
433 * All nodes which define registers in @p reg_map must keep @p reg_map current.
435 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
437 ia32_abi_env_t *env = self;
438 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
439 ia32_code_gen_t *cg = isa->cg;
441 if (! env->flags.try_omit_fp) {
442 ir_node *bl = get_irg_start_block(env->irg);
443 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
444 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
445 ir_node *noreg = ia32_new_NoReg_gp(cg);
448 /* ALL nodes representing bp must be set to ignore. */
449 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
452 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp, curr_bp);
453 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
454 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
456 /* the push must have SP out register */
457 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
458 set_ia32_flags(push, arch_irn_flags_ignore);
460 /* move esp to ebp */
461 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
462 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
463 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
464 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
466 /* beware: the copy must be done before any other sp use */
467 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
468 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
469 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
470 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
472 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
473 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
482 * Generate the routine epilogue.
483 * @param self The callback object.
484 * @param bl The block for the epilog
485 * @param mem A pointer to the mem node. Update this if you define new memory.
486 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
487 * @return The register which shall be used as a stack frame base.
489 * All nodes which define registers in @p reg_map must keep @p reg_map current.
491 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
493 ia32_abi_env_t *env = self;
494 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
495 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
497 if (env->flags.try_omit_fp) {
498 /* simply remove the stack frame here */
499 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
500 add_irn_dep(curr_sp, *mem);
502 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
503 ia32_code_gen_t *cg = isa->cg;
504 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
505 ir_graph *irg = current_ir_graph;
507 if (ia32_cg_config.use_leave) {
511 leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
512 set_ia32_flags(leave, arch_irn_flags_ignore);
513 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
514 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
516 ir_node *noreg = ia32_new_NoReg_gp(cg);
519 /* the old SP is not needed anymore (kill the proj) */
520 assert(is_Proj(curr_sp));
521 be_kill_node(curr_sp);
523 /* copy ebp to esp */
524 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
525 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
526 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
529 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp);
530 set_ia32_flags(pop, arch_irn_flags_ignore);
531 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
532 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
534 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
536 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
537 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
540 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
541 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
545 * Initialize the callback object.
546 * @param call The call object.
547 * @param aenv The architecture environment.
548 * @param irg The graph with the method.
549 * @return Some pointer. This pointer is passed to all other callback functions as self object.
551 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
553 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
554 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
555 env->flags = fl.bits;
558 env->isa = aenv->isa;
563 * Destroy the callback object.
564 * @param self The callback object.
566 static void ia32_abi_done(void *self) {
571 * Produces the type which sits between the stack args and the locals on the stack.
572 * it will contain the return address and space to store the old base pointer.
573 * @return The Firm type modeling the ABI between type.
575 static ir_type *ia32_abi_get_between_type(void *self)
577 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
578 static ir_type *omit_fp_between_type = NULL;
579 static ir_type *between_type = NULL;
581 ia32_abi_env_t *env = self;
583 if (! between_type) {
584 ir_entity *old_bp_ent;
585 ir_entity *ret_addr_ent;
586 ir_entity *omit_fp_ret_addr_ent;
588 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
589 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
591 between_type = new_type_struct(IDENT("ia32_between_type"));
592 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
593 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
595 set_entity_offset(old_bp_ent, 0);
596 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
597 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
598 set_type_state(between_type, layout_fixed);
600 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
601 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
603 set_entity_offset(omit_fp_ret_addr_ent, 0);
604 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
605 set_type_state(omit_fp_between_type, layout_fixed);
608 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
613 * Get the estimated cycle count for @p irn.
615 * @param self The this pointer.
616 * @param irn The node.
618 * @return The estimated cycle count for this operation
620 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
623 ia32_op_type_t op_tp;
628 if (!is_ia32_irn(irn))
631 assert(is_ia32_irn(irn));
633 cost = get_ia32_latency(irn);
634 op_tp = get_ia32_op_type(irn);
636 if (is_ia32_CopyB(irn)) {
639 else if (is_ia32_CopyB_i(irn)) {
640 int size = get_ia32_copyb_size(irn);
641 cost = 20 + (int)ceil((4/3) * size);
643 /* in case of address mode operations add additional cycles */
644 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
646 In case of stack access and access to fixed addresses add 5 cycles
647 (we assume they are in cache), other memory operations cost 20
650 if(is_ia32_use_frame(irn) ||
651 (is_ia32_NoReg_GP(get_irn_n(irn, 0)) &&
652 is_ia32_NoReg_GP(get_irn_n(irn, 1)))) {
663 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
665 * @param irn The original operation
666 * @param i Index of the argument we want the inverse operation to yield
667 * @param inverse struct to be filled with the resulting inverse op
668 * @param obstack The obstack to use for allocation of the returned nodes array
669 * @return The inverse operation or NULL if operation invertible
671 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
675 ir_node *block, *noreg, *nomem;
679 /* we cannot invert non-ia32 irns */
680 if (! is_ia32_irn(irn))
683 /* operand must always be a real operand (not base, index or mem) */
684 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
687 /* we don't invert address mode operations */
688 if (get_ia32_op_type(irn) != ia32_Normal)
691 /* TODO: adjust for new immediates... */
692 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
696 irg = get_irn_irg(irn);
697 block = get_nodes_block(irn);
698 mode = get_irn_mode(irn);
699 irn_mode = get_irn_mode(irn);
700 noreg = get_irn_n(irn, 0);
701 nomem = new_r_NoMem(irg);
702 dbg = get_irn_dbg_info(irn);
704 /* initialize structure */
705 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
709 switch (get_ia32_irn_opcode(irn)) {
712 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
713 /* we have an add with a const here */
714 /* invers == add with negated const */
715 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
717 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
718 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
719 set_ia32_commutative(inverse->nodes[0]);
721 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
722 /* we have an add with a symconst here */
723 /* invers == sub with const */
724 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
726 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
729 /* normal add: inverse == sub */
730 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
737 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
738 /* we have a sub with a const/symconst here */
739 /* invers == add with this const */
740 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
741 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
742 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
746 if (i == n_ia32_binary_left) {
747 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
750 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
758 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
759 /* xor with const: inverse = xor */
760 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
761 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
762 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
766 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
772 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
777 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
782 /* inverse operation not supported */
789 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
791 if(mode_is_float(mode))
798 * Get the mode that should be used for spilling value node
800 static ir_mode *get_spill_mode(const ir_node *node)
802 ir_mode *mode = get_irn_mode(node);
803 return get_spill_mode_mode(mode);
807 * Checks whether an addressmode reload for a node with mode mode is compatible
808 * with a spillslot of mode spill_mode
810 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
812 if(mode_is_float(mode)) {
813 return mode == spillmode;
820 * Check if irn can load it's operand at position i from memory (source addressmode).
821 * @param self Pointer to irn ops itself
822 * @param irn The irn to be checked
823 * @param i The operands position
824 * @return Non-Zero if operand can be loaded
826 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
827 ir_node *op = get_irn_n(irn, i);
828 const ir_mode *mode = get_irn_mode(op);
829 const ir_mode *spillmode = get_spill_mode(op);
832 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
833 get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */
834 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
835 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
836 ! ia32_is_spillmode_compatible(mode, spillmode) ||
837 (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
838 is_ia32_use_frame(irn)) /* must not already use frame */
841 if (i == n_ia32_binary_left) {
842 const arch_register_req_t *req;
843 if(!is_ia32_commutative(irn))
845 /* we can't swap left/right for limited registers
846 * (As this (currently) breaks constraint handling copies)
848 req = get_ia32_in_req(irn, n_ia32_binary_left);
849 if(req->type & arch_register_req_type_limited) {
857 static void ia32_perform_memory_operand(const void *self, ir_node *irn,
858 ir_node *spill, unsigned int i)
860 const ia32_irn_ops_t *ops = self;
861 ia32_code_gen_t *cg = ops->cg;
863 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
865 if (i == n_ia32_binary_left) {
866 ia32_swap_left_right(irn);
869 set_ia32_op_type(irn, ia32_AddrModeS);
870 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
871 set_ia32_use_frame(irn);
872 set_ia32_need_stackent(irn);
874 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
875 set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
876 set_irn_n(irn, n_ia32_mem, spill);
878 /* immediates are only allowed on the right side */
879 if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
880 ia32_swap_left_right(irn);
884 static const be_abi_callbacks_t ia32_abi_callbacks = {
887 ia32_abi_get_between_type,
888 ia32_abi_dont_save_regs,
893 /* fill register allocator interface */
895 static const arch_irn_ops_if_t ia32_irn_ops_if = {
896 ia32_get_irn_reg_req,
901 ia32_get_frame_entity,
902 ia32_set_frame_entity,
903 ia32_set_frame_offset,
906 ia32_get_op_estimated_cost,
907 ia32_possible_memory_operand,
908 ia32_perform_memory_operand,
911 static ia32_irn_ops_t ia32_irn_ops = {
918 /**************************************************
921 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
922 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
923 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
924 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
927 **************************************************/
929 static void ia32_before_abi(void *self) {
930 lower_mode_b_config_t lower_mode_b_config = {
931 mode_Iu, /* lowered mode */
932 mode_Bu, /* prefered mode for set */
933 0, /* don't lower direct compares */
935 ia32_code_gen_t *cg = self;
937 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
939 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
943 * Transforms the standard firm graph into
946 static void ia32_prepare_graph(void *self) {
947 ia32_code_gen_t *cg = self;
949 /* do local optimisations */
950 optimize_graph_df(cg->irg);
952 /* TODO: we often have dead code reachable through out-edges here. So for
953 * now we rebuild edges (as we need correct user count for code selection)
956 edges_deactivate(cg->irg);
957 edges_activate(cg->irg);
961 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
964 /* used for examination purposes only
966 dump_irg_grgen(cg->irg, "-pre_transform");
969 /* transform nodes into assembler instructions by PBQP magic */
970 ia32_transform_graph_by_pbqp(cg);
974 be_dump(cg->irg, "-after_pbqp_transform", dump_ir_block_graph_sched);
976 /* transform remaining nodes into assembler instructions */
977 ia32_transform_graph(cg);
979 /* do local optimisations (mainly CSE) */
980 optimize_graph_df(cg->irg);
983 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
985 /* optimize address mode */
986 ia32_optimize_graph(cg);
989 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
991 /* do code placement, to optimize the position of constants */
995 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
999 * Dummy functions for hooks we don't need but which must be filled.
1001 static void ia32_before_sched(void *self) {
1005 static void turn_back_am(ir_node *node)
1007 ir_graph *irg = current_ir_graph;
1008 dbg_info *dbgi = get_irn_dbg_info(node);
1009 ir_node *block = get_nodes_block(node);
1010 ir_node *base = get_irn_n(node, n_ia32_base);
1011 ir_node *index = get_irn_n(node, n_ia32_index);
1012 ir_node *mem = get_irn_n(node, n_ia32_mem);
1013 ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg);
1017 const ir_edge_t *edge;
1019 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1020 load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1022 ia32_copy_am_attrs(load, node);
1023 set_irn_n(node, n_ia32_mem, new_NoMem());
1025 switch (get_ia32_am_arity(node)) {
1027 set_irn_n(node, n_ia32_unary_op, load_res);
1030 case ia32_am_binary:
1031 if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
1032 assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) ||
1033 is_ia32_Test(node) || is_ia32_Test8Bit(node));
1034 set_irn_n(node, n_ia32_binary_left, load_res);
1036 set_irn_n(node, n_ia32_binary_right, load_res);
1040 case ia32_am_ternary:
1041 set_irn_n(node, n_ia32_binary_right, load_res);
1046 set_irn_n(node, n_ia32_base, noreg);
1047 set_irn_n(node, n_ia32_index, noreg);
1048 set_ia32_am_offs_int(node, 0);
1049 set_ia32_am_sc(node, NULL);
1050 set_ia32_am_scale(node, 0);
1051 clear_ia32_am_sc_sign(node);
1053 /* rewire mem-proj */
1054 if (get_irn_mode(node) == mode_T) {
1056 foreach_out_edge(node, edge) {
1057 ir_node *out = get_edge_src_irn(edge);
1058 if(get_Proj_proj(out) == pn_ia32_mem) {
1064 if(mem_proj != NULL) {
1065 set_Proj_pred(mem_proj, load);
1066 set_Proj_proj(mem_proj, pn_ia32_Load_M);
1070 set_ia32_op_type(node, ia32_Normal);
1071 if (sched_is_scheduled(node))
1072 sched_add_before(node, load);
1075 static ir_node *flags_remat(ir_node *node, ir_node *after)
1077 /* we should turn back source address mode when rematerializing nodes */
1078 ia32_op_type_t type = get_ia32_op_type(node);
1082 if (is_Block(after)) {
1085 block = get_nodes_block(after);
1089 case ia32_AddrModeS: turn_back_am(node); break;
1091 case ia32_AddrModeD:
1092 /* TODO implement this later... */
1093 panic("found DestAM with flag user %+F this should not happen", node);
1096 default: assert(type == ia32_Normal); break;
1099 copy = exact_copy(node);
1100 set_nodes_block(copy, block);
1101 sched_add_after(after, copy);
1107 * Called before the register allocator.
1108 * Calculate a block schedule here. We need it for the x87
1109 * simulator and the emitter.
1111 static void ia32_before_ra(void *self) {
1112 ia32_code_gen_t *cg = self;
1114 /* setup fpu rounding modes */
1115 ia32_setup_fpu_mode(cg);
1118 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1121 ia32_add_missing_keeps(cg);
1126 * Transforms a be_Reload into a ia32 Load.
1128 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1129 ir_graph *irg = get_irn_irg(node);
1130 dbg_info *dbg = get_irn_dbg_info(node);
1131 ir_node *block = get_nodes_block(node);
1132 ir_entity *ent = be_get_frame_entity(node);
1133 ir_mode *mode = get_irn_mode(node);
1134 ir_mode *spillmode = get_spill_mode(node);
1135 ir_node *noreg = ia32_new_NoReg_gp(cg);
1136 ir_node *sched_point = NULL;
1137 ir_node *ptr = get_irg_frame(irg);
1138 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1139 ir_node *new_op, *proj;
1140 const arch_register_t *reg;
1142 if (sched_is_scheduled(node)) {
1143 sched_point = sched_prev(node);
1146 if (mode_is_float(spillmode)) {
1147 if (ia32_cg_config.use_sse2)
1148 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
1150 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
1152 else if (get_mode_size_bits(spillmode) == 128) {
1153 // Reload 128 bit sse registers
1154 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1157 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1159 set_ia32_op_type(new_op, ia32_AddrModeS);
1160 set_ia32_ls_mode(new_op, spillmode);
1161 set_ia32_frame_ent(new_op, ent);
1162 set_ia32_use_frame(new_op);
1164 DBG_OPT_RELOAD2LD(node, new_op);
1166 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1169 sched_add_after(sched_point, new_op);
1173 /* copy the register from the old node to the new Load */
1174 reg = arch_get_irn_register(cg->arch_env, node);
1175 arch_set_irn_register(cg->arch_env, new_op, reg);
1177 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1179 exchange(node, proj);
1183 * Transforms a be_Spill node into a ia32 Store.
1185 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1186 ir_graph *irg = get_irn_irg(node);
1187 dbg_info *dbg = get_irn_dbg_info(node);
1188 ir_node *block = get_nodes_block(node);
1189 ir_entity *ent = be_get_frame_entity(node);
1190 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1191 ir_mode *mode = get_spill_mode(spillval);
1192 ir_node *noreg = ia32_new_NoReg_gp(cg);
1193 ir_node *nomem = new_rd_NoMem(irg);
1194 ir_node *ptr = get_irg_frame(irg);
1195 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1197 ir_node *sched_point = NULL;
1199 if (sched_is_scheduled(node)) {
1200 sched_point = sched_prev(node);
1203 /* No need to spill unknown values... */
1204 if(is_ia32_Unknown_GP(val) ||
1205 is_ia32_Unknown_VFP(val) ||
1206 is_ia32_Unknown_XMM(val)) {
1211 exchange(node, store);
1215 if (mode_is_float(mode)) {
1216 if (ia32_cg_config.use_sse2)
1217 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
1219 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
1220 } else if (get_mode_size_bits(mode) == 128) {
1221 // Spill 128 bit SSE registers
1222 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
1223 } else if (get_mode_size_bits(mode) == 8) {
1224 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
1226 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
1229 set_ia32_op_type(store, ia32_AddrModeD);
1230 set_ia32_ls_mode(store, mode);
1231 set_ia32_frame_ent(store, ent);
1232 set_ia32_use_frame(store);
1233 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1234 DBG_OPT_SPILL2ST(node, store);
1237 sched_add_after(sched_point, store);
1241 exchange(node, store);
1244 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1245 ir_graph *irg = get_irn_irg(node);
1246 dbg_info *dbg = get_irn_dbg_info(node);
1247 ir_node *block = get_nodes_block(node);
1248 ir_node *noreg = ia32_new_NoReg_gp(cg);
1249 ir_node *frame = get_irg_frame(irg);
1251 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, sp, noreg);
1253 set_ia32_frame_ent(push, ent);
1254 set_ia32_use_frame(push);
1255 set_ia32_op_type(push, ia32_AddrModeS);
1256 set_ia32_ls_mode(push, mode_Is);
1258 sched_add_before(schedpoint, push);
1262 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1263 ir_graph *irg = get_irn_irg(node);
1264 dbg_info *dbg = get_irn_dbg_info(node);
1265 ir_node *block = get_nodes_block(node);
1266 ir_node *noreg = ia32_new_NoReg_gp(cg);
1267 ir_node *frame = get_irg_frame(irg);
1269 ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, new_NoMem(), sp);
1271 set_ia32_frame_ent(pop, ent);
1272 set_ia32_use_frame(pop);
1273 set_ia32_op_type(pop, ia32_AddrModeD);
1274 set_ia32_ls_mode(pop, mode_Is);
1276 sched_add_before(schedpoint, pop);
1281 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
1282 ir_graph *irg = get_irn_irg(node);
1283 dbg_info *dbg = get_irn_dbg_info(node);
1284 ir_node *block = get_nodes_block(node);
1285 ir_mode *spmode = mode_Iu;
1286 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1289 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1290 arch_set_irn_register(cg->arch_env, sp, spreg);
1296 * Transform memperm, currently we do this the ugly way and produce
1297 * push/pop into/from memory cascades. This is possible without using
1300 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1301 ir_graph *irg = get_irn_irg(node);
1302 ir_node *block = get_nodes_block(node);
1306 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1307 const ir_edge_t *edge;
1308 const ir_edge_t *next;
1311 arity = be_get_MemPerm_entity_arity(node);
1312 pops = alloca(arity * sizeof(pops[0]));
1315 for(i = 0; i < arity; ++i) {
1316 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1317 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1318 ir_type *enttype = get_entity_type(inent);
1319 unsigned entsize = get_type_size_bytes(enttype);
1320 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1321 ir_node *mem = get_irn_n(node, i + 1);
1324 /* work around cases where entities have different sizes */
1325 if(entsize2 < entsize)
1327 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1329 push = create_push(cg, node, node, sp, mem, inent);
1330 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1332 /* add another push after the first one */
1333 push = create_push(cg, node, node, sp, mem, inent);
1334 add_ia32_am_offs_int(push, 4);
1335 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1338 set_irn_n(node, i, new_Bad());
1342 for(i = arity - 1; i >= 0; --i) {
1343 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1344 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1345 ir_type *enttype = get_entity_type(outent);
1346 unsigned entsize = get_type_size_bytes(enttype);
1347 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1350 /* work around cases where entities have different sizes */
1351 if(entsize2 < entsize)
1353 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1355 pop = create_pop(cg, node, node, sp, outent);
1356 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1358 add_ia32_am_offs_int(pop, 4);
1360 /* add another pop after the first one */
1361 pop = create_pop(cg, node, node, sp, outent);
1362 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1369 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1370 sched_add_before(node, keep);
1372 /* exchange memprojs */
1373 foreach_out_edge_safe(node, edge, next) {
1374 ir_node *proj = get_edge_src_irn(edge);
1375 int p = get_Proj_proj(proj);
1379 set_Proj_pred(proj, pops[p]);
1380 set_Proj_proj(proj, pn_ia32_Pop_M);
1383 /* remove memperm */
1384 arity = get_irn_arity(node);
1385 for(i = 0; i < arity; ++i) {
1386 set_irn_n(node, i, new_Bad());
1392 * Block-Walker: Calls the transform functions Spill and Reload.
1394 static void ia32_after_ra_walker(ir_node *block, void *env) {
1395 ir_node *node, *prev;
1396 ia32_code_gen_t *cg = env;
1398 /* beware: the schedule is changed here */
1399 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1400 prev = sched_prev(node);
1402 if (be_is_Reload(node)) {
1403 transform_to_Load(cg, node);
1404 } else if (be_is_Spill(node)) {
1405 transform_to_Store(cg, node);
1406 } else if(be_is_MemPerm(node)) {
1407 transform_MemPerm(cg, node);
1413 * Collects nodes that need frame entities assigned.
1415 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1417 be_fec_env_t *env = data;
1419 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1420 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1421 int align = get_mode_size_bytes(mode);
1422 be_node_needs_frame_entity(env, node, mode, align);
1423 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1424 && is_ia32_use_frame(node)) {
1425 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1426 const ir_mode *mode = get_ia32_ls_mode(node);
1427 const ia32_attr_t *attr = get_ia32_attr_const(node);
1428 int align = get_mode_size_bytes(mode);
1430 if(attr->data.need_64bit_stackent) {
1433 if(attr->data.need_32bit_stackent) {
1436 be_node_needs_frame_entity(env, node, mode, align);
1437 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
1438 || is_ia32_vfld(node)) {
1439 const ir_mode *mode = get_ia32_ls_mode(node);
1441 be_node_needs_frame_entity(env, node, mode, align);
1442 } else if(is_ia32_FldCW(node)) {
1443 /* although 2 byte would be enough 4 byte performs best */
1444 const ir_mode *mode = mode_Iu;
1446 be_node_needs_frame_entity(env, node, mode, align);
1449 assert(is_ia32_St(node) ||
1450 is_ia32_xStoreSimple(node) ||
1451 is_ia32_vfst(node) ||
1452 is_ia32_vfist(node) ||
1453 is_ia32_FnstCW(node));
1460 * We transform Spill and Reload here. This needs to be done before
1461 * stack biasing otherwise we would miss the corrected offset for these nodes.
1463 static void ia32_after_ra(void *self) {
1464 ia32_code_gen_t *cg = self;
1465 ir_graph *irg = cg->irg;
1466 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1468 /* create and coalesce frame entities */
1469 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1470 be_assign_entities(fec_env);
1471 be_free_frame_entity_coalescer(fec_env);
1473 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1477 * Last touchups for the graph before emit: x87 simulation to replace the
1478 * virtual with real x87 instructions, creating a block schedule and peephole
1481 static void ia32_finish(void *self) {
1482 ia32_code_gen_t *cg = self;
1483 ir_graph *irg = cg->irg;
1485 ia32_finish_irg(irg, cg);
1487 /* we might have to rewrite x87 virtual registers */
1488 if (cg->do_x87_sim) {
1489 x87_simulate_graph(cg->arch_env, cg->birg);
1492 /* do peephole optimisations */
1493 ia32_peephole_optimization(cg);
1495 /* create block schedule, this also removes empty blocks which might
1496 * produce critical edges */
1497 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1501 * Emits the code, closes the output file and frees
1502 * the code generator interface.
1504 static void ia32_codegen(void *self) {
1505 ia32_code_gen_t *cg = self;
1506 ir_graph *irg = cg->irg;
1508 ia32_gen_routine(cg, irg);
1512 /* remove it from the isa */
1515 assert(ia32_current_cg == cg);
1516 ia32_current_cg = NULL;
1518 /* de-allocate code generator */
1519 del_set(cg->reg_set);
1523 static ir_node *ia32_get_pic_base(void *self) {
1525 ia32_code_gen_t *cg = self;
1526 ir_node *get_eip = cg->get_eip;
1531 block = get_irg_start_block(cg->irg);
1532 get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block);
1533 cg->get_eip = get_eip;
1535 add_irn_dep(get_eip, get_irg_frame(cg->irg));
1540 static void *ia32_cg_init(be_irg_t *birg);
1542 static const arch_code_generator_if_t ia32_code_gen_if = {
1545 ia32_before_abi, /* before abi introduce hook */
1548 ia32_before_sched, /* before scheduling hook */
1549 ia32_before_ra, /* before register allocation hook */
1550 ia32_after_ra, /* after register allocation hook */
1551 ia32_finish, /* called before codegen */
1552 ia32_codegen /* emit && done */
1556 * Initializes a IA32 code generator.
1558 static void *ia32_cg_init(be_irg_t *birg) {
1559 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1560 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1562 cg->impl = &ia32_code_gen_if;
1563 cg->irg = birg->irg;
1564 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1565 cg->arch_env = birg->main_env->arch_env;
1568 cg->blk_sched = NULL;
1569 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1575 if (isa->name_obst) {
1576 obstack_free(isa->name_obst, NULL);
1577 obstack_init(isa->name_obst);
1581 cur_reg_set = cg->reg_set;
1583 ia32_irn_ops.cg = cg;
1585 assert(ia32_current_cg == NULL);
1586 ia32_current_cg = cg;
1588 return (arch_code_generator_t *)cg;
1593 /*****************************************************************
1594 * ____ _ _ _____ _____
1595 * | _ \ | | | | |_ _|/ ____| /\
1596 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1597 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1598 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1599 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1601 *****************************************************************/
1604 * Set output modes for GCC
1606 static const tarval_mode_info mo_integer = {
1613 * set the tarval output mode of all integer modes to decimal
1615 static void set_tarval_output_modes(void)
1619 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1620 ir_mode *mode = get_irp_mode(i);
1622 if (mode_is_int(mode))
1623 set_tarval_mode_output_option(mode, &mo_integer);
1627 const arch_isa_if_t ia32_isa_if;
1630 * The template that generates a new ISA object.
1631 * Note that this template can be changed by command line
1634 static ia32_isa_t ia32_isa_template = {
1636 &ia32_isa_if, /* isa interface implementation */
1637 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1638 &ia32_gp_regs[REG_EBP], /* base pointer register */
1639 -1, /* stack direction */
1640 NULL, /* main environment */
1641 7, /* costs for a spill instruction */
1642 5, /* costs for a reload instruction */
1644 NULL, /* 16bit register names */
1645 NULL, /* 8bit register names */
1646 NULL, /* 8bit register names high */
1649 NULL, /* current code generator */
1650 NULL, /* abstract machine */
1652 NULL, /* name obstack */
1657 * Initializes the backend ISA.
1659 static void *ia32_init(FILE *file_handle) {
1660 static int inited = 0;
1667 set_tarval_output_modes();
1669 isa = xmalloc(sizeof(*isa));
1670 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1672 if(mode_fpcw == NULL) {
1673 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1676 ia32_register_init();
1677 ia32_create_opcodes();
1679 be_emit_init(file_handle);
1680 isa->regs_16bit = pmap_create();
1681 isa->regs_8bit = pmap_create();
1682 isa->regs_8bit_high = pmap_create();
1683 isa->types = pmap_create();
1684 isa->tv_ent = pmap_create();
1685 isa->cpu = ia32_init_machine_description();
1687 ia32_build_16bit_reg_map(isa->regs_16bit);
1688 ia32_build_8bit_reg_map(isa->regs_8bit);
1689 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1692 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1693 obstack_init(isa->name_obst);
1696 /* enter the ISA object into the intrinsic environment */
1697 intrinsic_env.isa = isa;
1698 ia32_handle_intrinsics();
1700 /* needed for the debug support */
1701 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1702 be_emit_cstring(".Ltext0:\n");
1703 be_emit_write_line();
1705 /* we mark referenced global entities, so we can only emit those which
1706 * are actually referenced. (Note: you mustn't use the type visited flag
1707 * elsewhere in the backend)
1709 inc_master_type_visited();
1717 * Closes the output file and frees the ISA structure.
1719 static void ia32_done(void *self) {
1720 ia32_isa_t *isa = self;
1722 /* emit now all global declarations */
1723 be_gas_emit_decls(isa->arch_isa.main_env, 1);
1725 pmap_destroy(isa->regs_16bit);
1726 pmap_destroy(isa->regs_8bit);
1727 pmap_destroy(isa->regs_8bit_high);
1728 pmap_destroy(isa->tv_ent);
1729 pmap_destroy(isa->types);
1732 obstack_free(isa->name_obst, NULL);
1742 * Return the number of register classes for this architecture.
1743 * We report always these:
1744 * - the general purpose registers
1745 * - the SSE floating point register set
1746 * - the virtual floating point registers
1747 * - the SSE vector register set
1749 static unsigned ia32_get_n_reg_class(const void *self) {
1755 * Return the register class for index i.
1757 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1761 assert(i < N_CLASSES);
1762 return &ia32_reg_classes[i];
1766 * Get the register class which shall be used to store a value of a given mode.
1767 * @param self The this pointer.
1768 * @param mode The mode in question.
1769 * @return A register class which can hold values of the given mode.
1771 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1772 const ir_mode *mode)
1776 if (mode_is_float(mode)) {
1777 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1780 return &ia32_reg_classes[CLASS_ia32_gp];
1784 * Get the ABI restrictions for procedure calls.
1785 * @param self The this pointer.
1786 * @param method_type The type of the method (procedure) in question.
1787 * @param abi The abi object to be modified
1789 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1796 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1799 /* set abi flags for calls */
1800 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1801 call_flags.bits.store_args_sequential = 0;
1802 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1803 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1804 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1806 /* set parameter passing style */
1807 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1809 if (get_method_variadicity(method_type) == variadicity_variadic) {
1810 /* pass all parameters of a variadic function on the stack */
1813 cc = get_method_calling_convention(method_type);
1814 if (get_method_additional_properties(method_type) & mtp_property_private
1815 && (ia32_cg_config.optimize_cc)) {
1816 /* set the calling conventions to register parameter */
1817 cc = (cc & ~cc_bits) | cc_reg_param;
1821 /* we have to pop the shadow parameter ourself for compound calls */
1822 if( (get_method_calling_convention(method_type) & cc_compound_ret)
1823 && !(cc & cc_reg_param)) {
1824 be_abi_call_set_pop(abi, get_mode_size_bytes(mode_P_data));
1827 n = get_method_n_params(method_type);
1828 for (i = regnum = 0; i < n; i++) {
1830 const arch_register_t *reg = NULL;
1832 tp = get_method_param_type(method_type, i);
1833 mode = get_type_mode(tp);
1835 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1838 be_abi_call_param_reg(abi, i, reg);
1841 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1842 * movl has a shorter opcode than mov[sz][bw]l */
1843 ir_mode *load_mode = mode;
1844 if (mode != NULL && get_mode_size_bytes(mode) < 4) load_mode = mode_Iu;
1845 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1849 /* set return registers */
1850 n = get_method_n_ress(method_type);
1852 assert(n <= 2 && "more than two results not supported");
1854 /* In case of 64bit returns, we will have two 32bit values */
1856 tp = get_method_res_type(method_type, 0);
1857 mode = get_type_mode(tp);
1859 assert(!mode_is_float(mode) && "two FP results not supported");
1861 tp = get_method_res_type(method_type, 1);
1862 mode = get_type_mode(tp);
1864 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1866 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1867 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1870 const arch_register_t *reg;
1872 tp = get_method_res_type(method_type, 0);
1873 assert(is_atomic_type(tp));
1874 mode = get_type_mode(tp);
1876 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1878 be_abi_call_res_reg(abi, 0, reg);
1883 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self,
1888 return &ia32_irn_ops;
1891 const arch_irn_handler_t ia32_irn_handler = {
1895 const arch_irn_handler_t *ia32_get_irn_handler(const void *self)
1898 return &ia32_irn_handler;
1901 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1905 if(!is_ia32_irn(irn)) {
1909 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1910 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1911 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1912 || is_ia32_Immediate(irn))
1919 * Initializes the code generator interface.
1921 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1924 return &ia32_code_gen_if;
1928 * Returns the estimated execution time of an ia32 irn.
1930 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1931 const arch_env_t *arch_env = env;
1932 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1935 list_sched_selector_t ia32_sched_selector;
1938 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1940 static const list_sched_selector_t *ia32_get_list_sched_selector(
1941 const void *self, list_sched_selector_t *selector)
1944 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1945 ia32_sched_selector.exectime = ia32_sched_exectime;
1946 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1947 return &ia32_sched_selector;
1950 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1957 * Returns the necessary byte alignment for storing a register of given class.
1959 static int ia32_get_reg_class_alignment(const void *self,
1960 const arch_register_class_t *cls)
1962 ir_mode *mode = arch_register_class_mode(cls);
1963 int bytes = get_mode_size_bytes(mode);
1966 if (mode_is_float(mode) && bytes > 8)
1971 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1972 const void *self, const ir_node *irn)
1974 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1975 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1976 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1979 static const be_execution_unit_t *_allowed_units_GP[] = {
1980 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1981 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1982 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1983 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1984 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1985 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1986 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1989 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1990 &be_machine_execution_units_DUMMY[0],
1993 static const be_execution_unit_t **_units_callret[] = {
1994 _allowed_units_BRANCH,
1997 static const be_execution_unit_t **_units_other[] = {
2001 static const be_execution_unit_t **_units_dummy[] = {
2002 _allowed_units_DUMMY,
2005 const be_execution_unit_t ***ret;
2008 if (is_ia32_irn(irn)) {
2009 ret = get_ia32_exec_units(irn);
2011 else if (is_be_node(irn)) {
2012 if (be_is_Call(irn) || be_is_Return(irn)) {
2013 ret = _units_callret;
2015 else if (be_is_Barrier(irn)) {
2030 * Return the abstract ia32 machine.
2032 static const be_machine_t *ia32_get_machine(const void *self) {
2033 const ia32_isa_t *isa = self;
2038 * Return irp irgs in the desired order.
2040 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2048 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2049 * @return 1 if allowed, 0 otherwise
2051 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2059 if(!ia32_cg_config.use_cmov) {
2060 /* TODO: we could still handle abs(x)... */
2064 /* we can't handle psis with 64bit compares yet */
2066 ir_node *pred = get_Proj_pred(sel);
2068 ir_node *left = get_Cmp_left(pred);
2069 ir_mode *cmp_mode = get_irn_mode(left);
2070 if(!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
2075 /* check the Phi nodes */
2076 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
2077 ir_mode *mode = get_irn_mode(phi);
2079 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2087 * Returns the libFirm configuration parameter for this backend.
2089 static const backend_params *ia32_get_libfirm_params(void) {
2090 static const ir_settings_if_conv_t ifconv = {
2091 4, /* maxdepth, doesn't matter for Psi-conversion */
2092 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2094 static const ir_settings_arch_dep_t ad = {
2095 1, /* also use subs */
2096 4, /* maximum shifts */
2097 31, /* maximum shift amount */
2098 ia32_evaluate_insn, /* evaluate the instruction sequence */
2100 1, /* allow Mulhs */
2101 1, /* allow Mulus */
2102 32 /* Mulh allowed up to 32 bit */
2104 static backend_params p = {
2105 1, /* need dword lowering */
2106 1, /* support inline assembly */
2107 NULL, /* no additional opcodes */
2108 NULL, /* will be set later */
2109 ia32_create_intrinsic_fkt,
2110 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2111 NULL, /* will be set below */
2114 ia32_setup_cg_config();
2117 p.if_conv_info = &ifconv;
2121 static const lc_opt_enum_int_items_t gas_items[] = {
2122 { "elf", GAS_FLAVOUR_ELF },
2123 { "mingw", GAS_FLAVOUR_MINGW },
2124 { "yasm", GAS_FLAVOUR_YASM },
2125 { "macho", GAS_FLAVOUR_MACH_O },
2129 static lc_opt_enum_int_var_t gas_var = {
2130 (int*) &be_gas_flavour, gas_items
2133 static const lc_opt_table_entry_t ia32_options[] = {
2134 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2138 const arch_isa_if_t ia32_isa_if = {
2141 ia32_get_n_reg_class,
2143 ia32_get_reg_class_for_mode,
2145 ia32_get_irn_handler,
2146 ia32_get_code_generator_if,
2147 ia32_get_list_sched_selector,
2148 ia32_get_ilp_sched_selector,
2149 ia32_get_reg_class_alignment,
2150 ia32_get_libfirm_params,
2151 ia32_get_allowed_execution_units,
2156 void ia32_init_emitter(void);
2157 void ia32_init_finish(void);
2158 void ia32_init_optimize(void);
2159 void ia32_init_transform(void);
2160 void ia32_init_x87(void);
2162 void be_init_arch_ia32(void)
2164 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2165 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2167 lc_opt_add_table(ia32_grp, ia32_options);
2168 be_register_isa_if("ia32", &ia32_isa_if);
2170 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2172 ia32_init_emitter();
2174 ia32_init_optimize();
2175 ia32_init_transform();
2177 ia32_init_architecture();
2180 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);